Heterojunction bipolar transistor with GAA structure and preparation method thereof

Abstract

The present invention provides a heterojunction bipolar transistor with a GAA structure and a preparation method thereof. The transistor is a small-size device, and mainly uses the process of a gate-all-around field effect transistor (GAAFET) to prepare a Si / SiGe heterojunction bipolar transistor. The emitter region and the base region of the structure form a fully surrounded heterogeneous emitter junction, and the base region and the collector region form a fully surrounded collector junction, which effectively increases the injection efficiency of the emitter junction and the ability of the collector region to extract carriers. For the Si / SiGe heterojunction, the carriers can be effectively controlled by adjusting the change in the band gap width of the SiGe material; by increasing the doping concentration of the SiGe base region, the device can obtain a higher Early voltage, reduce the base resistance, and weaken the large injection effect; by thinning the base region thickness, the base region transit time is greatly shortened, and the excellent performance of ultra-high frequency, ultra-high speed and low noise can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a heterojunction bipolar transistor with a GAA structure and a preparation method thereof. Background Art

[0002] The development history of semiconductor integrated circuit technology is essentially the history of transistor size reduction, from the 10μm planar structure in the 1970s, to the 22nm-FinFET three-dimensional structure in 2012, and then to the 5nm-FinFET, following Moore's Law step by step. After 5nm, the FinFET structure is difficult to meet the electrostatic control required by the transistor. In 2019, Samsung clearly stated that it will apply the Gate-All-Around FET technology at the next technology node 3nm.

[0003] The new GAA structure can achieve better control over the field effect transistor channel because the contact area between the gate and the channel is larger, increasing from three-sided contact in the FinFET structure to four-sided contact in the GAA structure, which will reduce the gate length, that is, the device feature size.

[0004] The improvement of the performance of digital integrated circuits and analog integrated circuits mainly relies on the reduction of transistor size, new device structures or new semiconductor materials. The latter is mainly composed of bipolar junction transistors (BJT). Therefore, for BJT, reducing its characteristic size and adopting new device structures or new semiconductor materials are of great significance.

[0005] The present invention is a heterojunction bipolar transistor with a GAA structure. The design principle of the heterojunction is to use the change of the band gap width of the semiconductor material and the electric field force acting on electrons and holes to control the distribution and flow of carriers. Compared with the homojunction of BJT, it has many advantages. The GAA structure is a new device structure that is the mainstream of the next technology node, which reduces the device feature size while improving the device performance. Summary of the invention

[0006] The technical problem to be solved by the present invention is that, in order to improve the performance of analog integrated circuits, the present application provides a heterojunction bipolar transistor with a GAA structure and a preparation method thereof.

[0007] Specifically, the present invention provides a method for preparing a heterojunction bipolar transistor with a GAA structure, which comprises the following steps:

[0008] Step 1: forming a stacked structure of a SiGe first sacrificial layer and a Si semiconductor nanosheet layer interlaced on a substrate, wherein the semiconductor nanosheet layer is an n-type Si material, etching the SiGe / Si / SiGe stacked structure to form a second sacrificial layer and a collector region, wherein the second sacrificial layer is a SiGe material, and the collector region is an n-type Si semiconductor nanosheet;

[0009] Step 2, forming a dummy gate on the SiGe / Si / SiGe stacked structure, and depositing a Si3N4 hard mask layer on the dummy gate;

[0010] Step 3, the second sacrificial layer is laterally etched from both sides in the Y direction to form a third sacrificial layer and a first SiO2 support layer is deposited on the device surface;

[0011] Step 4, depositing a first SiON layer on the SiO2 first support layer, and planarizing the device by chemical mechanical polishing (CMP);

[0012] Step 5, anisotropically etching the device surface downward, using the dummy gate as an etching stop layer, to form a second SiO2 support layer and a second SiON layer;

[0013] Step 6, removing the dummy gate and SiO2 and SiON on its surface to form a first groove, then selectively etching the third sacrificial layer laterally to remove the SiGe material used as the sacrificial layer in the first groove to form a fourth sacrificial layer, wherein the fourth sacrificial layer is made of SiGe material, so that the collector region in the first groove is suspended above the substrate and is rounded to form a racetrack-shaped structure in cross-section;

[0014] Step 7, depositing a first insulating layer of SiO2 in the first groove, and then planarizing the device;

[0015] Step eight, spin-coating a layer of photoresist, transferring the pattern on the mask to the device surface by photolithography, etching to form the second groove and the third groove, the third support layer and the third SiON layer; removing the fourth sacrificial layer, so that the collector area located in the second groove and the third groove is suspended above the substrate, and then rounding this part of the collector area to form a racetrack-shaped structure in the cross-section;

[0016] Step nine, epitaxially growing a SiGe base region around the collector region located in the second groove and the third groove;

[0017] Step 10, removing the photoresist, depositing SiO2 in the second groove and the third groove, and after the device is planarized, forming the fourth groove and the fifth groove by etching and photolithography processes to form a fourth supporting layer, and the collector region and the base region located in the fourth groove and the fifth groove are suspended above the substrate;

[0018] Step 11, epitaxially growing a Si emitter around the base region located in the fourth groove and the fifth groove, removing the third SiON layer, and then depositing SiO2 on the device surface, and using the CMP method to planarize the device. The SiO2 deposited in this step and the SiO2 with supporting and insulating functions in the previous step together form a second insulating layer;

[0019] Step twelve, a high-stress Si3N4 covering layer is deposited on the surface of the device, a collector window, a base window and an emitter window are etched on the surface respectively, and polysilicon is deposited to form a collector, a base and an emitter.

[0020] In a preferred embodiment of the present invention, the manufacturing method is implemented using equipment compatible with the all-around gate field effect transistor manufacturing process.

[0021] In a preferred embodiment of the present invention, the base region is a compressively strained p-type SiGe, and forms a fully surrounding collector junction with the collector region.

[0022] In a preferred embodiment of the present invention, the emitter region is n-type Si, and forms a fully surrounded heterogeneous emitter junction with the base region.

[0023] In step six and step eight, the collector region of the semiconductor nanosheet layer, which is an n-type Si material, is rounded by oxidation followed by wet etching, and then hydrogen annealing is performed at a temperature of 800° C. to 1200° C.

[0024] In a preferred embodiment of the present invention, in step seven, SiO2 is deposited by HDP CVD, and the device is planarized by CMP.

[0025] The present invention also provides a heterojunction bipolar transistor with a GAA structure, which is arranged in sequence from bottom to top: a Si substrate, a SiO2 second insulating layer, an n-type Si emitter region, a p-type SiGe base region, an n-type Si collector region, a Si3N4 stress layer, an emitter, a base and a collector;

[0026] A polysilicon emitter is formed above the emitter region; a polysilicon base is formed above the base region; and a polysilicon collector is formed above the collector region;

[0027] The Si3N4 stress layer covers the device surface, provides uniaxial stress, and improves carrier mobility.

[0028] In a preferred embodiment of the present invention, the collector region is surrounded by the base region to form a Si / SiGe fully surrounding collector junction; meanwhile, the base region is surrounded by the emitter region to form a Si / SiGe fully surrounding heterogeneous emitter junction.

[0029] In a preferred embodiment of the present invention, the thickness of the n-type Si collector region is 10nm-100nm; the thickness of the p-type SiGe base region is 10nm-50nm; and the thickness of the n-type emitter region is 10nm-100nm.

[0030] Compared with the prior art, the heterojunction bipolar transistor with a GAA structure and the preparation method thereof provided by the present application have the following beneficial effects:

[0031] The heterojunction bipolar transistor provided in the present application combines the GAA process, the heterojunction bipolar transistor (HBT) and the strained Si technology, and adopts the Si / SiGe heterojunction on the basis of reducing the characteristic size of the device. The carriers can be effectively controlled by adjusting the change of the band gap width of the SiGe material. By increasing the doping concentration of the SiGe base region, the device can obtain a higher Early voltage, reduce the base resistance, weaken the large injection effect, and shorten the base region transit time by thinning the base region, thereby achieving excellent performance of ultra-high frequency, ultra-high speed and low noise.

[0032] The heterojunction bipolar transistor provided in the present application has a Si3N4 stress layer covering the device surface to provide uniaxial stress, thereby improving the mobility of electrons, further reducing the base region transit time, and increasing the cutoff frequency and maximum oscillation frequency of the device.

[0033] The heterojunction bipolar transistor provided in the present application has a structure in which the emitter region and the base region form a fully surrounding heterogeneous emitter junction, and the base region and the collector region form a fully surrounding collector junction, which effectively increases the injection efficiency of the emitter junction and the ability of the collector region to extract carriers. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 and Figure 2 It is a structural schematic diagram of step 1 of manufacturing a heterojunction bipolar transistor with a GAA structure of the present application;

[0035] Figure 3A and Figure 3B It is a schematic diagram of step 2 of manufacturing a heterojunction bipolar transistor with a GAA structure of the present application;

[0036] Figure 4A and Figure 4B It is a schematic diagram of step 3 of preparing a heterojunction bipolar transistor with a GAA structure of the present application;

[0037] Figure 5A and Figure 5B It is a schematic diagram of step 4 of manufacturing a heterojunction bipolar transistor with a GAA structure of the present application;

[0038] Fig. 6A and Figure 6B It is a schematic diagram of step 5 of preparing a heterojunction bipolar transistor with a GAA structure of the present application;

[0039] Fig. 7A and Figure 7B It is a schematic diagram of step 6 of preparing a heterojunction bipolar transistor with a GAA structure of the present application;

[0040] Fig. 8A and Figure 8B Schematic diagram of step 7 of manufacturing a heterojunction bipolar transistor with a GAA structure of the present application;

[0041] Fig. 9A and Fig. 9B It is a schematic diagram of step eight of preparing a heterojunction bipolar transistor with a GAA structure of the present application;

[0042] Fig. 10A and Fig. 10B It is a schematic diagram of step nine of manufacturing a heterojunction bipolar transistor with a GAA structure of the present application;

[0043] Fig.11A and Fig. 11B 10 is a schematic diagram of the preparation step of the heterojunction bipolar transistor with a GAA structure of the present application;

[0044] Fig. 12A and Fig. 12B 11 is a schematic diagram of the manufacturing step of the heterojunction bipolar transistor of the GAA structure of the present application;

[0045] Fig.13A and Fig. 13B It is a schematic diagram of step 12 of preparing the heterojunction bipolar transistor with a GAA structure of the present application.

[0046] Description of reference numerals:

[0047] 101 substrate, 201 first sacrificial layer, 202 semiconductor nanosheet layer, 102 second sacrificial layer, 103 collector region, 203 virtual gate, 204 hard mask layer, 1021 third sacrificial layer, 106 first supporting layer, 205 first SiON layer, 107 second supporting layer, 206 second SiON layer, 301 first groove, 1022 fourth sacrificial layer, 110 photoresist, 108 third supporting layer, 109 first insulating layer, 207 third SiON layer, 302 second groove, 303 third groove, 304 fourth groove, 305 fifth groove, 111 base region, 112 fourth supporting layer, 113 second insulating layer, 114 emitter region, 116 Si3N4 capping layer, 403 collector, 401 base, 402 emitter. DETAILED DESCRIPTION

[0048] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0049] Hereinafter, the specific embodiments of the present application will be described in detail with reference to the accompanying drawings. According to these detailed descriptions, those skilled in the art can clearly understand the present application and can implement the present application. Without violating the principles of the present application, the features in the various embodiments can be combined to obtain new implementations, or certain features in certain embodiments can be replaced to obtain other preferred implementations.

[0050] Figures 1 to 13B FIG. 1 is a schematic diagram of the device structure at each stage of the manufacturing process of the heterojunction bipolar transistor with a GAA structure according to an embodiment of the present invention, wherein Figure 1 and Figure 2 is the stereogram corresponding to step 1; FIG. 3A to FIG. 13A It is a cross-sectional view, and the cross-sectional position is AA; FIG. 3B to FIG. 9B is a cross-sectional view, the cross-sectional position is BB, and the cross-sectional positions AA and BB are the center lines of the directions respectively; Fig. 10B and Fig. 11B It is a cross-section diagram, and the cross-section position is BB 1 and BB 2 ,BB 1 and BB 2 The structure of the cross-section is the same even though the cross-section positions are different; Fig. 12B and Fig. 13B It is a cross-section diagram, and the cross-section position is BB 3 and BB 4 ,BB 3 and BB 4 The cross-sectional structures are the same despite different cross-sectional positions.

[0051] Step 1: forming a stacked structure of a first sacrificial layer 201 and a semiconductor nanosheet layer 202 interlaced on the substrate 101, such as Figure 1 It should be noted that in the drawings of the present invention, except for Si material and SiO2 material without filling patterns, other materials will use the same filling pattern to represent the same material layer, and the description is omitted in the drawings. For example, Figure 1In the figure, both the upper and lower sides of the semiconductor nanosheet layer 202 are the first sacrificial layer 201, but only one of them is marked, and the other first sacrificial layer 201 is represented by the same filling pattern. Specifically, a superlattice growth method is used on the substrate 101 to grow a stacked structure of the first sacrificial layer 201 and the semiconductor nanosheet layer 202. The first sacrificial layer 201 is a SiGe material, and the semiconductor nanosheet layer 202 is above the first sacrificial layer 201. The semiconductor nanosheet layer 202 is an n-type Si material, and the n-type impurities can be phosphorus or arsenic. 201 / 202 / 201 are epitaxially grown to form a SiGe / Si / SiGe structure, wherein the thickness of the first sacrificial layer 201 is 5-100nm, and the thickness of the semiconductor nanosheet layer 202 is 5-100nm. Then, the SiGe / Si / SiGe stacked structure is formed by photolithography and etching processes. Figure 2 As shown in the structure, the purpose of this step is to form a second sacrificial layer 102 and a collector region 103, and the collector region 103 is an n-type semiconductor nanosheet Si.

[0052] Step 2: Figure 2 A virtual gate 203 is formed on the SiGe / Si / SiGe stacked structure shown in the figure. The method for forming the virtual gate 203 structure is not particularly limited, and it can generally be composed of polycrystalline or amorphous Si, Ge or SiGe materials. The virtual gate 203 can be formed by low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD) or other suitable process methods, but it is not limited to these. A hard mask layer 204 is deposited on the virtual gate 203 using the above method or other suitable process methods. The hard mask layer 204 is composed of Si3N4 material, such as Figure 3A and Figure 3B .

[0053] Step 3, the second sacrificial layer 102 is laterally etched from both sides in the Y direction to form a third sacrificial layer 1021, and a first supporting layer 106 is deposited on the surface of the device. The first supporting layer 106 is made of SiO2 material. There is no particular limitation on the deposition method, which can generally be ALD, LPCVD, HDP CVD, PECVD and other suitable processes, such as Figure 4A and Figure 4B .

[0054] Step 4: deposit a first SiON layer 205 on the first support layer 106 in step 3. The method for forming the first SiON layer 205 is not particularly limited. For example, the first SiON layer 205 may be deposited by PECVD or HDP CVD, and the device may be planarized by chemical mechanical polishing (CMP). Figure 5A and Figure 5BThe first SiON layer 205 is used as a bottom anti-reflection layer of photolithography and is composed of a high extinction material, which can absorb light passing through the photoresist layer and reduce the influence of the standing wave effect.

[0055] Step 5: Fig. 6A and Figure 6B As shown, a portion of the insulating material is removed from the device horizontal surface by anisotropic etching, and the dummy gate 203 is used as an etching stop layer to form a second supporting layer 107 and a second SiON layer 206, wherein the second supporting layer 107 is made of SiO2 material.

[0056] Step 6: Fig. 7A and Figure 7B As shown, the virtual gate 203 and the SiO2 and SiON on its surface are removed to form a first groove 301, and then the third sacrificial layer 1021 is selectively etched laterally to remove the SiGe material used as the sacrificial layer in the first groove to form a fourth sacrificial layer 1022. There is no particular limitation on the method of removing the SiGe material used as the sacrificial layer. For example, HF, HNO3, and H2O etching solutions can be used, but are not limited to these. After removal, the collector region 103 located in the first groove 301 is suspended above the substrate 101. The collector region 103 located in the first groove 301 is rounded by oxidation followed by wet etching to form a fourth sacrificial layer 1022. Figure 7B The formation method of the cross-sectional racetrack structure shown is not particularly limited. For example, the semiconductor nanosheet Si located in the collector region 103 of the first groove 301 may be first oxidized, and then the oxide layer is wet-etched by dilute hydrofluoric acid (DHF), buffered hydrofluoric acid etching solvent (HF / NH4F) or other suitable solvents to obtain a cross-sectional racetrack shape, but the method is not limited thereto. Then, hydrogen annealing is performed at a temperature of 800°C-1200°C to make the surface of the collector region 103 located in the first groove 301 smoother and denser.

[0057] Step 7: forming a first insulating layer 109 in the first groove 301 in step 6. The first insulating layer is made of SiO2 material. The method of forming the first insulating layer is not particularly limited. In the present invention, it is preferably deposited by HDP CVD and then planarized by CMP, but it is not limited to this method. Fig. 8A and Figure 8B shown.

[0058] Step eight, spin-coat a layer of photoresist 110, transfer the pattern on the mask to the device surface by photolithography technology, and etch the second support layer 107 and the second SiON layer 206 to form the third support layer 108 (i.e., the remaining part after the second support layer 107 is etched) and the third SiON layer 207, and the second groove 302 and the third groove 303. Remove the fourth sacrificial layer 1022 in step six, and the removal method is the same as that in step six, so that the collector region 103 is partially suspended above the substrate 101, and the collector region 103 located in the second groove 302 and the third groove 303 is obtained by the same process as in step six. The racetrack-shaped cross-sectional view formed in this step should have an area greater than or equal to the racetrack-shaped cross-sectional view formed in step six. In this embodiment, the former and the latter have the same cross-sectional area. The purpose of this practice is to suppress the current edge gathering effect. Then, hydrogen annealing is performed at a temperature of 800°C to 1200°C to make the surface of the collector region 103 located in the second groove 302 and the third groove 303 smoother and denser. This process can increase the junction area of ​​the collector junction and the emitter junction, and improve the interface state between the emitter region and the base region, and between the base region and the collector region, such as Fig. 9A and Fig. 9B shown.

[0059] Step nine, epitaxially grow compressively strained p-type SiGe as base region 111 around collector region 103 located in second groove 302 and third groove 303, the thickness of base region 111 is not particularly limited, preferably 10nm-50nm, and p-type impurities are not particularly limited, preferably boron or aluminum. Thus, a fully surrounding collector junction is formed, such as Fig. 10A and Fig. 10B shown.

[0060] Step ten, remove the photoresist 110, deposit SiO2 in the second groove 302 and the third groove 303, the deposition method here is not particularly limited, preferably can be ALD, LPCVD, HDP CVD and PECVD and other suitable processes, and then form the fourth groove 304 and the fifth groove 305 by etching and photolithography, the collector region 103 and the base region 111 are partially suspended above the substrate 101, and the SiO2 that is not removed and the third support layer 108 together form a fourth support layer 112, as shown in FIG. Fig.11A and Fig. 11B shown.

[0061] Step 11: epitaxially grow n-type Si as the emitter region 114 around the base region 111 located at the fourth groove 304 and the fifth groove 305. The thickness of the emitter region 114 is not particularly limited, preferably 10nm-100nm. The n-type impurity is not particularly limited, preferably phosphorus or arsenic. Remove the third SiON layer 207 and then deposit SiO2 on the device surface, and planarize the device using the CMP method. The SiO2 deposited in this step and the SiO2 with supporting and insulating functions in the previous step together form the second insulating layer 113, as shown in FIG. Fig. 12A and Fig. 12B shown.

[0062] Step 12: Fig.13A and Fig. 13B As shown, a high stress Si3N4 capping layer 116 is deposited, and the deposition method is not particularly limited, for example, it can be through a PECVD method. The Si3N4 capping layer 116 provides uniaxial stress. Then, a collector window, a base window and an emitter window are etched out in the Si3N4 capping layer 116, and polysilicon is deposited to form a collector 403, a base 401 and an emitter 402, which are in contact with the collector region, the base region and the emitter region respectively.

[0063] Thus, a heterojunction bipolar transistor with a special GAA structure of the present invention is formed. The preparation method of the present invention is compatible with the preparation process of a full-surround gate field effect transistor, and general equipment can be used, which is conducive to cost reduction.

[0064] The embodiments described above are only descriptions of the preferred implementation modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A method for preparing a heterojunction bipolar transistor with a GAA structure, characterized in that: It includes the following steps: Step 1: forming a SiGe / Si / SiGe stacking structure in which a SiGe first sacrificial layer and a Si semiconductor nanosheet layer are interlaced on a substrate, wherein the semiconductor nanosheet layer is an n-type Si material, etching the SiGe / Si / SiGe stacking structure, and the remaining first sacrificial layer forms a second sacrificial layer, and the remaining semiconductor nanosheet layer forms a collector region; Step 2, forming a dummy gate on the SiGe / Si / SiGe stacked structure, and depositing a Si3N4 hard mask layer on the dummy gate; Step three, in the Y direction, the two ends of the second sacrificial layer are laterally etched so that the two ends of the second sacrificial layer are recessed inward relative to the collector region, the unremoved second sacrificial layer forms a third sacrificial layer, and a SiO2 first support layer is deposited on the device surface; Step 4, depositing a first SiON layer on the SiO2 first supporting layer and planarizing the device; Step 5, anisotropically etching the device surface downward, using the dummy gate as an etching stop layer, removing the Si3N4 hard mask layer and part of the SiO2 first support layer and part of the first SiON layer, and forming a SiO2 second support layer and a second SiON layer from the unremoved SiO2 first support layer and the first SiON layer; Step 6, removing the dummy gate to form a first groove, then using selective lateral etching to remove the third sacrificial layer corresponding to the first groove, and forming a fourth sacrificial layer by the third sacrificial layer that is not removed, so that the collector region located in the first groove is suspended above the substrate, and the collector region is rounded to form a racetrack-shaped structure in cross-section; Step 7, depositing a first insulating layer of SiO2 in the first groove, and then planarizing the device; Step eight, spin-coating a layer of photoresist, transferring the pattern on the mask to the photoresist, using the photoresist as a mask, removing the SiO2 second support layer and the second SiON layer directly above the fourth sacrificial layer in the Y direction, and removing the fourth sacrificial layer, thereby forming a second groove and a third groove, the unremoved second SiON layer forms a third SiON layer, and the unremoved SiO2 second support layer forms a SiO2 third support layer, so that the collector region located in the second groove and the third groove is partially suspended above the substrate, and the corners are rounded to form a structure with a cross-section racetrack shape, and then hydrogen annealing is performed at a temperature of 800° C. to 1200° C.; Step nine, epitaxially growing a base region around the collector region located in the second groove and the third groove; Step ten, removing the photoresist, depositing SiO2 in the second groove and the third groove, planarizing the device, and then removing part of the SiO2 on both sides of the SiO2 first insulating layer in the Y direction, thereby forming a fourth groove and a fifth groove, in which the collector region and the base region in the fourth groove and the fifth groove are partially suspended above the substrate and the SiO2 that is not removed and the SiO2 third supporting layer together form a fourth supporting layer; Step 11, epitaxially growing around the base region located in the fourth groove and the fifth groove to form an emitter region, removing the third SiON layer and then depositing SiO2 again, and planarizing the device by a CMP method, the SiO2 deposited in this step and the SiO2 not removed in step 10 together form a second insulating layer; Step 12: a high stress Si3N4 covering layer is deposited on the surface of the device obtained in step 11, a collector window, a base window and an emitter window are respectively etched on the surface of the Si3N4 covering layer, and polysilicon is deposited in each window to form a collector, a base and an emitter.

2. The method for preparing a heterojunction bipolar transistor with a GAA structure according to claim 1, characterized in that: The preparation method is implemented by using equipment compatible with the preparation process of the all-around gate field effect transistor.

3. The method for preparing a heterojunction bipolar transistor with a GAA structure according to claim 1, characterized in that: The base region is a compressively strained p-type SiGe, and forms a fully surrounding collector junction with the collector region.

4. The method for preparing a heterojunction bipolar transistor with a GAA structure according to claim 1, characterized in that: The emitter region is n-type Si, and forms a fully surrounded heterogeneous emitter junction with the base region.

5. The method for preparing a heterojunction bipolar transistor with a GAA structure according to claim 1, characterized in that: In step 4, the device is planarized using chemical mechanical polishing (CMP); In step six and step eight, the collector region is rounded by oxidation followed by wet etching, and the collector region is an n-type Si semiconductor nanosheet.

6. The method for preparing a heterojunction bipolar transistor with a GAA structure according to claim 1, characterized in that: In step seven, SiO2 is deposited by HDP CVD, and the device is planarized by chemical mechanical polishing (CMP).

7. A heterojunction bipolar transistor with a GAA structure, characterized in that: It is prepared by the preparation method according to any one of claims 1 to 6, comprising a Si substrate, a SiO2 second insulating layer, an n-type Si emitter region, a p-type SiGe base region, an n-type Si collector region, a Si3N4 stress layer, an emitter, a base and a collector; A polysilicon emitter is formed above the emitter region; a polysilicon base is formed above the base region; and a polysilicon collector is formed above the collector region; The Si3N4 stress layer covers the device surface, provides uniaxial stress, and improves carrier mobility.

8. The heterojunction bipolar transistor with a GAA structure as claimed in claim 7, characterized in that: The collector region is surrounded by the base region to form a Si / SiGe full-surround collector junction; At the same time, the base region is surrounded by the emitter region to form a Si / SiGe fully surrounding heterogeneous emitter junction.

9. The heterojunction bipolar transistor with a GAA structure as claimed in claim 7, characterized in that: The thickness of the n-type Si collector region is 10nm-100nm; The thickness of the p-type SiGe base region is 10nm-50nm; The thickness of the n-type Si emitter region is 10nm-100nm.

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