Thin film transistor, preparation method thereof, and display device

Abstract

Embodiments of the present invention provide a thin film transistor, a preparation method of the thin film transistor, and a display device, which relate to the field of semiconductor electronic devices. The thin film transistor and its preparation method sequentially arrange a gate electrode, a gate insulating layer, and a semiconductor layer on a substrate, then arrange a source electrode and a drain electrode on both sides of the semiconductor layer, and arrange a passivation layer covering the source electrode and the drain electrode on the semiconductor layer. Wherein, a first insulating interface layer is formed at the contact interface between the source electrode and the semiconductor layer, and a second insulating interface layer is formed at the contact interface between the drain electrode and the semiconductor layer. By arranging the first insulating interface layer and the second insulating interface layer, a Schottky barrier can be formed between the source-drain electrode and the semiconductor layer, thereby forming a Schottky barrier TFT. At the same time, there is no need to additionally deposit an insulating layer, so that the device has low cost and good reliability, and the saturation voltage can be greatly reduced by forming the Schottky barrier, thereby reducing the working energy consumption of the TFT.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor electronic devices, and more particularly, to a thin film transistor, a method for manufacturing the thin film transistor, and a display device. Background Art

[0002] In recent years, oxide semiconductor thin film transistors have been widely used because of their high mobility, good uniformity, and low-temperature preparation characteristics. Currently, in the mainstream oxide semiconductor thin film transistors, the contact between the source and drain electrodes and the semiconductor is mainly an ohmic contact. With the development of display technology, the power consumption requirements for display devices are becoming more and more stringent. Compared with ohmic contact TFTs, Schottky barrier TFTs can significantly reduce the saturation voltage, thereby reducing the working energy consumption of TFTs.

[0003] Currently, in practice, there is no good way to select suitable source and drain electrodes and deposition conditions to form Schottky barrier TFTs with good performance in terms of cost, reliability, and performance. Summary of the Invention

[0004] The objectives of the present invention include, for example, providing a thin film transistor, a method for manufacturing the thin film transistor, and a display device, which can form Schottky barrier TFTs, while having low cost, good reliability, and can significantly reduce the saturation voltage, thereby reducing the working energy consumption of TFTs.

[0005] Embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a thin film transistor, comprising:

[0007] a substrate;

[0008] a gate electrode disposed on the substrate;

[0009] a gate insulating layer disposed on the substrate and covering the gate electrode;

[0010] a semiconductor layer disposed on the gate insulating layer;

[0011] a source electrode and a drain electrode disposed on the gate insulating layer and on both sides of the semiconductor layer;

[0012] and a passivation layer disposed on the semiconductor layer and covering the source electrode and the drain electrode.

[0013] Wherein, a first insulating interface layer is formed at the contact interface between the source electrode and the semiconductor layer, so as to form a Schottky barrier between the source electrode and the semiconductor layer; a second insulating interface layer is formed between the drain electrode and the semiconductor layer, so as to form a Schottky barrier at the contact interface between the drain electrode and the semiconductor layer.

[0014] In an alternative embodiment, a highly conductive layer is formed at the contact interface between the passivation layer and the semiconductor layer. The source electrode and the drain electrode are respectively located on both sides of the highly conductive layer, and the highly conductive layer is used to improve the conductivity of the semiconductor layer.

[0015] In an alternative embodiment, the semiconductor layer is an indium-containing oxide having semiconductor properties.

[0016] In an alternative embodiment, the highly conductive layer contains the material indium.

[0017] In an alternative embodiment, the thickness of the highly conductive layer is 1 - 20 nm.

[0018] In an alternative embodiment, both the source electrode and the drain electrode are metal thin film layers, and the metal thin film layers are used to chemically react with the semiconductor layer.

[0019] In an alternative embodiment, the thickness of the metal thin film layer is 10 - 2000 nm.

[0020] In an alternative embodiment, both the first insulating interface layer and the second insulating interface layer are metal oxide layers, and the metal oxide layers are formed after annealing treatment.

[0021] In an alternative embodiment, the thickness of both the first insulating interface layer and the second insulating interface layer is 1 - 20 nm.

[0022] In a second aspect, the present invention provides a method for manufacturing a thin film transistor for manufacturing the thin film transistor according to any one of the foregoing embodiments. The manufacturing method includes:

[0023] Depositing and forming a gate electrode on a substrate;

[0024] Depositing and forming a gate insulating layer covering the gate electrode on the substrate;

[0025] Depositing and forming a semiconductor layer on the gate insulating layer;

[0026] Depositing and forming a source electrode and a drain electrode respectively located on both sides of the semiconductor layer on the gate insulating layer;

[0027] Depositing and forming a passivation layer covering the source electrode and the drain electrode on the semiconductor;

[0028] Performing an annealing treatment to form a first insulating interface layer at the contact interface between the source electrode and the semiconductor layer, and simultaneously form a second insulating interface layer between the drain electrode and the semiconductor layer;

[0029] Wherein, a Schottky barrier is formed at the contact interface between the source electrode and the semiconductor layer, and a Schottky barrier is formed at the contact interface between the drain electrode and the semiconductor layer.

[0030] In an alternative embodiment, the step of depositing a passivation layer on the semiconductor to cover the source and the drain includes:

[0031] Depositing an insulating film by magnetron sputtering to form the passivation layer;

[0032] Utilizing the bombardment effect of magnetron sputtering particles to form a highly conductive layer at the contact interface between the passivation layer and the semiconductor layer.

[0033] In a third aspect, the present invention provides a display device including the thin film transistor according to any one of the foregoing embodiments.

[0034] The beneficial effects of the embodiments of the present invention include, for example:

[0035] The thin film transistor, its manufacturing method and the display device provided by the embodiments of the present invention sequentially arrange a gate, a gate insulating layer and a semiconductor layer on a substrate, then arrange a source and a drain on both sides of the semiconductor layer, and arrange a passivation layer covering the source and the drain on the semiconductor layer. Wherein, a first insulating interface layer is formed at the contact interface between the source and the semiconductor layer, and a second insulating interface layer is formed at the contact interface between the drain and the semiconductor layer. By providing the first insulating interface layer and the second insulating interface layer, a Schottky barrier can be formed between the source-drain and the semiconductor layer, thereby forming a Schottky barrier TFT. At the same time, no additional insulating layer needs to be deposited, so that the device has low cost and good reliability, and the saturation voltage can be greatly reduced by forming the Schottky barrier, thereby reducing the working power consumption of the TFT. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic structural diagram of the thin film transistor provided by the present invention;

[0038] Figure 2 It is a step block diagram of the manufacturing method of the thin film transistor provided by the present invention;

[0039] Figure 3 It is an output characteristic curve diagram of the thin film transistor provided by the present invention.

[0040] Icon: 100 - thin film transistor; 110 - substrate; 120 - gate; 130 - gate insulating layer; 140 - semiconductor layer; 141 - highly conductive layer; 150 - source electrode; 151 - first insulating interface layer; 160 - drain electrode; 161 - second insulating interface layer; 170 - passivation layer. Detailed implementation manners

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0043] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0044] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the present invention is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention.

[0045] In addition, if terms such as "first", "second", etc. are only used for distinguishing descriptions, they cannot be understood as indicating or implying relative importance.

[0046] As disclosed in the background art, the existing oxide semiconductor thin film transistors generally adopt ohmic contact TFTs, which have a relatively high saturation voltage and high energy consumption. Research has shown that if Schottky barrier TFTs are used, the saturation voltage can be significantly reduced, thereby reducing the operating energy consumption of the TFTs. Currently, the preparation methods of Schottky barrier oxide semiconductor TFTs reported in the literature include using Pt as the source and drain electrodes and introducing oxygen during the deposition of Pt. However, Pt is a precious metal, and the material cost is high. At the same time, introducing oxygen during the deposition process will form oxides of Pt, resulting in an increase in the resistivity of Pt and a large signal delay, which is not conducive to use in display devices.

[0047] To solve the above problems, the present invention proposes a preparation method for a Schottky barrier oxide semiconductor thin film transistor with a bottom gate structure. The thin film transistor provided in this embodiment is a Schottky barrier oxide semiconductor thin film transistor with a low saturation voltage and high current output ability. By using an active metal material as the source and drain electrodes to chemically react with the oxide semiconductor, a Schottky barrier interface layer is formed. At the same time, the channel conductivity is improved by using a passivation layer, thereby preparing a Schottky barrier oxide semiconductor TFT with low power consumption and high current output ability. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0048] First Embodiment

[0049] Refer to Figure 1 , this embodiment provides a thin film transistor 100, which does not require additional deposition of an insulating layer, making the device cost low and reliable, and can significantly reduce the saturation voltage by forming a Schottky barrier, thereby reducing the operating energy consumption of the TFT.

[0050] A thin film transistor 100 provided in this embodiment includes a substrate 110, a gate electrode 120, a gate insulating layer 130, a semiconductor layer 140, a source electrode 150, a drain electrode 160, and a passivation layer 170. The gate electrode 120 is disposed on the substrate 110, the gate insulating layer 130 is disposed on the substrate 110 and covers the gate electrode 120, the semiconductor layer 140 is disposed on the gate insulating layer 130, the source electrode 150 and the drain electrode 160 are disposed on the gate insulating layer 130 and are located on both sides of the semiconductor layer 140, and the passivation layer 170 is disposed on the semiconductor layer 140 and covers the source electrode 150 and the drain electrode 160. Among them, a first insulating interface layer 151 is formed at the contact interface between the source electrode 150 and the semiconductor layer 140 to form a Schottky barrier between the source electrode 150 and the semiconductor layer 140; a second insulating interface layer 161 is formed at the contact interface between the drain electrode 160 and the semiconductor layer 140 to form a Schottky barrier at the contact interface between the drain electrode 160 and the semiconductor layer 140.

[0051] In this embodiment, the substrate 110 may be a glass substrate, the gate 120 is a conventional metal electrode, and the gate insulating layer 130 may be a thin film with insulating properties. Specifically, a molybdenum thin film may be deposited on the glass substrate by means of DC sputtering deposition, and the molybdenum thin film is patterned by wet etching to form the gate 120. Among them, the thickness of the gate 120 may be 300 nm. After the gate 120 is formed, a silicon oxide thin film with a thickness of 200 nm may be continuously deposited by plasma enhanced chemical vapor deposition as the gate insulating layer 130. The preparation method and structure of the gate 120 and the gate insulating layer 130 are the same as those of the bottom gate structure in the prior art, and will not be introduced in detail here.

[0052] In this embodiment, the semiconductor layer 140 and the gate 120 may adopt an alignment structure, and the semiconductor layer 140 is an oxide semiconductor thin film with semiconductor properties, preferably an indium-containing oxide thin film, for example, it may be an indium gallium zinc oxide thin film. Specifically, after the gate insulating layer 130 is formed, a 25-nm-thick indium gallium zinc oxide thin film is deposited as the semiconductor layer 140 by radio frequency magnetron sputtering at room temperature, patterned by wet etching, and then annealed in an air atmosphere at 400 °C for 60 minutes to form the semiconductor layer 140.

[0053] In this embodiment, after the semiconductor layer 140 is formed, the source electrode 150 and the drain electrode 160 may be prepared. The source electrode 150 and the drain electrode 160 are both metal thin film layers, and the metal thin film layers are used to chemically react with the semiconductor layer 140. Among them, the thickness of the metal thin film layer is 10 - 2000 nm, and the source electrode 150 and the drain electrode 160 may adopt metal thin films that can react with the oxide semiconductor material, for example, they may be metal thin films such as aluminum, hafnium, zirconium, and titanium. Specifically, after the semiconductor layer 140 is formed, a 200-nm-thick aluminum thin film is deposited by DC magnetron sputtering and patterned by wet etching to form the source-drain electrodes.

[0054] In this embodiment, after the source electrode 150 and the drain electrode 160 are formed, a passivation layer 170 may be further deposited. Specifically, the passivation layer 170 is an insulating thin film. A 100-nm-thick aluminum oxide may be deposited by radio frequency magnetron sputtering as the passivation layer 170.

[0055] In this embodiment, a highly conductive layer 141 is formed at the contact interface between the passivation layer 170 and the semiconductor layer 140. The source electrode 150 and the drain electrode 160 are respectively located on both sides of the highly conductive layer 141, and the highly conductive layer 141 is used to improve the conductivity of the semiconductor layer 140. Specifically, the highly conductive layer 141 contains indium. When the passivation layer 170 is deposited by radio frequency magnetron sputtering, since the semiconductor layer 140 contains In2O3, during the sputtering process of the passivation layer 170, various energetic particles such as Al2O3 and Ar will bombard the surface of the active layer, breaking the In-O bonds, and a highly conductive layer 141 rich in indium is formed at the interface between the passivation layer 170 and the semiconductor layer 140, improving the conductivity of the semiconductor layer 140.

[0056] In this embodiment, the thickness of the highly conductive layer 141 is 1 - 20 nm. Preferably, by controlling the radio frequency magnetron sputtering process, a highly conductive layer 141 with a thickness of about 10 nm can be formed to improve the conductivity of the semiconductor layer 140.

[0057] It should be noted that after the passivation layer 170 is formed, the device can be placed in an argon atmosphere at 300 °C and annealed for 60 minutes to cause a chemical reaction between the aluminum source electrode 150, drain electrode 160 and the semiconductor layer 140, forming a first insulating interface layer 151 and a second insulating interface layer 161, thereby manufacturing the thin film transistor 100 described in the present invention.

[0058] In this embodiment, both the first insulating interface layer 151 and the second insulating interface layer 161 are metal oxide layers, which are formed after the annealing treatment. In this embodiment, an aluminum thin film is used as the source and drain electrodes, directly reacting with the semiconductor layer 140 to form a Schottky barrier, simplifying the manufacturing process of the oxide semiconductor thin film transistor 100, thereby effectively improving the production efficiency and reducing the manufacturing cost.

[0059] In this embodiment, the thickness of both the first insulating interface layer 151 and the second insulating interface layer 161 is 1 - 20 nm. Preferably, the thickness of the first insulating interface layer 151 and the second insulating interface layer 161 can be controlled by controlling the annealing temperature and annealing time. For example, both the first insulating interface layer 151 and the second insulating interface layer 161 can be 10 nm.

[0060] See Figure 2 , this embodiment also provides a manufacturing method of the thin film transistor 100 for manufacturing the aforementioned thin film transistor 100, and this manufacturing method includes:

[0061] S1: Deposit and form the gate electrode 120 on the substrate 110.

[0062] Specifically, a substrate 110 can be provided, and one or more conductive thin films are deposited on the substrate 110 and patterned to form a gate 120. In actual preparation, a 300-nm molybdenum thin film can be deposited on a glass substrate by DC sputtering, and the molybdenum thin film is patterned by wet etching to form the gate 120.

[0063] S2: A gate insulating layer 130 covering the outside of the gate 120 is deposited on the substrate 110.

[0064] Specifically, one or more insulating thin films can be deposited as the gate insulating layer 130, and the gate insulating layer 130 can cover the outside of the gate 120. In actual preparation, a 200-nm thick silicon oxide thin film can be deposited by plasma enhanced chemical vapor deposition as the insulating layer.

[0065] S3: A semiconductor layer 140 is deposited on the gate insulating layer 130.

[0066] Specifically, one or more oxide semiconductor thin films are continuously deposited and patterned to form the semiconductor layer 140, and then annealed in an atmosphere such as air, oxygen, nitrogen or argon at 100 - 500 °C for 10 to 120 minutes. Of course, annealing treatment can also be not carried out here. In actual preparation, a 25-nm indium gallium zinc oxide thin film can be deposited as the semiconductor layer 140 by RF magnetron sputtering at room temperature, patterned by wet etching, and then annealed in an air atmosphere at 400 °C for 60 minutes to form the semiconductor layer 140.

[0067] S4: Source and drain electrodes 150 and 160 respectively located on both sides of the semiconductor layer 140 are deposited on the gate insulating layer 130.

[0068] Specifically, one or more conductive thin films are continuously deposited on the gate insulating layer 130 and the semiconductor layer 140 and patterned to form source-drain electrodes. In actual preparation, a 200-nm thick aluminum thin film can be deposited by DC magnetron sputtering and patterned by wet etching to form source-drain electrodes.

[0069] S5: A passivation layer 170 covering the source electrode 150 and the drain electrode 160 is deposited on the semiconductor.

[0070] Specifically, an insulating thin film is deposited by magnetron sputtering to form the passivation layer 170, and a highly conductive layer 141 is formed at the contact interface between the passivation layer 170 and the semiconductor layer 140 by using the bombardment effect of magnetron sputtered particles. Among them, the highly conductive layer 141 contains indium. In actual preparation, a 100-nm thick aluminum oxide can be deposited by RF magnetron sputtering as the passivation layer 170, and a highly conductive indium-rich layer 141 is formed between the aluminum oxide and the indium gallium zinc oxide thin film.

[0071] S6: Annealing treatment is performed to form a first insulating interface layer 151 at the contact interface between the source electrode 150 and the semiconductor layer 140, and simultaneously form a second insulating interface layer 161 between the drain electrode 160 and the semiconductor layer 140.

[0072] Specifically, in an atmosphere such as air, oxygen, nitrogen, or argon, annealing is carried out at 100 - 500 °C for 10 to 120 minutes to fabricate the thin film transistor 100 device of this embodiment. In actual preparation, annealing can be performed in an argon atmosphere at 300 °C for 60 minutes, causing a chemical reaction between the source electrode 150 and drain electrode 160 made of aluminum and the semiconductor layer 140 to form an insulating interface layer of aluminum oxide, that is, simultaneously forming the first insulating interface layer 151 and the second insulating interface layer 161, thereby fabricating the thin film transistor 100 described in this embodiment. Among them, a Schottky barrier is formed at the contact interface between the source electrode 150 and the semiconductor layer 140, and a Schottky barrier is formed at the contact interface between the drain electrode 160 and the semiconductor layer 140.

[0073] Since the semiconductor layer 140 of this embodiment contains In2O3, during the sputtering process of the passivation layer 170, various energetic particles such as Al2O3 and Ar will bombard the surface of the semiconductor layer 140, breaking the In - O bonds and forming a high - conductivity indium - rich layer 141 at the interface between the passivation layer 170 and the semiconductor layer 140, improving the conductivity of the semiconductor layer 140. At the same time, using Al as the source - drain electrode and directly reacting with the semiconductor layer 140 to form a Schottky barrier simplifies the manufacturing process of the oxide semiconductor thin film transistor 100, thereby effectively improving production efficiency and reducing manufacturing costs.

[0074] The output characteristic curve measured for the thin film transistor 100 prepared in this embodiment is as Figure 3 shown. When the gate electrode 120 voltage is 20 V, the saturation voltage is less than 3 V, and the output current is greater than 25 μA.

[0075] In summary, for the thin film transistor 100 and its manufacturing method provided in this embodiment, a gate electrode 120, a gate insulating layer 130, and a semiconductor layer 140 are sequentially disposed on a substrate 110. Then, a source electrode 150 and a drain electrode 160 are disposed on two sides of the semiconductor layer 140, and a passivation layer 170 covering the source electrode 150 and the drain electrode 160 is disposed on the semiconductor layer 140. Among them, a first insulating interface layer 151 is formed at a contact interface between the source electrode 150 and the semiconductor layer 140, a second insulating interface layer 161 is formed at a contact interface between the drain electrode 160 and the semiconductor layer 140, and a highly conductive layer 141 is further formed at a contact interface between the passivation layer 170 and the semiconductor layer 140. By providing the first insulating interface layer 151 and the second insulating interface layer 161, a Schottky barrier can be formed between the source-drain electrode 160 and the semiconductor layer 140, thereby forming a Schottky barrier TFT. At the same time, no additional insulating layer needs to be deposited, making the device cost low and reliable. And by forming the Schottky barrier, the saturation voltage can be greatly reduced, thereby reducing the working power consumption of the TFT. At the same time, the highly conductive layer 141 is used to improve the conductivity of the semiconductor layer 140, thereby manufacturing a Schottky barrier oxide semiconductor thin film transistor 100 with low power consumption and high current output capability.

[0076] Second Embodiment

[0077] This embodiment provides a display device, which includes a thin film transistor 100. The basic structure, principle, and technical effects of the thin film transistor 100 are the same as those of the first embodiment. For a brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding content in the first embodiment.

[0078] In this embodiment, the display device may include a substrate and a thin film transistor 100. Among them, a pixel circuit is further disposed on the substrate. The thin film transistor 100 can be used as a driving TFT in the pixel circuit. Since a Schottky barrier can be formed between the source-drain electrode and the semiconductor layer 140, the saturation voltage of the TFT can be greatly reduced, effectively reducing the working power consumption of the display device. Of course, the basic structure, principle, and technical effects of the display device here are the same as those of a conventional display panel. For a brief description, for parts not mentioned in this embodiment, reference may be made to existing display panels.

[0079] The above is only a specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A thin film transistor, characterized in that, Comprising: A substrate; A gate disposed on the substrate; A gate insulating layer disposed on the substrate and covering the gate; A semiconductor layer disposed on the gate insulating layer; A source electrode and a drain electrode disposed on the gate insulating layer and on both sides of the semiconductor layer; And a passivation layer disposed on the semiconductor layer and covering the source electrode and the drain electrode; Wherein, a first insulating interface layer is formed at the contact interface between the source electrode and the semiconductor layer, so as to form a Schottky barrier between the source electrode and the semiconductor layer; a second insulating interface layer is formed at the contact interface between the drain electrode and the semiconductor layer, so as to form a Schottky barrier at the contact interface between the drain electrode and the semiconductor layer; Both the source electrode and the drain electrode are metal thin film layers, and the metal thin film layer is used to chemically react with the semiconductor layer during annealing and form the first insulating interface layer and the second insulating interface layer; Wherein, the first insulating interface layer is directly formed by the reaction between the source electrode and the semiconductor layer, and the second insulating interface layer is directly formed by the reaction between the drain electrode and the semiconductor layer.

2. The thin film transistor according to claim 1, wherein A highly conductive layer is formed at the contact interface between the passivation layer and the semiconductor layer, the source electrode and the drain electrode are respectively located on both sides of the highly conductive layer, and the highly conductive layer is used to improve the conductivity of the semiconductor layer.

3. The thin film transistor according to claim 2, wherein, The semiconductor layer is an indium-containing oxide having semiconductor properties.

4. The thin film transistor according to claim 2, wherein The highly conductive layer contains the material indium.

5. The thin film transistor according to claim 4, characterized in that, The thickness of the highly conductive layer is 1 - 20 nm.

6. The thin film transistor according to claim 1, wherein The thickness of the metal thin film layer is 10 - 2000 nm.

7. The thin film transistor according to claim 2, wherein Both the first insulating interface layer and the second insulating interface layer are metal oxide layers, and the metal oxide layers are formed after annealing treatment.

8. The thin film transistor according to claim 1, characterized in that, The thickness of both the first insulating interface layer and the second insulating interface layer is 1 - 20 nm.

9. A method for fabricating a thin film transistor, for fabricating the thin film transistor according to any one of claims 1-8, characterized in that, The manufacturing method includes: Depositing and forming a gate on the substrate; Depositing and forming a gate insulating layer covering the gate on the substrate; Depositing and forming a semiconductor layer on the gate insulating layer; Depositing and forming a source electrode and a drain electrode respectively located on both sides of the semiconductor layer on the gate insulating layer; Depositing and forming a passivation layer covering the source electrode and the drain electrode on the semiconductor; Annealing treatment, so as to form a first insulating interface layer at the contact interface between the source electrode and the semiconductor layer, and at the same time form a second insulating interface layer between the drain electrode and the semiconductor layer; Wherein, a Schottky barrier is formed at the contact interface between the source electrode and the semiconductor layer, and a Schottky barrier is formed at the contact interface between the drain electrode and the semiconductor layer.

10. The manufacturing method of the thin film transistor according to claim 9, characterized in that, The step of depositing and forming a passivation layer covering the source electrode and the drain electrode on the semiconductor includes: Using magnetron sputtering to deposit an insulating film to form the passivation layer; Utilizing the bombardment effect of magnetron sputtering particles to form a highly conductive layer at the contact interface between the passivation layer and the semiconductor layer.

11. A display device, characterized in that, Including the thin film transistor according to any one of claims 1 - 8.

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