Overvoltage protection circuit and device

Abstract

The present invention provides an overvoltage protection circuit and device, the circuit comprising: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube and a level conversion circuit; when the voltage of the external signal end is higher than the carrying voltage of the target chip, the level conversion circuit outputs a preset voltage; there is a voltage difference between the preset voltage and the voltage of the external signal end, the fifth PMOS tube and the sixth PMOS tube are controlled to be turned on, and the second PMOS tube and the fourth PMOS tube are turned off, so as to realize overvoltage protection of the target chip. The circuit can realize overvoltage protection of the chip by only using a single type of high-voltage resistant PMOS tube, thereby reducing the dependence on the process of NMOS devices.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to an overvoltage protection circuit and device. Background Technology

[0002] During use, chips are often damaged due to improper operation or abnormal interface signals or power supply, which can cause overvoltage or overcurrent at the chip's I / O terminals. Therefore, in applications with extremely high reliability requirements, it is necessary to take measures to enable the chip to protect itself under abnormal conditions and avoid failure.

[0003] Circuits typically used for overvoltage protection at chip outputs employ a transmission gate structure composed of dual high-voltage PMOS and NMOS transistors plus dual high-voltage NMOS transistors. When an external signal experiences an overvoltage, the detection circuit generates a shutdown signal, closing the transmission gate and thus achieving overvoltage protection. Both the PMOS and NMOS transistors in this structure must meet high voltage withstand requirements. Specifically, the NMOS device must not only withstand high voltage but also be sufficiently isolated from the chip substrate; therefore, existing overvoltage protection circuits are highly dependent on the fabrication process of the NMOS device. Summary of the Invention

[0004] The purpose of this invention is to provide an overvoltage protection circuit and device that can achieve overvoltage protection of a chip using only a single type of high-voltage PMOS transistor, thereby reducing dependence on the process of NMOS devices.

[0005] In a first aspect, embodiments of the present invention provide an overvoltage protection circuit, wherein the circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a level conversion circuit; the source of the first PMOS transistor is connected to an external signal terminal of the target chip; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the gate of the first PMOS transistor is connected to the drain of the third PMOS transistor; the drain of the second PMOS transistor is connected to an internal signal terminal of the target chip; the gate of the second PMOS transistor is connected to the drain of the third PMOS transistor; the third PMOS transistor... The source of the OS transistor is connected to the drain of the fourth PMOS transistor; the gate of the third PMOS transistor is connected to the source of the sixth PMOS transistor; the gate of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor; the gates of the fifth PMOS transistor and the sixth PMOS transistor are connected to the level conversion circuit; when the voltage of the external signal terminal is higher than the bearing voltage of the target chip, the level conversion circuit outputs a preset voltage; the voltage difference between the preset voltage and the voltage of the external signal terminal controls the fifth and sixth PMOS transistors to conduct, and the second and fourth PMOS transistors to turn off, so as to realize the overvoltage protection of the target chip.

[0006] In conjunction with the first aspect, the present invention provides a first possible implementation of the first aspect, wherein the level conversion circuit includes: an NMOS transistor, a clamping diode, and a first resistor; the gate of the NMOS transistor is connected to an alarm circuit of an external device; the source of the NMOS transistor is grounded; the drain of the NMOS transistor is connected to the first resistor; the first resistor is connected to the anode of the clamping diode; the cathode of the clamping diode is connected to an external signal terminal; when the voltage of the external signal terminal is higher than the carrying voltage range of the target chip, the alarm circuit of the external device outputs a conduction signal of the NMOS transistor; the NMOS transistor is turned on, and the anode of the clamping diode outputs the preset voltage.

[0007] In conjunction with the first possible implementation of the first aspect, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the clamping diode is of the type of Zener diode.

[0008] In conjunction with the first possible implementation of the first aspect, the present invention provides a third possible implementation of the first aspect, wherein the level conversion circuit further includes: a second resistor; the second resistor is connected in parallel with the clamping diode; the second resistor is used to shunt the current to the clamping diode.

[0009] In conjunction with the third possible implementation of the first aspect, this embodiment of the invention provides a fourth possible implementation of the first aspect, wherein if the reverse breakdown voltage of the clamping diode is VB, the value of the preset voltage is the difference between the voltage of the external signal terminal and the reverse breakdown voltage.

[0010] In conjunction with the first aspect, this embodiment of the invention provides a fifth possible implementation of the first aspect, wherein the voltage carrying range of the target chip is the CMOS level range.

[0011] Secondly, embodiments of the present invention provide an overvoltage protection device, wherein the device includes any one of the overvoltage protection circuits in the first aspect to the fifth possible implementation of the first aspect; the device further includes: a negative pressure pump; a first pin of the negative pressure pump is connected to the source of the fourth PMOS transistor and the gate of the third PMOS transistor; a second pin of the negative pressure pump is grounded; the negative pressure pump is used to generate a negative potential when the target chip is working normally; the first PMOS transistor and the second PMOS transistor are turned on to transmit the CMOS level generated by the chip to the external signal terminal.

[0012] In conjunction with the second aspect, the present invention provides a first possible implementation of the second aspect, wherein the negative pressure pump is turned off when the voltage of the external signal terminal is higher than the bearing voltage of the target chip.

[0013] In conjunction with the second aspect, this embodiment of the invention provides a second possible implementation of the second aspect, wherein the negative pressure pump is turned off when the voltage of the external signal terminal is lower than the operating level of the target chip.

[0014] In conjunction with the second aspect, the present invention provides a third possible implementation of the second aspect, wherein the device further includes: a third resistor; one end of the negative pressure pump is connected to the gate of the third PMOS transistor through the third resistor; the third resistor is used to divide the gate voltage of the third PMOS transistor.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] The overvoltage protection circuit and device provided in this embodiment of the invention include: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a level conversion circuit; the source of the first PMOS transistor is connected to an external signal terminal of the target chip; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the gate of the first PMOS transistor is connected to the drain of the third PMOS transistor; the drain of the second PMOS transistor is connected to an internal signal terminal of the target chip; the gate of the second PMOS transistor is connected to the drain of the third PMOS transistor; the third PMOS transistor... The source of the fourth PMOS transistor is connected to its drain; the gate of the third PMOS transistor is connected to its source; the gate of the fourth PMOS transistor is connected to its source; the gates of the fifth and sixth PMOS transistors are connected to the level conversion circuit. When the voltage at the external signal terminal is higher than the load-bearing voltage of the target chip, the level conversion circuit outputs a preset voltage. A voltage difference exists between the preset voltage and the voltage at the external signal terminal, controlling the fifth and sixth PMOS transistors to conduct, and the second and fourth PMOS transistors to turn off, thereby achieving overvoltage protection for the target chip. This circuit can achieve overvoltage protection for the chip using only a single type of high-voltage PMOS transistor, thus reducing dependence on the NMOS device process.

[0017] Other features and advantages disclosed in this embodiment will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0018] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a conventional overvoltage protection circuit structure provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of an overvoltage protection circuit structure provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of a level conversion circuit structure provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of an overvoltage protection device provided in an embodiment of the present invention.

[0024] Icons: 101-First PMOS transistor; 102-Second PMOS transistor; 103-Third PMOS transistor; 104-Fourth PMOS transistor; 106-Level conversion circuit; 108-NMOS transistor; 107-Clamping diode; 110-First resistor; 105-Negative pressure pump. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Figure 1 This is a schematic diagram of a conventional overvoltage protection circuit structure provided in an embodiment of the present invention. Figure 1 As observed, existing circuits for overvoltage protection at chip outputs employ a transmission gate structure composed of dual high-voltage PMOS and NMOS plus dual high-voltage NMOS. When an external signal experiences an overvoltage, the detection circuit generates a shutdown signal, closing the transmission gate and thus achieving overvoltage protection. Both the PMOS and NMOS in this structure need to meet high voltage withstand requirements. Specifically, the NMOS device must not only withstand high voltage but also be sufficiently isolated from the chip substrate; therefore, existing overvoltage protection circuits are highly dependent on the fabrication process of the NMOS device.

[0027] Based on this, embodiments of the present invention provide an overvoltage protection circuit and device. This circuit can achieve overvoltage protection for the chip using only a single type of high-voltage PMOS transistor, thereby reducing dependence on the process technology of NMOS devices. To facilitate understanding of this embodiment, an overvoltage protection circuit disclosed in this invention will first be described in detail.

[0028] Example 1

[0029] Figure 2 This is a schematic diagram of an overvoltage protection circuit structure provided in an embodiment of the present invention. Figure 2 As seen, the circuit includes: a first PMOS transistor 101, a second PMOS transistor 102, a third PMOS transistor 103, a fourth PMOS transistor 104, a fifth PMOS transistor, a sixth PMOS transistor, and a level conversion circuit 106.

[0030] In this configuration, the source of the first PMOS transistor 101 is connected to the external signal terminal of the target chip; the drain of the first PMOS transistor 101 is connected to the source of the second PMOS transistor 102; the gate of the first PMOS transistor 101 is connected to the drain of the third PMOS transistor 103; the drain of the second PMOS transistor 102 is connected to the internal signal terminal of the target chip; the gate of the second PMOS transistor 102 is connected to the drain of the third PMOS transistor 103; the source of the third PMOS transistor 103 is connected to the drain of the fourth PMOS transistor 104; the gate of the third PMOS transistor 103 is connected to the source of the sixth PMOS transistor; the gate of the fourth PMOS transistor 104 is connected to the source of the sixth PMOS transistor; and the gates of the fifth and sixth PMOS transistors are connected to the level conversion circuit.

[0031] When the voltage at the external signal terminal is higher than the bearing voltage of the target chip, the level conversion circuit outputs a preset voltage; the preset voltage has a voltage difference with the voltage at the external signal terminal, which controls the fifth PMOS transistor and the sixth PMOS transistor to conduct, and the second PMOS transistor 102 and the fourth PMOS transistor 104 to turn off, so as to realize the overvoltage protection of the target chip.

[0032] Here, the voltage carrying range of the target chip is the CMOS level range.

[0033] Furthermore, the level conversion circuit 106 is represented as follows: Figure 2 The Level Shift module in [the context of the project].

[0034] In this embodiment, the first PMOS transistor 101, the second PMOS transistor 102, the third PMOS transistor 103, the fourth PMOS transistor 104, the fifth PMOS transistor, and the sixth PMOS transistor are all high-voltage PMOS transistors.

[0035] In one implementation, Figure 3 This is a schematic diagram of a level conversion circuit structure provided in an embodiment of the present invention. Figure 3 As can be seen, the level conversion circuit includes: NMOS transistor 108, clamping diode 107 and first resistor 110.

[0036] The gate of the NMOS transistor 108 is connected to the external alarm circuit; the source of the NMOS transistor 108 is grounded; the drain of the NMOS transistor 108 is connected to the first resistor 110; the first resistor 110 is connected to the positive terminal of the clamping diode; the negative terminal of the clamping diode 107 is connected to the external signal terminal.

[0037] When the voltage at the external signal terminal is higher than the carrying voltage range of the target chip, the alarm circuit of the peripheral device outputs the conduction signal of the NMOS transistor 108; when the NMOS transistor 108 is turned on, the positive terminal of the clamping diode 107 outputs the preset voltage.

[0038] The level conversion circuit further includes a second resistor R3; the second resistor is connected in parallel with the clamping diode; the second resistor R3 is used to shunt the current to the clamping diode.

[0039] In one embodiment, the clamping diode is a Zener diode.

[0040] In another embodiment, if the reverse breakdown voltage of the clamping diode is VB, the value of the preset voltage is the difference between the voltage of the external signal terminal and the reverse breakdown voltage.

[0041] In actual operation, the level shift module receives alarm signals from the peripheral alarm circuit and converts these signals into a control signal that is lower than the target chip's external signal terminal by one Zener reverse breakdown voltage VB to activate the circuit. Figure 2 The fifth and sixth PMOS transistors in the circuit. When the fifth and sixth PMOS transistors are turned on... Figure 2 The positions of points G1 and G2 will change simultaneously following point A, therefore Figure 2 The second and fourth PMOS transistors in the chip will be turned off, isolating the high voltage signal at the external signal terminal of the target chip from the internal signal terminal of the target chip, thus achieving positive voltage protection.

[0042] The overvoltage protection circuit provided in this embodiment of the invention includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a level conversion circuit; the source of the first PMOS transistor is connected to an external signal terminal of the target chip; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the gate of the first PMOS transistor is connected to the drain of the third PMOS transistor; the drain of the second PMOS transistor is connected to an internal signal terminal of the target chip; the gate of the second PMOS transistor is connected to the drain of the third PMOS transistor; the source of the third PMOS transistor... The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor; the gate of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor; the gates of the fifth and sixth PMOS transistors are connected to the level conversion circuit. When the voltage at the external signal terminal is higher than the load-bearing voltage of the target chip, the level conversion circuit outputs a preset voltage. A voltage difference exists between the preset voltage and the voltage at the external signal terminal, controlling the fifth and sixth PMOS transistors to conduct, and the second and fourth PMOS transistors to turn off, thereby achieving overvoltage protection for the target chip. This circuit can achieve overvoltage protection for the chip using only a single type of high-voltage PMOS transistor, thus reducing dependence on the NMOS device process.

[0043] Example 2

[0044] exist Figure 2 Based on the overvoltage protection circuit diagram provided in the embodiment of the present invention, the embodiment of the present invention also provides an overvoltage protection device. Figure 4 This is a schematic diagram of an overvoltage protection device provided in an embodiment of the present invention.

[0045] Depend on Figure 4 As seen, the device includes: the overvoltage protection circuit in Embodiment 1; the overvoltage protection device also includes: a negative pressure pump 105.

[0046] The first pin of the negative pressure pump is connected to the source of the fourth PMOS transistor and the gate of the third PMOS transistor; the 105 pin of the negative pressure pump is grounded.

[0047] When the target chip is working normally, the negative pressure pump 105 generates a negative potential; the first PMOS transistor and the second PMOS transistor are turned on, transmitting the CMOS level generated by the chip to the external signal terminal.

[0048] In one embodiment, the negative pressure pump is turned off 105 when the voltage of the external signal terminal is higher than the bearing voltage of the target chip.

[0049] In another implementation, the negative pressure pump is turned off when the voltage at the external signal terminal is lower than the operating level of the target chip 105.

[0050] Furthermore, the device also includes a third resistor R1.

[0051] One end of the negative pressure pump is connected to the gate of the third PMOS transistor through the third resistor R1; the third resistor R1 is used to divide the gate voltage of the third PMOS transistor 103.

[0052] The overvoltage protection device provided in this embodiment of the invention has the same technical features as the overvoltage protection circuit provided in the above embodiments, and therefore can solve the same technical problems and achieve the same technical effects. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0053] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0054] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0055] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0056] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0057] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0058] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An overvoltage protection circuit, characterized in that: The circuit comprises: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube and a level conversion circuit; The source of the first PMOS tube is connected to the external signal terminal of the target chip; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the gate of the first PMOS tube is connected to the drain of the third PMOS tube; The drain of the second PMOS tube is connected to the internal signal terminal of the target chip; the gate of the second PMOS tube is connected to the drain of the third PMOS tube; The source of the third PMOS tube is connected to the drain of the fourth PMOS tube; the gate of the third PMOS tube is connected to the source of the sixth PMOS tube; The gate of the fourth PMOS tube is connected to the source of the sixth PMOS tube; The gate of the fifth PMOS tube and the gate of the sixth PMOS tube are connected to the level conversion circuit; the drain of the fifth PMOS tube is connected to the gate of the first PMOS tube and the gate of the second PMOS tube; the source of the fifth PMOS tube is connected to the drain of the first PMOS tube and the source of the second PMOS tube; the drain of the sixth PMOS tube is connected to the source of the third PMOS tube and the drain of the fourth PMOS tube; When the voltage of the external signal terminal is higher than the carrying voltage of the target chip, the level conversion circuit outputs a preset voltage; there is a voltage difference between the preset voltage and the voltage of the external signal terminal, and the fifth PMOS tube and the sixth PMOS tube are controlled to be turned on, and the second PMOS tube and the fourth PMOS tube are turned off, so as to realize overvoltage protection of the target chip; wherein the level conversion circuit includes: an NMOS tube, a clamping diode and a first resistor; The gate of the NMOS tube is connected to the external alarm circuit; the source of the NMOS tube is grounded; the drain of the NMOS tube is connected to the first resistor; the first resistor is connected to the positive electrode of the clamping diode; the negative electrode of the clamping diode is connected to the external signal terminal; When the voltage of the external signal terminal is higher than the carrying voltage range of the target chip, the alarm circuit of the peripheral device outputs a conduction signal of the NMOS tube; the NMOS tube is turned on, and the anode of the clamping diode outputs the preset voltage.

2. The overvoltage protection circuit according to claim 1, characterized in that: The type of the clamping diode is a Zener diode.

3. The overvoltage protection circuit according to claim 1, characterized in that: The level conversion circuit further includes: a second resistor; The second resistor is connected in parallel with the clamping diode; the second resistor is used to shunt the clamping diode.

4. The overvoltage protection circuit according to claim 3, characterized in that: If the reverse breakdown voltage of the clamping diode is VB, the value of the preset voltage is the difference between the voltage of the external signal terminal and the reverse breakdown voltage.

5. The overvoltage protection circuit according to claim 1, characterized in that: The carrying voltage range of the target chip is a CMOS level range.

6. An overvoltage protection device, characterized in that: The device comprises the overvoltage protection circuit according to any one of claims 1 to 5; the device further comprises: a negative pressure pump; The first pin of the negative pressure pump is connected to the source of the fourth PMOS tube and the gate of the third PMOS tube; the second pin of the negative pressure pump is grounded; The negative pressure pump is used to generate a negative potential when the target chip is working normally; the first PMOS tube and the second PMOS tube are turned on to transmit the CMOS level generated by the chip to the external signal terminal.

7. The overvoltage protection device according to claim 6, characterized in that: When the voltage of the external signal terminal is higher than the carrying voltage of the target chip, the negative pressure pump is turned off.

8. The overvoltage protection device according to claim 6, characterized in that: When the voltage of the external signal terminal is lower than the working level of the target chip, the negative pressure pump is turned off.

9. The overvoltage protection device according to claim 6, characterized in that: The device further comprises: a third resistor; One end of the negative pressure pump is connected to the gate of the third PMOS tube through the third resistor; the third resistor is used to divide the gate voltage of the third PMOS tube.

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