Method and apparatus for voltage regulation using a pre-charge rail with predictive charging

Abstract

Generally disclosed is a voltage regulator circuit for a voltage rail using predictive pre - charge. For example, the voltage regulator circuit can include a main switching regulator configured to provide a target voltage, the main switching regulator having a first voltage node; a pre - charge switching regulator configured to provide a pre - charge voltage, the pre - charge switching regulator having a second voltage node, the pre - charge voltage being based on a difference between the target voltage and the next target voltage to be provided by the main switching regulator; and a pre - charge switching circuit configured to selectively couple the second voltage node to an output voltage node based on a transition from the target voltage to the next target voltage.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 553,035, filed on August 27, 2019, entitled "METHOD AND APPARATUSES FOR VOLTAGE REGULATION USING PRECHARGE RAILS", the entire content of which is incorporated herein by reference. FIELD OF THE DISCLOSURE

[0003] Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly to voltage regulator circuits. BACKGROUND OF THE DISCLOSURE

[0004] A wireless communication network may include multiple base stations that may support communication for multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. The base station may transmit data and control information to the mobile station on the downlink, and / or may receive data and control information from the mobile station on the uplink. The base station and / or the mobile station may include one or more power amplifiers (PAs) for amplifying signals for transmission.

[0005] To improve the power efficiency of a mobile station, average power tracking (APT) may be used to regulate the supply voltage to a discrete voltage for one or more PAs based on the output power level of the amplified signal to be transmitted during a transmission period. The supply voltage may be provided by a voltage regulator capable of regulating the output voltage to a discrete voltage to be supplied to one or more PAs. However, there is a transient delay in changing the output voltage between discrete voltages. Depending on the amount of the transient delay, there may not be enough time to adequately regulate the discrete voltage to a different value for the next transmission period. Therefore, it would be beneficial to find a solution to reduce the transient delay when changing between discrete voltages. SUMMARY OF THE DISCLOSURE

[0006] Certain aspects of the present disclosure generally relate to improving the output voltage response of an adjustable voltage regulator using precharge rails.

[0007] Certain aspects of the present disclosure provide a voltage regulation circuit. The voltage regulation circuit generally includes a main switching regulator configured to provide a target voltage, the main switching regulator having a first voltage node; a pre-charge switching regulator configured to provide a pre-charge voltage, the pre-charge switching regulator having a second voltage node, the pre-charge voltage being based on a difference between the target voltage and a next target voltage to be provided by the main switching regulator; and a pre-charge switching circuit configured to selectively couple an output voltage node of the pre-charge switching regulator to an output voltage node of the main switching regulator based on a transition from the target voltage to the next target voltage.

[0008] Certain aspects of the present disclosure provide a method for regulating voltage using a pre-charge switching regulator. The method generally includes determining a next target output voltage to be supplied by a main switching regulator; charging a capacitor coupled to an output of the pre-charge switching regulator to a pre-charge voltage level, the pre-charge voltage level being based on a current target output voltage supplied by the main switching regulator and the next target output voltage; and selectively coupling the output of the pre-charge switching regulator to the output of the main switching regulator based on a transition from the current target output voltage to the next target output voltage.

[0009] Certain aspects of the present disclosure provide a voltage regulation circuit. The voltage regulation circuit generally includes: a first switching regulator configured to provide a first target voltage to an output voltage node; an output inductor having a first terminal coupled to an output of the first switching regulator and a second terminal coupled to the output voltage node; a second switching regulator configured to charge a pre-charge output capacitor to a pre-charge voltage level, the pre-charge voltage level being based on a difference between the first target voltage and a second target voltage to be provided by the first switching regulator; and a pre-charge switching circuit configured to selectively couple the charged pre-charge output capacitor to the output voltage node based on a transition from the first target voltage to the second target voltage.

[0010] Certain aspects of the present disclosure provide an apparatus for providing voltage regulation. The apparatus generally includes means for determining a next target output voltage to be supplied by a main switching regulator; means for storing charge; means for charging the means for storing charge to a pre-charge voltage level via an output of the pre-charge switching regulator, the pre-charge voltage level being based on a current target output voltage supplied by the main switching regulator and the next target output voltage; and means for selectively coupling the means for storing to the output of the main switching regulator based on a transition from the current target output voltage to the next target output voltage. Description of the Drawings

[0011] To understand the above features of the present disclosure in detail, a more specific description of the above briefly summarized content can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate certain typical aspects of the present disclosure and should not be considered as limiting its scope, as the description may admit other equally valid aspects.

[0012] Figure 1 is a diagram of an example wireless communication network in accordance with certain aspects of the present disclosure.

[0013] Figure 2 is a block diagram of an example access point (AP) and an example user terminal in accordance with certain aspects of the present disclosure.

[0014] Figure 3 is a block diagram of an example transceiver front end in accordance with certain aspects of the present disclosure.

[0015] Figure 4 is a block diagram of a voltage regulation circuit using a precharge rail in accordance with certain aspects of the present disclosure.

[0016] Figure 5 is a block diagram of an average power tracking (APT) voltage regulator circuit in accordance with certain aspects of the present disclosure.

[0017] Figure 6 is an APT voltage regulator circuit using a power multiplexer in accordance with certain aspects of the present disclosure Figure 5 block diagram.

[0018] Figure 7 is a block diagram of an APT voltage regulator circuit using a switching regulator output switch in accordance with certain aspects of the present disclosure.

[0019] Figure 8 is a block diagram of an APT voltage regulator circuit using two adjustable precharge voltage circuits in accordance with certain aspects of the present disclosure.

[0020] Figure 9 is a block diagram of an APT voltage regulator circuit using two switching regulators in accordance with certain aspects of the present disclosure.

[0021] Figure 10 is a block diagram of an APT voltage regulator circuit 1000 using two switching regulators and a capacitor switching network in accordance with certain aspects of the present disclosure.

[0022] Figure 11 is an example operation of a voltage regulation method using a precharge voltage rail in accordance with certain aspects of the present disclosure.

[0023] Figure 12is a circuit diagram of an example voltage regulation circuit for a pre - charge voltage rail using predictive charging according to certain aspects of the present disclosure.

[0024] Figure 13 is according to certain aspects of the present disclosure Figure 12 example timing diagram of a voltage regulation circuit.

[0025] Figure 14 is a block diagram of an example user terminal architecture that implements a voltage regulation circuit using a pre - charge voltage rail with predictive charging according to certain aspects of the present disclosure.

[0026] Figure 15 is an example operation of a voltage regulation method for a pre - charge voltage rail using predictive charging according to certain aspects of the present disclosure. Detailed Description

[0027] In the following, various aspects of the present disclosure are described more fully with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether implemented independently of any other aspect of the present disclosure or in combination with any other aspect of the present disclosure. For example, any number of the aspects set forth herein may be used to implement a device or practice a method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functions, or combinations of structures and functions in addition to or other than the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0028] As used herein, the term "exemplary" is used to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" need not be construed as superior or preferred to other aspects.

[0029] As used herein, the term "connected to" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected to" may also be used herein to mean that element A and B are electrically connected using a wire, trace, or other conductive material (and any components electrically connected between them).

[0030] Wireless System Example

[0031] Figure 1A wireless communication system 100 having an access point 110 and user terminals 120 is shown. Aspects of the present disclosure may be practiced in the wireless communication system 100. For simplicity, Figure 1 only one access point 110 is shown. An access point (AP) is generally a fixed station that communicates with user terminals and may also be referred to as a base station (BS), evolved Node B (eNB), or some other term. A user terminal (UT) may be fixed or mobile and may also be referred to as a mobile station (MS), access terminal, user equipment (UE), station (STA), client, wireless device, or some other term. A user terminal may be a wireless device such as a cellular phone, personal digital assistant (PDA), handheld device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0032] The access point 110 may communicate with one or more user terminals 120 on the downlink and uplink at any given time. The downlink (i.e., forward link) is the communication link from the access point to the user terminal, and the uplink (i.e., reverse link) is the communication link from the user terminal to the access point. A user terminal may also communicate peer-to-peer with another user terminal. The system controller 130 is coupled to the access point and provides coordination and control for the access point.

[0033] The wireless communication system 100 employs multiple transmit antennas and multiple receive antennas for data transmission on the downlink and uplink. The access point 110 may be equipped with N ap antennas to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. A group of N u selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and / or receives user-specific data from the access point. Generally, each selected user terminal may be equipped with one or more antennas (i.e., N ut ≥1). The N u selected user terminals may have the same or different numbers of antennas.

[0034] The wireless communication system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication system 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional cost can be supported). In certain aspects of the present disclosure, the access point 110 and / or user terminal 120 may include at least one voltage regulator to regulate the supply voltage of one or more power amplifiers (PAs), as described in more detail herein.

[0035] Figure 2 shows a block diagram of an access point 110 and two user terminals 120m and 120x in a wireless communication system 100. The access point 110 is equipped with N ap antennas 224a through 224ap. The user terminal 120m is equipped with N ut,m antennas 252ma through 252mu, and the user terminal 120x is equipped with N ut,x antennas 252xa through 252xu. The access point 110 is a transmission entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmission entity for the uplink and a receiving entity for the downlink. As used herein, a "transmission entity" is an independently operating device or equipment capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operating device or equipment capable of receiving data via a frequency channel. In the following description, the subscript "dn" represents the downlink, the subscript "up" represents the uplink, N up user terminals are selected for simultaneous transmission on the uplink, N dn user terminals are selected for simultaneous transmission on the downlink, N up may be equal to or may not be equal to N dn , and N up and N dn may be a static value or may vary for each scheduling interval. Beam control or some other spatial processing technique may be used at the access point and the user terminals.

[0036] On the uplink, at each user terminal 120 selected for uplink transmission, the TX data processor 288 receives traffic data from the data source 286 and control data from the controller 280. The TX data processor 288 processes (e.g., encodes, interleaves, and modulates) the traffic data {d up} of the user terminal based on the coding modulation scheme associated with the rate selected for the user terminal, and provides a data symbol stream {s ut,m} for one of the N up antennas. The transceiver front end (TX / RX) 254 (also referred to as the radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and upconverts) the corresponding symbol stream to generate an uplink signal. For example, the transceiver front end 254 may also route the uplink signal to one of the N ut,m antennas via an RF switch to achieve transmit diversity. The controller 280 may control the routing within the transceiver front end 254. The memory 282 may store data and program code for the user terminal 120 and may interface with the controller 280.

[0037] Nup A user terminal 120 can be scheduled for simultaneous transmission on the uplink. Each of these user terminals transmits a set of processed symbol streams on the uplink to the access point.

[0038] At the access point 110, N ap antennas 224a to 224ap receive uplink signals from all N up user terminals transmitting on the uplink. For receive diversity, the transceiver front end 222 can select a signal received from one of the antennas 224 for processing. Signals received from multiple antennas 224 can be combined to achieve enhanced receive diversity. The transceiver front end 222 of the access point also performs processing complementary to that performed by the transceiver front end 254 of the user terminal, and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is an estimate of the data symbol stream {s up} transmitted by the user terminal. The RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream according to the rate for the stream to obtain decoded data. The decoded data of each user terminal can be provided to the data sink 244 for storage and / or provided to the controller 230 for further processing. The transceiver front end (TX / RX) 222 of the access point 110 and / or the transceiver front end 254 of the user terminal 120 can include at least one PA, as described in more detail herein.

[0039] On the downlink, at the access point 110, the TX data processor 210 receives traffic data for N dn user terminals scheduled for downlink transmission from the data source 208, receives control data from the controller 230, and may receive other data from the scheduler 234. Various types of data can be transmitted on different transmission channels. The TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data of each user terminal based on the rate selected for each user terminal. The TX data processor 210 can provide a downlink data symbol stream to be transmitted from one of the N dn antennas for one or more of the N ap user terminals. The transceiver front end 222 receives and processes (e.g., converts to analog, amplifies, filters, and upconverts) the symbol stream to generate a downlink signal. For example, the transceiver front end 222 can also route the downlink signal to one or more of the N ap antennas 224 via an RF switch to achieve transmit diversity. The controller 230 can control the routing within the transceiver front end 222. The memory 232 can store data and program code for the access point 110 and can interface with the controller 230.

[0040] At each user terminal 120, N ut,m antennas 252 receive downlink signals from the access point 110. For receive diversity at the user terminal 120, the transceiver front-end 254 may select a signal received from one of the antennas 252 for processing. Signals received from multiple antennas 252 may be combined to achieve enhanced receive diversity. The transceiver front-end 254 of the user terminal also performs processing complementary to that performed by the transceiver front-end 222 of the access point and provides a recovered downlink data symbol stream. The RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

[0041] Figure 3 is a block diagram of an exemplary transceiver front-end 300, such as Figure 2 the transceiver front-ends 222, 254 in

[0042] which aspects of the present disclosure may be practiced. The transceiver front-end 300 includes a transmit (TX) path 302 (also referred to as a transmit chain) for transmitting signals via one or more antennas and a receive (RX) path 304 (also referred to as a receive chain) for receiving signals via the antenna. When the TX path 302 and the RX path 304 share the antenna 303, these paths may be connected to the antenna via an interface 306, which may include any of a variety of suitable RF devices, such as a duplexer, a switch, a diplexer, etc.

[0043] The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, mixer 324, and BBF 326 may be included in a radio frequency integrated circuit (RFIC), which may be the same as or different from the RFIC including the TX path components. The RF signal received via the antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., down-convert). The baseband signal output by the mixer 324 may be filtered by the BBF 326 before being converted to a digital I or Q signal by an analog-to-digital converter (ADC) 328 for digital signal processing. In certain aspects of the present disclosure, the PA 316 may implement average power tracking (APT) by regulating the supply voltage of the PA 316 using a voltage regulator having one or more pre-charge rails, as described in more detail herein.

[0044] Although it is desirable for the output of the LO to remain stable in frequency, tuning the LO to different frequencies typically requires the use of a variable frequency oscillator, which involves a trade-off between stability and tunability. Modern systems may employ a frequency synthesizer with a voltage controlled oscillator (VCO) to generate a stable and tunable LO with a specific tuning range. Thus, the transmit LO frequency may be generated by the TX frequency synthesizer 318 and may be buffered or amplified by the amplifier 320 before being mixed with the baseband signal in the mixer 312. Similarly, the receive LO frequency may be generated by the RX frequency synthesizer 330 and may be buffered or amplified by the amplifier 332 before being mixed with the RF signal in the mixer 324.

[0045] Although Figures 1 - 3 A wireless communication system in which certain aspects of the present disclosure may be implemented is provided as an example application for ease of understanding, but certain aspects provided herein may be applied to amplify signals in any one of a variety of other suitable systems.

[0046] Example voltage regulator circuit

[0047] For a voltage regulator with an adjustable voltage output, stepping between voltages within an operating voltage range (e.g., 0.4V to 2V) requires a certain amount of time. Depending on the requirements of the application, the voltage regulator may have to step between the minimum and maximum of the operating voltage range over a period of time. Since applications may continuously require more stringent requirements on the time for output voltage changes, it would be beneficial to reduce the time required for the voltage regulator to step between output voltages.

[0048] Now refer to Figure 4 ,Figure 4 It is a block diagram of a voltage regulation circuit 400 using a pre-charge rail according to certain aspects of the present disclosure. The voltage regulation circuit includes a voltage regulator 402 configured to regulate the voltage of an output voltage (Vout) provided at the output of the voltage regulator 402. The voltage regulator 402 can be configured according to various voltage regulator topologies. For example, the voltage regulator can include a linear regulator (e.g., a low dropout (LDO) regulator) or a switching regulator (e.g., buck, buck-boost, boost).

[0049] The voltage regulation circuit 400 further includes n pre-charge voltage circuits 404, each of the pre-charge voltage circuits 404 having an output selectively coupled to the output of the voltage regulator 402. The pre-charge voltage circuit can be referred to as a pre-charger. Each of the pre-charge voltage circuits 404 is configured to store a voltage corresponding to one of the output voltage levels, and the voltage regulator 402 is configured to provide the output voltage level as the output voltage Vout. In one implementation, the output voltage provided by the voltage regulator 402 to the pre-charge voltage circuit 404 is used to store the voltage. In another implementation, each of the pre-charge voltage circuits 404 includes a voltage regulator configured to provide the voltage to be stored.

[0050] During a change from a current target output voltage level to a next target voltage level, a precharge voltage circuit 404 having a stored voltage substantially corresponding to the next target voltage level (e.g., within a voltage tolerance or including a voltage offset) is coupled to the output of a voltage regulator 402. In one implementation, the offset is based on the difference between the current target output voltage and the next target output voltage. By coupling the precharge voltage circuit 404, the output voltage is pulled to the voltage stored in the precharge voltage circuit 404, which can achieve a faster output voltage transition compared to a voltage regulator without a precharge voltage circuit. In one implementation, the voltage regulator 402 can have one or more feedback comparators (not shown), each feedback comparator being set to an available target output voltage of the voltage regulator 402. When the voltage regulator 402 changes to the next target output voltage, the feedback comparator set to the corresponding voltage can be coupled into a feedback loop (not shown) for regulating the output voltage of the voltage regulator 402. By using one or more feedback comparators, the amount of time it takes for the voltage regulator 402 to regulate the output voltage to the next target voltage level can be improved. In one implementation, multiple precharge voltage circuits 404 can be located together on a voltage hub (not shown) and connected to multiple voltage regulators 402 that can be located away from the voltage hub. Each of the precharge voltage circuits 404 can be configured to be selectively coupled to the output of one of the voltage regulators 402 via the voltage hub. In one implementation, the voltage hub further includes multiple switches configured to couple the precharge voltage circuit 404 to the output of the voltage hub, the output of the voltage hub being coupled to one of the multiple voltage regulators 402. An exemplary benefit of the voltage hub is that each of the voltage regulators 402 can independently supply current to a load (e.g., a power amplifier supply line) by selectively coupling different precharge voltage circuits 404 of the voltage hub to the load.

[0051] Exemplary average power tracking regulator circuit

[0052] Power amplifiers (PAs) for standards such as 5G millimeter wave (mmWave) may need to implement average power tracking (APT). APT adjusts the voltage supplied to the power amplifier according to the output power level of the signal to be transmitted to improve power efficiency while maintaining the linearity of the power amplifier. In 5G mmWave, the output power level can be adjusted every 9.8 microseconds. In some implementations, to support APT in 5G mmWave, the voltage regulator may need to step from a first voltage level (e.g., 0.8V) to a second voltage level (e.g., 2V) within a required time period (e.g., 100 nanoseconds). This required time period can be based on the operational requirements of the desired steady-state time within a portion of the symbol to be transmitted (e.g., cyclic prefix). Certain aspects of the present disclosure provide a voltage regulation circuit that allows for output voltage changes within increasingly demanding time periods.

[0053] Reference Figure 5 , Figure 5 FIG. is a block diagram of an average power tracking (APT) voltage regulator circuit 500 according to certain aspects of the present disclosure. The APT voltage regulator circuit 500 includes a switching regulator 502. In one implementation, the switching regulator 502 includes a buck converter configured to step down an input voltage to a target output voltage at an output voltage node 503. The switching regulator 502 also includes an output inductor 504 coupled to a first terminal of an output capacitor 506. A second terminal of the output capacitor 506 is coupled to a reference potential (e.g., ground). The output voltage node 503 is also coupled to a voltage supply line of a power amplifier array 508, which includes one or more power amplifiers 510 configured to amplify signals for transmission. In one implementation, the power amplifier array 508 includes four power amplifiers 510a-d.

[0054] The APT voltage regulator circuit 500 further includes a plurality of pre-charge voltage circuits 404. In one implementation, each of the pre-charge voltage circuits 404 includes a pre-charge voltage regulator 511, a capacitor 512 coupled between the output of the voltage regulator 511 and ground, and a switch 514. The pre-charge voltage regulator 511 may include a linear regulator (e.g., LDO) or a switching regulator (e.g., buck converter). Each of the pre-charge voltage circuits 404 is configured to store a certain amount of voltage (i.e., voltage level) by charging the capacitor 512. For example, each of the pre-charge voltage circuits 404 may store a different amount of voltage corresponding to the available voltage output of the switching regulator 502. The amount of voltage stored by each pre-charge voltage circuit may include a fixed amount of voltage, or the pre-charge voltage circuits 404 may be configured to adjust the amount of voltage to be stored between different amounts of voltage. As another example, the pre-charge voltage circuit 404 may store an amount of charge corresponding to a voltage based on a change from the current target voltage output level of the switching regulator 502 to the next target voltage level of the switching regulator 502. In such an example, the amount of charge stored by the pre-charge voltage circuit may correspond to a voltage value different from the next target voltage level (i.e., a higher or lower amount of voltage).

[0055] The switch 514 is configured to selectively couple / de-couple the corresponding pre-charge voltage circuit 404 from the output voltage node 503. The pre-charge voltage circuit 404 coupled to the output has a voltage level stored therein that substantially corresponds to the set output voltage amount of the switching regulator 502. For example, when the switching regulator 502 has a set output voltage of 0.8V, the pre-charge voltage circuit 404 configured to store 0.8V is coupled to the output voltage node 503, while the remaining pre-charge voltage circuits 404 are de-coupled from the output voltage node 503. When the switching regulator 502 steps to the next target output voltage (e.g., 2V), the pre-charge voltage circuit 404 currently coupled to the output voltage node 503 is de-coupled, and the pre-charge voltage circuit configured to store a voltage level substantially corresponding to the next target output voltage (e.g., 2V) is coupled to the output voltage node 503. To avoid possible through-current through the pre-charge voltage circuit due to voltage mismatch, the pre-charge voltage circuit 404 is de-coupled from the output voltage node 503 before coupling the pre-charge voltage circuit 404 corresponding to the next target output voltage. By coupling the pre-charge voltage circuit 404 storing the amount of voltage corresponding to the target output voltage to the output voltage node 503, the output voltage rises to the target output voltage faster compared to using only the switching regulator 502.

[0056] It should be noted that the speed at which a switching regulator can change between voltage levels can depend on the capacitance of the output of the switching regulator (i.e., the body capacitance). A smaller body capacitance may result in a fast switching time between voltage levels. However, the transient response of the switching regulator in response to a load attack may be negatively affected because the charging current available to compensate for the load attack decreases as the capacitance decreases. In one implementation, the capacitor 512 of the precharge voltage circuit 404 can be selected to include a capacitance value that constitutes most of the body capacitance of the APT voltage regulator circuit 500 when coupled to the output voltage node 503. Additionally, the output capacitor 506 can be selected to constitute a small portion of the body capacitance. For example, compared to the capacitance of the output capacitor 506 (e.g., 1 microfarad), the capacitance of each capacitor 512 of the precharge voltage circuit can be ten times that (e.g., 10 microfarads). Thus, the switching time between voltage levels of the switching regulator 502 can be reduced by implementing an output capacitor 506 with a smaller capacitance, while still providing a larger overall body capacitance via the capacitor 512 with a larger capacitance to compensate for a load attack.

[0057] When switching between target output voltage levels, there may be a voltage error associated with the switching from the current target output voltage level to the next target output voltage level. This voltage error may be due to charge sharing between the output capacitor 506 charged to the current target output voltage level when coupling the capacitor 512 corresponding to the voltage level with the next target output voltage level to the output voltage node 503. Exemplary causes of the voltage error will now be discussed according to Equations 1 - 3. The charge of a capacitor is given by Equation (1).

[0058] Equation (1): Q = CV

[0059] Where: Q = Charge stored in the capacitor

[0060] C = Capacitance of the capacitor; and

[0061] V = Voltage of the capacitor

[0062] Since the output capacitor 506 and the capacitors of the coupled precharge voltage circuit will be connected in parallel, Equation (2) provides the combination of the charges of the output capacitor and the capacitor 512.

[0063] Equation (2): Q Final = Q 1 + Q 2

[0064] Where: Q 1 = Charge of the output capacitor; and

[0065] Q 2 = Charge of the capacitor of the precharge voltage circuit

[0066] Given Equation (2), the final output voltage will be given by Equation (3).

[0067] Equation (3): V Final = (C 1 V 1 + C 2 V 2 ) / (C 1 + C 2 )

[0068] Where: C 1 = capacitance of the output capacitor

[0069] V 1 = current target voltage

[0070] C 2 = capacitance of the pre-charge circuit; and

[0071] V 2 = next target voltage stored on C 2

[0072] As can be seen from Equation (3), the voltage error between the final voltage V Final is a function of the capacitor sizes of the output capacitor 506 and the capacitor 512 of the pre-charge voltage circuit 404 and their respective voltages. Thus, knowing the capacitance values and the current and next target voltages, the voltage offset can be determined by the pre-charge voltage regulator 511 to be added or subtracted by an amount of voltage corresponding to the next target voltage stored on the capacitor 512 to improve the output voltage accuracy when the output voltage varies. The amount of voltage offset can be stored in a pre-defined look-up table (LUT) that contains the voltage offsets for possible output voltage transitions. Alternatively, the LUT can be updated by comparing the output voltage when the pre-charge voltage circuit is coupled to the voltage output rail with the target output voltage. The difference between the output voltage and the target output voltage can be used to update the LUT. By updating the LUT, the APT voltage regulator circuit 500 can address the voltage errors caused by the operating conditions due to capacitor derating and / or capacitor aging. The LUT can be updated continuously or only when an error threshold is reached and / or exceeded.

[0073] ​In order to charge the capacitor 512 of the pre-charge voltage circuit 404, the APT voltage regulator circuit 500 can implement an initialization phase. In one implementation, the initialization phase includes decoupling the pre-charge voltage circuit 404 from the output voltage node 503 and charging the capacitor 512 to the target voltage amount using the corresponding pre-charge voltage regulator 511. In another implementation, the capacitor 512 is charged using the output voltage of the switching regulator 502. The capacitor 512 can be charged by the switching regulator 502, which outputs the target voltage amount and is coupled to the pre-charge voltage circuit 404 configured to charge to a voltage level corresponding to the target amount. The remaining pre-charge voltage circuit can be decoupled. Alternatively, the switching regulator 502 can charge the capacitor 512 by initially coupling the pre-charge voltage circuit 404 to the output voltage node 503 and cycling the output voltage from the lowest voltage level, and gradually stepping up between the voltage amounts to be stored in the pre-charge voltage circuit 404. When the output voltage exceeds the voltage level to be stored in the pre-charge voltage circuit 404, the corresponding pre-charge voltage circuit 404 is decoupled from the output voltage node 503. This process continues until the capacitor 512 of the pre-charge voltage circuit 404 is charged to its corresponding target voltage amount. An exemplary benefit of using the switching regulator 502 to charge the capacitor 512 is that the pre-charge voltage regulator 511 of the pre-charge voltage circuit can be configured to maintain the voltage stored on the capacitor, which can be reduced, for example, by capacitor leakage. Since the pre-charge voltage regulator 511 can only compensate for leakage compared to fully charging the capacitor, a smaller voltage regulator can be used, which can reduce cost and save area.

[0074] Reference now Figure 6 , Figure 6 A power multiplexer according to certain aspects of the present disclosure is used Figure 5 6 is a block diagram of an APT voltage regulator circuit of the present invention. The APT regulator circuit 600 includes a plurality of multiplexers 602 (i.e., power multiplexers) capable of processing the output voltage of the switching regulator 502, each of the power multiplexers 602 having an input coupled to the output of the pre-charge voltage circuit 404, and an output coupled to the output voltage node 604 of the switching regulator 502 and the supply line of the power amplifier 510. The power multiplexer is configured to selectively couple the pre-charge voltage circuit 404 to the supply line and the output voltage node 604. The reason for implementing the power multiplexer 602 is that the isolation between the power amplifier 510 and the pre-charge voltage circuit 404 can be further improved compared to separately implementing the switch 514 to selectively couple the pre-charge voltage circuit 404.

[0075] Reference now Figure 7 , Figure 7FIG. 700 is a block diagram of an APT voltage regulator circuit 700 that uses a switched regulator output switch in accordance with certain aspects of the present disclosure. The APT voltage regulator circuit 700 includes a plurality of output switches 702 having a first terminal coupled to the switched regulator 502 at an output voltage node 704. The plurality of output switches 702 further includes a second terminal coupled to a respective precharge voltage circuit 404. Each of the precharge voltage circuits 404 is further coupled to an input of a plurality of power multiplexers 602. The plurality of power multiplexers 602 are configured to selectively couple the precharge voltage circuits 404 to respective supply lines 510 of each of a plurality of power amplifiers. The plurality of output switches 702 are configured to couple the output voltage node 704 to the precharge voltage circuits 404, which are coupled to the supply lines of the power amplifiers 510. An exemplary benefit of the topology of the APT voltage regulator circuit 700 is that the power loss associated with the precharge voltage circuits 404 can be reduced by removing switches (such as Figure 5 switch 514 in

[0076] Now referring to Figure 8 , Figure 8Block diagram of an APT voltage regulator circuit 800 using two adjustable precharge voltage circuits, in accordance with certain aspects of the present disclosure. In one implementation, each of the precharge voltage circuits 404 includes a precharge voltage regulator 511 configured as an adjustable voltage output push-pull regulator. The push-pull regulator can be configured according to various push-pull topologies, such as a push-pull converter, a push-pull linear regulator, etc. In operation, the precharge voltage circuits 404 are configured to be alternately coupled to the output voltage node 503 of the switching regulator 502 to change from the current target output voltage level to the next target output voltage level. For example, the precharge voltage circuit 404a can be coupled to the output voltage node 503, where the stored voltage level corresponds to the current output voltage of the switching regulator 502, while the precharge voltage circuit 404b is decoupled. When the precharge voltage circuit 404b is decoupled, the capacitor 512b is charged / discharged to the next output voltage by charging the capacitor 512b to a voltage amount corresponding to the next output voltage of the switching regulator 502 using the precharge voltage regulator 511b via the push-pull regulator. When the output voltage of the switching regulator 502 changes from the current output voltage to the next output voltage, the precharge voltage circuit 404a is decoupled from the output voltage node 503, and the precharge voltage circuit 404b is coupled to the output voltage node 503. After the subsequent next output voltage level is determined, the capacitor 512a is charged to a voltage level corresponding to the subsequent next output voltage level by the precharge voltage circuit 404a, and the process is repeated. An exemplary advantage of using two adjustable voltage regulators to switch between the current output voltage and the next output voltage is that the number of precharge voltage circuits required to cover the output voltage range of the switching regulator 502 can be reduced, which can reduce costs and / or area requirements.

[0077] Now refer to Figure 9 , Figure 9FIG. 900 is a block diagram of an APT voltage regulator circuit using two switching regulators in accordance with certain aspects of the present disclosure. The switching regulators 502a-b may be configured according to the same switching regulator topology. For example, the switching regulators may include buck converters using output inductors 504a-b and output capacitors 506a-b, and the output inductors 504a-b and output capacitors 506a-b are configured with the same corresponding inductance values and capacitance values. Each of the outputs of the switching regulators 502a-b is coupled to a first terminal of a corresponding switch 902a-b. A second terminal of the switches 902a-b is coupled to the output voltage node 903. The output voltage node 903 is also coupled to the supply rail of the power amplifier array 508. The APT voltage regulator circuit 900 may also include a capacitor 904 having a first terminal coupled to the output voltage node 503 and a second terminal coupled to ground. In operation, one of the switching regulators 502 is configured to supply the current output voltage while being coupled to the output voltage node 903 via the corresponding switch 902, while the other switching regulator 502 is decoupled from the output voltage node 903 and charges the corresponding output capacitor 506 to the next output voltage to be provided to the power amplifier array 508. When the power amplifier array 508 requires the next output voltage, the switching regulator 502 providing the current output voltage is decoupled from the output voltage node 903, while the switching regulator 502 charging the output capacitor 506 to the next output voltage level is coupled to the output voltage node 903. However, prior to the coupling / decoupling of the switching regulators, it may be necessary to regulate the current in the output inductor 504 to avoid large variations in the current at the output voltage node 903. This process repeats, where the now decoupled switching regulator 502 charges the corresponding output capacitor 506 to the next output voltage to be provided to the power amplifier array 508.

[0078] When coupled to the output voltage node 903, the capacitance of the output capacitors 506a-b may include most of the bulk capacitance of the APT voltage regulator circuit 900, while the capacitor 904 may include a significantly smaller capacitance (e.g., 1 / 10). By making the capacitor 904 smaller than the capacitance of the output capacitors 506, the voltage error associated with the output voltage when switching between the switching regulators 502a-b can be reduced because the capacitor 904 will constitute a smaller amount of the shared charge with the coupled output capacitors 506.

[0079] Now referring to Figure 10 , Figure 10FIG. 1000 is a block diagram of an APT voltage regulator circuit 1000 using two switching regulators and a capacitor switching network according to certain aspects of the present disclosure. The APT voltage regulator circuit 900 includes a first switching regulator 502a coupled to an output voltage node 1003, which is also coupled to a supply line of a power amplifier array 508 and an output of a capacitor switching network 1004. A second switching regulator 502b is coupled to an input of the capacitor switching network 1004. In one implementation, the first switching regulator 502a is configured to supply current to the power amplifier array 508 (i.e., the load), while the second switching regulator 502b is configured to selectively charge the capacitors 1006 (i.e., pre-charge capacitors) of the capacitor switching network 1004. Thus, since the second switching regulator 502b is responsible for charging the capacitors 1006, the second switching regulator can be of reduced size compared to the first switching regulator 502a, which is responsible for supplying current to the power amplifier array 508.

[0080] In operation, the capacitor switching network 1004 is configured to selectively couple the capacitors substantially charged to the current output voltage provided by the first switching regulator 502a to the output voltage node 1003. The capacitor switching network 1004 is also configured to couple the remaining capacitors 1006 to the output of the second switching regulator 502b. The second switching regulator 506b is configured to charge the capacitors 1006 coupled to the output of the second switching regulator 506b to the next output voltage to be provided by the first switching regulator 502a. When the first switching regulator supplies the next output voltage to the output voltage node 1003, the capacitive switching network 1004 is configured to decouple the capacitor 1006 storing the current output voltage from the output voltage node 503 and decouple the capacitor 1006 storing the next output voltage from the output of the second switching regulator 502a. The capacitor switching network 1004 will further couple the capacitor 1006 storing the next output voltage to the output voltage node 1003 and couple the capacitor 1006 storing the current output voltage to the output of the second switching regulator 502b. After the subsequent next output voltage to be provided by the first switching regulator 502a is determined, the second switching regulator 502b will continue to charge the coupled capacitors 1006 to the subsequent next output voltage. Switch S1 is configured to selectively couple / de-couple the capacitor 1006a to / from the output of the second switching regulator 502b, while switch S3 is configured to selectively couple / de-couple the capacitor 1006a to / from the output voltage node 1003. Similarly, switch S2 is configured to selectively couple / de-couple the capacitor 1006b to / from the output of the second switching regulator 502b, while switch S4 is configured to selectively couple / de-couple the capacitor 1006b to / from the output voltage node 1003.

[0081] It should be noted that although Figure 10 the capacitor switching network 1004 of Figure 10 shows two capacitors 1006, any number of capacitors can be implemented in the capacitor switching network.

[0082] Now referring to Figure 11 , an example operation of a voltage regulation method 1100 using a pre-charge voltage rail in accordance with certain aspects of the present disclosure is shown. This operation can be performed by a circuit such as Figures 5 - 10 in Figures 5 - 10 .

[0083] At block 1102, a target output voltage level to be supplied by the voltage regulator is determined. In one implementation, the target output voltage level is based on a signal to be transmitted using one or more power amplifiers. One or more power amplifiers can be biased using the target output voltage according to an average power tracking (APT) scheme. The APT tracking scheme can be executed on a TX data processor or a separate processing circuit. The APT tracking scheme determines the target output voltage based on the output power level of the signal to be transmitted. The power level of the signal can vary on a per time slot (e.g., time slot) basis to transmit the signal. For example, the APT tracking scheme can determine that for a particular time slot of the signal to be transmitted, one or more power amplifiers should be biased to have a target output voltage of 1.4V.

[0084] At block 1104, the target output voltage is provided via the voltage regulator by coupling at least a pre-charge voltage circuit whose capacitance is charged to a voltage level substantially equal to the target output voltage to the voltage output of the voltage regulator. The charged voltage level can be substantially equal within a fault tolerance range (e.g., 1% of the target output voltage), and / or include a voltage offset added to or subtracted from the target output voltage level. The pre-charge voltage circuit can be coupled to the voltage output via one or more switches and / or one or more power multiplexers.

[0085] At block 1106, the next target output voltage to be supplied by the voltage regulator is determined. For example, the APT tracking scheme can determine that based on the output power level required for a subsequent time slot, a different target output voltage may be required for a subsequent time slot of the signal to be transmitted to one or more power amplifiers.

[0086] At block 1108, the next target output voltage is provided via the voltage regulator by coupling at least a pre-charge voltage circuit whose capacitance is charged to a voltage level substantially equal to the next target output voltage to the voltage output of the voltage regulator. The capacitance can be charged using a fixed or adjustable voltage regulator. The pre-charge voltage circuit can be coupled after decoupling the pre-charge voltage circuit coupled in block 1104.

[0087] Now referring toFigure 12 , a circuit diagram of an example voltage regulation circuit 1200 using predictive charging for a pre-charge voltage rail is shown, in accordance with certain aspects of the present disclosure. The voltage regulation circuit 1200 includes a power management circuit 1202 and a radio frequency front end (RFFE) circuit 1204. It should be noted that the box representing the power management circuit 1202 represents a boundary. The power management circuit 1202 includes a main switch regulator 1206, a pre-charge switch regulator 1208, a pre-charge switch circuit 1210, and predictive pre-charge logic 1212. The main switch regulator 1206 and the pre-charge switch regulator 1208 may be configured according to various switch regulator topologies (e.g., buck, boost, buck-boost). In Figure 12In the implementation shown, the main switch regulator 1206 and the pre - charge switch regulator 1208 are configured according to an exemplary buck regulator topology. The main switch regulator 1206 and the pre - charge switch regulator 1208 can be implemented according to a single - phase or multi - phase configuration. The main switch regulator 1206 and the pre - charge switch regulator 1208 can also be configured to operate at the same switching frequency (e.g., 3.2 MHz). The main switch regulator 1206 includes a high - side switch 1214, a low - side switch 1216, and a main control circuit 1218. The high - side switch 1214 has a first terminal coupled to the input voltage (Vin) and a second terminal coupled to the switching voltage node (Vswm) of the main switch regulator 1206. The low - side switch 1216 has a first terminal coupled to the second terminal of the high - side switch 1214 and Vswm and a second terminal coupled to a reference potential such as ground (GND). The pre - charge switch regulator 1208 includes a high - side switch 1220, a low - side switch 1222, and a pre - charge control circuit 1224. The high - side switch 1220 has a first terminal coupled to the input voltage (Vin) and a second terminal coupled to the switching voltage node (Vswp) of the pre - charge switch regulator 1208. The low - side switch 1222 has a first terminal coupled to the second terminal of the high - side switch 1220 and Vswp and a second terminal coupled to a reference potential such as ground (GND). The main switch regulator 1206 and the pre - charge switch regulator 1208 can be coupled to the same input voltage Vin, or can be coupled to separate input voltages, which can have the same or different voltage levels. In one implementation, the high - side switches 1214, 1220 are implemented as positive metal - oxide - semiconductor (PMOS) field - effect transistors (FETs), and the low - side switches 1216, 1222 are implemented as negative metal - oxide - semiconductor (NMOS) field - effect transistors. However, various other transistor topologies can be used to implement the high - side and low - side switches. The main control circuit 1218 is configured to control the operation (i.e., turn - on and turn - off) of the high - side switch 1214 and the low - side switch 1216 using one or more control signals via at least one output coupled to the control terminals (e.g., gate terminals) of the high - side switch 1214 and the low - side switch 1216. For example, the main control circuit 1218 can output only a single control signal to control both the high - side switch 1214 and the low - side switch 1216, or alternatively, can output two control signals, where one control signal controls the high - side switch 1214 and the other control signal controls the low - side switch 1216. Similarly, the pre - charge control circuit 1224 is configured to control the operation (i.e., turn - on and turn - off) of the high - side switch 1220 and the low - side switch 1222 using one or more control signals via at least one output coupled to the control terminals (e.g., gate terminals) of the high - side switch 1220 and the low - side switch 1222.

[0088] The pre - charge switch circuit 1210 is configured to selectively couple the output voltage node 1228 of the pre - charge switch regulator 1208 to the output voltage node 1226 of the main switch regulator 1206. The pre - charge switch circuit 1210 includes a pre - charge switch 1230. In one implementation, the pre - charge switch 1230 includes an NMOS field - effect transistor. A first terminal (e.g., drain) of the pre - charge switch 1230 is coupled to the output voltage node 1226 of the main switch regulator 1206, and a second terminal (e.g., source) is coupled to the output voltage node 1228. The operation of the pre - charge switch 1230 can be driven by a drive amplifier 1232 coupled to the control terminal (e.g., gate) of the pre - charge switch 1230, where the operation is based on a control switch signal received from the predictive pre - charge logic 1212. Alternatively, the operation of the pre - charge switch 1230 can be directly controlled by the control signal output of the predictive pre - charge logic 1212, which can omit or bypass the drive amplifier 1232. The pre - charge switch circuit 1210 further includes a comparator 1233 having a first input coupled to the voltage node 1226 of the main switch regulator 1206 and a second input coupled to the output of the main control circuit 1218. In one implementation, the comparator 1233 receives the output voltage Vpa of the main switch regulator 1206 via the output voltage node 1226, compares it with the target output voltage provided to the second input from the main control circuit 1218, and outputs the difference to the predictive pre - charge logic 1212. The predictive pre - charge logic 1212 can use the output of the comparator 1233 to control the operation of the pre - charge switch 1230. For example, when changing the main switch regulator 1206 from the current output voltage Vpa to the next target output voltage, the pre - charge switch 1230 can be closed to couple the output voltage node 1226 of the main switch regulator 1206 to the output voltage node 1228 of the pre - charge switch regulator 1208. When the comparator 1233 presents an output to the predictive pre - charge logic 1212 indicating that the output voltage Vpa has reached the target output voltage provided by the main control circuit 1218 (e.g., indicated by an output of 0V, within a margin of 0V, etc.), the predictive pre - charge logic 1212 can decouple the output voltage nodes 1226, 1228 by providing a control switch signal (or ceasing to assert) for disconnecting (e.g., turning off) the pre - charge switch 1230. In one implementation, the predictive pre - charge logic can limit the period of time the pre - charge switch can be closed (i.e., turned on). For example, a timer can be used to set the maximum “on” time of the pre - charge switch 1230. Although the comparator 1233 is shown as part of the pre - charge switch circuit 1210, the comparator 1233 can form part of the predictive pre - charge logic 1212 or separate control logic (not shown).

[0089] In Figure 12In an example implementation, the main switch regulator 1206 has a main output inductor 1234. The main output inductor 1234 has a first terminal coupled to the main switch voltage node Vswm and a second terminal coupled to the first terminal of the main output capacitor 1236. The second terminal of the main output capacitor 1236 is coupled to ground. Additionally, the second terminal of the main output inductor 1234 and the first terminal of the main output capacitor 1236 are coupled to the output voltage node 1226 of the main switch regulator 1206 to provide the output voltage (Vpa) of the main switch regulator to the output voltage node 1226. Via the coupling to the output voltage node 1226, the output voltage Vpa is further provided as an input to the main control circuit 1218 as part of a feedback control loop to regulate the output voltage Vpa of the main switch regulator 1206. Similarly, the precharge switch regulator 1208 has a precharge output inductor 1238. The precharge output inductor 1238 has a first terminal coupled to the precharge switch voltage node Vswp and a second terminal coupled to the first terminal of the precharge output capacitor 1240. The second terminal of the precharge output capacitor 1240 is coupled to ground. Additionally, the second terminal of the precharge output inductor 1238 and the first terminal of the precharge output capacitor 1240 are also coupled to the voltage node 1228 of the precharge switch regulator 1208 to provide the voltage stored on the precharge output capacitor (Vpchg) to the output voltage node 1228. Via the coupling to the voltage node 1228, the output voltage Vpchg is further provided as an input to the precharge control circuit 1224 as part of a feedback control loop to regulate the charging of the precharge output capacitor 1240 to a desired level of Vpchg. The capacitance values for the main output capacitor 1236 and the precharge output capacitor 1240 can be the same or different (i.e., higher or lower capacitance).

[0090] The target output voltage of Vpa is to be provided as a voltage supply to one or more power amplifiers 1205 of the RFFE circuit 1204, and the desired level of Vpchg is determined by the predictive precharge logic 1212 based on the information received at the input of the predictive precharge logic 1212. In one implementation, the predictive precharge logic 1212 receives information about the symbols to be amplified by one or more power amplifiers 1205 for transmission from the radio frequency front-end (RFFE) serial bus. For example, the information can include the voltage information V SYM [n], where n is an integer. In one implementation, the predictive precharge logic 1212 also includes an RFFE decoder (not shown) configured to decode the received information for use by the predictive precharge logic 1212. The predictive precharge logic 1212 can scale the voltage symbol V SYM[n], such as according to the APT scheme, to determine the target output voltage of the main switching regulator 1206, as shown in Equation (1).

[0091] V MAIN [n]=scaling constant×V SYM [n] Equation (1)

[0092] Based on the voltage information associated with the sign of the next target output voltage (e.g., V SYM [n]), and the voltage information associated with the sign of the current target output voltage (e.g., V SYM [n - 1]), the predictive pre - charge logic 1212 also uses the pre - charge switching regulator 1208 to determine the level of the pre - charge voltage to be stored on the pre - charge output capacitor 1240. For example, the level of the pre - charge voltage includes a voltage level offset from the target output voltage V SYM [n] based on the difference between the voltage information associated with the sign of the next target output voltage (e.g., V SYM [n]) and the voltage information associated with the sign of the current target output voltage (e.g., V MAIN [n - 1]). In one implementation, the difference between the voltage information is scaled by a coefficient k. The coefficient k can be based on the capacitance values of the main output capacitor 1236 and the pre - charge output capacitor 1240. The coefficient k can also be chosen to balance design requirements, such as performance compared to power loss (e.g., the slew rate of the output voltage) (e.g., based on the power dissipated across the pre - charge switch 1230 by the current supplied / absorbed by the pre - charge capacitor). For example, a higher coefficient may result in a larger difference between the pre - charge voltage and the next target output voltage, which may cause a larger amount of current to flow through the pre - charge switch 1230 to / from the pre - charge output capacitor 1240 when coupled to the main switching regulator 1206. This difference can be further scaled by a scaling constant, which is used to determine the voltage V PCHG [n] to be stored on the pre - charge capacitor, as shown in Equation (2).

[0093] V PCHG [n]=scaling constant×(V SYM [n]+k(V SYM [n]-V SYM [n - 1])) Equation (2)

[0094] In one implementation, different values of k can be used, depending on whether the next target output voltage of the main switching regulator 1206 needs to be charged up (i.e., an increase in the target output voltage) or discharged (i.e., a decrease in the target output voltage). The predictive pre - charge logic can be based on the voltage information of the next sign (e.g., V SYM[n]) and the voltage information of the current symbol (e.g., V SYM [n-1]), to determine whether the next target output voltage is to be charged up or down. For example, the predictive pre-charge logic 1212 may determine to use the up-charge factor k SYM [n] > V SYM [n-1], or use the down-charge factor k U when V SYM [n] <= V SYM [n-1]. D .

[0095] Although Figure 12 the example implementation shows a single predictive pre-charge switching regulator 1208, it should be understood that multiple predictive pre-charge switching regulators 1208 may be used. For example, each predictive pre-charge switching regulator 1208 may be configured to initially store a certain amount of voltage (e.g., 1V, 1.5V, etc.) on the corresponding predictive pre-charge output capacitor 1240. After the predictive pre-charge voltage level is determined, if necessary, the predictive pre-charge switching regulator 1208 with the initially stored voltage closest to the determined predictive pre-charge voltage may be selected for charging and output the determined predictive pre-charge voltage level. The outputs of multiple predictive pre-charge switching regulators 1208 may be selectively connected to the predictive pre-charge switching circuit 1210 via a multiplexer or switch and controlled by the predictive pre-charge logic 1212 using one or more control signals. By selecting the predictive pre-charge switching regulator 1208 of the charged predictive pre-charge output capacitor 1240 with the closest predictive pre-charge voltage level, the charging time to reach the predictive pre-charge voltage level can be reduced.

[0096] Now refer to Figure 13 , Figure 13 which is an example timing diagram of the voltage regulation circuit of Figure 12 in accordance with certain aspects of the present disclosure. In the example timing diagram, the voltage regulation circuit 1200 operates according to the mmW APT transmission scheme. In the example mmW APT transmission scheme, symbols for uplink (UL) communication are allocated 8.9 microseconds (μS) in a transmission time interval (TTI). The predictive pre-charge logic 1212 is configured to receive voltage information including symbol n (represented by V SYM[n] indicates the signal for the desired voltage of the voltage supply line to be applied to one or more power amplifiers, for transmitting data during a certain period (e.g., 5 μS) before transmitting symbols from the RFFE serial bus. The RFFE serial bus also provides a trigger signal (indicated by Trigger) to the predictive precharge logic 1212 to indicate when to adjust to the next target output voltage of the voltage supply line to be provided to one or more power amplifiers 1205 for amplifying data for transmission during the allocated TTI. The determined next target output voltage of the main switch regulator 1206 is indicated by the signal V MAINSET while the voltage level to be stored on the precharge output capacitor 1240 is indicated by the signal V PCHGSET . Taking symbol [n - 2] as an example, the predictive precharge logic 1212 determines V SYM [n - 2] based on the voltage information of the received symbol V SET [n - 2] and the current target output voltage V PCHGSET [n - 3]. Using the determined precharge voltage level V PCHGSET [n - 2] received from the predictive precharge logic 1212, the precharge switch regulator 1208 starts charging the precharge output capacitor 1240 to the set voltage level over time (t), as shown by the voltage waveform 1302 of the precharge output capacitor V PCHG (t). When the predictive precharge logic 1212 receives the trigger signal Trigger[n - 2], the predictive precharge logic 1212 sends a control signal to the main switch regulator 1206 to adjust the output voltage of the main switch regulator 1206 according to V MAINSET [n - 2]. Additionally, in response to receiving Trigger[n - 2], the predictive precharge logic 1212 asserts a control signal, as indicated by the signal PCHG SW.CTL, to close (i.e., turn on) the precharge switch 1230 to couple the voltage node 1226 of the main switch regulator 1206 with the voltage node 1228 of the precharge switch regulator 1208. When the voltage node 1226 and the voltage node 1228 are respectively coupled to the outputs of the main switch regulator 1206 and the precharge output capacitor 1240 through the coupled voltage nodes, the charge stored on the precharge output capacitor 1240 assists the main switch regulator 1206 to achieve the next target output voltage, as shown by the voltage waveform V of the output voltage of the main switch regulator 1206, denoted as V APT(t). By coupling the voltage stored on the pre - charge output capacitor 1240 to the voltage node 1226 of the main switch regulator 1206, the output voltage conversion rate of the main switch regulator 1206 is improved (e.g., a 10 - fold improvement) compared to a main switch regulator that separately regulates the target output voltage. In an example implementation, the pre - charge switch regulator 1208 is configured to enter a tri - state mode to present a high impedance when receiving a trigger signal until voltage information for the next symbol [n - 1] is received or expected (e.g., every 8.9 μS period of a TTI). The tri - state mode includes turning off at least a part of the high - side switch 1220, the low - side switch 1222, and the pre - charge control circuit 1224 (e.g., the part responsible for regulating the switching of the high - side and low - side switches). By putting the pre - charge switch regulator 1208 into the tri - state mode when the pre - charge output capacitor 1240 does not need to be charged, power can be saved.

[0097] When the output voltage V APT reaches the next target output voltage of symbol [n - 2], as set by the voltage level of V MAINSET [n - 2], a signal indicating that the pre - charge output capacitor 1240 can be decoupled (denoted as PCHG DONE) is generated and provided to the predictive pre - charge logic 1212. For example, the PCHG DONE signal can be generated from the output of a comparator 1233 of the pre - charge switch circuit 1210. Upon receiving the generated PCHG DONE signal, the predictive pre - charge logic 1212 stops asserting the PCHG SW.CTL control signal to disconnect (i.e., turn off) the pre - charge switch 1230 to decouple the voltage nodes 1226, 1228. After the voltage nodes are decoupled, the main switch regulator 1206 uses a feedback loop to control the output voltage to stabilize the output voltage, as indicated by V MAINSET [n - 2]. Then the process starts again, where the next symbol will be amplified for transmission [n - 1].

[0098] Now referring Figure 14 , a block diagram of an example user terminal architecture 1400 implementing a voltage regulation circuit using a pre - charge rail for predictive charging for mmW APT in accordance with certain aspects of the present disclosure is shown. The user terminal architecture includes a power management integrated circuit (PMIC) 1402, a radio frequency front - end (RFFE) circuit 1404, an antenna array 1406 including a plurality of antennas, and a baseband processor 1408.

[0099] The RFFE circuit 1404 includes a radio frequency (RF) transceiver 1410 configured to communicate with the baseband processor 1408. The RFFE circuit 1404 also includes a power amplifier 1412 for amplifying the signal to be transmitted (such as Figure 3a power amplifier 316), a low-noise amplifier 1414 (such as Figure 3 the LNA 322) configured to amplify a signal received from the antenna array 1406, and a transmit / receive (T / R) switch 1416 configured to selectively connect the individual power amplifier 1412 and LNA 1414 in the power amplifier 1412 and LNA 1414 to corresponding antennas of the antenna array 1406. For example, the T / R switch 1416 can connect the power amplifier 1412 to the antenna during a transmission period and then connect the LNA 1414 to the same antenna during a reception period. The RFFE circuit 1404 can reside on a single RFFE IC or can include multiple ICs and / or components external to the (multiple) ICs.

[0100] The PMIC 1402 is configured to receive at least one input voltage (Vin) and provide a supply voltage to the RFFE circuit 1404. The PMIC 1402 can include one or more power management circuits for providing one or more supply voltages to the power amplifier according to the APT scheme, such as Figure 12 the power management circuit 1202. The PMIC 1402 is also configured to be coupled to the baseband processor 1408 via the RFFE bus to receive control signals. For example, the control signals can include voltage information (e.g., V SYM [n]) about the symbols to be transmitted on the antenna array 1406 via the RFFE circuit 1404, and when the power amplifier 1412 should amplify the symbols for transmission (e.g., a trigger signal).

[0101] Now referring to Figure 15 , an example operation of a voltage regulation method 1500 for a pre-charge voltage rail using predictive charging in accordance with certain aspects of the present disclosure is shown.

[0102] At block 1502, the next target output voltage to be supplied by the main switch regulator is determined. The next target output voltage is determined based on voltage information about the symbols to be transmitted on one or more antennas. In one implementation, the predictive pre-charge logic can receive the voltage information from the baseband processor via the RFFE serial bus. The voltage information can be modified, such as scaled, to determine the next target output voltage. For example, the voltage information can be scaled according to the APT scheme. In another implementation, the baseband processor can directly provide the next target output voltage to the main switch regulator.

[0103] At block 1504, a capacitor coupled to the output of the pre-charge switching regulator is charged to a pre-charge voltage level. The pre-charge voltage level can be determined by the predictive pre-charge logic of the voltage regulation circuit. The pre-charge voltage level is based on the current target output voltage and the next target output voltage supplied by the main switching regulator. In one implementation, the voltage level is based on the difference between the current target output voltage and the next target output voltage. For example, the current target output can include 1V and the next target output voltage can include 2V, such that the difference between the target voltages is 1V. The pre-charge switching regulator can charge the pre-charge voltage level to the next target output voltage (e.g., 2V) plus an offset including the difference (e.g., 1V), such that the pre-charge voltage level in this example is 3V. Before adding the offset to the next target output voltage to determine the pre-charge voltage level, the offset can be further modified by multiplying the difference (e.g., 1V) by a coefficient (e.g., in the range between 0 and 2.5). Depending on whether the next target output voltage is higher or lower than the current target output voltage, the coefficient used can be different. For example, a first coefficient can be used when the next target output voltage increases, while a second coefficient can be used when the next target voltage is less than the next target output voltage. When the next target output voltage is the same as the current target output voltage, a third coefficient can be used, or alternatively, the third coefficient can include the first coefficient or the second coefficient.

[0104] At block 1506, based on the transition from the current target output voltage to the next target voltage, the capacitor of the pre-charge switching regulator is selectively coupled to the output of the main switching regulator. In one implementation, the selective coupling is achieved via a pre-charge switch coupled between the voltage node of the main switching regulator and the voltage node of the pre-charge switching regulator. The pre-charge switch can selectively couple the voltage nodes based on a trigger signal received by the baseband processor, via a control signal from the predictive pre-charge logic, to supply or absorb current to / from the capacitor. When the output voltage of the main switching regulator is equal to the next target output voltage, the predictive pre-charge logic can further provide a control signal to decouple the voltage nodes.

[0105] The various operations of the above method can be performed by any suitable device capable of performing the corresponding functions. The device can include various hardware components and / or modules, including but not limited to one or more circuits. Generally, in cases where there are operations shown in the figures, these operations can have corresponding device plus function components with similar numbers. For example, the device for providing a regulated voltage can include, for example, a voltage regulator, such as Figure 5 the switching regulator 502. The device for pre-charging multiple voltage rails to multiple corresponding voltages can include, for example, a pre-charge voltage circuit, such as Figure 4The pre-charge voltage circuit 404. Apparatus for selectively coupling a voltage rail among a plurality of voltage rails to a voltage output may include, for example, a switch, such as Figure 5 switch 514 or Figure 7 switch 702. Apparatus for determining a next target output voltage to be supplied by a main switch regulator may include Figure 12 predictive pre-charge logic 121. For example, apparatus for storing charge may include Figure 12 pre-charge output capacitor 1240. Apparatus for charging apparatus for storing charge may include, for example, Figure 12 pre-charge switch regulator 1208. Apparatus for selectively coupling apparatus for storing to an output of a main switch regulator may include, for example, Figure 12 pre-charge switch circuit 1210. Apparatus for determining a difference between a current target output voltage and a next target output voltage may include, for example, Figure 12 comparator 1233.

[0106] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or other data structure), ascertaining, etc. Further, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Further, "determine" may include resolving, selecting, picking, establishing, etc.

[0107] As used herein, a phrase referring to "at least one" in a list of items means any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination having multiple of the same element (e.g.,,, aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0108] The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure may be implemented or performed with discrete hardware components designed to perform the functions described herein.

[0109] The methods disclosed herein include one or more steps or acts for implementing the described methods. Without departing from the scope of the claims, the method steps and / or acts may be interchanged with one another. In other words, unless a specific order of steps or acts is specified, the order and / or use of specific steps and / or acts may be modified without departing from the scope of the claims.

[0110] It should be understood that the claims are not limited to the exact configurations and components described above. Various modifications, alterations, and variations to the arrangements, operations, and details of the above methods and apparatuses can be made without departing from the scope of the claims.

Claims

1. A voltage regulation circuit, comprising: A main switch regulator configured to provide a target voltage, the main switch regulator having a first voltage node; A pre-charge switch regulator configured to provide a pre-charge voltage, the pre-charge switch regulator having a second voltage node, the level of the pre-charge voltage being determined based on the difference between the target voltage and the next target voltage to be provided by the main switch regulator; And A pre-charge switch circuit configured to selectively couple the output voltage node of the pre-charge switch regulator to the output voltage node of the main switch regulator based on the transition from the target voltage to the next target voltage, wherein the voltage regulation circuit is coupled to a radio frequency front-end circuit configured to transmit one or more symbols via an antenna, the levels of the target voltage and the next target voltage corresponding to the power level of the one or more symbols, the voltage regulation circuit being configured to receive voltage information of the one or more symbols to determine the next target voltage, and wherein the voltage information includes the levels of the target voltage and the next target voltage corresponding to the power level of the one or more symbols.

2. The voltage regulation circuit according to claim 1, further comprising predictive pre-charge logic configured to determine the level of the pre-charge voltage.

3. The voltage regulation circuit according to claim 2, wherein the predictive pre-charge logic is further configured to control the main switch regulator and the pre-charge switch regulator.

4. The voltage regulation circuit according to claim 3, wherein: The main switch regulator includes: A main control circuit configured to receive a first output from the predictive pre-charge logic; A high-side switch having a first terminal coupled to an input voltage, a second terminal coupled to the first voltage node, and a gate terminal coupled to the output of the main control circuit; and A low-side switch having a first terminal coupled to the first voltage node, a second terminal coupled to a reference voltage, and a gate terminal coupled to the output of the main control circuit.

5. The voltage regulation circuit according to claim 3, wherein: The pre-charge switch regulator includes: A pre-charge control circuit configured to receive a second output from the predictive pre-charge logic; A high-side switch having a first terminal coupled to an input voltage, a second terminal coupled to the second voltage node, and a gate terminal coupled to the output of the pre-charge control circuit; and A low-side switch having a first terminal coupled to the second voltage node, a second terminal coupled to a reference voltage, and a gate terminal coupled to the output of the pre-charge control circuit.

6. The voltage regulation circuit according to claim 1, further comprising: A first inductor having a first terminal coupled to the first voltage node and a second terminal coupled to an output capacitor and the output voltage node of the main switch regulator; And A second inductor having a first terminal coupled to the second voltage node and a second terminal coupled to the output voltage node of the precharge capacitor and the precharge switching regulator.

7. The voltage regulation circuit according to claim 6, wherein the precharge switching circuit includes a switch having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the second terminal of the second inductor.

8. The voltage regulation circuit according to claim 7, wherein the gate terminal of the switch of the precharge switching circuit is configured to be controlled by a switching signal, wherein the switching signal is based on the transition from the target voltage to the next target voltage.

9. The voltage regulation circuit according to claim 8, further comprising predictive precharge logic configured to output the switching signal.

10. The voltage regulation circuit according to claim 9, wherein the precharge switching circuit further includes a comparator having a first input coupled to the output voltage node, a second input coupled to the main switching regulator, and an output coupled to an input of the predictive precharge logic.

11. The voltage regulation circuit according to claim 10, wherein the comparator is configured to output the difference between the voltage level received at the first input and the voltage level corresponding to the next target voltage received at the second input.

12. The voltage regulation circuit according to claim 1, wherein the first voltage node is coupled to the voltage supply line of one or more power amplifiers.

13. The voltage regulation circuit according to claim 12, wherein the one or more power amplifiers are configured to amplify one or more signals to be transmitted based on the next target voltage provided via the supply line.

14. The voltage regulation circuit according to claim 1, wherein the level of the precharge voltage corresponds to the next target voltage plus an offset corresponding to the difference between the target voltage and the next target voltage.

15. The voltage regulation circuit according to claim 1, wherein the level of the precharge voltage corresponds to the next target voltage plus an offset corresponding to the difference between the target voltage and the next target voltage scaled by a factor.

16. The voltage regulation circuit according to claim 15, wherein the factor is further based on whether the next target voltage is being charged up or down.

17. A method for regulating voltage using a precharge switching regulator, the method comprising: determining a next target output voltage to be supplied by a main switching regulator, the next target output voltage being determined at least in part based on voltage information of one or more symbols transmitted via an antenna using a radio frequency front-end circuit; charging a capacitor coupled to the output of the precharge switching regulator to a precharge voltage level based on a target output voltage supplied by the main switching regulator and the next target output voltage; and Based on the transition from the target output voltage to the next target output voltage, selectively couple the output of the pre - charge switch regulator to the output of the main switch regulator, wherein the voltage information includes the levels of the target output voltage and the next target output voltage corresponding to the power levels of the one or more symbols.

18. The method according to claim 17, wherein the pre - charge voltage level is based on the difference between the target output voltage and the next target output voltage.

19. The method according to claim 18, further comprising: Determining the pre - charge voltage level by multiplying the difference by a coefficient value.

20. The method according to claim 19, wherein the coefficient value is based on the difference.

21. The method according to claim 20, wherein when the difference indicates that the next target output voltage is greater than the target output voltage, a first value is used for the coefficient value; and wherein when the difference indicates that the next target output voltage is less than the target output voltage, a second value is used for the coefficient value.

22. The method according to claim 17, further comprising: Supplying an output voltage corresponding to the next target output voltage to a voltage supply line of the one or more power amplifiers.

23. A voltage regulation circuit, comprising: A first switch regulator configured to provide a first target voltage to an output voltage node; An output inductor having a first terminal coupled to the output of the first switch regulator and a second terminal coupled to the output voltage node; A second switch regulator configured to charge a pre - charge output capacitor to a pre - charge voltage level, the pre - charge voltage level being determined based on the difference between: the first target voltage, and a second target voltage to be provided by the first switch regulator; and A pre - charge switch circuit configured to selectively couple the charged pre - charge output capacitor to the output voltage node based on the transition from the first target voltage to the second target voltage, wherein the voltage regulation circuit is coupled to a radio frequency front - end circuit configured to transmit one or more symbols via an antenna, the levels of the first target voltage and the second target voltage corresponding to the power levels of the one or more symbols, the voltage regulation circuit being configured to receive voltage information of the one or more symbols to determine the second target voltage, and wherein the voltage information includes the levels of the first target voltage and the second target voltage corresponding to the power levels of the one or more symbols.

24. The voltage regulation circuit according to claim 23, further comprising a pre - charge output inductor having a first terminal coupled to the output of the second switch regulator and a second terminal coupled to the pre - charge output capacitor; wherein the second terminal of the pre - charge output inductor is further coupled to the pre - charge switch circuit.

25. The voltage regulation circuit according to claim 23 further includes predictive precharge logic configured to control the first switching regulator and the second switching regulator, and the predictive precharge logic has an input coupled to a bus of the radio frequency front-end circuit of the mobile device.

26. A device for providing voltage regulation, comprising: means for determining a next target output voltage to be supplied by a main switching regulator; means for storing charge; means for charging the means for storing charge to a precharge voltage level via an output of a precharge switching regulator, the precharge voltage level being based on the target output voltage supplied by the main switching regulator and the next target output voltage; and means for selectively coupling the means for storing charge to an output of the main switching regulator based on a transition from the target output voltage to the next target output voltage, wherein the next target output voltage is determined at least in part based on voltage information of one or more symbols transmitted via an antenna using a radio frequency front-end circuit, and wherein the voltage information includes the levels of the target output voltage and the next target output voltage corresponding to the power levels of the one or more symbols.

27. The device according to claim 26, wherein the means for determining the next target output voltage further comprises: means for determining a difference between the target output voltage and the next target output voltage.

28. The device according to claim 27, wherein the precharge voltage level is based on the determined difference.

29. The device according to claim 28, wherein the precharge voltage level includes a sum of the determined difference and the next target output voltage.

30. The device according to claim 29, wherein the determined difference is scaled by a coefficient before being summed.

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