Indirect Branch Predictor and Prediction Method Based on Global History Classification
By designing an indirect branch predictor based on global history classification, using path history and direction history information to predict, and selecting the optimal target address through the target address arbitration module, the problem of low prediction accuracy in the existing technology is solved, and higher prediction accuracy and more reasonable resource utilization are achieved.
Patent Information
- Application Number
- CN202111517099.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-08
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2041-12-08
AI Technical Summary
Existing indirect branch predictors cannot make full use of path history and direction history information, resulting in low prediction accuracy.
An indirect branch predictor based on global history classification is designed. Through a single-target address prediction module, a multi-target address prediction module, a target address arbitration module and a multiple-channel selection module, the command path history and direction history are used to predict, and the target address with high confidence is selected through the target address arbitration module.
It improves the prediction accuracy of indirect branch predictors, rationally utilizes hardware resources, avoids the problem of wasted resources or insufficient channels, has better applicability and a wider range of applications.
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Figure CN114296803B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an indirect branch predictor and a prediction method based on global history classification, and belongs to the field of branch predictor design of a processor. Background Art
[0002] In recent years, with the development of superscalar and deep pipeline technologies, branch predictors have increasingly become an indispensable part of modern high-performance processors.
[0003] A branch predictor mainly completes the prediction of the direction (whether to jump) of a branch instruction in the program flow and the jump target address. According to the source of the target address of the branch instruction, it can be divided into two categories, namely direct jump branches and indirect jump branches. For a direct jump branch, since its offset is given in the form of an immediate number, there will only be a single target address; while for an indirect jump branch, since its offset is derived from a general-purpose register and the value of this general-purpose register may change as the program runs, there will be a single or multiple target addresses.
[0004] Previous research on branch predictors mainly focused on direct jump branch prediction techniques with high prediction accuracy. For the prediction of indirect jump branches, it is generally difficult to achieve good prediction results. In recent years, with the development of object-oriented languages such as C++ and Java, the application scenarios of indirect jump branches have become increasingly extensive. Therefore, improving the prediction accuracy of indirect jump branches is of great significance for improving the performance of modern processors.
[0005] In modern processors, a branch target buffer (BTB) is usually used to predict the target address of single-target branch instructions and can achieve good prediction results; for multi-target indirect jump branches, if only the BTB is still used, it is difficult to meet the requirements of high prediction accuracy. Therefore, an indirect branch predictor with tag matching (such as TTC, Cascade, ITTAGE predictors, etc.) is usually used to predict its target address.
[0006] The structure of the TTC predictor (see P.Y. Chang, E. Hao, and Y.N. Patt, “Target prediction for indirect jumps,” in Proceedings of the 24th annual international symposium on Computer architecture, ISCA 97, pp. 274–283, 1997.) is as Figure 1As shown, it first performs a hashing operation on the PC value of the instruction and the value of the global history register (GHR); then, according to the hashing result, it indexes its branch prediction table to obtain corresponding prediction information, which includes the mapping pairs of multiple-way (way) tags and targets. Among them, the tag is used to determine whether the information of this way matches the current branch, and the target is the target address predicted by this way; finally, according to the matching result of the tag, the finally predicted target is selected. Since the number of target addresses for each indirect jump branch in the program flow may be different, it is impossible to determine the specific number of ways for each table entry. If a certain compromise number of ways is uniformly adopted, for those indirect jump branches with fewer target addresses, it will cause waste of hardware resources, while for those indirect jump branches with more target addresses, it will cause the problem of insufficient number of ways.
[0007] The Cascade predictor (see K. Driesen and U. “The cascaded predictor: economical and adaptive branch target prediction,” in Proceedings of the 31st annual ACM / IEEE international symposium on Microarchitecture, MICRO 31, pp. 249–258, 1998.) is shown in the block diagram as Figure 2 shown. It integrates the BTB and TTC predictors. Compared with the TTC predictor, this predictor can well distinguish single-target and multi-target indirect jump branches, thus saving hardware resources for single-target indirect jump branches. However, for those indirect jump branches with multiple targets, there are still the same problems as the TTC predictor.
[0008] The structure of the ITTAGE predictor (see A. Seznec, “A 64-kbytes ittage indirect branch predictor,” in Proceedings of the JWAC-2: Championship Branch Prediction, June 2011.) is as Figure 3 shown. It consists of a basic component T0, N tagged components (T1 to T N ) and a global history register (GHR). Among them, T0 is a basic prediction table composed of target addresses target, and only the PC of the instruction is used for indexing; T1 to T NThe tag prediction table consists of a matching tag, a confidence counter ctr, a target address target, and a u-bit indicating whether this table entry is still in use. It is indexed by the hash result of the instruction PC address and the global history of length L i where L N > L N-1 > … > L1 > 0. During prediction, all components (T0 to T N ) are accessed simultaneously, and each gives its own prediction information. Then, the ITTAGE predictor selects the target address target of the most suitable component as the final output based on the prediction information of each component and the prediction of the meta-predictor USE_ALT_ON_NA. This predictor can automatically allocate appropriate table entries for indirect jump branches according to the correctness of each prediction, thus well solving the problems existing in the above TTC and Cascade predictors. Moreover, through the multi-history length and multi-component cascading method, the prediction accuracy for indirect jump branches is greatly improved. However, although the ITTAGE predictor has many advantages as mentioned above, the area and power consumption of the ITTAGE predictor are large, and the complexity of the comparison algorithm is very high, so it will bring problems of power consumption and area to the processor.
[0009] In addition, the three indirect branch predictors proposed in the above research all use the global history for hash operations. This global history is a simple concatenation of the instruction path history and the direction history, without subdividing these two historical information. Experiments show that, as can be seen in Table 1, for indirect jump branches in some program flows, such as the test stimuli CLIENT05, CLIENT10, CLIENT11, CLIENT16, INT05, INT06, MM01, and SERVER04 provided by the Third Branch Prediction Tournament (https: / / jilp.org / jwac-2 / ), whether the indirect branch predictor uses the path history or the direction history for hash operations has a great impact on its prediction accuracy. Among them, the path history is the history of the least significant bit of the instruction PC address, and the direction history is the history of instruction jumps.
[0010] Table 1 shows the MPPKI values of the ITTAGE predictor using the path history, the direction history, and the global history for hash operations respectively. MPPKI is the misprediction penalty value per 1000 instructions on average. The smaller the MPPKI value, the higher the prediction accuracy of the predictor.
[0011] Table 1 MPPKI values of the ITTAGE predictor when using each history for hash calculation
[0012]
[0013] As can be seen from Table 1, when performing hash operations using path history, CLIENT05, CLIENT10, INT05, and INT06 have the highest prediction accuracy. However, when using global history for hash operations, the prediction accuracy will be affected by the direction history. On the other hand, when performing hash operations using direction history, CLIENT11, CLIENT16, MM01, and SERVER04 have the highest prediction accuracy. When using global history for hash operations, the prediction accuracy will be affected by the path history. Summary of the Invention
[0014] To solve the problem of the current indirect branch predictor being unable to fully utilize the advantages of path history and direction history information, resulting in low prediction accuracy, the present invention provides an indirect branch predictor and prediction method based on global history classification.
[0015] The first object of the present invention is to provide an indirect branch predictor based on global history classification, and the predictor includes:
[0016] A single target address prediction module, a multi-target address prediction module, a target address arbitration module, and a multiplexing module;
[0017] The single target address prediction module is connected to the multiplexing module, and the multi-target address prediction module is connected to the multiplexing module through the target address arbitration module;
[0018] The single target address prediction module is used to predict the target address of a single target indirect jump branch;
[0019] The multi-target address prediction module is used to predict the target addresses of multi-target indirect jump branches, and the multi-target address prediction module includes: two or more predictors with tag matching;
[0020] The target address arbitration module is used to select a target address from the multiple target addresses output by the multi-target address prediction module for output;
[0021] The multiplexing module selects and outputs the final target address according to the target addresses output by the single target address prediction module and the target address arbitration module.
[0022] Optionally, the single target address prediction module includes: a basic predictor P0; the multi-target address prediction module includes: a first predictor with tag matching P1 and a second predictor with tag matching P2;
[0023] The basic predictor P0 is used to predict the target address of a single target indirect jump branch, and the internal branch prediction table is indexed by the instruction PC address;
[0024] The first tagged matching predictor P1 and the second tagged matching predictor P2 are used to predict the target address of a multi-target indirect jump branch. Among them, the branch prediction table inside the first tagged matching predictor P1 is indexed by the hash result of the instruction PC address and the path history PHIST, and outputs the first target address target1; the branch prediction table inside the second tagged matching predictor P2 is indexed by the hash result of the instruction PC address and the direction history DHIST, and outputs the second target address target2.
[0025] Optionally, the target address arbitration module includes: a target address arbiter;
[0026] The target address arbiter selects the target address to be output according to the confidence levels of the first target address target1 and the second target address target2.
[0027] Optionally, the target address arbiter includes: a branch prediction table T whose table entries consist of m weight counters, a confidence level generation module, and a numerical comparator; the branch prediction table T, the confidence level generation module, and the numerical comparator are connected in sequence;
[0028] When the indirect branch predictor makes a prediction, the target address arbiter first indexes the branch prediction table T according to the hash results of the first target address target1 and the second target address target2 to obtain the weight counter values W0~W of the current indirect jump branch m-1 ; then the confidence level generation module calculates the confidence levels of the first target address target1 and the second target address target2 respectively according to the weight counter values W0~W m-1 , denoted as conf1 and conf2 respectively; finally, the numerical comparator selects the target address with the higher confidence level as the output according to the magnitude relationship between the confidence levels conf1 and conf2;
[0029] When the indirect branch predictor is updated, the target address arbiter needs to update the weight counter value of the index table entry in the branch prediction table T according to the actual target address of the indirect jump branch. The update method is:
[0030] If the i-th bit of the actual target address is 0, the corresponding weight counter value W i is decremented by 1, i.e., W i =W i -1;
[0031] If the i-th bit of the actual target address is 1, the corresponding weight counter value W i is incremented by 1, i.e., W i =W i+1。
[0032] Optionally, the calculation method of the confidence level is as follows:
[0033] conf = target[0] * W0 + target[1] * W1 +... + target[m - 1] * W m-1
[0034] where target[i] represents the i-th bit of the target address target, and 0 ≤ i ≤ m - 1.
[0035] Optionally, the multiplexing module includes: a multiplexer;
[0036] The multiplexer selects and outputs the final target address from the target address output by the basic predictor P0 and the target address arbiter according to the selection signal S generated by the target address arbiter.
[0037] Optionally, the selection signal S is:
[0038] S = hit1 || hit2
[0039] where hit1 is the hit signal output by the first tagged matching predictor P1, and hit2 is the hit signal output by the second tagged matching predictor P2;
[0040] The selection strategy of the multiplexer for the target address is:
[0041] If the selection signal S output by the target address arbiter is 1, then select the target address output by the target address arbiter as the final prediction for output;
[0042] If the selection signal S output by the target address arbiter is 0, then select the target address output by the basic predictor P0 as the final prediction for output.
[0043] Optionally, the basic predictor P0 is implemented by a branch target buffer BTB.
[0044] Optionally, the first tagged matching predictor P1 and the second tagged matching predictor P2 are implemented by a TTC predictor or an ITTAGE predictor.
[0045] The second object of the present invention is to provide an indirect branch prediction method based on global history classification. The method is implemented based on the above indirect branch predictor. The indirect branch prediction method includes:
[0046] S1: Use the base predictor P0 to predict the target address of a single-target indirect jump branch. The branch prediction table inside the base predictor P0 is indexed by the instruction PC address and outputs the base prediction target address target0;
[0047] Use the first tag-matching predictor P1 and the second tag-matching predictor P2 to predict the target address of a multi-target indirect jump branch, where:
[0048] The branch prediction table inside the first tag-matching predictor P1 is indexed by the hash result of the instruction PC address and the path history PHIST, and outputs the first target address target1;
[0049] The branch prediction table inside the second tag-matching predictor P2 is indexed by the hash result of the instruction PC address and the direction history DHIST, and outputs the second target address target2;
[0050] S2: The target address arbiter selects the target address with a higher confidence from the first target address target1 and the second target address target2 and outputs it;
[0051] Obtain the selection signal S of the multiplexer according to the hit signal hit1 output by the first tag-matching predictor P1 and the hit signal hit2 output by the second tag-matching predictor P2;
[0052] S3: The multiplexer selects and outputs the final target address from the base prediction target address target0 and the target address output by the target address arbiter according to the selection signal S.
[0053] The beneficial effects of the present invention are:
[0054] The indirect branch predictor proposed by the present invention abandons the scheme of using global history information for prediction in the existing indirect branch predictors, makes full use of the prediction advantages of the instruction path history and the direction history, and calculates the confidence levels of the target addresses indexed by the two histories respectively through the target address arbitration module, and selects the target address with a higher confidence as the output. Compared with the prior art, the present invention can effectively improve the prediction accuracy of the indirect branch predictor;
[0055] In addition, in the design of the branch predictor, the designer can flexibly select the implementation methods of the multi-objective address prediction module according to the requirements of the processor for performance, area, power consumption, etc., such as the TTC and ITTAGE predictors. Therefore, compared with the existing indirect branch predictors, the present invention can reasonably utilize hardware resources, overcome the problems of resource waste or insufficient number of ways, and has better applicability and a wider scope of application. Brief Description of the Drawings
[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0057] Figure 1 is a schematic structural diagram of an existing TTC indirect branch predictor.
[0058] Figure 2 is a block diagram of the structure of an existing Cascade indirect branch predictor.
[0059] Figure 3 is a schematic structural diagram of an existing ITTAGE indirect branch predictor.
[0060] Figure 4 is a block diagram of the structure of the indirect branch predictor based on global history classification provided by the present invention.
[0061] Figure 5 is a schematic structural diagram of the basic predictor P0 in the embodiment of the present invention implemented using an existing branch target buffer BTB.
[0062] Figure 6 is a schematic structural diagram of the predictors P1 and P2 in the embodiment of the invention implemented using an existing ITTAGE predictor.
[0063] Figure 7 is the process of the target address arbiter in the embodiment of the invention obtaining the weight counter value.
[0064] Figure 8 is a comparison simulation diagram of MPPKI between the indirect branch predictor provided by the present invention and the existing ITTAGE predictor. Detailed Embodiments
[0065] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will further describe the embodiments of the present invention in detail with reference to the drawings.
[0066] Embodiment 1:
[0067] This embodiment provides an indirect branch predictor based on global history classification. The indirect branch predictor includes: a basic predictor P0, a predictor P1 with tag matching, a predictor P2 with tag matching, a target address arbiter, and a multiplexer; both the predictor P1 and the predictor P2 are connected to the target address arbiter, and both the predictor P0 and the target address arbiter are connected to the multiplexer.
[0068] The basic predictor P0 is used to predict the target address of a single-target indirect jump branch, and can be implemented using an existing branch target buffer BTB. The branch prediction table inside P0 is indexed by the instruction PC address.
[0069] Both the predictor P1 and the predictor P2 are used to predict the target addresses of those multi-target indirect jump branches, and have similar functions and component structures, and can be implemented using existing TTC or ITTAGE predictors; the difference is that the branch prediction table inside P1 is indexed by the hash result of the instruction PC address and the path history PHIST, while the index address of the branch prediction table inside P2 is the hash result of the instruction PC address and the direction history DHIST.
[0070] The target address arbiter is used to select the target address with higher confidence from the target address target1 output by the predictor P1 and the target address target2 output by the predictor P2 for output, and obtain the selection signal S of the multiplexer according to the hit signal hit1 output by the predictor P1 and the hit signal hit2 output by the predictor P2.
[0071] The multiplexer is used to select a more appropriate target address from the target address target0 output by the basic predictor P0 and the target address output by the target address arbiter according to the selection signal S output by the target address arbiter as the final prediction output.
[0072] This embodiment designs and provides an indirect branch predictor based on global history classification. The indirect branch predictor can respectively utilize the prediction advantages of the instruction path history and the direction history, and calculate the confidence levels of the target addresses indexed by the two histories respectively according to the weight counter value in the target address arbiter, and select the target address with higher confidence as the output, so as to improve the prediction accuracy of the indirect branch predictor; moreover, the predictors P1 and P2 in the indirect branch predictor can be implemented using a variety of existing indirect branch predictors, such as TTC and ITTAGE predictors, etc., so that designers can flexibly select the implementation methods of the predictors P1 and P2 according to the performance and area requirements of the processor.
[0073] Embodiment Two:
[0074] This embodiment provides an indirect branch predictor based on global history classification. See Figure 4 , the indirect branch predictor includes: a basic predictor P0, a predictor P1 with tag matching, a predictor P2 with tag matching, a target address arbiter, and a multiplexer.
[0075] The basic predictor P0 is used to predict the target address of a single-target indirect jump branch, and is implemented using an existing branch target buffer BTB. Its structure is as Figure 5 shown.
[0076] Both predictors P1 and P2 are used to predict the target addresses of those multi-target indirect jump branches, and have similar functions and component structures; the structures of P1 and P2 implemented using existing ITTAGE predictors are as Figure 6 shown; the difference is that the branch prediction table inside P1 is indexed by the hash result of the instruction PC address and the path history PHIST, while the index address of the branch prediction table inside P2 is the hash result of the instruction PC address and the direction history DHIST.
[0077] The target address arbiter is used to select the target address with higher confidence from the target address target1 output by predictor P1 and the target address target2 output by predictor P2 for output, and to obtain the selection signal S of the multiplexer according to the hit signal hit1 output by predictor P1 and the hit signal hit2 output by predictor P2;
[0078] The implementation method of the function of the target address arbiter is:
[0079] (1) The selection strategy of the target address target1 and the target address target2
[0080] The target address arbiter includes a branch prediction table T whose table entries consist of m weight counters, a confidence generation module, and a numerical comparator; the branch prediction table T, the confidence generation module, and the numerical comparator are connected in sequence;
[0081] When the indirect branch predictor makes a prediction, the target address arbiter first indexes the branch prediction table T according to the hash results of the target addresses target1 and target2 to obtain the weight counter values W0 to W of the current indirect jump branch m-1 , this process can be seen in Figure 7 ; then the confidence generation module generates confidence according to the weight counter values W0 to W m-1Calculate the confidence levels of the target addresses target1 and target2 respectively, denoted as conf1 and conf2. Among them, the formula for calculating the confidence level conf based on the target address target is: conf = target[0]*W0 + target[1]*W1 +... + target[m - 1]*W m-1 , where target[i] represents the i-th bit of the target address target, 0 ≤ i ≤ m - 1; finally, the numerical comparator selects the target address with the higher confidence level as the output according to the magnitude relationship between conf1 and conf2;
[0082] When the indirect branch predictor is updated, the target address arbiter needs to update the weight counter value of the index entry in the branch prediction table T according to the actual target address of the indirect jump branch. The update method is:
[0083] (a) If the i-th bit of the actual target address is 0, then the value of the corresponding weight counter W i is decremented by 1, that is, W i = W i - 1;
[0084] (b) If the i-th bit of the actual target address is 1, then the value of the corresponding weight counter W i is incremented by 1, that is, W i = W i + 1;
[0085] (2) Generation method of the selection signal S
[0086] Perform a logical OR on the hit signal hit1 output by the predictor P1 and the hit signal hit2 output by the predictor P2 to obtain the selection signal S of the multiplexer, that is, S = hit1 || hit2.
[0087] The multiplexer is used to select a more appropriate target address from the target address target0 output by the basic predictor P0 and the target address output by the target address arbiter as the final prediction output according to the selection signal S output by the target address arbiter;
[0088] Among them, the selection strategy of the multiplexer for the target address is:
[0089] (a) If the selection signal S output by the target address arbiter is 1, then select the target address output by the target address arbiter as the final prediction for output;
[0090] (b) If the selection signal S output by the target address arbiter is 0, then select the target address output by the basic predictor P0 as the final prediction for output.
[0091] Embodiment III:
[0092] This embodiment provides an indirect branch prediction method based on global history classification. The method is implemented based on the indirect branch predictor described in Embodiment 1 or Embodiment 2, and includes:
[0093] S1: Use the basic predictor P0 to predict the target address of a single-target indirect jump branch. The branch prediction table inside the basic predictor P0 is indexed by the instruction PC address, and outputs the basic prediction target address target0;
[0094] Use the first tag-matching predictor P1 and the second tag-matching predictor P2 to predict the target address of a multi-target indirect jump branch, where:
[0095] The branch prediction table inside the first tag-matching predictor P1 is indexed by the hash result of the instruction PC address and the path history PHIST, and outputs the first target address target1;
[0096] The branch prediction table inside the second tag-matching predictor P2 is indexed by the hash result of the instruction PC address and the direction history DHIST, and outputs the second target address target2;
[0097] S2: The target address arbiter selects the target address with high confidence from the first target address target1 and the second target address target2 and outputs it;
[0098] Obtain the selection signal S of the multiplexer according to the hit signal hit1 output by the first tag-matching predictor P1 and the hit signal hit2 output by the second tag-matching predictor P2;
[0099] S3: The multiplexer selects and outputs the final target address from the basic prediction target address target0 and the target address output by the target address arbiter according to the selection signal S.
[0100] To verify the prediction accuracy of the indirect branch predictor and prediction method of the embodiments of the present invention, the present invention conducts an algorithm simulation experiment on the simulation model provided by the 3rd Championship Branch Prediction (http: / / www.jilp.org / jwac-2 / framework.html). This simulation model simulates a superscalar out-of-order processor with a 14-stage pipeline. The test stimuli of this simulation model include 5 categories (CLIENT, INT, MM, SERVER, WS), a total of 40 application programs, and approximately 50 million microinstructions.
[0101] The control experiment in this embodiment uses the champion predictor ITTAGE of the indirect branch predictor group of the third branch prediction tournament (for reference, see https: / / jilp.org / jwac-2 / program / JWAC-2-program.htm). The parameter configuration information of the ITTAGE predictor is shown in Table 2.
[0102] Table 2 Experimental parameters of the ITTAGE predictor
[0103]
[0104]
[0105] The parameter configuration of predictor P0 in this embodiment: the depth of the branch prediction table is 4K, and the width of the tag is 20.
[0106] The parameter configurations of predictors P1 and P2 in this embodiment are the same as those of the champion predictor ITTAGE.
[0107] The parameter configuration of the target address arbiter in this embodiment: the number m of weight counters is 8, the value range of the weight counters is 0 to 15, and the depth of the branch prediction table T is 0.5K.
[0108] Figure 8 Shows the comparison simulation diagram of MPPKI (Misprediction Penalty per Kilo Instructions) between the indirect branch predictor provided by the present invention and the ITTAGE predictor; MPPKI is the misprediction penalty value per 1000 instructions on average, and the smaller the MPPKI value, the higher the prediction accuracy of the predictor.
[0109] Figure 8 In, the abscissa is 40 application programs (sorted) of the third branch prediction tournament, and the ordinate is MPPKI ITTAGE* -MPPKI ITTAGE results, where ITTAGE* represents the indirect branch predictor provided by the present invention, predictors P1 and P2 are both implemented using ITTAGE, and ITTAGE represents the existing ITTAGE predictor; from Figure 8 The experimental results in can be seen that compared with the existing ITTAGE predictor in this embodiment, the average value of MPPKI is reduced by 0.6229, and the prediction accuracy is further improved.
[0110] Some steps in the embodiments of the present invention can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk, etc.
[0111] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. An indirect branch predictor based on global history classification, characterized in that, The indirect branch predictor includes: a single-target address prediction module, a multi-target address prediction module, a target address arbitration module, and a multiplexing module; The single-target address prediction module is connected to the multiplexing module, and the multi-target address prediction module is connected to the multiplexing module through the target address arbitration module; The single-target address prediction module is used to predict the target address of a single-target indirect jump branch; The multi-target address prediction module is used to predict the target address of a multi-target indirect jump branch; The target address arbitration module is used to select a target address for output according to the confidence levels of multiple target addresses output by the multi-target address prediction module; The multiplexing module selects and outputs a final target address according to the target addresses output by the single-target address prediction module and the target address arbitration module; The single-target address prediction module includes: a basic predictor P0; the multi-target address prediction module includes: a first tagged matching predictor P1 and a second tagged matching predictor P2; The basic predictor P0 is used to predict the target address of a single-target indirect jump branch, and the internal branch prediction table is indexed by the instruction PC address; The first tagged matching predictor P1 and the second tagged matching predictor P2 are used to predict the target address of a multi-target indirect jump branch. Among them, the internal branch prediction table of the first tagged matching predictor P1 is indexed by the hash result of the instruction PC address and the path history PHIST, and outputs a first target address target1; the internal branch prediction table of the second tagged matching predictor P2 is indexed by the hash result of the instruction PC address and the direction history DHIST, and outputs a second target address target2; The target address arbitration module includes: a target address arbiter; The target address arbiter selects the target address with a higher confidence level as the output according to the confidence levels of the first target address target1 and the second target address target2; The multiplexing module includes: a multiplexer; The multiplexer selects and outputs a final target address from the target address output by the basic predictor P0 and the target address arbiter according to the selection signal S generated by the target address arbiter; The selection signal S is: where hit1 is the hit signal output by the first tagged matching predictor P1, and hit2 is the hit signal output by the second tagged matching predictor P2; The selection strategy of the multiplexer for the target address is: If the selection signal S is 1, select the target address output by the target address arbiter as the final target address for output; If the selection signal S is 0, select the target address output by the basic predictor P0 as the final target address for output.
2. The indirect branch predictor according to claim 1, wherein The target address arbiter includes: a branch prediction table T, a confidence level generation module, and a numerical comparator; the table entries of the branch prediction table T include: m weight counters; the branch prediction table T, the confidence level generation module, and the numerical comparator are connected in sequence; When making a prediction using the indirect branch predictor, the target address arbiter first indexes the branch prediction table T based on the hash results of the first target address target1 and the second target address target2 to obtain the weight counter values W0 to W of the current indirect jump branch. m-1 Then, the confidence generation module calculates the confidence levels of the first target address target1 and the second target address target2 respectively according to the weight counter values W0 to W m-1 which are denoted as conf1 and conf2 respectively; finally, the value comparator selects the target address with a higher confidence level as the output according to the magnitude relationship between the confidence levels conf1 and conf2. When the indirect branch predictor is updated, the target address arbiter needs to update the weight counter value of the index entry in the branch prediction table T according to the actual target address of the indirect jump branch. The update method is as follows: If the i-th bit of the actual target address is 0, then the value W of the corresponding weight counter i is decremented by 1, that is ; If the i-th bit of the actual target address is 1, then the value W of the corresponding weight counter i is incremented by 1, that is .
3. The indirect branch predictor according to claim 2, wherein The calculation method of the confidence level is as follows: Among them, represents the i-th bit of the target address target, .
4. The indirect branch predictor according to claim 1, wherein The basic predictor P0 is implemented by using a branch target buffer BTB.
5. The indirect branch predictor according to claim 1, characterized in that, The first tagged matching predictor P1 and the second tagged matching predictor P2 are implemented by using a TTC predictor or an ITTAGE predictor.
6. An indirect branch prediction method based on global history classification, characterized in that The method is implemented based on the indirect branch predictor as claimed in claim 5. The indirect branch prediction method includes: S1: Use the basic predictor P0 to predict the target address of the single-target indirect jump branch. The branch prediction table inside the basic predictor P0 is indexed by the instruction PC address, and the basic prediction target address target0 is output. Use the first tagged matching predictor P1 and the second tagged matching predictor P2 to predict the target address of the multi-target indirect jump branch, where: The branch prediction table inside the first tagged matching predictor P1 is indexed by the hash result of the instruction PC address and the path history PHIST, and the first target address target1 is output. The branch prediction table inside the second tagged matching predictor P2 is indexed by the hash result of the instruction PC address and the direction history DHIST, and the second target address target2 is output. S2: The target address arbiter selects the target address with a high confidence level from the first target address target1 and the second target address target2 and outputs it. According to the hit signal hit1 output by the first tagged matching predictor P1 and the hit signal hit2 output by the second tagged matching predictor P2, obtain the selection signal S of the multiplexer. S3: The multiplexer selects and outputs the final target address from the basic prediction target address target0 and the target address output by the target address arbiter according to the selection signal S.