Resistor DAC Layout Structure

Abstract

The present invention provides a resistive DAC layout structure at least including a resistive structure, the resistive structure including a plurality of first sub-resistance structures and at least one second sub-resistance structure electrically connected; wherein the plurality of first sub-resistance structures are formed by a plurality of third resistors connected in series, and the plurality of first sub-resistance structures are arranged in a regular pattern; and the second sub-resistance structure is formed by a plurality of third resistors connected in series, the number of third resistors is greater than the number of third resistors in the first sub-resistance structure, and the second sub-resistance structure is arranged on at least one side of the plurality of first sub-resistance structures; and a metal connection is used to connect the plurality of adjacent first sub-resistance structures and at least one second sub-resistance structure. The present invention reduces the influence of parasitic, matching and other factors in the layout design on the accuracy, and the differential nonlinearity and integral nonlinearity indicators of the DAC of the present invention structure are effectively controlled within a certain resistance range.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a resistive DAC layout structure. Background Art

[0002] DAC (Digital to Analog Converter) is a device that converts digital signals into analog signals and is widely used in digital circuits. The biggest limitation of resistor-type DAC (digital analog converter) is the challenge of achieving high resolution and maintaining its linearity. The number of conventional resistor string DACs increases exponentially with the increase in resolution. Figure 1 ) This problem can be solved directly by using a binary weighted resistor ladder structure, reducing the required resistors from 2^n to about 3n. The characteristic of the R-2R structure is that the resistance value of each node in the circuit looking to the right is 2R.

[0003] However, the current R-2R structure is still limited by matching accuracy in high-performance applications. In addition to the resistor process deviation, the inevitable non-idealities in layout design, such as parasitic resistance, may cause problems such as poor matching accuracy and low linearity, thereby affecting DAC performance.

[0004] like Figure 1 As shown, it is an ideal R-2R structure. Figure 2 It is an R-2R structure with metal wiring resistance Rm between resistors. The absolute value and improper matching of the metal wiring resistance will affect the accuracy indicators of DAC, differential nonlinearity (DNL) and integral nonlinearity (INL).

[0005] In the existing R-2R structure DAC design, parasitics, matching and other factors in the layout design are often ignored, so its accuracy is difficult to improve. A high-precision resistor layout structure design is needed to improve the linearity of the R-2R structure DAC and make it more accurate. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a resistive DAC layout structure to solve the problem that in the existing R-2R structure DAC design in the prior art, factors such as parasitics and matching in the layout design are often ignored, making it difficult to improve its accuracy.

[0007] To achieve the above objectives and other related objectives, the present invention provides a resistive DAC layout structure, including:

[0008] A resistor structure, the resistor structure comprising a plurality of first sub-resistance structures and at least one second sub-resistance structure electrically connected;

[0009] Each of the first sub-resistance structures is formed by connecting a plurality of third resistors in series, and the plurality of the first sub-resistance structures are arranged at equal intervals; and

[0010] The second sub-resistance structure is formed by a plurality of third resistors connected in series, the number of third resistors is greater than the number of third resistors in the first sub-resistance structure, and the second sub-resistance structure is placed at the end of the plurality of first sub-resistance structures electrically connected;

[0011] A metal connection line, used to connect two adjacent first sub-resistance structures, and used to connect the first sub-resistance structure at the end with the second sub-resistance structure, so as to form a weighted resistance network in which the resistance values ​​of the metal connections are all equal;

[0012] The resistance value of the metal connection is less than a set threshold.

[0013] Preferably, the number of the third resistors in the first sub-resistance structure is three.

[0014] Preferably, the number of the third resistors in the second sub-resistance structure is four.

[0015] Preferably, the first sub-resistance structure and the second sub-resistance structure are both arranged in an S-shape.

[0016] Preferably, the set threshold is smaller than a minimum resistance value of the third resistor mismatch.

[0017] Preferably, the three third resistors connected in series in the first sub-resistance structure are defined as a fourth resistor, a fifth resistor and a sixth resistor in a series order, respectively;

[0018] The fourth resistor is defined as an R structure, and its resistance value is R. The fifth resistor and the sixth resistor are defined as a 2R structure, and their total resistance value is 2R. A free end of the fourth resistor away from the fifth and sixth resistors of the 2R structure is defined as a first end, and an end of the first fourth resistor close to the fifth and sixth resistors of the 2R structure is defined as a second end.

[0019] A free end of the sixth resistor away from the fifth resistor is defined as a weighted output end; and

[0020] The two free ends of the second sub-resistance structure are defined as two 2R structures connected in series, wherein the two 2R structures are defined as a weighted output end and a default end, respectively.

[0021] Preferably, the number of the second sub-resistance structure is one.

[0022] Preferably, in two adjacent first sub-resistance structures, one end of the metal line is electrically connected to the first end of one of the first sub-resistance structures, and the other end of the metal line is electrically connected to the second end of the other first sub-resistance structure; in adjacent first sub-resistance structures and second sub-resistance structures, one end of the metal line is electrically connected to the first end of the first sub-resistance structure, and the other end of the metal line is electrically connected to two third resistors without free ends in the second sub-resistance structure, and the overall structure formed is defined as a first arrangement layout structure.

[0023] Preferably, the number of the second sub-resistance structures is two, which are respectively arranged at the extreme ends on both sides of the plurality of sub-resistance structures, and the structure formed by them is defined as a second arrangement layout structure.

[0024] Preferably, the second arrangement layout structure is a symmetrical mirror structure, the second arrangement layout structure is a symmetrical mirror structure, and the first sub-resistance structures of the symmetrical structures in the second arrangement layout are connected in parallel with metal wires, so that the resistance value of the two first sub-resistance structures of the symmetrical structure after parallel connection is 2R.

[0025] Preferably, the method for making the resistance value of the two first sub-resistance structures connected in parallel to be 2R includes: providing the first layout structure with a symmetrical distribution; replacing the resistance value of the R structure therein with 2R, replacing the resistance value of the 2R structure with 4R, and replacing the resistance value of the third resistor with 2R; connecting the symmetrically distributed first sub-resistance structures in parallel through metal wiring, wherein the two ends of the metal connection are electrically connected to two symmetrical fifth resistors respectively.

[0026] Preferably, in two symmetrical first sub-resistance structures, two ends of the metal connection line are connected to two first ends respectively.

[0027] As described above, the resistive DAC layout structure of the present invention has the following beneficial effects:

[0028] The influence of parasitic and matching factors in layout design on the accuracy is reduced, and the differential nonlinearity (DNL) and integral nonlinearity (INL) indicators of the DAC of the structure of the present invention are effectively controlled within a certain resistance range, thereby improving the accuracy of the resistance-type DAC circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shows a schematic diagram of an ideal R-2R structure provided by the prior art;

[0030] Figure 2 Shown is a schematic diagram of an R-2R structure with parasitic resistance provided by the prior art;

[0031] Figure 3 Shown is a schematic diagram of a layout in an embodiment provided by the present invention;

[0032] Figure 4 Shown is a schematic diagram of a layout in another embodiment provided by the present invention;

[0033] Figure 5 Shown is a schematic diagram of a first sub-resistance structure in an embodiment provided by the present invention;

[0034] Figure 6 Shown is a schematic diagram of the second sub-resistance structure in an embodiment provided by the present invention.

[0035] in,

[0036] The first sub-resistance structure 11

[0037] The second sub-resistance structure 12

[0038] Metal Connection 2

[0039] The third resistor 3

[0040] The fourth resistor 31

[0041] Fifth resistor 32

[0042] The sixth resistor 33 . DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Embodiment 1

[0045] The present invention provides a resistive DAC layout structure, including the following graphics (wherein the following various structures are graphics in the layout design):

[0046] The resistor structure includes a plurality of first sub-resistance structures 11 and at least one second sub-resistance structure 12 which are electrically connected. The number of the first sub-resistance structures 11 is determined by the number of bits of a binary number in an actual design. The value represented by each 1 in a multi-bit binary number is called the weight of the bit.

[0047] In an optional implementation, the first sub-resistance structure 11 and the second sub-resistance structure 12 are both arranged in an S shape.

[0048] Wherein, a plurality of first sub-resistance structures 11 are formed by connecting a plurality of third resistors 3 in series, and the plurality of first sub-resistance structures 11 are arranged in a regular pattern;

[0049] In an alternative embodiment, see Figure 5 The number of the third resistors 3 in the first sub-resistance structure 11 is three, and the three third resistors 3 are alternately arranged in an S shape.

[0050] In an alternative embodiment, see Figure 6 The number of the third resistors 3 in the second sub-resistance structure 12 is four, and their arrangement is also alternating in an S-shape.

[0051] See also Figure 5 In a possible implementation, the first sub-resistance structure 11 uses three third resistors 3 connected in series, and the three third resistors 3 connected in series in the first sub-resistance structure 11 are respectively defined as a fourth resistor 31, a fifth resistor 32 and a sixth resistor 33;

[0052] The fourth resistor 31 is defined as an R structure, and its resistance value is R. The fifth resistor 32 and the sixth resistor 33 are defined as a 2R structure. Compared with the single resistor structure with a resistance value of 2R in the prior art, two resistor structures connected in series with a total resistance value of 2R are used to replace it. The end of the fourth resistor 31 away from the 2R structure is a free end, which is defined as the first end, and the end of the first resistor close to the 2R structure is defined as the second end.

[0053] An end of the sixth resistor 33 away from the fifth resistor 32 is defined as a weighted output end; and

[0054] The second sub-resistance structure 12 is defined as two 2R structures connected in series, wherein the two 2R structures are defined as a weighted output terminal and a default terminal, respectively.

[0055] The second sub-resistance structure 12 is formed by a plurality of third resistors 3 connected in series, wherein the number of third resistors 3 is greater than the number of third resistors 3 in the first sub-resistance structure 11, and the second sub-resistance structure 12 is arranged on at least one side of the plurality of first sub-resistance structures 11. In an asymmetric layout design, the first sub-resistance structure 11 can be set to one and can be arranged on the left or right side of the layout design. In a symmetric layout design, the second sub-resistance structure 12 is two symmetrically distributed.

[0056] The metal connection line 2 is used to connect the adjacent plurality of first sub-resistance structures 11 and at least one second sub-resistance structure 12, so as to form a weighted resistance network in which the resistance values ​​of the metal connection lines 2 are all equal. The metal connection lines 2 have resistance values, which may affect the accuracy of the layout design.

[0057] The resistance value of the metal connection 2 is less than the set threshold value. Specifically, the set threshold value is less than the minimum value of the mismatch of the third resistor 3. This resistance value is determined by the designed DAC accuracy. According to its accuracy requirements, the minimum value of the mismatch of the third resistor 3 is calculated. The resistance value of the metal connection 2 should be less than R*σ%, and σ% is determined according to the required accuracy to reduce the influence of the parasitic resistance to a negligible level.

[0058] Embodiment 2

[0059] In an alternative embodiment, see Figure 3 , the number of at least one second sub-resistance structure 12 is one.

[0060] In an optional embodiment, in a plurality of adjacent first sub-resistance structures 11, one end of the metal connection 2 is electrically connected to the first end of a second sub-resistance structure 12, and the other end of the metal connection 2 is electrically connected to the second end of another adjacent first sub-resistance structure 11; in adjacent first sub-resistance structures 11 and second sub-resistances, one end of the metal connection 2 is electrically connected to the first end of the first sub-resistance structure 11, and the other end of the metal connection 2 is electrically connected to two 2R structures in the second sub-resistance structure 12, and the overall structure formed is defined as a first arrangement layout structure.

[0061] Embodiment 3

[0062] In another alternative embodiment, see Figure 4 The number of at least one second sub-resistance structure 12 is two, which are respectively arranged on both sides of the multiple sub-resistance structures, and the structure formed by them is defined as a second arrangement layout structure.

[0063] In another optional implementation, the second arrangement layout structure is a symmetrical mirror structure, and metal wiring 2 is connected in parallel between the symmetrical structures in the second arrangement layout, so that the resistance value of the symmetrical structure after the connection is 2R.

[0064] In another optional embodiment, a method for making the resistance value of the symmetrical structure after parallel connection be 2R includes: providing a symmetrically distributed first layout structure; replacing the resistance value in the R structure therein with 2R, and replacing the resistance value of the 2R structure with 4R; connecting the symmetrically distributed first sub-resistance structures 11 in parallel through a metal connection 2, wherein the two ends of the metal connection are electrically connected to two symmetrical fifth resistors 32 respectively.

[0065] Embodiment 4

[0066] In an optional embodiment, through post-layout Virtuoso simulation verification, the R-2R DAC with different third resistor 3 values ​​is simulated using a model with a metal connection 2 resistor, which is 4Ω, 2Ω, and 0Ω in order. The first two are the metal connection 2 resistance values ​​simulated after layout, and 0Ω is the ideal model pre-simulation condition. It can be found that the differential nonlinearity (DNL) and integral nonlinearity (INL) indicators of the DAC using the structure of the present invention are effectively controlled within a certain resistance range. When the metal connection 2 resistance is 2Ω, the maximum DNL value is 0.16LSB, and the maximum INL value is 0.12LSB. Using the layout structure of the present invention, the existence of the metal connection resistance is only 0.05 to 0.1LSB larger than the ideal state.

[0067] The present invention has been verified by silicon, and the differential nonlinearity (DNL) and integral nonlinearity (INL) indicators of the DAC and ADC using the design scheme of the present invention meet the design expectations and have been successfully applied to the product end.

[0068] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0069] In summary, the present invention reduces the influence of parasitic and matching factors in layout design on the accuracy, and the differential nonlinearity (DNL) and integral nonlinearity (INL) indicators of the DAC of the present invention structure are effectively controlled within a certain resistance range. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A resistive DAC layout structure, characterized in that: At least: A resistor structure, the resistor structure comprising a plurality of first sub-resistance structures and at least one second sub-resistance structure electrically connected; Each of the first sub-resistance structures is formed by connecting a plurality of third resistors in series, and the plurality of the first sub-resistance structures are arranged at equal intervals; and The second sub-resistance structure is formed by a plurality of third resistors connected in series, the number of third resistors is greater than the number of third resistors in the first sub-resistance structure, and the second sub-resistance structure is placed at the end of the plurality of first sub-resistance structures electrically connected; A metal connection line, used to connect two adjacent first sub-resistance structures, and used to connect the first sub-resistance structure at the end with the second sub-resistance structure, so as to form a weighted resistance network in which the resistance values ​​of the metal connections are all equal; The resistance value of the metal connection is less than a set threshold.

2. The resistive DAC layout structure according to claim 1, wherein: The number of the third resistors in the first sub-resistance structure is three.

3. The resistive DAC layout structure according to claim 1, wherein: The number of the third resistors in the second sub-resistance structure is four.

4. The resistive DAC layout structure according to claim 1, wherein: The first sub-resistance structure and the second sub-resistance structure are both arranged in an S shape.

5. The resistive DAC layout structure according to claim 1, wherein: The set threshold is smaller than a minimum resistance value of the third resistor mismatch.

6. The resistive DAC layout structure according to any one of claims 1 to 5, characterized in that: The three third resistors connected in series in the first sub-resistance structure are defined as fourth to sixth resistors in the series order respectively; The resistance of the fourth resistor is R, the total resistance of the fifth resistor and the sixth resistor is 2R, the free end of the fourth resistor is defined as the first end, and the other end is defined as the second end; The free end of the sixth resistor is defined as a weighted output end; and The two free ends of the second sub-resistance structure are respectively defined as a weighted output end and a default end.

7. The resistive DAC layout structure according to claim 1, wherein: The number of the second sub-resistance structure is one.

8. The resistive DAC layout structure according to claim 7, characterized in that: In two adjacent first sub-resistance structures, one end of the metal line is electrically connected to the first end of one of the first sub-resistance structures, and the other end of the metal line is electrically connected to the second end of the other first sub-resistance structure; in adjacent first sub-resistance structures and second sub-resistance structures, one end of the metal line is electrically connected to the first end of the first sub-resistance structure, and the other end of the metal line is electrically connected to one end of a third resistor without a free end in the second sub-resistance structure, and the overall structure formed is defined as a first arrangement layout structure.

9. The resistive DAC layout structure according to claim 1, wherein: The number of the second sub-resistance structures is two, which are respectively arranged at the two ends of the plurality of sub-resistance structures, and the structure formed by them is defined as a second arrangement layout structure.

10. The resistive DAC layout structure according to claim 9, characterized in that: The second arrangement layout structure is a symmetrical mirror structure. The symmetrical first sub-resistance structures in the second arrangement layout are connected in parallel with metal wires, so that the resistance value of the two first sub-resistance structures connected in parallel is 2R.

11. The resistive DAC layout structure according to claim 10, characterized in that: In two adjacent first sub-resistance structures, one end of the metal connection is electrically connected to the first end of one of the first sub-resistance structures, and the other end of the metal connection is electrically connected to the second end of the other first sub-resistance structure; in adjacent first sub-resistance structures and second sub-resistance structures, one end of the metal connection is electrically connected to the first end of the first sub-resistance structure, and the other end of the metal connection is electrically connected to two third resistors without free ends in the second sub-resistance structure.

12. The resistive DAC layout structure according to claim 9 or claim 10, characterized in that: In the two symmetrical first sub-resistance structures, two ends of the metal connection line are respectively connected to the two first ends.

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