On-die testing of memory devices
By integrating an evaluation processor onto the memory die, the communication limitations and speed bottlenecks in the memory die evaluation process are resolved, enabling more efficient fault detection and repair, and improving the flexibility and information resolution of the evaluation.
CN114300031BActive Publication Date: 2026-07-24MICRON TECHNOLOGY INC
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2021-09-29
- Publication Date
- 2026-07-24
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Figure CN114300031B_ABST
Abstract
This application relates to on-die testing of memory devices. In some examples, a memory die can include processing circuitry configured to perform an evaluation of the memory die based on commands or instructions received from an external device. The processing circuitry can be configured to detect a failure of the memory die and transmit a relevant indication to the external device based on the on-die detection. In some examples, the processing circuitry can be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry can be configured to perform operations in accordance with an internally generated clock signal that operates at a faster rate or speed than a clock signal from the external device. In some examples, the processing circuitry can include analog-to-digital conversion capabilities for digital communication of analog characteristics internal to the memory die.
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