Processing method of semiconductor packaging structure and semiconductor packaging structure

Abstract

The present invention discloses a processing method of a semiconductor packaging structure and a semiconductor packaging structure, wherein the processing method comprises: providing a wafer, wherein a solder pad is exposed on a first surface of the wafer; sequentially forming a patterned first passivation layer and a wiring layer on the first surface, wherein the wiring layer is electrically connected to the solder pad; forming a patterned second passivation layer on the second surface; using the second passivation layer as a mask, performing a first set of etching steps on the wafer to etch a non-through hole on the wafer, wherein a preset distance exists between the bottom of the non-through hole and the first passivation layer; continuing to perform a second set of etching steps on the wafer to form a silicon through hole that penetrates the wafer, wherein the etching depth and etching rate of the first set of etching steps are greater than the etching depth and etching rate of the second set of etching steps; filling a dielectric layer at the bottom of the silicon through hole; back-etching to remove the dielectric layer and the first passivation layer at the position of the silicon through hole until the wiring layer is exposed; forming a metal column in the silicon through hole, wherein the metal column is electrically connected to the wiring layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a processing method of a semiconductor packaging structure and a semiconductor packaging structure. Background Art

[0002] Following Moore's Law, the minimum line width of the chip is getting smaller and smaller, but when it is small to a certain size, quantum effects will appear, changing the physical laws currently followed by the chip. This size reduction is mainly in the planar area. For packaging, if the three-dimensional space can be used, the integration of the chip will be increased, which can be regarded as a continuation of Moore's Law. Stacking packaging using three-dimensional space is called 3D system-level packaging, which has higher capacity, better performance, and higher yield. Compared with traditional packaging that processes a single chip, wafer-level packaging processes the entire wafer first and then cuts it, which can reduce processing costs.

[0003] To achieve 3D system-level packaging, through silicon via technology is a common method in the existing technology, so as to realize the interconnection between different chips in 3D space. Specifically speaking, the two most important steps are through silicon via etching and metal filling. When etching through silicon vias, the Bosch process is usually used (the Bosch process refers to the process of depositing a layer of etching film on the lateral side walls of the etching in order to prevent or weaken lateral etching in the manufacture of integrated circuits). However, after etching to the stop layer (the stop layer has chemical properties that are very different from the etched material. When etching to the stop layer, the etching effect is greatly weakened, achieving the effect of stopping etching), due to charge accumulation and high aspect ratio structure, the etching will proceed to both sides, thereby forming a bottom gap. Reference Figure 1 Specifically, since the plasma is electrically neutral as a whole, negative charges such as electrons are light in mass and move fast, and are easily quenched by objects such as the chamber wall. Therefore, the physical bombardment during etching is mainly caused by positively charged ions, which continuously accumulate positive charges on the insulating stop layer. When over-etching occurs (due to differences in etching rates, over-etching will inevitably occur), the physical bombardment will be reflected to form a bottom gap. If the bottom gap is too large, it will be impossible to fill the gap in the subsequent coating process, resulting in abnormalities such as device leakage.

[0004] Therefore, how to eliminate the gap at the bottom of the through hole is a problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the present invention is to provide a processing method of a semiconductor packaging structure and a semiconductor packaging structure, which can eliminate the problem of a gap at the bottom of a through silicon via.

[0006] Based on the above purpose, the present invention provides a method for processing a semiconductor packaging structure, comprising:

[0007] Providing a wafer, the wafer comprising a first surface and a second surface opposite to each other, the first surface of the wafer exposing a bonding pad;

[0008] Sequentially forming a patterned first passivation layer and a wiring layer on the first surface, wherein the wiring layer is electrically connected to the pad;

[0009] forming a patterned second passivation layer on the second surface;

[0010] Using the second passivation layer as a mask, performing a first set of etching steps on the wafer to etch a non-through hole on the wafer, wherein a preset distance exists between the bottom of the non-through hole and the first passivation layer;

[0011] Continuing to perform a second set of etching steps on the wafer to form a through silicon via penetrating the wafer, wherein the etching depth and etching rate of the first set of etching steps are greater than the etching depth and etching rate of the second set of etching steps;

[0012] Filling a dielectric layer at the bottom of the through silicon via;

[0013] Etching back to remove the dielectric layer and the first passivation layer at the location of the through silicon via until the wiring layer is exposed;

[0014] A metal column is formed in the through silicon via, the metal column electrically connecting the wiring layer.

[0015] In an optional solution, the first set of etching steps adopts a Bosch process, including multiple cycles, each cycle including:

[0016] Deposition step: ventilating a deposition gas into the reaction chamber to perform a deposition process;

[0017] Physical bombardment step: stopping the input of the deposition gas, introducing the etching gas into the reaction chamber under the first process condition, and performing a first etching on the wafer mainly based on the physical bombardment step;

[0018] Chemical etching step: continuously introducing etching gas, and performing a second etching mainly based on chemical etching on the wafer under a second process condition.

[0019] In an optional solution, the process conditions of the deposition step include: chamber pressure range 5-500mTorr, upper electrode power range 500-5000W, lower electrode power 0W, SF 6 Flow rate 0sccm, C 4 F 8 Flow rate 10~1000sccm;

[0020] The first process conditions include: chamber pressure range 5 ~ 500mTorr, upper electrode power range 500 ~ 5000W, lower electrode power range 5 ~ 500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0 sccm;

[0021] The second process conditions include: chamber pressure range 5 ~ 500mTorr, upper electrode power range 500 ~ 5000W, lower electrode power range 5 ~ 500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0sccm.

[0022] In an optional solution, the second group of etching steps adopts the Bosch process, and under third process conditions, the silicon through hole is finally formed by cyclically executing the deposition step and the etching step, wherein the chamber pressure of the second group of etching steps is greater than the chamber pressure of the first group of etching steps.

[0023] In an optional solution, the deposition step of the third process condition includes: chamber pressure range 5-500mTorr, upper electrode power range 500-5000W, lower electrode power 0W, SF 6 Flow rate 0sccm, C 4 F 8 The etching step of the third process condition includes: chamber pressure range 5 ~ 500mTorr, upper electrode power range 500 ~ 5000W, lower electrode power range 5 ~ 500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0sccm.

[0024] In an optional solution, the second set of etching steps is performed under a fourth process condition by single etching until the through silicon via is formed.

[0025] In the optional scheme, the fourth process conditions include: chamber pressure range 5-500mTorr; upper electrode power range 500-5000W; lower electrode power range 5-500W; oxygen flow rate 10-1000sccm; SF 6 Flow rate: 10~1000sccm.

[0026] In an optional solution, before filling the dielectric layer at the bottom of the through silicon via, the method includes: using a plasma etching process to remove the polymer in the through silicon via under a fifth process condition.

[0027] In the optional scheme, the fifth process conditions include: chamber pressure range 50-1000mTorr, upper electrode power range 750-3000W, lower electrode power range 5-500W, argon flow range 50-500sccm, oxygen flow range 50-500sccm, CF 4 Flow rate range: 50~500sccm.

[0028] In an optional solution, the dielectric layer is filled at the bottom of the through silicon via, including:

[0029] The sol-gel method is used to prepare the glue solution;

[0030] Applying the glue on the surface of the wafer by dipping and pulling method;

[0031] The wafer coated with the glue is subjected to heat treatment.

[0032] In an optional solution, the sol-gel method is used to prepare the glue solution, comprising:

[0033] Mixing and stirring tetraethyl orthosilicate, anhydrous ethanol and F-silane coupling agent to form a tetraethyl orthosilicate mixed liquid;

[0034] Adding nitric acid and dimethylformamide to adjust the pH value of the ethyl orthosilicate mixed solution so that the pH value is greater than 1;

[0035] The ethyl orthosilicate mixed solution, deionized water, dimethylformamide and nitric acid are mixed in a preset ratio to form the glue solution.

[0036] The present invention also provides a semiconductor packaging structure, which is manufactured by adopting the above processing method.

[0037] The beneficial effects of the present invention are:

[0038] The present invention adopts two groups of etching steps, wherein the rate of the second group of etching steps is lower than the rate of the first group of etching steps, so the process conditions of the second group of etching steps (such as chamber pressure, process gas flow, electrode power, etc.) are easier to control, that is, it is easy to grasp the etching progress at the bottom of the silicon via, and then it is easy to grasp the bottom morphology of the silicon via, which is conducive to eliminating the phenomenon of the gap at the bottom of the silicon via. When the dielectric layer is filled at the bottom of the silicon via and the dielectric layer is removed by back etching, the downward etching rate is greater than the lateral etching rate, which reduces the formation of the gap at the bottom of the silicon via (part of the dielectric layer remains on the sidewall of the formed silicon via), and the etching selectivity of the dielectric layer and the wafer is different (etching the dielectric layer is faster), so the formation of the bottom gap can be further reduced. The first group of etching steps is faster, which shortens the etching time for the overall formation of the silicon via.

[0039] The present invention has other features and advantages, which will be apparent from or will be described in detail in the accompanying drawings and the following detailed description incorporated herein, which together serve to explain the specific principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

[0041] Figure 1 A schematic diagram showing a notch at the bottom of a through silicon via in the prior art is shown.

[0042] Figure 2 A flow chart of a method for processing a semiconductor package structure according to an embodiment of the present invention is shown.

[0043] Figure 3 A structural schematic diagram corresponding to different steps of a method for processing a semiconductor packaging structure according to an embodiment of the present invention is shown.

[0044] Figure 4 A structural diagram of a through silicon via formed after the first set of etching steps is completed according to an embodiment of the present invention is shown.

[0045] Figure 5 The structure of the through silicon via formed after the second set of etching steps is completed according to an embodiment of the present invention is shown.

[0046] Figure 6 A structural diagram of a through silicon via formed after the second set of etching steps is completed according to another embodiment of the present invention is shown.

[0047] Figure 7 A schematic diagram of a through silicon via structure according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] The present invention will be described in more detail below. Although the present invention provides preferred embodiments, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0049] An embodiment of the present invention provides a method for processing a semiconductor packaging structure. Figure 2 A flow chart showing the steps of the method is shown. Figure 2 , the method comprising:

[0050] Providing a wafer, the wafer comprising a first surface and a second surface opposite to each other, the first surface of the wafer exposing a bonding pad;

[0051] Sequentially forming a patterned first passivation layer and a wiring layer on the first surface, wherein the wiring layer is electrically connected to the pad;

[0052] forming a patterned second passivation layer on the second surface;

[0053] Using the second passivation layer as a mask, performing a first set of etching steps on the wafer to etch a non-through hole on the wafer, wherein a preset distance exists between the bottom of the non-through hole and the first passivation layer;

[0054] Continuing to perform a second set of etching steps on the wafer to form a through silicon via penetrating the wafer, wherein the etching depth and etching rate of the first set of etching steps are greater than the etching depth and etching rate of the second set of etching steps;

[0055] Filling a dielectric layer at the bottom of the through silicon via;

[0056] Etching back to remove the dielectric layer and the first passivation layer at the location of the through silicon via until the wiring layer is exposed;

[0057] A metal column is formed in the through silicon via, the metal column electrically connecting the wiring layer.

[0058] The present invention adopts two groups of etching steps, wherein the rate of the second group of etching steps is lower than the rate of the first group of etching steps, so the process conditions of the second group of etching steps (such as chamber pressure, process gas flow, electrode power, etc.) are easier to control, that is, it is easy to grasp the etching progress of the bottom of the silicon via, and then it is easy to grasp the bottom morphology of the silicon via, which is conducive to eliminating the phenomenon of the gap at the bottom of the silicon via. When the dielectric layer is filled at the bottom of the silicon via and the dielectric layer is removed by back etching, since the downward etching rate is greater than the lateral etching rate, the formation of the gap at the bottom of the silicon via is reduced (part of the dielectric layer remains on the side wall of the formed silicon via, and the position of the dielectric layer remains is equivalent to the position of the bottom gap in the prior art), and the etching selectivity of the dielectric layer and the wafer is different (etching the dielectric layer is faster), so the formation of the bottom gap can be further reduced. The first group of etching steps is faster, which shortens the etching time for the overall formation of the silicon via. The etching depth of the first group of etching steps is greater than the etching depth of the second group of etching steps, and there is no strict limit on the ratio between the two. It can be understood that when the first group of etching steps reaches a certain depth and there is a tendency for a notch to form at the bottom of the through hole, it is more appropriate to start the second group of etching steps. In the optional example, the total depth of the silicon via is 50 microns, and the etching depth of the first group of etching steps is about 90% of the total depth of the through hole. It can be understood that the deeper the total depth of the silicon via, the greater the proportion of the etching depth of the second group of etching steps. In practical applications, the ratio of the etching depths of the two groups of etching steps can be selected according to the process accuracy requirements and speed requirements.

[0059] The first set of etching steps and the second set of etching steps both include multiple cycles. In one embodiment, the first set of etching steps adopts the Bosch process to form a better sidewall verticality.

[0060] In a specific example, the first group of etching steps includes multiple cycles, each cycle includes: a deposition step: ventilating a deposition gas into a reaction chamber to perform a deposition process; a physical bombardment step: stopping the input of the deposition gas, and under the first process conditions, introducing an etching gas into the reaction chamber to perform a first etching mainly based on the physical bombardment step on the wafer; a chemical etching step: continuously introducing an etching gas, and under the second process conditions, performing a second etching mainly based on chemical etching on the wafer. Among them, the first etching and the second etching both include physical bombardment and chemical etching, the intensity of the physical bombardment in the first etching is greater than the intensity of the chemical etching, and the intensity of the physical bombardment in the second etching is less than the intensity of the chemical etching. As described in the background art, the physical bombardment in etching is mainly caused by positively charged ions. When over-etching occurs (due to the difference in etching rates, over-etching will inevitably occur), the physical bombardment will be reflected to form a bottom notch. This method minimizes the formation of the bottom notch in the first group of etching steps and takes into account the etching speed.

[0061] In a specific example, the process conditions of the above deposition step include: chamber pressure range 5-500mTorr, upper electrode power range 500-5000W, lower electrode power 0W, SF 6 Flow rate 0sccm, C 4 F 8 Flow rate 10~1000sccm;

[0062] The first process conditions include: chamber pressure range 5 ~ 500mTorr, upper electrode power range 500 ~ 5000W, lower electrode power range 5 ~ 500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0 sccm;

[0063] The second process conditions include: chamber pressure range 5 ~ 500mTorr, upper electrode power range 500 ~ 5000W, lower electrode power range 5 ~ 500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0sccm.

[0064] For semiconductor devices with both middle and edge gas inlet, specifically, the gas inlet conditions of the above deposition step include: center SF 6 Flow rate 0sccm, edge SF 6 Flow rate 0sccm, center C 4 F 8 Flow rate 10~1000sccm, edge C 4 F 8 Flow rate 10~1000sccm, and center C 4 F 8 Flow rate below edge C 4 F 8 Flow rate; The first process conditions include: center SF 6 Flow rate 10~1000sccm sccm, edge SF 6 Flow rate 10~1000sccm, center C 4 F 8 Flow rate 0sccm, edge C 4 F 8 Flow rate 0sccm, and center SF 6 Traffic is higher than edge SF 6 Flow rate; The second process conditions include: center SF 6 Flow rate 10~1000sccm, edge C 4 F 8 Flow rate 0sccm, center C 4 F 8Flow rate 0sccm, edge C 4 F 8 Flow rate 0sccm, and center SF 6 Traffic is higher than edge SF 6 Flow rate. The above-mentioned central air intake and edge method can improve the accuracy and efficiency of etching. In one embodiment, the first group of etching steps and the second group of etching steps both adopt the Bosch process. Under the third process conditions, the second group of etching steps finally forms the silicon through hole by cyclically executing the deposition step and the etching step, wherein the chamber pressure of the second group of etching steps is greater than the chamber pressure of the first group of etching steps. A high chamber pressure can reduce the intensity of physical bombardment, reduce the reflection of positively charged ions, and thereby reduce the formation of bottom gaps. In a specific example, the deposition step of the third process condition includes: a chamber pressure range of 5 to 500 mTorr, an upper electrode power range of 500 to 5000 W, a lower electrode power of 0 W, and SF 6 Flow rate 0sccm, C 4 F 8 Flow rate 10~1000sccm;

[0065] The etching step of the third process condition includes: chamber pressure range 5-500mTorr, upper electrode power range 500-5000W, lower electrode power range 5-500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0sccm.

[0066] Similarly, for a semiconductor device with both middle gas inlet and edge gas inlet, specifically, the gas inlet conditions of the deposition step of the third process condition include: edge SF 6 Flow rate 0sccm, center SF 6 Flow rate 0sccm, edge C 4 F 8 Flow rate 10~1000sccm, center C 4 F 8 Flow rate 10~1000sccm, and center C 4 F 8 Flow rate below edge C 4 F 8 The inlet conditions of the etching step of the third process condition include: edge SF 6 Flow rate 10~1000sccm, center SF 6 Flow rate 10~1000sccm, edge C 4 F 8 Flow rate 0sccm, center C 4 F 8 Flow rate 0sccm, and center SF 6Traffic below edge SF 6 The above-mentioned central air intake and edge air intake can improve the etching accuracy and efficiency.

[0067] In another embodiment, the first group of etching steps adopts a Bosch process, the second group of etching steps adopts a non-Bosch process, and the second group of etching steps is etched in a single step under a fourth process condition until the through silicon via is formed. In a specific example, the fourth process condition includes: a chamber pressure range of 5 to 500 mTorr; an upper electrode power range of 500 to 5000 W; a lower electrode power range of 5 to 500 W; an oxygen flow rate of 10 to 1000 sccm; and a SF 6 Flow rate: 10~1000sccm.

[0068] In one embodiment, before the dielectric layer is filled at the bottom of the silicon through hole, the process includes: using a plasma etching process to remove the polymer in the silicon through hole under the fifth process conditions. The fifth process conditions include: a chamber pressure range of 50 to 1000 mTorr, an upper electrode power range of 750 to 3000 W, a lower electrode power range of 5 to 500 W, an argon flow range of 50 to 500 sccm, an oxygen flow range of 50 to 500 sccm, and a CF 4 The flow rate range is 50 to 500 sccm. Compared with the wet removal process, the plasma etching process can make the side wall of the through hole hydrophilic, which is conducive to the subsequent sol-gel method to form the dielectric layer. The sol-gel method will be described in detail later. The dielectric layer can also be formed by other methods. The material of the dielectric layer can be silicon oxide, silicon nitride, aluminum oxide, etc. In the optional example, the material of the dielectric layer is the same as the material of the passivation layer. When the dielectric layer is removed by etching back, the passivation layer at the bottom of the dielectric layer is directly removed, which can simplify the process flow.

[0069] refer to Figure 3 , each step of this method is introduced in detail.

[0070] Step 1: providing a device wafer, wherein a bonding pad is exposed on a first surface of the device wafer.

[0071] Step 2: Form a passivation layer, which covers the first surface and the pad. Use PECVD to grow a passivation layer such as silicon oxide or silicon nitride, with a thickness of 0.1 to 2 microns, preferably 0.5 microns, wherein the chamber pressure can be in the range of 20 to 200 Pa, the plasma power can be in the range of 50 to 500 W, and SiH 4 The flow rate range is 5~150sccm, N 2 The flow rate range of O is 100~5000sccm, N 2The flow rate range is 100-5000sccm, the growth temperature range is 100-500°C, and the growth time is selected according to the thickness and growth rate. For example, it takes 1450s to grow the preferred thickness of 0.5 microns under the above-mentioned preferred conditions. 2 O is used to provide oxygen ions and adjust the discharge characteristics of plasma (it is easier to ionize than other gases), while N 2 It plays the role of diluting the reactants.

[0072] Step 3: Spin-coat photoresist on the passivation layer with a thickness of 0.5 to 10 microns, preferably 3 microns.

[0073] Step 4, exposure and development. The mask template is designed and processed in advance as needed. The exposure time is preferably 6 seconds, with a range of 3 to 20 seconds. The development time is preferably 75 seconds, with a range of 45 to 120 seconds. The fixing time is preferably 120 seconds, with a range of 60 to 300 seconds, to pattern the photoresist and expose the area where the silicon through hole needs to be formed.

[0074] Step 5: Etch the passivation layer to expose the area where the pad is located. For example, if the passivation layer is silicon dioxide, the chamber pressure range is 1 to 30 mTorr, the upper electrode power range is 600 to 3000 W, the lower electrode power range is 50 to 500 W, the argon flow range is 10 to 100 sccm, and the CF 4 Flow rate range 10~100sccm (C 4 F 8 , CHF 3 and other carbon-fluorine gases), the base coolant temperature range is -15 to 10°C.

[0075] Step 6: Wet degumming (organic solution, such as acetone, etc.) to obtain a device wafer with a passivated surface and holes on the pads.

[0076] Step 7: Form a photoresist mask to expose the area where the RDL (redistribution layer) circuit needs to be formed.

[0077] Step 8, PVD plating of metal titanium and copper, wherein the thickness of titanium is 0.05-0.2 microns, preferably 0.1 microns, and the thickness of copper is 0.1-0.5 microns, preferably 0.3 microns. In terms of process conditions, the chamber pressure range is 10-100 mTorr, the upper electrode power range is 750-3000 W, the lower electrode power range is 5-500 W, and the argon flow rate range is 50-500 sccm.

[0078] Step 9: electroplating copper with a thickness of 0.5 to 5 microns, preferably 2 microns, to prepare RDL (redistribution layer) circuits.

[0079] Step 10: Wet stripping (organic solution, such as acetone, etc.) to obtain a surface-passivated device wafer with RDL prepared.

[0080] Step 11: flip the wafer, spin-coat photoresist, expose and develop under similar conditions as above.

[0081] Step 12: performing a first set of etching steps and a second set of etching steps in sequence to form through-silicon vias penetrating the wafer on the second surface.

[0082] The first set of etching steps uses the Bosch process, and the process recipe is shown in Table 1:

[0083] Table 1

[0084]

[0085] * The power of the lower electrode increases from the initial value to the final value as the number of cycles increases;

[0086] **The flow rate increases from the initial value to the final value as the number of cycles increases;

[0087] ***The single-step process time increases from the initial value to the final value as the number of cycles increases.

[0088] The through-hole structure formed is as follows Figure 4 As shown, in this step, etching is first performed to a position about 2 microns away from the passivation layer. The etching depth in this step is about 50 microns.

[0089] The Bosch process is used to perform the second set of etching steps, and the process recipe used is shown in Table 2.

[0090] Table 2

[0091]

[0092] * The flow rate increases from the initial value to the final value as the number of cycles increases.

[0093] The optional ranges of the above two groups of Bosch process recipes are: chamber pressure range 5 ~ 500mTorr, the chamber pressure of the second group of Bosch process is significantly higher than that of the first group (the beneficial effects refer to the previous text), the upper electrode power range 500 ~ 5000W, the lower electrode power range 5 ~ 500W, the center SF 6 Flow rate 10~1000sccm, edge SF 6 Flow rate 10~1000sccm, center C 4 F 8 Flow rate 10~1000sccm, edge C 4 F 8The flow rate is 10 to 1000 sccm, and the process time is not limited in range, depending on the etching depth. Figure 5 shown.

[0094] In another example, the second set of etching steps is a non-Bosch process, and the process recipe used is shown in Table 3:

[0095] Table 3

[0096]

[0097] The optional range of the above process recipe is: chamber pressure range 5-500mTorr, preferably 50mTorr; upper electrode power range 500-5000W, preferably 1200W; lower electrode power range 5-500W, preferably 50W; oxygen flow rate 10-1000sccm, preferably 50sccm; SF 6 The flow rate is 10 to 1000 sccm, preferably 50 sccm; the process time is not limited in range and depends on the etching depth. Figure 6 shown.

[0098] Step 13: Remove the residual polymer in the previous process by direct plasma etching. This step can make the side wall of the through hole hydrophilic, which is conducive to the subsequent sol-gel method. In terms of process conditions, the chamber pressure range is 50-1000mTorr, the upper electrode power range is 750-3000W, the lower electrode power range is 5-500W, the argon flow range is 50-500sccm, the oxygen flow range is 50-500sccm, and the CF 4 The flow rate range is 50 to 500 sccm, and the etching time should ensure that there is some photoresist left.

[0099] Step 14, fill the dielectric layer at the bottom of the silicon through hole, prepare the oxygen glue solution by sol-gel method; apply the glue solution on the surface of the wafer by immersion and pulling method; and heat treat the wafer coated with the glue solution. The method for preparing the glue solution includes: mixing and stirring ethyl orthosilicate, anhydrous ethanol, and F-silane coupling agent to form a ethyl orthosilicate mixed solution; adding nitric acid and dimethylformamide to adjust the pH value of the ethyl orthosilicate mixed solution so that the pH value is greater than 1; mixing the ethyl orthosilicate mixed solution, deionized water, dimethylformamide and nitric acid in a preset ratio to form the glue solution. Specifically, using tetraethyl orthosilicate as a precursor, first, 1 / 2 of the amount of tetraethyl orthosilicate and anhydrous ethanol are mixed and stirred in a blender for 10 minutes; another 1 / 2 of the amount of tetraethyl orthosilicate and anhydrous ethanol are also mixed, and no stirring is required after mixing. Instead, F-silane coupling agent is added, and the three are stirred for 10 minutes. After the above two mixtures are stirred, both are added to a three-necked flask at the same time. In order to make the mixing more complete, it is necessary to stir it again. After stirring, nitric acid and dimethylformamide are added to adjust the pH of the entire mixed solution to ensure that the pH of the solution is greater than 1, and then the mixed solutions are allowed to continue to react at a constant temperature of 55°C, and the stand-by mixture containing tetraethyl orthosilicate, deionized water, dimethylformamide and nitric acid is taken out, and the molar ratio of the substance is: 21:81:4:1 to obtain a glue solution. The wafer surface is evenly coated with glue using the immersion and pulling method. After coating, the wafer is placed in an oven for heat treatment. The treatment time is generally about 15 minutes and the treatment temperature is 40°C.

[0100] Step 15: Back-etching and bottom opening, removing the silicon oxide at the bottom after filling (the silicon oxide can be 2-3 microns) and the passivation layer at the bottom of the silicon oxide, the conditions are similar to step 5. Figure 7 shown.

[0101] Step 16: PVD-plating a titanium nitride barrier layer with a thickness of 0.2 to 1 micron, preferably 0.5 micron. The process conditions are similar to those of step 8.

[0102] Step 17, PVD plating of metal titanium and copper, wherein the thickness of titanium is 0.05-0.2 microns, preferably 0.1 microns, and the thickness of copper is 0.1-0.5 microns, preferably 0.3 microns, and the process conditions are similar to step 8.

[0103] Step 18: electroplating copper to fill the inside of the through hole. In terms of process conditions, the voltage range is 1 to 30 V, preferably 5 V, and the current range is 1 to 100 mA / cm2, preferably 75 mA / cm2.

[0104] Step 19: Wet degumming (organic liquid, such as acetone, etc.).

[0105] Step 20, etching to expose the copper in the through hole, the optional range of the process recipe is: chamber pressure range 5 ~ 500mTorr, preferably 25mTorr; upper electrode power range 500 ~ 5000W, preferably 2200W; lower electrode power range 30 ~ 500W, preferably 50W; SF6 flow rate 10 ~ 1000sccm, preferably 750sccm; process time has no range limit, depending on the etching depth.

[0106] Step 21: forming a passivation layer covering the surface of the wafer, the conditions are similar to step 2.

[0107] Step 22: Etch the passivation layer to expose the RDL wiring layer.

[0108] Step 23: Bonding to achieve 3D stacking. Finally, wafer dicing is performed.

[0109] An embodiment of the present invention also provides a semiconductor packaging structure, which is manufactured using the processing method described above. In this embodiment, two groups of etching steps are used to form silicon through holes, wherein the rate of the second group of etching steps is less than the rate of the first group of etching steps, so the process conditions of the second group of etching steps (such as chamber pressure, process gas flow, electrode power, etc.) are easier to control, that is, it is easy to grasp the etching progress at the bottom of the silicon through hole, and then it is easy to grasp the bottom morphology of the silicon through hole, which is conducive to eliminating the phenomenon of the gap at the bottom of the silicon through hole. When the dielectric layer is filled at the bottom of the silicon through hole and the dielectric layer is removed by etching back, since the downward etching rate is greater than the lateral etching rate, the formation of the gap at the bottom of the silicon through hole is reduced (part of the dielectric layer remains on the sidewall of the formed silicon through hole), and the etching selectivity of the dielectric layer and the wafer is different (the dielectric layer is etched faster), so the formation of the bottom gap can be further reduced. The first group of etching steps is faster, which shortens the etching time for the overall formation of the silicon through hole.

[0110] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for processing a semiconductor packaging structure, It is characterized in that include: Providing a wafer, the wafer comprising a first surface and a second surface opposite to each other, the first surface of the wafer exposing a bonding pad; Sequentially forming a patterned first passivation layer and a wiring layer on the first surface, wherein the wiring layer is electrically connected to the pad; forming a patterned second passivation layer on the second surface; Using the second passivation layer as a mask, performing a first set of etching steps on the wafer to etch a non-through hole on the wafer, wherein a preset distance exists between the bottom of the non-through hole and the first passivation layer; Continuing to perform a second set of etching steps on the wafer to form a through silicon via penetrating the wafer, wherein the etching depth and etching rate of the first set of etching steps are greater than the etching depth and etching rate of the second set of etching steps; Using a plasma etching process to remove the polymer in the through silicon via under a fifth process condition; Filling a dielectric layer at the bottom of the through silicon via, wherein the dielectric layer fills the gap around the bottom of the through silicon via; Back-etching and removing the dielectric layer and the first passivation layer at the position of the through silicon via until the wiring layer is exposed to form a final through silicon via, and the dielectric layer filling the gap position is retained on the side wall of the final through silicon via; forming a metal column in the through silicon via, wherein the metal column is electrically connected to the wiring layer; Wherein, the dielectric layer is filled at the bottom of the through silicon via, including: The sol-gel method is used to prepare the glue solution; Applying the glue on the surface of the wafer by dipping and pulling method; The wafer coated with the glue is subjected to heat treatment.

2. The method for processing a semiconductor packaging structure according to claim 1, It is characterized in that The first set of etching steps adopts the Bosch process and includes multiple cycles, each cycle including: Deposition step: ventilating a deposition gas into the reaction chamber to perform a deposition process; Physical bombardment step: stopping the input of the deposition gas, introducing the etching gas into the reaction chamber under the first process condition, and performing a first etching on the wafer mainly based on the physical bombardment step; Chemical etching step: continuously introducing etching gas, and performing a second etching mainly based on chemical etching on the wafer under a second process condition.

3. The method for processing a semiconductor packaging structure according to claim 2, It is characterized in that The process conditions of the deposition step include: chamber pressure range 5-500mTorr, upper electrode power range 500-5000W, lower electrode power 0W, SF 6 Flow rate 0sccm, C 4 F 8 Flow rate 10~1000sccm; The first process conditions include: chamber pressure range 5 ~ 500mTorr, upper electrode power range 500 ~ 5000W, lower electrode power range 5 ~ 500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0 sccm; The second process conditions include: chamber pressure range 5 ~ 500mTorr, upper electrode power range 500 ~ 5000W, lower electrode power range 5 ~ 500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0sccm.

4. The method for processing a semiconductor packaging structure according to claim 2, It is characterized in that The second set of etching steps adopts the Bosch process, and under the third process conditions, the silicon through hole is finally formed by cyclically executing the deposition step and the etching step, wherein the chamber pressure of the second set of etching steps is greater than the chamber pressure of the first set of etching steps.

5. The method for processing a semiconductor packaging structure according to claim 4, It is characterized in that The deposition step of the third process condition includes: chamber pressure range 5-500mTorr, upper electrode power range 500-5000W, lower electrode power 0W, SF 6 Flow rate 0sccm, C 4 F 8 Flow rate 10~1000sccm; The etching step of the third process condition includes: chamber pressure range 5-500mTorr, upper electrode power range 500-5000W, lower electrode power range 5-500W, SF 6 Flow rate 10~1000sccm, C 4 F 8 Flow rate 0sccm.

6. The method for processing a semiconductor packaging structure according to claim 2, It is characterized in that The second set of etching steps is performed under a fourth process condition by single-step etching until the through silicon via is formed.

7. The method for processing a semiconductor packaging structure according to claim 6, It is characterized in that The fourth process conditions include: chamber pressure range 5-500mTorr; upper electrode power range 500-5000W; lower electrode power range 5-500W; oxygen flow rate 10-1000sccm; SF 6 Flow rate: 10~1000sccm.

8. The method for processing a semiconductor packaging structure according to claim 1, It is characterized in that The fifth process conditions include: chamber pressure range 50-1000 mTorr, upper electrode power range 750-3000 W, lower electrode power range 5-500 W, argon flow range 50-500 sccm, oxygen flow range 50-500 sccm, CF 4 Flow rate range: 50~500sccm.

9. The method for processing a semiconductor packaging structure according to claim 1, It is characterized in that The sol-gel method is used to prepare the glue solution, comprising: Mixing and stirring tetraethyl orthosilicate, anhydrous ethanol and F-silane coupling agent to form a tetraethyl orthosilicate mixed liquid; Adding nitric acid and dimethylformamide to adjust the pH value of the ethyl orthosilicate mixed solution so that the pH value is greater than 1; The ethyl orthosilicate mixed solution, deionized water, dimethylformamide and nitric acid are mixed in a preset ratio to form the glue solution.

10. A semiconductor packaging structure, It is characterized in that The invention is manufactured by the processing method described in any one of claims 1 to 9.

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