Substrate with buried conductor under active area for enhanced thermal conductivity and RF shielding

Abstract

The invention relates to a substrate with a buried conductor under an active region for enhanced thermal conductivity and RF shielding. A semiconductor device is provided, comprising a substrate with a merged cavity in the substrate. An active region is located above the merged cavity in the substrate. A thermally conductive layer is located in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavity in the substrate with a metallization layer above the active region.

Description

TECHNICAL FIELD

[0001] The disclosed embodiments relate generally to semiconductor devices, and more particularly to semiconductor devices with improved thermal conductivity and methods of manufacturing the same. BACKGROUND

[0002] As more devices are packed onto a single chip, the scaling of semiconductor devices results in an increase in power density. Heat needs to be transferred out of the device during device operation to improve device performance and reliability. The generated heat can be transferred from the device to an external heat sink.

[0003] The heat conduction from the device to the external heat sink is less efficient because the heat is conducted through semiconductor device layers (e.g., substrate layers or dielectric layers) that have low thermal conductivity. The inefficient heat transfer can result in an increase in device temperature during device operation, which causes a decrease in device performance and reliability. Therefore, there is a need for an improved semiconductor device to overcome the above challenges. SUMMARY

[0004] In an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a substrate having a merged cavity therein. An active region is located over the merged cavity in the substrate. A thermally conductive layer is located in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavity in the substrate with a metallization layer over the active region.

[0005] In another aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a substrate having a merged cavity therein. An active region is located over the merged cavity in the substrate, wherein the active region includes an epitaxial layer. The merged cavity in the substrate can extend across at least a portion of a width and a length of the active region. A thermally conductive layer is located in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavity in the substrate with a metallization layer over the active region.

[0006] In yet another aspect of the disclosure, a method of manufacturing a semiconductor device is provided. The method includes providing a substrate having a merged cavity therein. An active region is disposed over the merged cavity in the substrate. A thermally conductive layer is formed in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate. A first contact pillar is formed that connects the thermally conductive layer in the merged cavity in the substrate with a metallization layer over the active region.

[0007] Many advantages can be obtained from the embodiments described below. Embodiments provide semiconductor devices with improved thermal conductivity. The devices can be fabricated using front-side processing steps, providing efficient integration with conventional semiconductor device fabrication. The thermally conductive layer in the substrate in the cavity incorporated can be precisely aligned in the substrate with respect to the active region in the device in terms of lateral position or depth, resulting in more efficient heat transfer during device operation. Heat generated during device operation can also be conducted from the active region to the thermally conductive layer in the cavity incorporated in the substrate through a contact pillar to an external heat sink. The contact pillar can be a through-silicon via (TSV) or a trench. The thermally conductive layer in the cavity incorporated in the substrate can also provide radio frequency (RF) or Faraday shielding between the substrate and RF devices in the active region. BRIEF DESCRIPTION OF DRAWINGS

[0008] The disclosed embodiments will be better understood from reading the following detailed description in conjunction with the drawings, in which:

[0009] FIG. 1A is a cross-sectional view of a semiconductor device according to an embodiment of the disclosure.

[0010] FIG. 1B is a schematic top view of a semiconductor device according to an embodiment of the disclosure.

[0011] FIGS. 2-18 shows a semiconductor device according to an embodiment of the disclosure. FIG. 1A is a manufacturing process flow for a semiconductor device.

[0012] FIG. 19 is a cross-sectional view of a semiconductor device according to another embodiment of the disclosure.

[0013] FIG. 20 is a cross-sectional view of a semiconductor device according to another embodiment of the disclosure.

[0014] For the sake of illustration and clarity, the drawings illustrate the general manner of construction, and specific description and details of well-known features and techniques can be omitted to prevent unnecessarily obscuring the discussion of the embodiments of the devices being described. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings can be exaggerated relative to other elements to help improve understanding of the embodiments of the devices. The same reference numbers in different drawings represent the same elements, while similar reference numbers can but do not necessarily represent similar elements. DETAILED DESCRIPTION

[0015] The following detailed description is exemplary in nature and is not intended to limit the devices or the application and uses of the devices. Furthermore, there is no intention to be bound by any theory of prior background or any theory presented in the following detailed description.

[0016] FIG. 1Ais a cross-sectional view of a semiconductor device 100 according to embodiments of the present disclosure. In one embodiment, the semiconductor device 100 can be a complementary metal-oxide-semiconductor (CMOS) or any other suitable semiconductor device. Referring to FIG. 1A The semiconductor device 100 includes a substrate 102 having a merged cavity 108 therein. An active region 138 is over the merged cavity 108 in the substrate 102. The active region 138 can include an epitaxial layer 132. A thermally conductive layer 148 can be located in the merged cavity 108 in the substrate 102, where the thermally conductive layer 148 at least partially fills the merged cavity 108 in the substrate 102. A first contact pillar 120a connects the thermally conductive layer 148 in the merged cavity 108 in the substrate 102 with a metallization layer 128 over the active region 138. The thermally conductive layer 148 can be made of a thermally conductive material having a higher thermal conductivity than silicon, such as copper (Cu), tungsten (W), graphene, aluminum nitride (AIN), carbon nanotubes (CNT), diamond (C), or any other suitable thermally conductive material.

[0017] The substrate 102 and the epitaxial layer 132 can be made of silicon (Si), other elemental semiconductor materials such as germanium (Ge), or compound semiconductors. The compound semiconductors can include gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), another suitable compound semiconductor, or combinations thereof. In some embodiments, the substrate 102 and the epitaxial layer 132 can be made of the same semiconductor material. In further embodiments, the substrate 102 and the epitaxial layer 132 can be made of different semiconductor materials.

[0018] The active region 138 can include the epitaxial layer 132 and a gate stack 106 of a transistor over the epitaxial layer 132. Although not shown, the active region 138 can include source, drain, and well regions located in the epitaxial layer 132. An isolation structure 110 can be formed in the epitaxial layer 132. In some embodiments, the isolation structure 110 can be a shallow trench isolation (STI) structure. The isolation structure 110 can extend at least across a partial thickness of the epitaxial layer 132. In further embodiments, the isolation structure 110 can extend across an entire thickness of the epitaxial layer 132. Although not shown, the active region 138 can further include an RF device or any other suitable active or passive device.

[0019] A plug 112 can be formed over an upper portion of the merged cavity 108 in the substrate 102. The plug 112 is an optional feature of embodiments and can be made of germanium, silicon, or any other suitable semiconductor material. The plug 112 can seal the upper portion of the merged cavity 108 in the substrate 102. The merged cavity 108 in the substrate 102 can directly contact the epitaxial layer 132 of the active region 138.

[0020] In one embodiment, an air gap 118 can extend across the merged cavity 108 in the substrate 102, where the air gap 118 can be surrounded by a thermally conductive layer 148. The air gap 118 is caused by the merged cavity 108 in the substrate 102 being incompletely filled by the thermally conductive layer 148. In further embodiments, the thermally conductive layer 148 can completely fill the remaining portion of the merged cavity 108 in the substrate 102 below the plug 112, thereby eliminating the air gap 118.

[0021] A dielectric liner 116 can be located on the sidewalls of the upper portion of the merged cavity 108 in the substrate 102, where the dielectric liner 116 can be disposed below the plug 112. The thermally conductive layer 148 in the merged cavity 108 in the substrate 102 can be electrically grounded by connecting the metallization layer 128 to a ground terminal. In embodiments, the metallization layer 128 can be connected to an external heat sink to further dissipate heat generated from the active region 138. In embodiments, the dielectric liner 116 can be located on a portion of the lower portion of the merged cavity 108 in the substrate 102 and expose the bottom of the merged cavity 108 in the substrate 102. As such, the bottom of the merged cavity 108 in the substrate 102 is not covered by the dielectric liner 116. The thermally conductive layer 148 can be in contact with the substrate 102 through the bottom of the merged cavity 108 in the substrate 102, thereby providing an alternative thermally conductive path for heat to dissipate from the substrate 102 through the thermally conductive layer 148 to the first and second contact pillars 120a and 120b, respectively. The dielectric liner 116 can be made of thermally grown or deposited silicon dioxide (Si02), aluminum oxide (AI2O3), or any other suitable electrically isolating dielectric material.

[0022] The second contact pillar 120b can connect the thermally conductive layer 148 in the merged cavity 108 in the substrate 102 with the metallization layer 128 above the active region 138. The first and second contact pillars 120a and 120b can be made of a suitable thermally conductive material, including copper (Cu), tungsten (W), or any other suitable thermally conductive material. In some embodiments, the first and second contact pillars 120a and 120b can be made of the same material as the thermally conductive layer 148. In further embodiments, the first and second contact pillars 120a and 120b can be made of a different material than the thermally conductive layer 148. A barrier liner material 122 can be formed on the sidewalls of the first and second contact pillars 120a and 120b. The barrier liner material 122 can be made of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), or any other suitable barrier liner material. The first and second contact pillars 120a and 120b can be metal wires, metal trenches, or through-silicon vias (TSVs).

[0023] Shallow trench isolations (STIs) 110 can surround portions of the first and second contact pillars 120a and 120b, respectively, in the epitaxial layer 132. In embodiments, the shallow trench isolations 110 can extend across a partial depth of the epitaxial layer 132. In further embodiments, the shallow trench isolations 110 can extend across an entire depth of the epitaxial layer 132. The shallow trench isolations 110 can electrically isolate the first and second contact pillars 120a and 120b, respectively, from the active region 138.

[0024] FIG. 1B is a schematic top view of a semiconductor device 100 according to embodiments of the present disclosure. Referring to FIG. 1B , the merged cavity 108 below the upper surface of the substrate 102 is shown as a dashed outline. An array of plugs 112 can be formed over an upper portion of the merged cavity 108 in the substrate 102, thereby filling the upper portion of the merged cavity 108 in the substrate 102. In embodiments, the upper portion of the merged cavity 108 in the substrate 102 and the plugs 112 can have a circular shape. In further embodiments, the upper portion of the merged cavity 108 in the substrate 102 and the plugs 112 can have a square or an elliptical shape. A continuous substrate layer 102 is located between the plugs 112 and over the merged cavity 108 in the substrate 102. For simplicity, the epitaxial layer 132, the gate stack 106, the first and second contact pillars 120a and 120b, the metallization layer 128, and the first and second interlayer dielectric layers 124 and 126 are not shown in FIG. 1B . Isolation structures 110 can be formed over the substrate 102 and along the periphery of the active region 138, thereby defining a length x and a width y of the active region 138. A length xl of the merged cavity 108 in the substrate 102 can be less than or equal to the length x of the active region 138. A width yl of the merged cavity 108 in the substrate 102 can be less than or equal to the width y of the active region 138. The merged cavity 108 in the substrate 102 can be tailored to cover the entire length x and width y of the active region 138 or to cover a specific portion of the semiconductor device 100.

[0025] During device operation, heat generated in the active region 138 can be conducted through the plugs 112 to the thermally conductive layer 148 in the upper portion of the merged cavity 108 in the substrate 102. The heat can be dissipated through the first and second contact pillars 120a and 120b, respectively, to the metallization layer 128 and an external heat sink. Alternatively, heat from the substrate 102 can be conducted through the bottom of the merged cavity 108 in the substrate 102 to the thermally conductive layer 148 in the lower portion of the merged cavity 108 in the substrate 102 and dissipated through the first and second contact pillars 120a and 120b, respectively. The dielectric liner 116 over the sidewalls of the upper portion of the merged cavity 108 in the substrate 102 and over a portion of the lower portion of the merged cavity 108 in the substrate 102 can act as a thermal insulator and control the flow of heat within the merged cavity 108 in the substrate 102.

[0026] FIGS. 2-18 A cross-sectional view of a partially completed semiconductor device 100 is shown in accordance with embodiments of the present disclosure. FIG. 1A A manufacturing process flow for the semiconductor device 100 is shown. FIG. 2 A cross-sectional view of a partially completed semiconductor device 100 is shown in accordance with embodiments of the present disclosure. Reference is made to FIG. 1A, which shows a cross-sectional view of a substrate 102 having a merged cavity 108 formed therein. FIG. 2 The substrate 102 having the merged cavity 108 formed therein can be provided. A protective nitride layer 150 can be disposed on an upper surface of the substrate 102. Formation of the merged cavity 108 in the substrate 102 can include forming a trench in the protective nitride layer 150 and an upper portion of the substrate 102. A protective dielectric spacer can be formed on sidewalls of the trench. In embodiments, the protective dielectric spacer can be made of silicon nitride, silicon dioxide, or any suitable dielectric material. A portion of the substrate 102 can be removed from a bottom of the trench using a wet etch or dry etch process, thereby forming the merged cavity 108 in the substrate 102. In embodiments, the protective dielectric spacer can be subsequently removed from the sidewalls of the trench by a wet etch or dry etch process. In further embodiments, the protective dielectric spacer can remain on the sidewalls of the trench. For simplicity, FIG. 2 The protective dielectric spacer is not shown in FIG. 1C. The trench can then be referred to as an upper portion of the merged cavity 108 in the substrate 102.

[0027] FIG. 3 A cross-sectional view of a partially completed semiconductor device 100 is shown in accordance with embodiments of the present disclosure after formation of a dielectric liner 116. In embodiments, the dielectric liner 116 can be formed on sidewalls and a bottom surface of the merged cavity 108 in the substrate 102. The dielectric liner 116 can be formed by thermal oxidation or any other suitable oxidation or deposition process.

[0028] FIG. 4 A cross-sectional view of a partially completed semiconductor device 100 is shown in accordance with embodiments of the present disclosure after removal of the protective nitride layer 150. The protective nitride layer 150 can be removed by a hot phosphoric acid solution or any other suitable removal process. The removal process leaves the dielectric liner 116 on the sidewalls and the bottom surface of the merged cavity 108 in the substrate 102 and exposes an upper surface of the substrate 102.

[0029] FIG. 5A cross-sectional view of the partially completed semiconductor device 100 after partially removing the dielectric liner 116 by a suitable removal process in one embodiment is shown. Some portions of the dielectric liner 116 can be removed from the top and bottom surfaces of the merged cavity 108 in the substrate 102 by a suitable removal process, which can be, for example, an anisotropic etch. The term "anisotropic etch" can refer to an etch process that is directional in nature. The upper portion of the substrate 102 adjacent to the top surface of the merged cavity 108 in the substrate 102 and the lower portion of the substrate 102 adjacent to the bottom surface of the merged cavity 108 in the substrate 102 can be exposed by the removal process. The removal process leaves the dielectric liner 116 located over the sidewalls and partially covering the lower portion of the merged cavity 108 in the substrate 102, thereby exposing the bottom surface of the merged cavity 108 in the substrate 102.

[0030] FIG. 6 A cross-sectional view of the partially completed semiconductor device 100 after forming the plug 112 over the upper portion of the merged cavity 108 in the substrate 102 and forming the lower portion 132a of the epitaxial layer in accordance with embodiments of the present disclosure is shown. The formation of the plug 112 can include depositing a layer of a suitable semiconductor material (e.g., germanium) over the top surface of the substrate 102 at a temperature equal to or greater than the reflow temperature of germanium. The germanium layer can reflow to plug or fill the top portion of the merged cavity 108 in the substrate 102 without filling the merged cavity 108 in the substrate 102. An epitaxial layer made of a suitable semiconductor material (e.g., silicon) can then be formed over the top surface of the substrate 102 and the plug 112 to form the lower portion 132a of the epitaxial layer, thereby providing a planar surface for subsequent device formation.

[0031] FIG. 7 A cross-sectional view of the partially completed semiconductor device 100 after forming the epitaxial layer 132 in accordance with some embodiments of the present disclosure is shown. An upper portion 132b of the epitaxial layer made of a suitable semiconductor material (e.g., silicon) can be formed over the lower portion 132a of the epitaxial layer, thereby forming the epitaxial layer 132. The thickness of the epitaxial layer 132 determines the distance of the merged cavity 108 in the substrate 102 from the top surface of the epitaxial layer 132. Thus, the merged cavity 108 in the substrate 102 can directly contact the epitaxial layer 132 to facilitate efficient heat dissipation from the epitaxial layer 132.

[0032] FIG. 8A cross-sectional view of the partially completed semiconductor device 100 after formation of isolation structures 110 in the epitaxial layer 132 over the merged cavity 108 in the substrate 102 is shown in accordance with an embodiment of the present disclosure. Formation of the isolation structures 110 can include forming trenches in the epitaxial layer 132, followed by deposition of a suitable insulating material (e.g., silicon dioxide) into the trenches. A suitable planarization process, such as chemical mechanical planarization (CMP), can be used to remove the silicon dioxide from the upper surface of the epitaxial layer 132, leaving the silicon dioxide in the trenches to form the isolation structures 110. The isolation structures 110 can define the area of the active region 138.

[0033] FIG. 9 A cross-sectional view of the partially completed semiconductor device 100 after formation of gate structures 106 over the epitaxial layer 132 is shown in accordance with an embodiment of the present disclosure. The gate structures 106 can include a gate electrode, a gate dielectric layer between the epitaxial layer 132 and the gate electrode, and a spacer structure on the sidewalls of the gate electrode. Formation of the gate structures 106 is well known in the art and will not be further detailed. Although not shown, well regions, as well as doped source and drain regions, can be formed in the epitaxial layer 132 over the merged cavity 108 in the substrate 102.

[0034] FIG. 10 A cross-sectional view of the partially completed semiconductor device 100 after formation of a first interlayer dielectric (ILD) layer 124 is shown in accordance with an embodiment of the present disclosure. The first interlayer dielectric layer 124 can include boron phosphorus silicon glass (BPSG), silicon dioxide, a low dielectric constant material, or any other suitable dielectric material. The term "low dielectric constant material" can refer to a dielectric material having a dielectric constant less than 3.9. The first interlayer dielectric layer 124 can be deposited over the gate structures 106 and the epitaxial layer 132 by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any other suitable deposition method.

[0035] FIG. 11 A cross-sectional view of the partially completed semiconductor device 100 after formation of via openings 152a-c in the first interlayer dielectric layer 124 is shown in accordance with an embodiment of the present disclosure. Formation of the via openings 152a-c can include a conventional photolithography process, including deposition and patterning of a photoresist material layer over the first interlayer dielectric layer 124. A wet etch or dry etch process can be used to remove the interlayer dielectric layer 124 not covered by the photoresist layer, thereby forming the via openings 152a-c. The photoresist layer can then be removed.

[0036] FIG. 12A cross-sectional view of the partially completed semiconductor device 100 after forming a photoresist layer 160 over the first interlayer dielectric layer 124 is shown in accordance with embodiments of the present disclosure. The photoresist layer 160 can fill the via openings 152a-c in the first interlayer dielectric layer 124. The edge portions of the merged cavity 108 in the substrate 102 and the openings 156a and 156b over the isolation structure 110 can be formed in the photoresist layer 160 by a conventional photolithography process.

[0037] FIG. 13 A cross-sectional view of the partially completed semiconductor device 100 after forming via openings 162a and 162b in the first interlayer dielectric layer 124 and the isolation structure 110 is shown in accordance with some embodiments of the present disclosure. A wet etch or dry etch process can be used to remove portions of the interlayer dielectric layer 124 and the isolation structure 110 that are not covered by the photoresist layer 160, thereby forming the via openings 162a and 162b.

[0038] FIG. 14 A cross-sectional view of the partially completed semiconductor device 100 after extending the via openings 162a and 162b to the merged cavity 108 in the substrate 102 is shown in accordance with some embodiments of the present disclosure. Portions of the epitaxial layer 132, the plug 112, the dielectric liner 116, and the substrate 102 that are located over the edge portions of the merged cavity 108 in the substrate 102 can be removed to extend the via openings 162a and 162b to the merged cavity 108 in the substrate 102. The removal process can be a wet etch or dry etch process.

[0039] FIG. 15 A cross-sectional view of the partially completed semiconductor device 100 after removing the photoresist layer 160 and forming a barrier liner 122 over the sidewalls and bottom surfaces of the via openings 162a, 162b and 152a, 152b, and 152c is shown in accordance with some embodiments of the present disclosure. The photoresist layer 160 can be removed by a conventional photoresist removal process, such as ashing. The formation of the barrier liner 122 can include depositing a layer of a suitable liner material, such as titanium nitride, by ALD, CVD, PVD, or any other suitable deposition process.

[0040] FIG. 16A cross-sectional view of the partially completed semiconductor device 100 after forming the thermally conductive layer 148 in the merged cavities 108 and the openings 162a, 162b, and 152a-c in the substrate 102 according to embodiments of the present disclosure is shown. The formation of the thermally conductive layer 148 can include depositing a suitable thermally conductive material having a higher thermal conductivity than silicon, such as tungsten, copper, graphene, aluminum nitride, carbon nanotubes, diamond, or any other suitable thermally conductive material, by ALD, CVD, PVD, or any other suitable deposition process. In some embodiments, the thermally conductive layer 148 can partially fill the merged cavities 108 in the substrate 102 and the air gaps 118 can extend across the merged cavities 108 in the substrate 102. In further embodiments, the thermally conductive layer 148 can completely fill the merged cavities 108 in the substrate 102.

[0041] FIG. 17 A cross-sectional view of the partially completed semiconductor device 100 after forming the first and second contact pillars 120a and 120b, respectively, according to embodiments of the present disclosure is shown. A suitable planarization process, such as CMP, can be used to remove the thermally conductive layer 148 from the upper surface of the first interlayer dielectric layer 124, leaving the thermally conductive layer 148 in the openings 162a and 162b, thereby forming the first and second contact pillars 120a and 120b, respectively.

[0042] FIG. 18 A cross-sectional view of the partially completed semiconductor device 100 after forming a second interlayer dielectric layer 126 over the first and second contacts 120a and 120b, respectively, and the first interlayer dielectric layer 124 according to embodiments of the present disclosure is shown. The formation of the second interlayer dielectric layer 126 can include depositing a layer of a suitable dielectric material, such as silicon dioxide or a low dielectric constant material, by ALD, CVD, PVD, or any other suitable deposition process. In embodiments, the first and second interlayer dielectric layers 124 and 126, respectively, can include the same material. In further embodiments, the first and second interlayer dielectric layers 124 and 126, respectively, can include different materials.

[0043] A metallization layer 128 can then be formed in the second interlayer dielectric layer 126 and over the first and second contact pillars 120a and 120b, respectively, to provide the semiconductor device 100 as shown. FIG. 1A The formation of the metallization layer 128 can include forming openings in the second interlayer dielectric layer 126 using a conventional photolithography process and wet etching or dry etching, followed by depositing a layer of a suitable metal, such as copper, to fill the openings. A planarization process, such as CMP, can be used to remove the copper from the upper surface of the second interlayer dielectric layer 126 and leave the copper in the openings, thereby forming the metallization layer 128.

[0044] FIGS. 1 through FIG. 18The illustrated embodiments can be modified to form alternative embodiments within the scope of the present disclosure. For example, FIG. 19 is a cross-sectional view of a semiconductor device 200 according to another embodiment of the present disclosure. In one embodiment, the semiconductor device 200 can be a bipolar junction transistor (BJT). FIGS. 1 to FIG. 18 The same reference numbers are used in FIG. 19 to refer to the same features.

[0045] Referring to FIG. 19 , the semiconductor device 200 includes a substrate 102 having a merged cavity 108 therein. An active region 238 can be over the merged cavity 108 in the substrate 102. The active region 238 can include an epitaxial layer 132. A thermally conductive layer 148 can be in the merged cavity 108 in the substrate 102, where the thermally conductive layer 148 at least partially fills the merged cavity 108 in the substrate 102. An air gap 118 can be disposed in the merged cavity 108 and can be surrounded by the thermally conductive layer 148. First and second contact pillars 120a and 120b can connect the thermally conductive layer 148 in the merged cavity 108 in the substrate 102 with a metallization layer 128 over the active region 238. A semiconductor plug 112 can be disposed over an upper portion of the merged cavity 108 in the substrate 102. A dielectric liner 116 can be disposed over sidewalls of the upper portion of the merged cavity 108 in the substrate 102, where the dielectric liner 116 can be disposed under the semiconductor plug 112. The dielectric liner 116 can be partially disposed over a lower portion of the merged cavity 108 in the substrate 102.

[0046] The active region 238 can include the epitaxial layer 132 and first, second, and third doped regions 250, 252, and 256 in the epitaxial layer 132. The first doped region 250 can be an n-doped collector region. The second doped region 252 can be a p-doped base region and can be disposed in the first doped region 250. The third doped region 256 can be an n-doped emitter region and can be disposed in the second doped region 252. Contact pillars 266, 268, and 270 can be disposed over the first, second, and third doped regions 250, 252, and 256, respectively. Metallization layers 272, 276, and 278 can be disposed over the contact pillars 266, 268, and 270, respectively. An isolation structure 110 can be formed in the epitaxial layer 132. In some embodiments, the isolation structure 110 can be a shallow trench isolation (STI) structure.

[0047] The manufacturing process flow of the merged cavity 108, the dielectric liner 116, the semiconductor plug 112, the epitaxial layer 132, and the isolation structure 110 in the substrate 102 of the semiconductor device 200 is similar to the manufacturing process flow of the merged cavity 108, the dielectric liner 116, the semiconductor plug 112, the epitaxial layer 132, and the isolation structure 110 in the substrate 102 of the semiconductor device 100. FIGS. 2-8A process flow for fabricating the cavity 108, the dielectric liner 116, the semiconductor plug 112, the epitaxial layer 132, and the isolation structure 110 in the substrate 102 of the illustrated semiconductor device 100 is shown. Referring to FIG. 19 The first doped region 250, the second doped region 252, and the third doped region 256 can be formed in the epitaxial layer 132. The formation of the first doped region 250, the second doped region 252, and the third doped region 256 is well known in the art and will not be further elaborated. The process flow for fabricating the first interlayer dielectric (ILD) layer 124 and the second interlayer dielectric (ILD) layer 126, the first contact pillar 120a and the second contact pillar 120b, the thermally conductive layer 148, the air gap 118, and the metallization layer 128 of the semiconductor device 200 is similar to FIGS. 10-18 The process flow for fabricating the first interlayer dielectric (ILD) layer 124 and the second interlayer dielectric (ILD) layer 126, the first contact pillar 120a and the second contact pillar 120b, the thermally conductive layer 148, the air gap 118, and the metallization layer 128 of the illustrated semiconductor device 100. The contact pillars 266, 268, and 270 can be formed with the first contact pillar 120a and the second contact pillar 120b. The metallization layers 272, 276, and 278 can be formed with the metallization layer 128.

[0048] FIG. 20 is a cross-sectional view of a semiconductor device 300 according to another embodiment of the disclosure. In one embodiment, the semiconductor device 300 can be a high electron mobility transistor (HEMT). Referring to FIG. 20 The semiconductor device 300 includes the substrate 102 having the cavity 108 therein. An active region 338 can be over the cavity 108 in the substrate 102. The active region 338 can include the epitaxial layer 132. The thermally conductive layer 148 can be in the cavity 108 in the substrate 102, where the thermally conductive layer 148 at least partially fills the cavity 108 in the substrate 102. The air gap 118 can be disposed in the cavity 108 and can be surrounded by the thermally conductive layer 148. The first contact pillar 120a and the second contact pillar 120b connect the thermally conductive layer 148 in the cavity 108 in the substrate 102 with the metallization layer 128 over the active region 338. The semiconductor plug 112 can be disposed over an upper portion of the cavity 108 in the substrate 102. The dielectric liner 116 can be disposed over a sidewall of the upper portion of the cavity 108 in the substrate 102, where the dielectric liner 116 can be disposed under the semiconductor plug 112. The dielectric liner 116 can be partially disposed over a lower portion of the cavity 108 in the substrate 102.

[0049] The active region 338 can include the epitaxial layer 132 and the barrier layer 348. The epitaxial layer 132 can be made of a suitable semiconductor material, such as gallium nitride (GaN). The barrier layer 348 can be disposed on the epitaxial layer 132 and can be made of a suitable doped semiconductor material, such as aluminum-doped gallium nitride (AlGaN). The cap layer 350 can be disposed on the barrier layer 348. The cap layer 350 can be made of a suitable semiconductor material, such as gallium nitride. The drain 352 and the source 356 can be disposed on the cap layer 350. The drain 352 and the source 356 can be made of a suitable conductive material, such as titanium (Ti) or gold (Au). The gate 354 can be disposed between the drain 352 and the source 356. The gate 354 can be made of a suitable conductive material, such as nickel (Ni) or gold. The contact pillars 366, 368, and 370 can be disposed on the source 356, the gate 354, and the drain 352, respectively. The metallization layers 372, 376, and 378 can be disposed on the contact pillars 366, 368, and 370, respectively. The isolation structure 110 can be formed in the epitaxial layer 132.

[0050] The fabrication process flow of the cavity 108, the dielectric liner 116, the semiconductor plug 112, the epitaxial layer 132, and the isolation structure 110 in the substrate 102 of the semiconductor device 300 is similar to the fabrication process flow of the cavity 108, the dielectric liner 116, the semiconductor plug 112, the epitaxial layer 132, and the isolation structure 110 in the substrate 102 of the semiconductor device 100 shown in FIGS. 2-8 FIG. 20 The formation of the barrier layer 348 can include doping a portion of the active layer 132 with a suitable dopant, such as aluminum (Al), thereby forming the barrier layer 348. The formation of the cap layer 350 can include epitaxially growing a suitable semiconductor material, such as gallium nitride, thereby forming the cap layer 350. The formation of the drain 352, the gate 354, and the source 356 can include patterning a layer of a suitable metal, such as gold, by a conventional lift-off process. A photoresist layer can be deposited on the cap layer 350 and patterned by a conventional photolithography process to form openings in the photoresist layer. A layer of gold can be deposited by a suitable deposition process, such as physical vapor deposition (PVD), to fill the openings in the photoresist layer. The photoresist layer can be removed, leaving the layer of gold on the cap layer 350, thereby forming the drain 352, the gate 354, and the source 356.

[0051] The fabrication process flow of the first interlayer dielectric (ILD) layer 124 and the second interlayer dielectric (ILD) layer 126, the first contact pillar 120a and the second contact pillar 120b, the thermally conductive layer 148, the air gap 118, and the metallization layer 128 of the semiconductor device 300 is similar to the fabrication process flow of the first interlayer dielectric (ILD) layer 124 and the second interlayer dielectric (ILD) layer 126, the first contact pillar 120a and the second contact pillar 120b, the thermally conductive layer 148, the air gap 118, and the metallization layer 128 in the substrate 102 of the semiconductor device 100 shown in FIGS. 10-18 ​Manufacturing process flow of the first and second interlayer dielectric (ILD) layers 124 and 126, the first and second contact pillars 120a and 120b, the thermally conductive layer 148, the air gap 118, and the metallization layer 128 of the illustrated semiconductor device 100. The contact pillars 366, 368, and 370 can be formed with the first and second contact pillars 120a and 120b. The metallization layers 372, 376, and 378 can be formed with the metallization layer 128.

[0052] The terms “first,” “second,” “third,” etc., if any, in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the devices described herein are, for example, capable of operation in other sequences than described or otherwise illustrated herein. The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for

[0053] While several exemplary embodiments have been given in the detailed description of the devices above, it will be understood that there are many variations. It will further be understood that the embodiments are only examples and are not intended to limit the scope, applicability, or configuration of the devices in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the devices, it being understood that various changes can be made in the function and arrangement of elements described in the exemplary embodiments without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A semiconductor device comprising: a substrate having a merged cavity therein; an active region located over the merged cavity in the substrate; a thermally conductive layer located in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate; a first contact pillar connecting the thermally conductive layer in the merged cavity in the substrate and a metallization layer over the active region; and a dielectric liner located over sidewalls of an upper portion of the merged cavity in the substrate, wherein the dielectric liner partially covers a lower portion of the merged cavity in the substrate.

2. The semiconductor device of claim 1, further comprising: a plug located over the upper portion of the merged cavity in the substrate, wherein the plug comprises a semiconductor material.

3. The semiconductor device of claim 1, further comprising: an air gap extending across the merged cavity in the substrate, wherein the air gap is surrounded by the thermally conductive layer.

4. The semiconductor device of claim 2, wherein the dielectric liner is disposed below the plug.

5. The semiconductor device of claim 1, wherein the thermally conductive layer comprises a thermally conductive material having a higher thermal conductivity than silicon.

6. The semiconductor device of claim 5, wherein the thermally conductive layer comprises copper (Cu), tungsten (W), graphene, aluminum nitride (AIN), carbon nanotubes (CNTs), or diamond (C).

7. The semiconductor device of claim 1, wherein the thermally conductive layer completely fills a remaining portion of the merged cavity in the substrate.

8. The semiconductor device of claim 1, wherein the first contact pillar comprises a trench or a through-silicon via (TSV).

9. The semiconductor device of claim 1, wherein the metallization layer is connected to a ground terminal.

10. The semiconductor device of claim 1, wherein the thermally conductive layer in the merged cavity in the substrate is in contact with the substrate through a bottom of the merged cavity.

11. A semiconductor device comprising: a substrate having a merged cavity therein; an active region located over the merged cavity in the substrate, wherein the active region comprises an epitaxial layer; the merged cavity in the substrate extends across at least a portion of a length and a width of the active region; a thermally conductive layer located in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate; a first contact pillar connecting the thermally conductive layer in the merged cavity in the substrate and a metallization layer over the active region; and a dielectric liner located over sidewalls of an upper portion of the merged cavity in the substrate, wherein the dielectric liner partially covers a lower portion of the merged cavity in the substrate.

12. The semiconductor device of claim 11, wherein the merged cavity in the substrate extends across the length and the width of the active region.

13. The semiconductor device of claim 12, wherein the merged cavity in the substrate directly contacts the active region.

14. The semiconductor device of claim 11, further comprising: ​ ​ an isolation structure surrounding a portion of the first contact pillar in the epitaxial layer to electrically isolate the first contact pillar from the active region.

15. A method of fabricating a semiconductor device, comprising: providing a substrate having a merged cavity therein; disposing an active region over the merged cavity in the substrate; forming a thermally conductive layer in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate; and forming a first contact pillar connecting the thermally conductive layer in the merged cavity in the substrate with a metallization layer over the active region, wherein providing a substrate having a merged cavity therein further comprises forming a dielectric liner over sidewalls of the merged cavity in the substrate and partially covering a lower portion of the merged cavity in the substrate.

16. The method of claim 15, wherein providing a substrate having a merged cavity therein further comprises: forming a plug over an upper portion of the merged cavity in the substrate.

17. The method of claim 16, wherein disposing an active region over the merged cavity in the substrate further comprises: forming an epitaxial layer over the merged cavity and the plug in the substrate.

18. The method of claim 17, wherein forming a thermally conductive layer in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate further comprises: depositing a thermally conductive layer in the merged cavity in the substrate, wherein the thermally conductive layer at least partially fills the merged cavity in the substrate.

19. The method of claim 18, wherein forming a first contact pillar connecting the thermally conductive layer in the merged cavity in the substrate with a metallization layer over the active region further comprises: forming a first contact pillar through the epitaxial layer, wherein the first contact pillar extends from the merged cavity in the substrate to over the epitaxial layer; and forming a metallization layer over the first contact pillar. ​

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