Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, at least one semiconductor device, a front source contact, and a back contact metal layer. The semiconductor substrate has a through-substrate hole (TBU). The semiconductor substrate includes a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer formed on a second surface of the high-resistance silicon carbide epitaxial layer. The semiconductor device is formed on the gallium nitride epitaxial layer. The front source contact is formed on the surface of the gallium nitride epitaxial layer and covers the TBU of the semiconductor substrate. The back contact metal layer is formed within the TBU of the semiconductor substrate and directly contacts the front source contact.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Epitaxial films have been widely used in the manufacture of radio frequency (RF) and power devices due to their high purity and excellent thickness controllability. RF devices can be used in 4G communications, 5G communications, satellite communications, and 5G front-end modules.

[0003] However, in the manufacturing process of RF devices, the original substrate thickness is usually thinned from one thickness to a thickness several levels smaller than the original thickness through processes such as grinding or polishing. Since the difference in the thickness of the substrate to be removed is too large, it is easy to cause the variation range of the final substrate thickness to be too large. For example, the substrate thickness is thinned from about 300μm to about 50μm, resulting in a variation range of about ±20% in the final substrate thickness. This has an adverse effect on the Through Silicon Via (TSV) process and is prone to problems such as device matching, thereby affecting the yield of RF devices. Summary of the Invention

[0004] The present invention is directed to a semiconductor device and a method for manufacturing the same, which can solve problems such as a wide variation range of substrate thickness, and has a small variation range of RF source impedance and RF front-to-backside capacitance.

[0005] According to an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, at least one semiconductor device, a front source contact, and a back contact metal layer. The semiconductor substrate has a through substrate hole, and the semiconductor substrate includes a high-resistivity silicon carbide epitaxial layer having a first surface and a second surface, and a gallium nitride epitaxial layer formed on the second surface of the high-resistivity silicon carbide epitaxial layer, wherein the first surface is opposite to the second surface. The semiconductor device is formed on the gallium nitride epitaxial layer. The front source contact is formed on the surface of the gallium nitride epitaxial layer and covers the through substrate hole of the semiconductor substrate. The back contact metal layer is formed in the through substrate hole of the semiconductor substrate and is in direct contact with the front source contact.

[0006] In the semiconductor device according to the embodiment of the present invention, the thickness of the high-resistance silicon carbide epitaxial layer is between 20 μm and 50 μm.

[0007] In a semiconductor device according to an embodiment of the present invention, the front source contact includes an adhesion layer, a barrier layer, and a highly conductive layer. The adhesion layer is formed on a surface of the gallium nitride epitaxial layer. The barrier layer is formed on a surface of the adhesion layer. The highly conductive layer is formed on a surface of the barrier layer.

[0008] In a semiconductor device according to an embodiment of the present invention, the adhesion layer comprises Ti, TiW, TiN, Ta, or TaN with a thickness between 2 nm and 200 nm. The barrier layer comprises Pt, Pd, or Mo with a thickness between 2 nm and 200 nm. The highly conductive layer comprises Au, Al, Al-Cu, or Cu with a thickness between 50 nm and 10 μm.

[0009] In a semiconductor device according to an embodiment of the present invention, the back contact metal layer includes an adhesive layer, a barrier layer, and a highly conductive layer. The adhesive layer is formed on the surface of the substrate through-hole. The barrier layer is formed on the surface of the adhesive layer. The highly conductive layer is formed on the surface of the barrier layer.

[0010] In a semiconductor device according to an embodiment of the present invention, the adhesion layer comprises Ti, TiW, TiN, Ta, or TaN with a thickness between 2 nm and 200 nm. The barrier layer comprises TiW, TiN, or TaN with a thickness between 2 nm and 200 nm. The highly conductive layer comprises Au, Al, Al-Cu, or Cu with a thickness between 50 nm and 10 μm.

[0011] In the semiconductor device according to the embodiment of the present invention, the angle between the cross section of the sidewall of the through-substrate hole and the surface of the gallium nitride epitaxial layer is between 45° and 90°.

[0012] In the semiconductor device according to the embodiment of the present invention, the angle between the cross section of the sidewall of the through-substrate hole and the surface of the gallium nitride epitaxial layer is between 85° and 90°.

[0013] In the semiconductor device according to the embodiment of the present invention, the through substrate via is a circular through substrate via having a diameter of 10 μm to 85 μm.

[0014] In the semiconductor device according to the embodiment of the present invention, the through substrate hole is an elliptical through substrate hole, and the product of the minor axis length and the major axis length of the elliptical through substrate hole is 10 μm×20 μm to 50 μm×120 μm.

[0015] In the semiconductor device according to the embodiment of the present invention, the depth of the through-substrate hole is between 10 μm and 200 μm.

[0016] In the semiconductor device according to the embodiment of the present invention, the cross section of the through substrate hole has a stepped profile, a stepped profile plus an inclined profile, profiles with the same slope, or profiles with different slopes.

[0017] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes epitaxially growing a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer on a first surface of an N-type silicon carbide substrate to obtain a semiconductor epitaxial substrate including the high-resistance silicon carbide epitaxial layer and the gallium nitride epitaxial layer. A front-side source contact is formed on the surface of the gallium nitride epitaxial layer, and at least one semiconductor device is formed on the gallium nitride epitaxial layer. After forming the front-side source contact and the at least one semiconductor device, a wafer carrier is bonded to the surface of the gallium nitride epitaxial layer. A laser is applied from a second surface of the N-type silicon carbide substrate to form a damaged layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate, wherein the second surface is opposite to the first surface of the N-type silicon carbide substrate, and then the N-type silicon carbide substrate and the semiconductor epitaxial substrate are separated from the damaged layer. Using the front source contact as an etch stop layer, a through-substrate hole is etched from the bottom of the semiconductor epitaxial substrate until a portion of the front source contact is exposed. A metallization process is then performed to form a back-side contact metal layer in the through-substrate hole.

[0018] In a manufacturing method according to another embodiment of the present invention, the step of forming the front source contact includes forming an adhesion layer on the surface of the GaN epitaxial layer, then forming a barrier layer on the surface of the adhesion layer, and then forming a highly conductive layer on the surface of the barrier layer.

[0019] In a manufacturing method according to another embodiment of the present invention, the step of forming the above-mentioned back contact metal layer includes forming an adhesive layer on the surface of the substrate through hole, then forming a barrier layer on the surface of the adhesive layer, and then forming a highly conductive layer on the surface of the barrier layer.

[0020] In a manufacturing method according to another embodiment of the present invention, the first surface of the N-type silicon carbide substrate has an angle no greater than 0°+ / -8° relative to the (0001) plane.

[0021] In a manufacturing method according to another embodiment of the present invention, the thickness variation rate of the high-resistance silicon carbide epitaxial layer is between 5% and 10%.

[0022] In a manufacturing method according to another embodiment of the present invention, the method of forming the damage layer includes applying laser light from the second surface of the N-type silicon carbide substrate into the N-type silicon carbide substrate to form the damage layer in the N-type silicon carbide substrate.

[0023] In a manufacturing method according to another embodiment of the present invention, after separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate, the method further includes removing the remaining N-type silicon carbide substrate.

[0024] In a manufacturing method according to another embodiment of the present invention, the method of forming the above-mentioned damage layer includes applying laser from the second surface of the N-type silicon carbide substrate into the high-resistance silicon carbide epitaxial layer to form a damage layer in the high-resistance silicon carbide epitaxial layer.

[0025] In another embodiment of the manufacturing method according to the present invention, after forming the back contact metal layer, the method further includes removing the wafer carrier and performing a die singulation process.

[0026] Based on the above, the method of the present invention can reduce the variation range of the substrate thickness, and by forming a back contact metal layer in the substrate through-hole exposing part of the front source contact, it can improve the electrical connection between the front and back devices, so as to produce a device with a small variation range of RF source impedance and RF front and back capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1A to 1G is a schematic cross-sectional view of manufacturing a semiconductor device according to a first embodiment of the present invention;

[0028] Figures 2A to 2G is a schematic cross-sectional view of manufacturing a semiconductor device according to a second embodiment of the present invention;

[0029] Figure 3A is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

[0030] Figure 3B is a schematic cross-sectional view of another semiconductor device according to the third embodiment;

[0031] Figure 3C is a schematic cross-sectional view of yet another semiconductor device according to the third embodiment;

[0032] Figure 3D is a schematic cross-sectional view of yet another semiconductor device according to the third embodiment;

[0033] Figure 3E FIG. 4 is a cross-sectional schematic diagram of another semiconductor device according to the third embodiment.

[0034] Description of Reference Numerals

[0035] 100: N-type silicon carbide substrate

[0036] 100a, 314a: first surface

[0037] 100b, 314b: second surface

[0038] 102, 312: Area

[0039] 104, 314: High-resistance silicon carbide epitaxial layer

[0040] 106, 316: Gallium nitride epitaxial layer

[0041] 106a, 316a: surface

[0042] 108, 320: Positive source contact

[0043] 108a, 116a, 322, 332: Adhesive layer

[0044] 108b, 116b, 324, 334: barrier layer

[0045] 108c, 116c, 326, 336: Highly conductive layers

[0046] 110: Laser

[0047] 112, 200: Damage layer

[0048] 114: Wafer carrier

[0049] 116, 330: Back contact metal layer

[0050] 300: Semiconductor devices

[0051] 310: Semiconductor substrate

[0052] D: Depth

[0053] ES: Semiconductor epitaxial substrate

[0054] L1~L6: Maximum width

[0055] t1, t2, t3: thickness

[0056] TSH, TSH1~TSH5: through-hole on substrate

[0057] TSHa: Cross Section

[0058] θ, θ1~θ5, θ3'~θ5': included angle DETAILED DESCRIPTION

[0059] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0060] Exemplary embodiments of the present invention will be fully described below with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. In the accompanying drawings, for the sake of clarity, the sizes and thicknesses of various regions, parts, and layers may not be drawn to scale. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description.

[0061] Figures 1A to 1G FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

[0062] Please refer to Figure 1A A high-resistance silicon carbide epitaxial layer 104 is epitaxially grown on a first surface 100a of an N-type silicon carbide substrate 100, wherein the thickness of the N-type silicon carbide substrate 100 is, for example, between 300 μm and 725 μm, and the angle of the first surface 100a of the N-type silicon carbide substrate 100 relative to the (0001) plane is, for example, 0°+ / -8°, preferably 0°+ / -5°, more preferably 0°+ / -3°, and most preferably 0°. The micropipe density (MPD) of the N-type silicon carbide substrate 100 is less than 1 ea / cm 2 , basal plane dislocation (BPD) less than 3000ea / cm 2 and threading screw dislocation (TSD) less than 1000ea / cm 2 . The resistance value of the N-type silicon carbide substrate 100 is approximately between 15mohm-cm and 26mohm-cm. In this embodiment, the N-type silicon carbide substrate 100 can be reused, thereby significantly reducing material costs. In this embodiment, the high-resistance silicon carbide epitaxial layer 104 also has a region 102 on the side close to the N-type silicon carbide substrate 100. Region 102 is, for example, a region of poor quality grown when the high-resistance silicon carbide epitaxial layer 104 is epitaxially grown. In one embodiment, region 102 is, for example, used as a buffer layer, and in subsequent processes (such as Figure 1D The high-resistance silicon carbide epitaxial layer 104 may be retained or removed, for example, semi-insulating silicon carbide (SI-SiC) or other semiconductor substrates suitable for radio frequency (RF) devices. The thickness of the high-resistance silicon carbide epitaxial layer 104 may be set between 20 μm and 100 μm, and the thickness variation rate of the high-resistance silicon carbide epitaxial layer 104 may be approximately in the range of 5% to 10%. The surface of the high-resistance silicon carbide epitaxial layer 104 may have an angle within the range of 0°+ / -8°, an angle within the range of 0°+ / -5°, or an angle within the range of 0°+ / -3° relative to the (0001) plane, for example, and the micropipe density (MPD) of the high-resistance silicon carbide epitaxial layer 104 may be less than 0.5 ea / cm 2, basal plane dislocation (BPD) can be less than 10ea / cm 2 , threading screw dislocation (TSD) can be less than 300ea / cm 2 In this embodiment, the resistance of the high-resistance silicon carbide epitaxial layer 104 is, for example, greater than 1E5 ohm-cm.

[0063] Then, a gallium nitride epitaxial layer 106 is epitaxially grown on the high-resistance silicon carbide epitaxial layer 104 to obtain a semiconductor epitaxial substrate ES consisting of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 .

[0064] Next, a front-side source contact 108 is formed on the surface 106a of the gallium nitride epitaxial layer 106. The front-side source contact 108 can be formed, for example, as a single layer or multiple layers. In this embodiment, the front-side source contact 108 is formed, for example, as a three-layer structure. For example, the steps of forming the front-side source contact 108 include forming an adhesion layer 108a on the surface 106a of the gallium nitride epitaxial layer 106, then forming a barrier layer 108b on the surface of the adhesion layer 108a, and then forming a highly conductive layer 108c on the surface of the barrier layer 108b, but the present invention is not limited thereto. In this embodiment, the formation of the adhesion layer 108a improves the contact between the front-side source contact 108 and the dielectric layer and semiconductor device. The formation of the barrier layer 108b prevents the metals of the highly conductive layer 108c and the adhesion layer 108a from intermixing. By forming the highly conductive layer 108c, current can be handled with low parasitic loss. The adhesion layer 108a is, for example, composed of Ti, TiW, TiN, Ta, or TaN with a thickness between 2nm and 200nm. The barrier layer 108b is, for example, composed of Pt, Pd, or Mo with a thickness between 2nm and 200nm. The highly conductive layer 108c is, for example, composed of Au, Al, Al-Cu, or Cu with a thickness between 50nm and 10μm. In one embodiment, the barrier layer 108b may not be formed between the adhesion layer 108a and the highly conductive layer 108c. This can be adjusted according to design requirements and is not limited in the present invention.

[0065] Then, semiconductor devices and other components are formed in the GaN epitaxial layer 106; Figures 1A to 1G The components are omitted in the figure.

[0066] Next, please refer to Figure 1B After forming the front source contact 108 and the semiconductor device (not shown), a wafer carrier 114 is bonded to the surface 106 a of the GaN epitaxial layer 106 , wherein the material of the wafer carrier 114 is, for example, glass or sapphire.

[0067] Then, please refer to Figure 1C A laser 110 is used to form a damaged layer 112 within the N-type silicon carbide substrate 100. In this embodiment, the method of forming the damaged layer 112 includes, for example, applying the laser 110 from the second surface 100b of the N-type silicon carbide substrate 100 into the N-type silicon carbide substrate 100, thereby forming the damaged layer 112 near the high-resistance silicon carbide epitaxial layer 104 in the N-type silicon carbide substrate 100, wherein the second surface 100b is opposite to the first surface 100a of the N-type silicon carbide substrate 100. By forming the damaged layer 112 using the laser 110, wafer-to-wafer and within-wafer calculation data can be obtained.

[0068] Afterwards, please refer to Figure 1D The N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 112, and a portion of the N-type silicon carbide substrate 100 may remain on the surface of the high-resistance silicon carbide epitaxial layer 104. Therefore, in one embodiment, the remaining N-type silicon carbide substrate 100 may be retained; in another embodiment, the remaining N-type silicon carbide substrate 100 may be removed, for example, by grinding. In this way, the thickness of the silicon carbide substrate 100 that needs to be ground away is thinner, reducing the range of variation in the final substrate thickness.

[0069] Because the first embodiment's process utilizes a laser 110 to form the separation damage layer 112 in the N-type SiC substrate 100 after forming the front source contact 108, the crystalline quality of the high-resistance SiC epitaxial layer 104 and the GaN epitaxial layer 106 is ensured. Furthermore, after separating the N-type SiC substrate 100 from the semiconductor epitaxial substrate ES from the damage layer 112, a sufficient thickness of the N-type SiC substrate 100 remains. This thickness is sufficient to support the films and components formed thereon and withstand subsequent processing. This allows the separated N-type SiC substrate 100 to be reused, significantly reducing material costs. Furthermore, the ability to more precisely control the substrate thickness significantly reduces parasitic losses.

[0070] Next, please refer to Figure 1E, using the front source contact 108 as an etching stop layer, a substrate through hole TSH is etched from the bottom of the semiconductor epitaxial substrate ES (for example, on the side of region 102) until a portion of the front source contact 108 is exposed, wherein the angle θ between the cross section TSHa of the sidewall of the substrate through hole TSH and the surface 106a of the gallium nitride epitaxial layer 106 is, for example, between 45° and 90°, preferably between 85° and 90°. The depth D of the substrate through hole TSH is, for example, between 10μm and 200μm. The substrate through hole TSH may be, for example, a circular substrate through hole or an elliptical substrate through hole. In one embodiment, if the substrate through hole TSH is a circular substrate through hole, the circular substrate through hole has a diameter of, for example, 10μm to 85μm; in another embodiment, if the substrate through hole TSH is an elliptical substrate through hole, the short axis length multiplied by the long axis length of the elliptical substrate through hole is, for example, 10μm×20μm to 50μm×120μm. In Figure 1E In the figure, although the cross section of the substrate through hole TSH is drawn as a profile with the same slope, in other embodiments, the cross section of the substrate through hole TSH may also be a stepped profile, a stepped profile plus an inclined profile, or a profile with different slopes, as described in detail below.

[0071] Then, please refer to Figure 1F, a metallization process is performed to form a back-side contact metal layer (back-side contact metal) 116 in the substrate through hole TSH. The back-side contact metal layer 116 is formed as a single layer or multiple layers, for example. In the present embodiment, the back-side contact metal layer 116 is formed as a three-layer structure, for example. For example, the step of forming the back-side contact metal layer 116 includes, for example, forming an adhesive layer 116a on the surface of the substrate through hole TSH, then forming a barrier layer 116b on the surface of the adhesive layer 116a, and then forming a highly conductive layer 116c on the surface of the barrier layer 116b, but the present invention is not limited thereto. The method of forming the back-side contact metal layer 116 is, for example, sputtering, electrical planting, or conformal coating. In one embodiment, if a thicker back-side contact metal layer 116 is to be formed, electroplating can be used to further reduce the manufacturing cost. In this embodiment, the adhesion layer 116a is formed to improve the contact between the back contact metal layer 116 and the side and back sides of the semiconductor device, as well as the contact with the front source contact 108. The barrier layer 116b is formed to prevent the highly conductive layer 116c from intermixing with the metal within the adhesion layer 116a. The formation of the highly conductive layer 116c enables current handling with low parasitic losses. The adhesion layer 116a is, for example, composed of Ti, TiW, TiN, Ta, or TaN with a thickness between 2 nm and 200 nm. The barrier layer 116b is, for example, composed of TiW, TiN, or TaN with a thickness between 2 nm and 200 nm. The highly conductive layer 116c is, for example, composed of Au, Al, Al-Cu, or Cu with a thickness between 50 nm and 10 μm. In another embodiment, the barrier layer 116b may not be formed between the adhesion layer 116a and the highly conductive layer 116c. This can be adjusted based on design requirements and is not a limitation of the present invention.

[0072] Afterwards, please refer to Figure 1G After forming the back contact metal layer 116, the wafer carrier 114 may be removed. Figure 1A In the process shown, multiple semiconductor devices and other components are formed in the gallium nitride epitaxial layer 106. Figure 1G For example, a monomerization process is also included, but the present invention is not limited thereto.

[0073] Because the first embodiment's process forms the back contact metal layer 116 within the through-substrate via (TSH) only after partially exposing the front source contact 108, direct contact between the front source contact 108 and the back contact metal layer 116 is ensured, thereby improving the electrical connection between the front and back devices. If applied to RF devices, this can further improve the RF source impedance and RF front and back capacitance, and can also reduce the variation range of the RF source impedance and RF front and back capacitance.

[0074] Figures 2A to 2G This is a schematic cross-sectional view of the manufacturing of a semiconductor device according to the second embodiment of the present invention, wherein the same device symbols as the first embodiment are used to represent the same or similar components, and the same or similar components can also refer to the relevant description of the first embodiment and will not be repeated.

[0075] Please refer to Figure 2A A high-resistance silicon carbide epitaxial layer 104 having a region 102 is epitaxially grown on a first surface 100a of an N-type silicon carbide substrate 100. Then, a gallium nitride epitaxial layer 106 is epitaxially grown on the high-resistance silicon carbide epitaxial layer 104 to obtain a semiconductor epitaxial substrate ES consisting of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106. A front source contact 108 is formed on the surface 106a of the gallium nitride epitaxial layer 106. Thereafter, semiconductor devices and other components are formed in the gallium nitride epitaxial layer 106; for clarity, Figures 2A to 2G The components are omitted in the figure.

[0076] Next, please refer to Figure 2B After forming the front source contact 108 and the semiconductor device (not shown), a wafer carrier 114 is bonded to the surface 106 a of the GaN epitaxial layer 106 .

[0077] Then, please refer to Figure 2C A laser 110 is used to form a damaged layer 200 within the semiconductor epitaxial substrate ES. In this embodiment, the damaged layer 200 is formed, for example, within the high-resistance silicon carbide epitaxial layer 104 and is located on a side relative to the region 102 of the N-type silicon carbide substrate 100. The method of forming the damaged layer 200 includes, for example, applying the laser 110 from the second surface 100b of the N-type silicon carbide substrate 100 into the high-resistance silicon carbide epitaxial layer 104 to form the damaged layer 200 within the high-resistance silicon carbide epitaxial layer 104. By forming the damaged layer 200 using the laser 110, wafer-to-wafer and intra-wafer calculation data can be obtained.

[0078] Afterwards, please refer to Figure 2D, separating the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES from the damaged layer 200. In this embodiment, since the region 102 and the N-type silicon carbide substrate 100 have been completely removed, grinding and other processes are not required. Compared with the first embodiment, some steps can be omitted, further reducing manufacturing costs.

[0079] Because the damaged layer 200 is formed within the high-resistance SiC epitaxial layer 104 in the process of the second embodiment, the intact N-type SiC substrate 100 can be retained after the N-type SiC substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 200. This allows the separated N-type SiC substrate 100 to be reused, significantly reducing material costs.

[0080] Next, please refer to Figure 2E , using the front source contact 108 as an etching stop layer, a through substrate hole TSH is etched from the bottom of the semiconductor epitaxial substrate ES (eg, on the high-resistance silicon carbide epitaxial layer 104 side) until a portion of the front source contact 108 is exposed.

[0081] Then, please refer to Figure 2F , a metallization process is performed to form a back contact metal layer 116 in the substrate through hole TSH. Figure 2G After forming the back contact metal layer 116, the wafer carrier 114 may be removed. In one embodiment, after the semiconductor device is formed, a singulation process may be performed subsequently, but the present invention is not limited thereto.

[0082] Because the second embodiment's process forms the back contact metal layer 116 within the through-substrate via (TSH) only after partially exposing the front source contact 108, direct contact between the front source contact 108 and the back contact metal layer 116 is ensured, thereby improving the electrical connection between the front and back devices. If applied to RF devices, this can further improve the RF source impedance and RF front and back capacitance, and reduce the range of variation in these two factors.

[0083] Figure 3A FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

[0084] Please refer to Figure 3A The semiconductor device 300 of this embodiment includes a semiconductor substrate 310 , at least one semiconductor device (not shown), a front source contact 320 , and a back contact metal layer 330 .

[0085] The semiconductor substrate 310 includes a high-resistance silicon carbide epitaxial layer 314 and a gallium nitride epitaxial layer 316. In this embodiment, the semiconductor substrate 310 is a semiconductor substrate suitable for radio frequency (RF) devices.

[0086] The high-resistance silicon carbide epitaxial layer 314 has a first surface 314a and a second surface 314b, wherein the first surface 314a is opposite to the second surface 314b. In this embodiment, the high-resistance silicon carbide epitaxial layer 314 further has a region 312 on the side of the first surface 314a. The region 312 is, for example, a region of poor quality grown during the epitaxial growth of the high-resistance silicon carbide epitaxial layer 314. In one embodiment, the region 312 is, for example, a buffer layer, and the thickness t1 of the buffer layer may be less than 1.5 μm; in another embodiment, the semiconductor substrate may not have the region 312. The high-resistance silicon carbide epitaxial layer 314 is, for example, semi-insulating silicon carbide (SI-SiC). In this embodiment, the thickness t2 of the high-resistance silicon carbide epitaxial layer 314 is, for example, between 20 μm and 50 μm. The second surface 314b of the high-resistance silicon carbide epitaxial layer 314 has an angle with respect to the (0001) plane within the range of 0°+ / -8°, for example, within the range of 0°+ / -5°, preferably within the range of 0°+ / -3°. The micropipe density (MPD) of the high-resistance silicon carbide epitaxial layer 314 is less than 0.5 ea / cm 2 , basal plane dislocation (BPD) less than 10ea / cm 2 and threading screw dislocation (TSD) less than 500ea / cm 2 The resistance of the high-resistance silicon carbide epitaxial layer 314 is greater than 1E5 ohm-cm. The resistance variation of the high-resistance silicon carbide epitaxial layer 314 is, for example, less than 50%. The so-called "resistance variation" refers to the result of dividing the standard deviation of the resistance by the average resistance.

[0087] The GaN epitaxial layer 316 is formed on the second surface 314b of the high-resistance SiC epitaxial layer 314, and a semiconductor device (not shown) is formed on the GaN epitaxial layer 316. In this embodiment, the thickness t3 of the GaN epitaxial layer 316 is less than 2 μm, and Figure 3A The structure can be manufactured using the method described in the first or second embodiment, and a step of removing residual structures other than the high-resistance silicon carbide epitaxial layer 314 can be added as needed. The resulting gallium nitride epitaxial layer 316 has been tested, and its full width at half maximum (FWHM) on the (002) plane of X-ray diffraction analysis is less than 100 arcsec, verifying that the grown epitaxial film is of excellent quality.

[0088] In this embodiment, the semiconductor substrate 310 has a through-substrate hole TSH1, wherein the angle θ1 between the cross section of the sidewall of the through-substrate hole TSH1 and the surface 316a of the GaN epitaxial layer 316 is, for example, between 45° and 90°, preferably between 85° and 90°. Figure 3A As shown in , the angle θ1 between the cross section of the side wall of the through substrate hole TSH1 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 90°. The depth D of the through substrate hole TSH1 is, for example, between 10μm and 200μm. The through substrate hole TSH1 may be, for example, a circular substrate through hole or an elliptical substrate through hole. In one embodiment, if the through substrate hole TSH1 is a circular substrate through hole, the circular substrate through hole has a diameter of, for example, 10μm to 85μm; in another embodiment, if the through substrate hole TSH1 is an elliptical substrate through hole, the short axis length multiplied by the long axis length of the elliptical substrate through hole is, for example, 10μm×20μm to 50μm×120μm. In Figure 3A , the cross section of the through-substrate hole TSH1 is illustrated as a profile having the same slope.

[0089] The front source contact 320 is formed on the surface 316a of the GaN epitaxial layer 316 and covers the through-substrate hole TSH1 of the semiconductor substrate 310. The front source contact 320 includes an adhesion layer 322, a barrier layer 324, and a highly conductive layer 326. The adhesion layer 322 is formed on the surface 316a of the GaN epitaxial layer 316. The barrier layer 324 is formed on the surface of the adhesion layer 322. The highly conductive layer 326 is formed on the surface of the barrier layer 324. In this embodiment, the adhesion layer 322 is composed of, for example, Ti, TiW, TiN, Ta, or TaN with a thickness between 2 nm and 200 nm. The barrier layer 324 is composed of, for example, Pt, Pd, or Mo with a thickness between 2 nm and 200 nm. The highly conductive layer 326 is composed of, for example, Au, Al, Al-Cu, or Cu with a thickness between 50 nm and 10 μm.

[0090] The back contact metal layer 330 is formed within the through-substrate hole TSH1 of the semiconductor substrate 310 and is in direct contact with the front source contact 320. The back contact metal layer 330 includes an adhesion layer 332, a barrier layer 334, and a highly conductive layer 336. The adhesion layer 332 is formed, for example, on the surface of the through-substrate hole TSH1. The barrier layer 334 is formed, for example, on the surface of the adhesion layer 332. The highly conductive layer 336 is formed, for example, on the surface of the barrier layer 334. In this embodiment, the adhesion layer 332 is composed of, for example, Ti, TiW, TiN, Ta, or TaN with a thickness between 2 nm and 200 nm. The barrier layer 334 is composed of, for example, TiW, TiN, or TaN with a thickness between 2 nm and 200 nm. The highly conductive layer 336 is composed of, for example, Au, Al, Al-Cu, or Cu with a thickness between 50 nm and 10 μm.

[0091] Figure 3B is a schematic cross-sectional view of another semiconductor device according to the third embodiment, wherein Figure 3A The same device symbols are used to represent the same or similar components, and the same or similar components can also refer to Figure 3A The relevant instructions are not repeated here.

[0092] exist Figure 3B In the figure, the cross-section of the through substrate hole TSH2 is illustrated as a trapezoidal profile. For example, the angle θ2 between the cross-section of the sidewall of the through substrate hole TSH2 and the surface 316a of the GaN epitaxial layer 316 is, for example, 45°, and the cross-sections of the sidewalls of the through substrate hole TSH2 have the same slope.

[0093] Figure 3C is a cross-sectional view of another semiconductor device according to the third embodiment, wherein Figure 3A The same device symbols are used to represent the same or similar components, and the same or similar components can also refer to Figure 3A The relevant instructions are not repeated here.

[0094] exist Figure 3C In the figure, the cross-section of the through-substrate via TSH3 is illustrated as a stepped profile. For example, the angle θ3 between the cross-section of the sidewall of the through-substrate via TSH3 within the GaN epitaxial layer 316 and the surface 316a of the GaN epitaxial layer 316 is, for example, 90°. The angle θ3′ between the cross-section of the sidewall of the through-substrate via TSH3 within the high-resistance SiC epitaxial layer 314 and the second surface 314b of the high-resistance SiC epitaxial layer 314 is, for example, 90°. The maximum width L1 of the cross-section of the through-substrate via TSH3 within the GaN epitaxial layer 316 is, for example, smaller than the maximum width L2 of the cross-section of the through-substrate via TSH3 within the high-resistance SiC epitaxial layer 314.

[0095] Figure 3D is a cross-sectional view of another semiconductor device according to the third embodiment, wherein Figure 3A The same device symbols are used to represent the same or similar components, and the same or similar components can also refer to Figure 3A The relevant instructions are not repeated here.

[0096] exist Figure 3DIn the figure, the cross-section of the through-substrate via TSH4 is illustrated as a stepped profile combined with an inclined profile. For example, the angle θ4 between the cross-section of the sidewall of the through-substrate via TSH4 located within the GaN epitaxial layer 316 and the surface 316a of the GaN epitaxial layer 316 is, for example, 60°; and the angle θ4′ between the cross-section of the sidewall of the through-substrate via TSH4 located within the high-resistance SiC epitaxial layer 314 and the second surface 314b of the high-resistance SiC epitaxial layer 314 is, for example, 60°. The maximum width L3 of the cross-section of the through-substrate via TSH4 located within the GaN epitaxial layer 316 is, for example, smaller than the maximum width L4 of the cross-section of the through-substrate via TSH4 located within the high-resistance SiC epitaxial layer 314.

[0097] Figure 3E is a cross-sectional view of another semiconductor device according to the third embodiment, wherein Figure 3A The same device symbols are used to represent the same or similar components, and the same or similar components can also refer to Figure 3A The relevant instructions are not repeated here.

[0098] exist Figure 3E In the figure, the cross-section of the through-substrate via TSH5 is illustrated as having profiles of different slopes. For example, the angle θ5 between the cross-section of the sidewall of the through-substrate via TSH5 located within the GaN epitaxial layer 316 and the surface 316a of the GaN epitaxial layer 316 is, for example, 45°; the angle θ5′ between the cross-section of the sidewall of the through-substrate via TSH5 located within the high-resistance SiC epitaxial layer 314 and the second surface 314b of the high-resistance SiC epitaxial layer 314 is, for example, 60°. The maximum width L5 of the cross-section of the through-substrate via TSH5 located within the GaN epitaxial layer 316 is, for example, smaller than the maximum width L6 of the cross-section of the through-substrate via TSH5 located within the high-resistance SiC epitaxial layer 314.

[0099] In summary, the present invention, by forming a damaged layer within an N-type silicon carbide substrate or a high-resistance silicon carbide epitaxial layer, not only allows the growth of high-quality gallium nitride with excellent crystallinity, but also, due to the presence of the damaged layer, preserves a large portion of the N-type silicon carbide substrate, enabling its reuse and thereby reducing substrate costs. Furthermore, by forming a front-side source contact covering a through-substrate via of a semiconductor substrate and then forming a back-side contact metal layer within the through-substrate via, the present invention improves the electrical connection between the front-side and back-side devices, improves the RF source impedance and the RF front-side and back-side capacitance, and reduces the range of variation of the RF source impedance and the RF front-side and back-side capacitance.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate having a through-substrate hole, the semiconductor substrate comprising: A high-resistance silicon carbide epitaxial layer having a first surface and a second surface, wherein a thickness variation rate of the high-resistance silicon carbide epitaxial layer on the first surface relative to the second surface is 5% to 10%; and a gallium nitride epitaxial layer formed on the second surface of the high-resistance silicon carbide epitaxial layer; at least one semiconductor device formed in the gallium nitride epitaxial layer; a front source contact formed on a surface of the gallium nitride epitaxial layer and covering the through-substrate hole of the semiconductor substrate; and A back contact metal layer is formed in the substrate through hole of the semiconductor substrate and directly contacts the front source contact.

2. The semiconductor device according to claim 1, wherein The thickness of the high-resistance silicon carbide epitaxial layer is between 20 μm and 50 μm.

3. The semiconductor device according to claim 1, wherein The front source contact includes: an adhesive layer formed on the surface of the gallium nitride epitaxial layer; a barrier layer formed on a surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer.

4. The semiconductor device according to claim 3, wherein The adhesion layer includes Ti, TiW, TiN, Ta or TaN with a thickness between 2nm and 200nm; the barrier layer includes Pt, Pd or Mo with a thickness between 2nm and 200nm; and the high conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50nm and 10μm.

5. The semiconductor device according to claim 1, wherein The back contact metal layer comprises: an adhesive layer formed on a surface of the through hole of the substrate; a barrier layer formed on a surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer.

6. The semiconductor device according to claim 5, wherein The adhesion layer includes Ti, TiW, TiN, Ta or TaN with a thickness between 2nm and 200nm; the barrier layer includes TiW, TiN or TaN with a thickness between 2nm and 200nm; and the high conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50nm and 10μm.

7. The semiconductor device according to claim 1, wherein An angle between a cross section of a sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 45° and 90°.

8. The semiconductor device according to claim 7, wherein An angle between a cross section of a sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 85° and 90°.

9. The semiconductor device according to claim 1, wherein The substrate through hole is a circular substrate through hole and has a diameter of 10 μm to 85 μm.

10. The semiconductor device according to claim 1, wherein The through-substrate hole is an elliptical through-substrate hole, and the product of a short axis length and a long axis length of the elliptical through-substrate hole is 10 μm×20 μm to 50 μm×120 μm.

11. The semiconductor device according to claim 1, wherein The depth of the substrate through hole is between 10 μm and 200 μm.

12. The semiconductor device according to claim 1, wherein The cross section of the substrate through hole is a stepped profile, a stepped profile plus an inclined profile, a profile with the same slope, or a profile with different slopes.

13. A method for manufacturing a semiconductor device, characterized in that: include: Epitaxially growing a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer on a first surface of an N-type silicon carbide substrate to obtain a semiconductor epitaxial substrate comprising the high-resistance silicon carbide epitaxial layer and the gallium nitride epitaxial layer, wherein the thickness variation rate of the high-resistance silicon carbide epitaxial layer is between 5% and 10%; forming a front source contact on a surface of the gallium nitride epitaxial layer; forming at least one semiconductor device on the gallium nitride epitaxial layer; After forming the front source contact and the at least one semiconductor device, bonding a wafer carrier to the surface of the gallium nitride epitaxial layer; Applying a laser from a second surface of the N-type silicon carbide substrate to form a damaged layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate, wherein the second surface is opposite to the first surface of the N-type silicon carbide substrate; separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate from the damaged layer; Using the front source contact as an etching stop layer, etching from the bottom of the semiconductor epitaxial substrate to form a substrate through-hole until a portion of the front source contact is exposed; as well as A metallization process is performed to form a back contact metal layer in the substrate through hole.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The steps of forming the front source contact include: forming an adhesion layer on the surface of the gallium nitride epitaxial layer; forming a barrier layer on a surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: The step of forming the back contact metal layer comprises: forming an adhesive layer on the surface of the through hole of the substrate; forming a barrier layer on a surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer.

16. The method for manufacturing a semiconductor device according to claim 13, wherein: The first surface of the N-type silicon carbide substrate has an angle within a range of 0°+ / −8° relative to a (0001) plane.

17. The method for manufacturing a semiconductor device according to claim 13, wherein: The method of forming the damaged layer includes applying the laser into the N-type silicon carbide substrate from the second surface of the N-type silicon carbide substrate to form the damaged layer in the N-type silicon carbide substrate.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: After separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate, the method further includes: removing the remaining N-type silicon carbide substrate.

19. The method for manufacturing a semiconductor device according to claim 13, wherein: The method for forming the damaged layer includes applying the laser from the second surface of the N-type silicon carbide substrate into the high-resistance silicon carbide epitaxial layer to form the damaged layer in the high-resistance silicon carbide epitaxial layer.

20. The method for manufacturing a semiconductor device according to claim 13, wherein: After forming the back contact metal layer, the method further includes: removing the wafer carrier; and performing a singulation process.

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