3D NAND flash memory element

Abstract

The present invention discloses a 3D NAND flash memory device, comprising: a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, a plurality of memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion extends axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate majority carriers for direct tunneling to the columnar channel portion to perform a program operation or an erase operation.

Description

Technical Field

[0001] The present invention relates to a NAND (Negative-AND) flash memory, and more particularly to a 3D NAND flash memory device. Background Art

[0002] Non-volatile memory devices have become a widely used memory device in personal computers and electronic devices due to the advantage that the stored data does not disappear even after power-off. Currently, the flash memory arrays commonly used in the industry include NOR (Negative-OR) type array structures and NAND (Negative-AND) type array structures. Since the non-volatile memory structure of the NAND type array connects each memory cell in series, its integration density and area utilization rate are relatively good, so it has been widely used in various electronic products.

[0003] Moreover, for the development of device miniaturization, currently, the mainstream of 3D NAND flash memories is to design the driving circuit under the NAND array. However, since the 3D NAND flash memory in the form of CuA (Circuit under Array) usually operates in the way of gate-induced drain leakage (GIDL), there is a problem of poor erase speed, and the GIDL operation is greatly affected by temperature. Therefore, currently, most improvement solutions are to increase the doping concentration of the drain end or the substrate. However, once the concentration increases, it is more likely to occur junction breakdown. In addition, as the number of stacked layers of the 3D NAND flash memory increases, the height of the channel also increases. Therefore, when erasing using GIDL, the amount of holes injected into the channel will be different due to the distance from the source end, resulting in different erase speeds for the same NAND string. Summary of the Invention

[0004] The present invention provides a 3D NAND flash memory device, which has the characteristics of no temperature dependence, fast and consistent erase speed, and can also be used for the layout design of the CuA architecture.

[0005] The 3D NAND flash memory element of the present invention includes: a substrate, a source line formed on the substrate, a stacked structure formed on the source line, a bit line, and at least one columnar channel portion. The stacked structure includes a first select transistor, a plurality of memory cells, and a second select transistor. The first select transistor includes a first select gate, the plurality of memory cells include a plurality of control gates, and the second select transistor includes a second select gate. The bit line is formed on the stacked structure, and the columnar channel portion axially extends from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate majority carriers to directly tunnel to the columnar channel portion to perform a programming operation or an erasing operation.

[0006] In an embodiment of the present invention, the above 3D NAND flash memory element may further include a driving circuit located on the substrate below the stacked structure.

[0007] In an embodiment of the present invention, the above first select transistor is a source-side select transistor, and the source-side select transistor may further include a first silicided metal layer and a first-type heavily doped region. The first silicided metal layer is formed between the source line and the first select gate and is isolated from the first select gate by an insulating layer. The first-type heavily doped region is formed between the first silicided metal layer and the columnar channel portion and directly contacts the first silicided metal layer and the columnar channel portion.

[0008] In an embodiment of the present invention, the materials of the above first select gate and the above second select gate include metal.

[0009] In an embodiment of the present invention, the material of the above control gate includes polysilicon.

[0010] In an embodiment of the present invention, the material of the above columnar channel portion includes n-doped polysilicon, p-doped polysilicon, or non-doped polysilicon.

[0011] In an embodiment of the present invention, the above columnar channel portion is a solid column or a hollow column.

[0012] In an embodiment of the present invention, an insulating column may further be included inside the above hollow column.

[0013] In an embodiment of the present invention, the first selection transistor is a drain-side selection transistor, and the drain-side selection transistor may further include a first silicided metal layer and a first-type heavily doped region. The first silicided metal layer is formed between the bit line and the first selection gate, and is isolated from the first selection gate by an insulating layer. The first-type heavily doped region is formed between the first silicided metal layer and the columnar channel portion, and is in direct contact with the first silicided metal layer and the columnar channel portion.

[0014] In an embodiment of the present invention, the material of the first silicided metal layer includes nickel silicide, cobalt silicide or titanium silicide.

[0015] In an embodiment of the present invention, the first-type heavily doped region includes an n+ doped region or a p+ doped region.

[0016] Based on the above, the present invention forms an ohmic contact by using an improved Schottky barrier (MSB) transistor at the source end or drain end of a 3D NAND flash memory element according to the structure design. Therefore, the program operation or erase operation can be performed through the direct tunneling of majority carriers. Therefore, the structure of the present invention is not only applicable to the CuA design with the drive circuit placed under the NAND array, but also can solve the disadvantages of complex drain-induced drain leakage (GIDL) erase method, inconsistent speeds of different pages, high temperature dependence and easy occurrence of junction breakdown.

[0017] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and are described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0018] Figure 1A is a schematic diagram of a 3D NAND flash memory element according to the first embodiment of the present invention;

[0019] Figure 1B is a waveform diagram of the conduction band and valence band of the MSB transistor of the 3D NAND flash memory element in the first embodiment during the erase operation;

[0020] Figure 1C is a simplified circuit diagram of a partial layout of the 3D NAND flash memory element in the first embodiment;

[0021] Figure 2A is a schematic diagram of a 3D NAND flash memory element according to the second embodiment of the present invention;

[0022] Figure 2BIt is a waveform schematic diagram of the conduction band and valence band for the program operation of the MSB transistor of the 3D NAND flash memory element in the second embodiment;

[0023] Figure 2C It is a simplified circuit diagram of a partial layout of the 3D NAND flash memory element in the second embodiment.

[0024] Symbol Description

[0025] 10: 3D NAND flash memory element

[0026] 100: Substrate

[0027] 102: Source line

[0028] 104: Stacked structure

[0029] 106: Bit line

[0030] 108: Columnar channel portion

[0031] 110: First select gate

[0032] 112: Second select gate

[0033] 114: Control gate

[0034] 116: First silicided metal layer

[0035] 118: First type heavily doped region

[0036] 120, 124: Insulating layer

[0037] 122: Charge trapping layer

[0038] 126: Driving circuit

[0039] 128: Dielectric layer

[0040] 132: NAND string

[0041] 200: Second silicided metal layer

[0042] 202: Second type heavily doped region Detailed implementation manners

[0043] Figure 1A It is a schematic diagram of a 3D NAND flash memory element according to the first embodiment of the present invention.

[0044] Please refer to Figure 1A, the 3D NAND flash memory element 10 of the first embodiment basically includes a substrate 100, a source line 102 formed on the substrate 100, a stack structure 104 formed on the source line 102, a bit line 106 formed on the stack structure 104, and at least one columnar channel portion 108. In the first embodiment, the stack structure 104 includes a first select transistor, a plurality of memory cells, and a second select transistor, wherein the first select transistor includes a first select gate 110, and the second select transistor includes a second select gate 112. The plurality of memory cells include a plurality of control gates 114. In one embodiment, the materials of the first select gate 110 and the second select gate 112 include a metal, such as tungsten. Figure 1A Although 4 layers of control gates 114 are shown in [the figure], it should be understood that the number of layers of the control gates 114 can be increased or decreased according to requirements, and the number of layers can be more than 10 layers, more than 20 layers, more than 30 layers, more than 40 layers, etc., and the material of the control gates 114 is, for example, polysilicon. In this embodiment, the first select transistor is a source-side select transistor, which is a modified Schottky Barrier transistor having a dopant segregated layer, and includes the first select gate 110, a first metal silicide layer 116, and a first-type heavily doped region (such as a p+ doped region) 118, and the first-type heavily doped region 118 is disposed between the columnar channel portion 108 and the first metal silicide layer 116, wherein the material of the first metal silicide layer 116 is, for example, nickel silicide (NiSi X ), cobalt silicide (CoSi X ), titanium silicide (TiSi X ), etc. The plurality of control gates 114 are located on the first select gate 110, and the second select gate 112 is located on the plurality of control gates 114, and insulating layers 120 are provided between the above gates (110, 114, 112). The bit line 106 is formed on the second select gate 112 of the stack structure 104.

[0045] Please continue to refer to Figure 1A, the columnar channel portion 108 extends axially from the source line 102 and penetrates the stacked structure 104 to be coupled to the bit line 106, where the material of the columnar channel portion 108 is, for example, n-doped polysilicon, p-doped polysilicon, or non-doped polysilicon. The plurality of memory cells may further include a charge trapping layer 122 formed between the control gate 114 and the columnar channel portion 108 and surrounding the columnar channel portion 108, where the charge trapping layer 122 includes, for example, a silicon oxide layer, a silicon nitride layer, a composite layer of silicon oxide layers (ONO layer), or other suitable structural layers. Since the source-side select transistor has the first silicided metal layer 116 and the first-type heavily doped region 118 to form an Ohmic Contact, the erase operation can be performed through the direct tunneling of majority carriers, which has the characteristics of fast erase speed and no temperature dependence compared with the conventional structure performing GIDL erase. As Figure 1B shown, the first (source-side) select gate 110 applies an erase voltage to turn on the source-side select transistor (n-state), so that majority carriers (i.e., holes) are generated and directly tunnel to the columnar channel portion 108 to perform the erase operation.

[0046] In Figure 1A , another insulating layer 124 may be further disposed between the first select gate 110 and the columnar channel portion 108 and between the second select gate 112 and the columnar channel portion 108 to electrically isolate the columnar channel portion 108 from the above select gates (110 and 112). In this embodiment, since the columnar channel portion 108 does not need to directly contact the substrate 100, the 3D NAND flash memory element 10 can be used in the CuA architecture, that is, a drive circuit 126, such as a CMOS circuit, can be further disposed on the substrate 100 below the stacked structure 104, and a dielectric layer 128 covers it, and a doped polysilicon layer or non-doped polysilicon layer serving as the source line 102 can be disposed between the dielectric layer 128 and the first silicided metal layer 116. Moreover, the columnar channel portion 108 in this embodiment shows a solid pillar, however, the present invention is not limited thereto; in another embodiment, the columnar channel portion 108 may be a hollow pillar, and an insulating pillar (not shown), such as an oxide, may be further included in the hollow pillar, thus constituting a structure similar to the SOI (silicon-on-insulator) concept.

[0047] Figure 1CA simplified circuit diagram of a partial layout of a 3D NAND flash memory element according to a first embodiment, in which a NAND string 132 is shown, and the NAND string 132 includes a first select transistor including a first select gate 110, a plurality of memory cells including a plurality of control gates 114, and a second select transistor including a second select gate 112. The NAND string 132 is configured between a bit line 106 and a source line 102, and an erase operation can be performed via direct tunneling.

[0048] Figure 2A A schematic diagram of a 3D NAND flash memory element according to a second embodiment of the present invention, in which the same or similar components are denoted by the same component symbols as those in the first embodiment, and the content of the same or similar components can also be referred to the content of the first embodiment and will not be repeated here.

[0049] Please refer to Figure 2A , the difference between this embodiment and the first embodiment is that the drain-side select transistor is also an improved Schottky barrier transistor, including a second (drain-side) select gate 112, a second silicide layer 200, and a second-type heavily doped region (such as an n+ doped region) 202 disposed between the columnar channel portion 108 and the second silicide layer 200, wherein the material of the second silicide layer 200 is the same as that of the first silicide layer 116. Since the drain-side select transistor forms an ohmic contact due to the second silicide layer 200 and the second-type heavily doped region 202, a programming operation can be performed through direct tunneling of majority carriers. As Figure 2B shown, a programming voltage is applied to the second select gate 112 to turn on the drain-side select transistor, so that majority carriers (i.e., electrons) are generated and directly tunnel to the columnar channel portion 108 to perform a programming operation. In addition, although terms such as "first" and "second" are used herein to describe different elements, regions, and film layers, these elements, regions, and film layers should not be limited by these terms. Instead, these terms are only used to distinguish one element, region, or film layer from another element, region, or film layer. Therefore, the above drain-side select transistor can also be referred to as the first select transistor, and the above source-side select transistor can also be referred to as the second select transistor without departing from the teachings of the embodiment.

[0050] Figure 2C A simplified circuit diagram of a partial layout of a 3D NAND flash memory element according to the second embodiment, in which the NAND string 132 and Figure 1CIt also includes a first select transistor including a first select gate 110, a plurality of memory cells including a plurality of control gates 114, and a second select transistor including a second select gate 112. Moreover, in addition to performing an erase operation via direct tunneling, the NAND string 132 can also perform a program operation through direct tunneling due to the provision of the second silicide metal layer 200 and the second-type heavily doped region 202.

[0051] In summary, in the 3D NAND flash memory device of the above embodiment, since the source-side select transistor replaces the conventional metal oxide semiconductor transistor with an improved Schottky barrier (MSB) transistor, the erase operation can be performed through the direct tunneling of majority carriers. Therefore, compared with the GIDL erase speed, it is faster and more consistent, and can be applied to the CuA design with the drive circuit placed under the NAND array, and the erase speed is not affected by temperature. In other embodiments, the improved MSB transistor serves as the drain-side select transistor, and is not limited to performing the erase operation, but can also be used to perform the program operation. Additionally, if the improved MSB transistors are used for both the source-side select transistor and the drain-side select transistor, the program operation and erase operation of the device can be achieved through the direct tunneling of majority carriers.

[0052] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A 3D NAND flash memory element, characterized in that, Comprising: A substrate; A source line formed on the substrate; A stacked structure formed on the source line, the stacked structure including a first select transistor, a plurality of memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the plurality of memory cells include a plurality of control gates, and the second select transistor includes a second select gate; A bit line formed on the stacked structure; and At least one columnar channel portion axially extending from the source line and penetrating the stacked structure to be coupled to the bit line, wherein the first select transistor further includes a first silicided metal layer and a first-type heavily doped region, the first-type heavily doped region being located at one end of the axial direction of the columnar channel portion, which is in direct contact with the first silicided metal layer and the columnar channel portion respectively and forms a modified Schottky barrier (MSB) transistor, so that the majority carriers of the first-type heavily doped region directly tunnel to the columnar channel portion to perform a programming operation or an erasing operation.

2. The 3D NAND flash memory device according to claim 1, further comprising a driving circuit located on the substrate below the stacked structure.

3. The 3D NAND flash memory device according to claim 1, wherein the first select transistor is a source-side select transistor, the first silicided metal layer is directly formed on the surface of the source line, and is isolated from the first select gate by an insulating layer.

4. The 3D NAND flash memory device according to claim 3, wherein the material of the first metal silicide layer comprises nickel silicide (NiSi X ), cobalt silicide (CoSi X ), or titanium silicide (TiSi X ).

5. The 3D NAND flash memory device according to claim 1, wherein the materials of the first select gate and the second select gate include metal.

6. The 3D NAND flash memory device according to claim 1, wherein the materials of the plurality of control gates include polysilicon.

7. The 3D NAND flash memory device according to claim 1, wherein the material of the columnar channel portion includes n-doped polysilicon, p-doped polysilicon, or non-doped polysilicon.

8. The 3D NAND flash memory device according to claim 1, wherein the columnar channel portion is a solid column or a hollow column.

9. The 3D NAND flash memory device according to claim 8, wherein an insulating column is further included inside the hollow column.

10. The 3D NAND flash memory device according to claim 1, wherein the first select transistor is a drain-side select transistor, the first silicided metal layer is directly formed on the surface of the bit line, and is isolated from the first select gate by an insulating layer.

11. The 3D NAND flash memory element according to claim 10, wherein the material of the first metal silicide layer comprises nickel silicide (NiSi X ), cobalt silicide (CoSi X ), or titanium silicide (TiSi X ).

12. The 3D NAND flash memory device according to claim 1, wherein the first-type heavily doped region includes an n+ doped region or a p+ doped region.

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