A gate-controlled avalanche trigger structure and semiconductor pulse power device

Abstract

The present invention discloses a gate-controlled avalanche trigger structure, which comprises, from bottom to top, a cathode metal, a substrate, an epitaxial layer, an anode metal, and a gate metal. A first doped region and a second doped region are provided within the epitaxial layer. The first doped region originates from the upper surface of the epitaxial layer and extends downward to the lower surface of the epitaxial layer. The second doped region originates from the upper surface of the epitaxial layer on the left and extends downward into the epitaxial layer, while a portion of the epitaxial layer is left as a drift region. The anode metal is located above the second doped region. The gate metal is located above the epitaxial layer between the first doped region and the second doped region, and a gate and a gate dielectric layer are provided between the gate metal and the epitaxial layer. The gate-controlled avalanche trigger structure provided by the present invention causes the device to avalanche by applying an external gate voltage, generating plasma to enable rapid conduction. This structure can separate the trigger signal from the operating current, reducing the complexity of the drive circuit design.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gate-controlled avalanche trigger structure and a semiconductor pulse power device. Background Art

[0002] With the deepening of technological research, this technology has gradually emerged in industrial production. Currently, pulse power has been widely used in many fields, including environmental protection, aerospace, biomedicine, resource extraction, military industry, and national defense. Pulse power switches are the core of pulse power technology. With the deepening of semiconductor theoretical research and the maturity of semiconductor manufacturing processes, semiconductor switches have occupied a key position in pulse power switching. Semiconductor switches used in pulse power technology are called semiconductor pulse power devices.

[0003] Traditional semiconductor pulse power devices primarily include gate-turn-off thyristors (GTOs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs). In recent years, with the continued advancement of pulse power technology, new devices have emerged, such as reversely switched dynistors (RSDs), fast ionization dynistors (FIDs), drift step recovery diodes (DSRDs), and diode avalanche shapers (DASs). These devices have important applications in a wide range of fields. As a type of pulse power device, closed-loop devices (CLDs) can quickly release energy stored in capacitors. They are commonly used in applications requiring high power output within a short period of time, such as spacecraft landings, missile launches, and electromagnetic pulses (EMPs).

[0004] However, the trigger circuits of existing closed-circuit devices (such as FIDs and DASs) are complex, requiring specific requirements for both the strength and speed of the trigger signal. Furthermore, as two-terminal devices, the trigger signal and operating current are coupled together, requiring additional circuit design to prevent interference between them. This further increases circuit complexity and results in high energy loss during the triggering process. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a gate-controlled avalanche trigger structure and a semiconductor pulse power device. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a gate-controlled avalanche trigger structure, which comprises, from bottom to top, a cathode metal, a substrate, an epitaxial layer, an anode metal, and a gate metal; wherein,

[0007] A first doping region and a second doping region are provided inside the epitaxial layer;

[0008] The first doped region starts from the upper surface of the epitaxial layer and extends downward to the lower surface of the epitaxial layer;

[0009] The second doped region starts from the upper surface of the epitaxial layer on the left and extends downward to the interior of the epitaxial layer, while leaving a portion of the epitaxial layer as a drift region;

[0010] The anode metal is located above the second doped region;

[0011] The gate metal is located above the epitaxial layer between the first doping region and the second doping region, and a gate electrode and a gate dielectric layer are provided between the gate metal and the epitaxial layer.

[0012] In one embodiment of the present invention, the epitaxial layer and the substrate are heterotype doped.

[0013] In one embodiment of the present invention, the first doping region, the second doping region, and the epitaxial layer have the same doping type.

[0014] In one embodiment of the present invention, both the first doping region and the second doping region are heavily doped regions, and the epitaxial layer is a lightly doped region.

[0015] In one embodiment of the present invention, the gate is made of polysilicon.

[0016] In one embodiment of the present invention, the substrate is N+ doped, the epitaxial layer is P- doped, and the first doped region and the second doped region are both P+ doped.

[0017] In a second aspect, the present invention also provides another gate-controlled avalanche trigger structure, comprising the gate-controlled avalanche trigger structure provided by the above embodiment in which two first doped regions are adjacent and symmetrically arranged; wherein a gate dielectric layer, a gate electrode and a gate metal are sequentially arranged above the first doped regions.

[0018] In a third aspect, the present invention further provides a semiconductor pulse power device comprising the gate-controlled avalanche trigger structure as described in any one of the above embodiments.

[0019] Beneficial effects of the present invention:

[0020] 1. The gate-controlled avalanche trigger structure provided by the present invention uses an external gate voltage to cause the device to avalanche, generating plasma to quickly turn on. This structure can separate the trigger signal from the operating current, reducing the complexity of the drive circuit design and reducing energy loss during the triggering process.

[0021] 2. The gate-controlled avalanche trigger structure provided by the present invention can be applied to certain closed devices in pulse power systems. The device breakdown voltage is controlled by the gate voltage, thereby changing the device breakdown voltage. When the applied gate voltage makes the device breakdown voltage lower than the voltage between the cathode and anode, the device will break down, and the plasma generated by the breakdown will cause the device to turn on quickly.

[0022] 3. The gate-controlled avalanche trigger structure provided by the present invention can also be used directly as a DAS. Compared with traditional DAS devices, the present invention uses a device with adjustable breakdown voltage to shape devices with more different pulse peaks, thereby broadening the peak range of a single DAS pulse shaping.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of a gate-controlled avalanche trigger structure provided by an embodiment of the present invention;

[0025] Figure 2 Schematic diagram of a gate-controlled avalanche trigger structure with an N+ substrate provided by an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of another gate-controlled avalanche trigger structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0028] Example 1

[0029] See Figure 1 , Figure 1 Schematic diagram of a gate-controlled avalanche trigger structure provided by an embodiment of the present invention, which includes, from bottom to top, a cathode metal 1, a substrate 2, an epitaxial layer 3, an anode metal 4, and a gate metal 5; wherein,

[0030] The epitaxial layer 3 is provided with a first doping region 31 and a second doping region 32;

[0031] The first doped region 31 starts from the right upper surface of the epitaxial layer 3 and extends downward to the lower surface of the epitaxial layer 3;

[0032] The second doped region 32 starts from the upper surface of the epitaxial layer 3 on the left and extends downward to the interior of the epitaxial layer 3 , while leaving a portion of the epitaxial layer 3 as a drift region 33 ;

[0033] The anode metal 4 is located above the second doping region 32;

[0034] The gate metal 5 is located above the epitaxial layer 3 between the first doping region 31 and the second doping region 32 , and a gate 6 and a gate dielectric layer 7 are further provided between the gate metal 5 and the epitaxial layer 3 .

[0035] The epitaxial layer 3 and the substrate 2 are heterotype doped.

[0036] Furthermore, the first doped region 31, the second doped region 32, and the epitaxial layer 3 have the same doping type. Furthermore, the first doped region 31 and the second doped region 32 are both heavily doped regions, while the epitaxial layer 3 is lightly doped. The second doped region 32 extends from the upper left corner of the left epitaxial layer 3 to the lower right into the epitaxial layer 3, and is spaced a certain distance L from the second doped region 32. Simultaneously, a drift region 33 with a thickness of D is formed in the epitaxial layer 3.

[0037] It can be understood that the drift region 33 is a lightly doped region, and its thickness D is smaller than the thickness of the epitaxial layer 3 .

[0038] Generally, the substrate can be N-type doped or P-type doped. Considering that N-type substrates are mostly used in practical applications, this embodiment preferably uses an N+ substrate and a P-epitaxial layer to implement the device structure. Among them, the material of the N+ substrate is a semiconductor material such as silicon or silicon carbide, and the interface between the cathode metal 1 and the substrate 2 forms an ohmic contact. Correspondingly, the epitaxial layer 3 is lightly P-doped, denoted as a P-epitaxial layer, which can be formed by homoepitaxial growth on the basis of the substrate. The first doped region 31 and the second doped region 32 are both P+ doped, the drift region 33 is a P-drift region, the interface between the anode metal 4 and the second doped region 32 forms an ohmic contact, and the gate 6 is formed of polysilicon material.

[0039] The principle of the gate-controlled avalanche trigger structure provided by this embodiment is described below by taking a gate-controlled avalanche trigger structure with an N+ substrate as an example.

[0040] See Figure 2 , Figure 2This is a schematic diagram of a gate-controlled avalanche trigger structure with an N+ substrate provided by an embodiment of the present invention. The gate-controlled avalanche trigger structure provided by this embodiment can be simply viewed as consisting of three parts: the first part is a punch-through PiN diode-like structure consisting of the p+ second doped region 32, the p- drift region 33, and the N+ substrate 2; the second part is a MOS structure consisting of the polysilicon gate 6, the gate dielectric layer 7, and the P- drift region 33; and the third part is a PN junction structure formed by the p+ first doped region 31 and the N+ substrate 2.

[0041] Assuming the static breakdown voltage of the punch-through PiN diode structure is V1, and the static breakdown voltage of the PN junction structure is V2, it is easy for V1 to be greater than V2. If V1>V>V2, then a voltage V is applied to the cathode metal 1, the anode metal 4 is connected to 0 potential, and no voltage is applied to the gate metal 5. At this time, the punch-through PiN structure is reversely stressed, and the P-drift region 33 is in a depleted state. At this time, gradually applying a negative voltage to the gate metal 5 will cause the area below the gate dielectric 7 to gradually change from a depleted state to an accumulated state. The applied voltage V will gradually be borne by the PN structure, and when the voltage across the PN junction reaches V2, the device will breakdown. Therefore, the device breakdown can be controlled by the voltage on the gate metal 5. The voltage on the gate metal 5 can be used to adjust the weight of the voltage distributed across the PN junction between the cathode metal 1 and the anode metal 4, thereby changing the device breakdown voltage. The range of breakdown voltage change is [V2, V1].

[0042] Furthermore, the breakdown voltage range of the structure can be adjusted by adjusting the doping concentration and thickness D of the drift region 33, the interval L between the second doping region 32 and the first doping region 31, or the doping concentration between the first doping region 31 and the second doping region 32 to change V2, V1, and their voltage difference.

[0043] The gate-controlled avalanche trigger structure provided in this embodiment uses an external gate voltage to cause the device to avalanche, generating plasma to enable it to turn on quickly; this structure can separate the trigger signal from the operating current, reduce the complexity of the drive circuit design, and reduce energy loss during the triggering process.

[0044] Example 2

[0045] Based on the above embodiment 1, this embodiment provides another gate-controlled avalanche trigger structure. Figure 3 , Figure 3 This is a schematic diagram of another gate-controlled avalanche trigger structure provided by an embodiment of the present invention, which includes the gate-controlled avalanche trigger structure provided by the above-mentioned embodiment 1 in which two first doped regions 31 are adjacent and symmetrically arranged; wherein, a gate dielectric layer 7, a gate 6 and a gate metal 5 are sequentially provided above the first doped regions 31.

[0046] Since the gate-controlled avalanche trigger structure provided in this embodiment is symmetrically formed by the gate-controlled avalanche trigger structure provided in the above-mentioned embodiment 1, and a MOS structure is also formed above the first doped region 31, the gate-controlled avalanche trigger structure of this embodiment also has the advantages of the above-mentioned embodiment 1. Its specific working principle can be found in the above-mentioned embodiment 1 and will not be described in detail here.

[0047] The gate-controlled avalanche trigger structure provided in this embodiment is based on the above-mentioned embodiment 1. Through one gate control, both sides can be turned on at the same time, thereby increasing the current density during conduction and improving the chip utilization efficiency without bringing additional process complexity.

[0048] Example 3

[0049] On the basis of the above-mentioned embodiment 1 or 2, this embodiment provides a semiconductor pulse power device, which includes the gate-controlled avalanche trigger structure described in the above-mentioned embodiment 1 or 2.

[0050] Specifically, since the gate-controlled avalanche trigger structure provided in the above-mentioned embodiment 1 and embodiment 2 has the function of using gate voltage to control the breakdown of the device and generate plasma, the device can be turned on in a short time and can be used for pulse generation, and thus can be used as a pulse power device.

[0051] Furthermore, since the breakdown voltage of the device in the first and second embodiments is affected by the gate voltage, that is, the breakdown voltage is sensitive to the gate charge, the device can also be used for electrostatic detection and electrostatic protection.

[0052] Furthermore, the gate-controlled avalanche trigger structure provided in this embodiment can also be used directly as a DAS. Because existing DASs are similar to PIN diodes, they can only shape pulses whose peak voltage exceeds their breakdown voltage. If the peak value exceeds the DAS breakdown voltage by a significant amount, the shaping effect is poor. However, using the device with adjustable breakdown voltage as a DAS, such as that provided in this embodiment, can shape pulses with a wider range of peak values, broadening the peak range of pulse shaping capabilities of a single DAS.

[0053] It should be noted that, in this embodiment, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0054] In addition, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0055] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0056] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A gate-controlled avalanche trigger structure, characterized in that: From bottom to top, it includes: cathode metal (1), substrate (2), epitaxial layer (3), anode metal (4) and gate metal (5); wherein, A first doping region (31) and a second doping region (32) are provided inside the epitaxial layer (3); The first doping region (31) starts from the upper surface of the epitaxial layer (3) and extends downward to the lower surface of the epitaxial layer (3); The second doping region (32) starts from the upper surface of the epitaxial layer (3) on the left and extends downward to the interior of the epitaxial layer (3), while a portion of the epitaxial layer (3) is reserved as a drift region (33); The anode metal (4) is located above the second doping region (32); The gate metal (5) is located above the epitaxial layer (3) between the first doping region (31) and the second doping region (32), and a gate (6) and a gate dielectric layer (7) are further provided between the gate metal (5) and the epitaxial layer (3); The first doping region (31) and the second doping region (32) are both heavily doped regions, and the epitaxial layer (3) is a lightly doped region; when the substrate (2) is N+ doped, the epitaxial layer (3) is P- doped, the first doping region (31) and the second doping region (32) are both P+ doped, and the drift region (33) is P- doped; the gate-controlled avalanche trigger structure comprises three parts, the first part being a punch-through PiN diode structure consisting of the P+ second doping region (32), the P- drift region (33) and the N+ substrate (2); the second part being the gate (6), the gate dielectric layer (6) and the gate dielectric layer (6). (7) and the P-drift region (33) constitute a MOS structure; the third part is a PN junction structure constituted by the P+ first doping region (31) and the N+ substrate (2); assuming that the static breakdown voltage of the punch-through PiN diode structure is V1, and the static breakdown voltage of the PN junction structure is V2, a voltage V is applied to the cathode metal (1), and the anode metal (4) is connected to 0 potential. The voltage on the gate metal (5) is used to adjust the weight of the voltage applied between the cathode metal (1) and the anode metal (4) on the PN junction, thereby changing the breakdown voltage of the device. The range of the breakdown voltage change is [V2, V1].

2. The gate-controlled avalanche trigger structure according to claim 1, characterized in that: The epitaxial layer (3) and the substrate (2) are heterotype doped.

3. The gate-controlled avalanche trigger structure according to claim 1, wherein: The first doping region (31), the second doping region (32) and the epitaxial layer (3) have the same doping type.

4. The gate-controlled avalanche trigger structure according to claim 1, wherein: The gate (6) is made of polysilicon.

5. A gate-controlled avalanche trigger structure, characterized in that: A gate-controlled avalanche trigger structure according to any one of claims 1 to 4, comprising two first doped regions (31) adjacent to and symmetrically arranged; wherein a gate dielectric layer (7), a gate electrode (6) and a gate metal (5) are sequentially arranged above the first doped regions (31).

6. A semiconductor pulse power device, characterized in that: The invention comprises a gate-controlled avalanche triggering structure as described in any one of claims 1 to 5.

Images