Electronic device and manufacturing method thereof

Abstract

An electronic device provided by the present invention may include a semiconductor memory configured to include a plurality of memory cells, wherein each of the plurality of memory cells may include: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple the electrical connection between the first electrode layer and the second electrode layer based on the magnitude of an applied voltage or an applied current relative to a threshold magnitude, wherein the selection element layer has a dopant concentration profile that decreases from an interface between the selection element layer and the first electrode layer to an interface between the selection element layer and the second electrode layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2020 - 0129145, filed on Oct. 7, 2020, with the title "Method of Manufacturing an Electronic Device", the entire content of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the disclosed technology relate to memory devices and their applications in electronic devices or systems. Background Art

[0004] With the latest developments in personal computers and mobile devices, there is a need for miniaturized, low - power, high - performance, multi - functional electronic devices capable of storing information. Examples of such electronic devices include, but are not limited to, memory devices that can store data using specific materials that have different resistance states depending on an applied voltage or current, such as RRAM (Resistive Random Access Memory), PRAM (Phase - Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), and electric fuses. Summary of the Invention

[0005] Embodiments of the technology disclosed in this patent document relate to memory circuits / devices and their applications in electronic devices / systems. The disclosed technology can be used in some embodiments to provide an electronic device including a semiconductor memory that stores data using variable - resistance elements that exhibit different resistance states.

[0006] In one aspect, an electronic device may include a semiconductor memory configured to include a plurality of memory cells, wherein each of the plurality of memory cells may include: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current relative to a threshold magnitude, wherein the selection element layer has a dopant concentration profile that decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

[0007] In another aspect, a method of manufacturing an electronic device, the electronic device including a semiconductor memory including a plurality of memory cells, the method may include: forming a first electrode layer in each memory cell over a substrate; forming a select element layer over the first electrode layer in each memory cell to turn on or off the memory cell; performing a first ion implantation process to inject a dopant into the resultant structure of each memory cell on the substrate including the first electrode layer and the select element layer such that a projected range associated with the first ion implantation process corresponds to an interface between the first electrode layer and the select element layer; and forming a second electrode layer over the select element layer.

[0008] These and other aspects, embodiments and related advantages are described in more detail in the drawings, the specification and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1D is a cross-sectional view showing a method of manufacturing a semiconductor memory based on an example where an undesired interface layer 14 formed between a switching element layer 13 and a lower electrode layer 12 is not controlled.

[0010] Figure 2 is a perspective view showing an example of a semiconductor memory based on an embodiment of the disclosed technology.

[0011] Figure 3 shows Figure 2 an example structure of the semiconductor memory shown.

[0012] Figures 4A to 4I is a cross-sectional view showing a method of manufacturing a semiconductor memory based on an embodiment of the disclosed technology.

[0013] Figure 5 shows an example configuration of a microprocessor including a memory circuit based on an embodiment of the disclosed technology.

[0014] Figure 6 shows an example configuration of a processor including a memory circuit based on an embodiment of the disclosed technology.

[0015] Figure 7 shows an example configuration of a system including a memory circuit based on an embodiment of the disclosed technology.

[0016] Figure 8 shows an example configuration of a storage system including a memory circuit based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0017] The technology disclosed in this patent document can be implemented in some embodiments to provide a semiconductor device capable of suppressing the formation of an undesired interface layer.

[0018] Figures 1A to 1D FIG. is a cross-sectional view showing a method of manufacturing a semiconductor memory based on an example in which an undesired interface layer 14 formed between a switching element layer 13 and a lower electrode layer 12 is not controlled.

[0019] Reference Figure 1D , the semiconductor memory may include a memory cell 10 formed above a substrate 11.

[0020] The memory cell 10 may include a lower electrode layer 12, a switching element layer 13, and an upper electrode layer 15.

[0021] The semiconductor memory including the memory cell 10 may have a cross-point memory array structure employed in a cell region of a highly integrated memory device. More specifically, the cross-point memory array structure may be included in a memory device such as RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), etc.

[0022] Reference Figure 1A , the lower electrode layer 12 may be formed on the substrate 11. The lower electrode layer 12 may have a single-layer structure or a multi-layer structure including various conductive materials (such as metals, metal nitrides, conductive carbon materials, or combinations thereof).

[0023] Reference Figure 1B , the switching element layer 13 may be formed above the lower electrode layer 12.

[0024] The switching element layer 13 may be configured to exhibit different states in response to a voltage or current applied to the switching element layer 13, and may be controlled to perform a threshold switching operation in a cross-point semiconductor array structure. To this end, the switching element layer 13 may be a free layer exhibiting different magnetization directions in a magnetic tunnel junction (MTJ) structure, and may be controlled to switch between different magnetization directions in response to the applied voltage or current.

[0025] The switching element layer 13 may be formed by forming a material layer 13A for the switching element layer 13 and then doping the material layer 13A with a dopant by performing an ion implantation process. For example, the material layer 13A may include silicon oxide, etc., and the dopant may include Cu, etc.

[0026] Reference Figure 1C, when forming the switching element layer 13 by forming the material layer 13A and performing an ion implantation process, an undesired interface layer 14 may be formed at the interface between the switching element layer 13 and the lower electrode layer 12 due to the reaction between the switching element layer 13 and the lower electrode layer 12.

[0027] Reference Figure 1D , an upper electrode layer 15 can be formed over the switching element layer 13. The upper electrode layer 15 can have a single-layer structure or a multi-layer structure including various conductive materials (such as metals, metal nitrides, conductive carbon materials, or combinations thereof).

[0028] Therefore, in Figures 1A to 1D The method for manufacturing a semiconductor memory as shown may generate an undesired interface layer 14 at the interface between the switching element layer 13 and the lower electrode layer 12. When forming the switching element layer 13, for example, due to interdiffusion or intermixing between the lower electrode layer 12 and the switching element layer 13, an interface layer 14 can be formed at the interface between the switching element layer 13 and the lower electrode layer 12. The interface layer 14 can include oxides, nitrides, or oxynitrides containing substances included in the lower electrode layer 12. For example, when the lower electrode layer 12 includes TiN, the interface layer 14 can include, for example, TiO x N y , which contains titanium, oxygen, and / or nitrogen.

[0029] The interface layer 14 formed between the lower electrode layer 12 and the switching element layer 13 causes an undesired increase in the forming voltage (Vf) used for the set / reset operation of the semiconductor memory. A high forming voltage (Vf) can deteriorate the off-state current (Ioff) characteristics. The off-state current Ioff may occur in the "off" state of the semiconductor memory, resulting in parasitic current or leakage current.

[0030] In an embodiment of the disclosed technology, a semiconductor memory can be formed in a manner that effectively controls the interface layer that may be generated at the interface between the switching element layer and the lower electrode layer during the formation of the switching element layer to improve the Vf and Ioff characteristics.

[0031] Figure 2 is a perspective view showing an example of a semiconductor memory based on an embodiment of the disclosed technology.

[0032] According to the present disclosure Figure 2The semiconductor memory according to the embodiment in [reference] may have a cross-point structure, which includes: a first line 110 extending in a first direction respectively; a second line 180 located above the first line 110 and extending in a second direction crossing the first direction respectively; and a memory cell 120 located between the first line 110 and the second line 180. The memory cell 120 is disposed at each cross-point of the first line 110 and the second line 180. In this patent document, the term "line" may be used to represent an interconnect line, which is conductive to carry an electrical signal.

[0033] Figure 3 shows Figure 2 an example structure of the semiconductor memory shown.

[0034] Referring to Figure 3 , each of the plurality of memory cells 120 may include a lower electrode layer 121, a barrier layer 122, a select element layer 123, an intermediate electrode layer 125, a variable resistance layer 127, and an upper electrode layer 129 which are sequentially stacked.

[0035] As Figure 2 and Figure 3 shown, each of the plurality of memory cells 120 may have a columnar shape. The plurality of memory cells 120 may be arranged in a matrix having rows and columns. The rows extend in the first direction respectively, while the columns extend in the second direction crossing the first direction. The memory cells 120 may be disposed in each cross-region between the first line 110 and the second line 180. In one embodiment, the size of each memory cell 120 may be substantially equal to or less than the size of the corresponding cross-region between each pair of the first line 110 and the second line 180. In another embodiment, the size of each memory cell 120 may be greater than the size of the corresponding cross-region between each pair of the first line 110 and the second line 180.

[0036] Reference will be made to Figures 4A to 4I for a more specific description of the semiconductor memory according to the embodiments of the disclosed technology in Figure 2 and Figure 3 .

[0037] Figures 4A to 4I is a cross-sectional view of a semiconductor device taken along line A-A' of Figure 2 .

[0038] Figures 4A to 4I is a cross-sectional view showing a method of manufacturing a semiconductor memory according to an embodiment of the disclosed technology.

[0039] Referring to Figure 4A , the substrate 100 may include in Figures 4A to 4IA structure (not shown) formed prior to the manufacturing process shown. For example, the structure may include one or more transistors to control formation on substrate 100 of Figure 2 , Figure 3 and Figure 4I first line 110, second line 180, or first line 110 and second line 180.

[0040] Each first line 110 extending in a first direction (e.g., the horizontal direction in Figure 2 ) may be formed above substrate 100. The first line 110 may have a single-layer structure or a multi-layer structure and may include a conductive material such as metal, metal nitride, etc. The first line 110 may be formed by depositing a layer including the conductive material and patterning the deposited layer. The space between the first lines 110 may be filled with an insulating material (not shown).

[0041] Referring to Figure 4B , the lower electrode layer 121 may be formed above the first line 110.

[0042] The lower electrode layer 121 may be located at the lowermost part of each memory cell 120 and serve as a circuit node for carrying voltage or current between a corresponding one of the first lines 110 and the rest of each memory cell 120 (e.g., elements 122, 123, 125, 127, and 129).

[0043] The lower electrode layer 121 may have a single-layer structure or a multi-layer structure and may include a conductive material such as metal, metal nitride, conductive carbon material, etc.

[0044] Referring to Figure 4C , the barrier layer 122 may be formed above the lower electrode layer 121.

[0045] The barrier layer 122 may be disposed between the lower electrode layer 121 and the select element layer 123. The barrier layer 122 may inhibit the formation of an undesired interface layer formed due to interdiffusion or intermixing between the lower electrode layer 121 and the select element layer 123, thereby effectively reducing Vf. The barrier layer 122 may also increase the barrier height acting as a tunnel barrier, thereby effectively reducing Ioff.

[0046] In one embodiment, the thickness of the barrier layer 122 may be in the range of 5 to 25 angstroms . The barrier layer 122 has a small thickness, e.g., thickness, so as to effectively inhibit the formation of an undesired interface layer, increase the barrier height, and prevent degradation of device characteristics.

[0047] In one embodiment, the blocking layer 122 may include one or more materials selected from silicon, oxides, nitrides, and oxynitrides. For example, the blocking layer 122 may include Al2O3, TiO2, TaAlON, MgO, Si3N4, Si, SiON, or similar materials.

[0048] Reference Figure 4D , a select element layer 123 may be formed over the blocking layer 122.

[0049] The select element layer 123 may be used to control access to the variable resistance layer 127 therein by conducting a circuit path to the variable resistance layer 127 to read or write data therein, or by turning off the circuit path to the variable resistance layer 127. Figure 3 and Figure 4I That is, the select element layer 123 may function as a switching element that turns off or deselects the memory cell 120 by preventing current from passing through the select element layer 123 when the magnitude of the applied voltage or applied current is below a threshold, and turns on or selects the memory cell 120 by allowing current to pass through the select element layer 123 when the magnitude of the applied voltage or applied current is substantially equal to or greater than the threshold. For example, the magnitude of the current flowing through the select element layer 123 is proportional to the magnitude of the voltage or current applied to the select element layer 123. The select element layer 123 may have a single-layer structure or a multi-layer structure that exhibits select element characteristics using a combination of two or more layers.

[0050] In some embodiments, the select element layer 123 may include: MIT (metal-insulator transition) elements such as NbO2 or TiO2; MIEC (mixed ionic-electronic conducting) elements such as ZrO2(Y2O3), Bi2O3-BaO, or (La2O3) x (CeO2) 1-x ; OTS (bidirectional threshold switch) elements that include chalcogenide-based materials such as Ge2Sb2Te5, As2Te3, As2, As2Se3; or combinations thereof.

[0051] In certain embodiments, the select element layer 123 may include a tunneling dielectric layer. The tunneling dielectric layer includes one or more of various dielectric materials such as silicon oxide, silicon nitride, and metal oxides. The thickness of the tunneling dielectric layer is small enough to allow electron tunneling to occur at a given voltage or given current.

[0052] In one embodiment, the select element layer 123 may be configured to perform a threshold switching operation. In this patent document, the term "threshold switching operation" may be used to indicate turning on or off the select element layer 123 when an external voltage is applied to the select element layer 123. In this case, the absolute value of the external voltage may gradually increase or decrease. When the absolute value of the external voltage applied to the select element layer 123 increases, the select element layer 123 may be turned on, resulting in a non-linear increase in the operating current when the absolute value of the external voltage is greater than a first threshold voltage. After the select element layer 123 is turned on, when the absolute value of the external voltage applied to the select element layer 123 decreases, the select element layer 123 may be turned off, resulting in a non-linear decrease in the operating current when the absolute value of the external voltage is less than a second threshold voltage. Thus, the select element layer 123 performing the threshold switching operation may have non-storage operating characteristics.

[0053] In one embodiment, the select element layer 123 may be formed by forming a material layer for the select element layer 123 and doping the material layer with a dopant.

[0054] The material layer for the select element layer 123 may include an insulating material such as silicon oxide, silicon nitride, metal oxide, metal nitride, or a combination thereof.

[0055] The dopant doped into the material layer for the select element layer 123 may include an n-type dopant or a p-type dopant. The dopant may be formed in the material layer by an ion implantation process.

[0056] The dopant doped into the material layer for the select element layer 123 may include, for example, one or more of B, N, C, P, As, Al, Si, or Ge.

[0057] The select element layer 123 may perform a threshold switching operation through a doped region formed in the material layer for the select element layer 123. Thus, the size of the threshold switching operation region may be controlled by the distribution region of the dopant. The dopant may form charge carrier trapping sites in the material layer for the select element layer 123. Based on the external voltage applied to the select element layer 123, the trapping sites may trap charge carriers moving in the select element layer 123 between the intermediate electrode layer (e.g., Figure 3 and Figure 4I the reference numeral 125 therein) and the upper electrode layer (e.g., Figure 3 and Figure 4I the reference numeral 129 therein). The trapping sites thereby provide the threshold switching characteristics and are used to perform the threshold switching operation.

[0058] When forming the select element layer 123 by forming a material layer for the select element layer 123 and doping the material layer with a dopant, an undesired interface layer may be formed due to interdiffusion or intermixing between the lower electrode layer 121 and the select element layer 123. As described above, the disclosed techniques may be implemented in some embodiments to inhibit the formation of the undesired interface layer by forming a barrier layer 122 between the lower electrode layer 121 and the select element layer 123.

[0059] In some embodiments, in addition to or instead of forming the barrier layer 122, the formation of the undesired interface layer may be inhibited by a high-energy ion implantation process as will be discussed below. In some cases, the barrier layer 122 may not be sufficient to completely prevent interdiffusion or intermixing between the lower electrode layer 121 and the select element layer 123, and thus, an undesired interface layer (e.g., Figure 4E with reference numeral IL) may be formed at the lower interface of the select element layer 123 (i.e., at the interface between the barrier layer 122 and the select element layer 123).

[0060] The interface layer IL may include an oxide, a nitride, or a nitrogen oxide, which contains the same substances as those included in the lower electrode layer 121. For example, when the lower electrode layer 121 includes TiN, the interface layer IL may include titanium, oxygen, and / or nitrogen, such as TiO x N y .

[0061] Reference Figure 4E , in some embodiments, the formation of the interface layer IL may be effectively controlled by breaking the bonds of the interface layer IL through a high-energy ion implantation process (high-energy IMP). In this way, at least a part of the interface layer IL may be removed through the high-energy ion implantation process.

[0062] The high-energy ion implantation process may be performed by adjusting the projected range (Rp) of the implanted ions to the depth at which the lower interface of the select element layer 123 is located.

[0063] In one embodiment, when there is no barrier layer 122, the projected range in the high-energy ion implantation process may correspond to the interface between the lower electrode layer 121 and the select element layer 123. In one example, by setting the projected range at the interface between the lower electrode layer 121 and the select element layer, the high-energy ion implantation process may break the bonds of the substances in the undesired interface layer IL formed at the interface between the lower electrode layer 121 and the select element layer 123.

[0064] In another embodiment, when the blocking layer 122 is present, the projected range in the high-energy ion implantation process can correspond to the interface between the blocking layer 122 and the select element layer 123. In one example, by setting the projected range at the interface between the blocking layer 122 and the select element layer 123, the high-energy ion implantation process can break the bonding of the substances in the undesired interface layer IL formed at the interface between the blocking layer 122 and the select element layer 123.

[0065] Thus, in order to effectively control the formation of the undesired interface layer IL that may inevitably form at the lower interface of the select element layer 123, a high-energy ion implantation process with the projected range adjusted to the depth where the lower interface of the select element layer 123 is located can be performed. Therefore, the bonding of the interface layer IL can be broken, thereby effectively reducing Vf and improving device characteristics.

[0066] The dopants used in the high-energy ion implantation process can include one or more of B, N, C, P, As, Al, Si, or Ge.

[0067] The high-energy ion implantation process for controlling the formation of the interface layer IL can be performed at a higher energy than the ion implantation process performed as described above to form the select element layer 123.

[0068] In one embodiment, the dopants used in the high-energy ion implantation process for controlling the formation of the interface layer IL can be the same as the dopants used in the ion implantation process performed as described above to form the select element layer 123.

[0069] In another embodiment, the dopants used in the high-energy ion implantation process for controlling the formation of the interface layer IL can be different from the dopants used in the ion implantation process performed as described above to form the select element layer 123.

[0070] Reference Figure 4F , the bonding of the undesired interface layer IL formed at the lower interface of the select element layer 123 can be broken through the high-energy ion implantation process, so that the interface layer IL can be effectively controlled.

[0071] Therefore, in some embodiments, after forming the select element layer 123 by forming a material layer for the select element layer 123 and then doping the material layer with a dopant, a high-energy ion implantation process with the projected range adjusted to the depth where the lower interface of the select element layer 123 is located can be performed. Thus, the select element layer 123 can have a doping concentration profile that decreases from the bottom to the top of the select element layer 123. That is, the lower part of the select element layer 123 can have a higher dopant concentration than the upper part of the select element layer 123.

[0072] In some embodiments, the select element layer 123 may include dopants introduced by a two-step ion implantation process (i.e., a first ion implantation process performed when forming the select element layer 123, and a subsequent high-energy ion implantation process performed after the first ion implantation process is completed). In one embodiment, the dopants introduced by each ion implantation process (the first ion implantation process and the subsequent ion implantation process) may be the same as each other. In another embodiment, the dopants introduced by the first ion implantation process may be different from the dopants introduced by the subsequent ion implantation process.

[0073] Referring Figure 4G , an intermediate electrode layer 125, a variable resistance layer 127, and an upper electrode layer 129 may be sequentially formed over the select element layer 123.

[0074] The intermediate electrode layer 125 may physically separate the select element layer 123 from the variable resistance layer 127 and may electrically couple the select element layer 123 to the variable resistance layer 127.

[0075] The intermediate electrode layer 125 may have a single-layer structure or a multi-layer structure and may include a conductive material such as a metal, a metal nitride, a conductive carbon material, etc.

[0076] The variable resistance layer 127 may switch between different resistance states based on a voltage or current applied to the variable resistance layer 127 through the upper electrode layer 129 and the intermediate electrode layer 125, thereby storing data having different values. For example, when the variable resistance layer 127 is in a low resistance state, data having a first logic value '1' may be stored in the variable resistance layer 127. On the other hand, when the variable resistance layer 127 is in a high resistance state, data having a second logic value '0' may be stored in the variable resistance layer 127. The variable resistance layer 127 may include one or more materials that can be used for RRAM, PRAM, FRAM, MRAM, or similar memory devices. For example, the variable resistance layer 127 may include one or more of the following: metal oxides, such as transition metal oxides or perovskite-based materials; phase change materials, such as chalcogenide-based materials; and ferroelectric materials, ferromagnetic materials. The variable resistance layer 127 may have a single-layer structure or a multi-layer structure, and the multi-layer structure exhibits variable resistance characteristics through the combination of two or more layers. However, other embodiments are also possible. For example, the memory cell 120 may include a memory layer capable of storing data in a manner different from the above-described variable resistance layer 127.

[0077] The upper electrode layer 129 may be located at the uppermost part of the memory cell 120 and may be used as a connection between the rest of the memory cell 120 and Figure 2 , Figure 3 and Figure 4IThe voltage or current transmission path corresponding to a second line 180. The upper electrode layer 129 may have a single-layer structure or a multi-layer structure, and may include a conductive material such as metal, metal nitride, conductive carbon material, etc.

[0078] A hard mask pattern 130 may be formed above the upper electrode layer 129.

[0079] The hard mask pattern 130 may be formed by forming a material layer for the hard mask pattern 130 and a photoresist pattern (not shown) and etching the material layer by using the photoresist pattern as an etching barrier layer. During the etching process of the material layer for forming the memory cell 120, the hard mask pattern 130 may be used as an etching barrier layer. The hard mask pattern 130 may include one or more materials capable of ensuring etching selectivity with respect to the memory cell 120. For example, each hard mask pattern 130 may have a single-layer structure or a multi-layer structure, and may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0080] Reference Figure 4H can be used to form the memory cell 120 by sequentially etching the upper electrode layer 129, the variable resistance layer 127, the intermediate electrode layer 125, the select element layer 123, the barrier layer 122, and the lower electrode layer 121 by using the hard mask pattern 130 as an etching barrier layer.

[0081] In one embodiment, the hard mask pattern 130 is removed during the etching process of the memory cell 120. In another embodiment, a part or all of the hard mask pattern 130 may be retained during the etching of the memory cell 120 and then removed by a subsequent planarization process.

[0082] Reference Figure 4I can be used to form an interlayer dielectric layer 150 above the memory cell 120. The interlayer dielectric layer 150 may be formed to have a certain thickness such that the interlayer dielectric layer 150 fills the space between the memory cells 120 and covers the top of the memory cell 120. The interlayer dielectric layer 150 may have a single-layer structure or a multi-layer structure, which includes various insulating materials such as silicon oxide, silicon nitride, or a combination thereof.

[0083] A planarization process such as a CMP (chemical mechanical polishing) process may be performed until the top surface of the memory cell 120 is exposed. Even if the hard mask pattern 130 is not completely removed during the etching process of the memory cell 120 as described above, the planarization process may be performed until the top surface of the memory cell 120 is exposed, so that the remaining hard mask pattern 130 can be removed in this process.

[0084] A plurality of second lines 180 may be formed over the storage cells 120 and the interlayer dielectric layer 150. The plurality of second lines 180 may be respectively coupled to the upper surfaces of the storage cells 120. Each of the plurality of second lines 180 extends in a second direction that intersects a first direction. For example, the second direction may be perpendicular to Figure 2 line A-A' shown. The second line 180 may have a single-layer structure or a multi-layer structure, and may include a conductive material such as metal or metal nitride. The second line 180 may be formed by depositing a conductive material and patterning the deposited material. The space between the second lines 180 may be filled with an insulating material (not shown).

[0085] Through the process described above, a Figure 2 , Figure 3 and Figure 4I semiconductor memory as shown can be manufactured.

[0086] Referring to Figure 2 , Figure 3 and Figure 4I , the semiconductor memory may include storage cells 120 disposed at the intersection regions between first lines 110 each extending in a first direction and second lines 180 each extending in a second direction.

[0087] In some embodiments, a blocking layer 122 may be formed at the interface between the lower electrode layer 121 and the select element layer 123 to control an undesired interface layer that may inevitably be formed at the lower interface of the select element layer 123 during the formation of the select element layer 123. In some embodiments, a high-energy ion implantation process may also be performed based on a projected range adjusted to the depth at which the lower interface of the select element layer 123 is located. As a result, the Vf characteristics and the Ioff characteristics can be effectively improved.

[0088] In some embodiments, the select element layer 123 may have a doping concentration profile that decreases from the bottom to the top of the select element layer 123. That is, the lower portion of the select element layer 123 may have a higher dopant concentration than the upper portion of the select element layer 123. The select element layer 123 may include dopants introduced through a two-step ion implantation process, i.e., dopants introduced through an ion implantation process performed during the step of forming the select element layer 123 and dopants introduced through a subsequent high-energy ion implantation process. In one embodiment, the dopants introduced through each ion implantation process may be the same as each other. In another embodiment, the dopants introduced through each ion implantation process may be different from each other.

[0089] The thickness of the blocking layer 122 may be in to within a range, and may include one or more materials selected from silicon, oxides, nitrides, and oxynitrides. For example, the blocking layer 122 may include materials such as Al2O3, TiO2, TaAlON, MgO, Si3N4, Si, SiON, and the like.

[0090] In some embodiments, each memory cell 120 includes a lower electrode layer 121, a blocking layer 122, a select element layer 123, an intermediate electrode layer 125, a variable resistance layer 127, and an upper electrode layer 129. However, the memory cell 120 may have a different structure. In some embodiments, at least one of the lower electrode layer 121, the intermediate electrode layer 125, and the upper electrode layer 129 may be omitted. In some embodiments, the select element layer 123 may be omitted. In some embodiments, the select element layer 123 and the variable resistance layer 127 may be stacked in a different order. For example, the select element layer 123 and the variable resistance layer 127 may be stacked in the opposite order with respect to the Figure 3 and Figure 4I direction shown, such that the select element layer 123 may be disposed above the variable resistance layer 127. In some embodiments, in addition to the Figure 3 and Figure 4I layers 121, 123, 125, 127, and 129 shown, the memory cell 120 may further include one or more layers (not shown) for enhancing the characteristics of the memory cell 120 or improving the manufacturing process.

[0091] In some embodiments, adjacent memory cells among the plurality of memory cells 120 may be spaced apart from each other at a predetermined interval, and trenches may exist between the plurality of memory cells 120. The ratio of the height to the width (i.e., the aspect ratio) of the trenches between adjacent memory cells 120 may be in the range of 1:1 to 40:1, 10:1 to 40:1, 10:1 to 20:1, 5:1 to 10:1, 10:1 to 15:1, 1:1 to 25:1, 1:1 to 30:1, 1:1 to 35:1, or 1:1 to 45:1.

[0092] In some embodiments, the trenches may have sidewalls that are substantially perpendicular to the upper surface of the substrate 100. In some embodiments, adjacent trenches may be spaced apart from each other by an equal or similar distance.

[0093] The memory cell 120 may store data having different values according to the voltage or current applied thereto through the first line 110 and the second line 180. In some embodiments, when the memory cell 120 includes a variable resistance element, each memory cell 120 may store data by switching between different resistance states.

[0094] One of the first lines 110 can be used as a word line, and one of the second lines 180 can be used as a bit line, and vice versa.

[0095] Although one cross-point structure has been described, two or more cross-point structures can be stacked in a vertical direction perpendicular to the top surface of the substrate 100.

[0096] The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a series of devices or systems. Figures 5 to 8 Some examples of devices or systems in which the memory circuits disclosed herein can be implemented are provided.

[0097] Figure 5 A configuration example of a microprocessor including a memory circuit based on the disclosed technology is shown.

[0098] Reference Figure 5 , the microprocessor 1000 can perform tasks of controlling and adjusting a series of processes including receiving data from various types of external devices, processing the data, and outputting the processing result to the external devices. The microprocessor 1000 can include a storage unit 1010, an arithmetic unit 1020, a control unit 1030, etc. The microprocessor 1000 can be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0099] The storage unit 1010 is a component in the microprocessor 1000 that stores data, such as processor registers or registers, etc. The storage unit 1010 can include various registers, such as data registers, address registers, and floating-point registers, etc. The storage unit 1010 can perform functions of temporarily storing data to be operated on by the arithmetic unit 1020, the result data of the operation, and the address where the data for performing the operation is stored.

[0100] According to an embodiment, the storage unit 1010 may include one or more of the above semiconductor devices. For example, the storage unit 1010 may include: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple the electrical connection between the first electrode layer and the second electrode layer based on the magnitude of an applied voltage or an applied current relative to a threshold magnitude, wherein the selection element layer has a dopant concentration profile that decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer. Thus, when the storage unit 1010 is formed, formation of an undesired interface layer can be suppressed, and / or the formed interface layer can be controlled, thereby effectively reducing Vf, increasing the barrier height, and effectively reducing Ioff. As a result, the electrical characteristics and operating characteristics of the microprocessor 1000 can be improved and the reliability of the microprocessor 1000 can be ensured.

[0101] The arithmetic unit 1020 may perform four arithmetical operations or logical operations according to the result of decoding a command by the control unit 1030. The arithmetic unit 1020 may include at least one arithmetic logic unit (ALU) or the like.

[0102] The control unit 1030 may receive signals from the storage unit 1010, the arithmetic unit 1020, and an external device of the microprocessor 1000, perform extraction and decoding of commands, control signal input and output of the microprocessor 1000, and perform processing represented by a program.

[0103] The microprocessor 1000 according to the present embodiment may further include a cache storage unit 1040, which may temporarily store data input from an external device other than the storage unit 1010 or data to be output to an external device. In this case, the cache storage unit 1040 may exchange data with the storage unit 1010, the arithmetic unit 1020, and the control unit 1030 through a bus interface 1050.

[0104] Figure 6 A configuration example of a processor including a memory circuit based on the disclosed technology is shown.

[0105] Reference Figure 6 , the processor 1100 may improve performance and achieve multi-functionality by including various functions in addition to the functions of the above microprocessor 1000. The processor 1100 may include: a core unit 1110 serving as a microprocessor, a cache storage unit 1120 for temporarily storing data, and a bus interface 1130 for transferring data between internal and external devices. The processor 1100 may include various system-on-chips (SoCs), such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0106] The core unit 1110 of this embodiment is a component that performs arithmetic and logical operations on data input from an external device, and may include a storage unit 1111, an arithmetic unit 1112, and a control unit 1113. The storage unit 1111, the arithmetic unit 1112, and the control unit 1113 may be substantially the same as the storage unit 1010, the arithmetic unit 1020, and the control unit 1030.

[0107] The cache memory unit 1120 is a component that temporarily stores data to compensate for the data processing speed difference between the high-speed operating core unit 1110 and the low-speed operating external device. The cache memory unit 1120 may include a first-level storage section 1121 and a second-level storage section 1122. In cases where a high storage capacity is required, the cache memory unit 1120 may further include a third-level storage section 1123. When the situation requires, the cache memory unit 1120 may include a larger number of storage sections. That is, the number of storage sections included in the cache memory unit 1120 may vary according to the design. The speeds at which the first-level storage section 1121, the second-level storage section 1122, and the third-level storage section 1123 store and identify data may be the same or different. In cases where the speeds of the respective storage sections 1121, 1122, and 1123 are different, the speed of the first-level storage section 1121 may be the highest. At least one of the first-level storage section 1121, the second-level storage section 1122, and the third-level storage section 1123 of the cache memory unit 1120 may include one or more of the semiconductor devices according to the embodiment described above. For example, the cache memory unit 1120 may include: a first electrode layer; a second electrode layer; and a select element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple the electrical connection between the first electrode layer and the second electrode layer based on the magnitude of an applied voltage or an applied current relative to a threshold magnitude, wherein the select element layer has a dopant concentration profile that decreases from the interface between the select element layer and the first electrode layer to the interface between the select element layer and the second electrode layer. Thus, when forming the cache memory unit 1120, the formation of an undesired interface layer can be suppressed, and / or the formed interface layer can be controlled, thereby effectively reducing Vf, increasing the barrier height, and effectively reducing Ioff. As a result, the electrical characteristics and operating characteristics of the processor 1100 can be improved and the reliability of the processor 1100 can be ensured.

[0108] Although in this embodiment, all of the first-level storage section 1121, the second-level storage section 1122, and the third-level storage section 1123 are shown to be configured inside the cache memory unit 1120, however, at least one of the first-level storage section 1121, the second-level storage section 1122, and the third-level storage section 1123 of the cache memory unit 1120 may be configured outside the core unit 1110 and may compensate for the difference in processing speed between the core unit 1110 and an external device.

[0109] The bus interface 1130 is a component that connects the core unit 1110, the cache memory unit 1120, and an external device and enables efficient data transmission.

[0110] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share the cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or may be connected through the bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the configuration of the core unit 1110 described above. The storage section in each core unit 1110 may be configured to share with a storage section outside the core unit 1110 through the bus interface 1130.

[0111] The processor 1100 according to the present embodiment may further include: an embedded storage unit 1140 that stores data; a communication module unit 1150 that can transmit data to an external device or receive data from an external device in a wired or wireless manner; a memory control unit 1160 that drives an external storage device; and a media processing unit 1170 that processes data processed by the processor 1100 or data input from an external input device and outputs the processed data to an external interface device or the like. In addition, the processor 1100 may include a plurality of various modules and devices. In this case, the additional plurality of modules may exchange data with the core unit 1110, the cache memory unit 1120, and with each other through the bus interface 1130.

[0112] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. The volatile memory may include DRAM (Dynamic Random Access Memory), mobile DRAM, SRAM (Static Random Access Memory), and memories having similar functions to the above memories. The non-volatile memory may include ROM (Read Only Memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memories having similar functions.

[0113] The communication module unit 1150 may include a module capable of connecting to a wired network, a module capable of connecting to a wireless network, and may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, power line communication (PLC), such as various devices that send and receive data through transmission lines, and so on. The wireless network module may include Infrared Data Association (IrDA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro), High Speed Downlink Packet Access (HSDPA), Wideband CDMA (WCDMA), Ultra Wideband (UWB), such as various devices that can send and receive data without a transmission line, and so on.

[0114] The memory control unit 1160 is used to manage and process data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, such as devices that can control IDE (Integrated Drive Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) card, Mini Secure Digital (mSD) card, Micro Secure Digital (micro SD) card, Secure Digital High Capacity (SDHC) card, Memory Stick card, Smart Media card (SM), Multimedia Card (MMC), Embedded MMC (eMMC), and Compact Flash (CF) card, etc.

[0115] The media processing unit 1170 can process the data processed by the processor 1100 or the data input from an external input device in the form of images, sounds, and others, and can output the data to an external interface device. The media processing unit 1170 may include a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), a High-Definition Audio device (HD Audio), and a High-Definition Multimedia Interface (HDMI) controller, etc.

[0116] Figure 7 A configuration example of a system implementing a memory circuit based on the disclosed technology is shown.

[0117] Reference Figure 7, as a device for processing data, the system 1200 can perform operations such as input, processing, output, communication, storage, etc. to perform a series of operations on the data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, an interface device 1240, etc. The system 1200 of the present embodiment may be various electronic systems that operate using a processor, such as a computer, a server, a PDA (Personal Digital Assistant), a portable computer, a network tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (Portable Multimedia Player), a camera, a Global Positioning System (GPS), a video camera, a recorder, a telematics, an audio-visual (AV) system, and a smart TV, etc.

[0118] The processor 1210 can decode the input commands, perform operations such as arithmetic and comparison on the data stored in the system 1200, and control these operations. The processor 1210 may be substantially the same as the above-mentioned microprocessor 1000 or the above-mentioned processor 1100.

[0119] The main storage device 1220 is such a storage device that can temporarily store, call, and execute program codes or data from the auxiliary storage device 1230 during program execution, and can retain the stored content even when the power is cut off. The auxiliary storage device 1230 is a storage device for storing program codes or data. Although the speed of the auxiliary storage device 1230 is slower than that of the main storage device 1220, the auxiliary storage device 1230 can store a larger amount of data. The main storage device 1220 or the auxiliary storage device 1230 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the main storage device 1220 or the auxiliary storage device 1230 may include: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple the electrical connection between the first electrode layer and the second electrode layer based on the magnitude of the applied voltage or the applied current relative to the threshold magnitude, wherein the selection element layer has a dopant concentration distribution that decreases from the interface between the selection element layer and the first electrode layer to the interface between the selection element layer and the second electrode layer. In this way, when forming the main storage device 1220 or the auxiliary storage device 1230, the formation of an undesired interface layer can be suppressed, and / or the formed interface layer can be controlled, thereby effectively reducing Vf, increasing the barrier height, and effectively reducing Ioff. As a result, the electrical characteristics and operating characteristics of the system 1200 can be improved and the reliability of the system 1200 can be ensured.

[0120] In addition, in addition to or without including the above-mentioned semiconductor devices, the main storage device 1220 or the auxiliary storage device 1230 may further include a storage system (see Figure 8 reference numeral 1300).

[0121] The interface device 1240 can be used to execute the exchange of commands and data between the system 1200 of this embodiment and external devices. The interface device 1240 can be a keypad, keyboard, mouse, speaker, microphone, display, various human-computer interaction devices (HID), and communication devices, etc. The communication device can be substantially the same as the above-mentioned communication module unit 1150.

[0122] Figure 8 A configuration example of a storage system including a memory circuit based on the disclosed technology is shown.

[0123] Reference Figure 8 , the storage system 1300 may include: a memory 1310, which has a non-volatile characteristic as a component for storing data; a memory controller 1320, which controls the memory 1310; an interface 1330, which is used to connect to external devices; and a buffer memory 1340, which is used to temporarily store data to effectively transfer data between the interface 1330 and the memory 1310. The storage system 1300 may simply refer to a memory for storing data, and may also refer to a data storage device for long-term storage of the stored data. The storage system 1300 may be a disk type such as a solid-state drive (SSD), etc., and a card type such as a USB memory (Universal Serial Bus memory), Secure Digital (SD) card, Mini Secure Digital (mSD) card, Micro Secure Digital (micro SD) card, Secure Digital High Capacity (SDHC) card, Memory Stick card, Smart Media (SM) card, Multimedia Card (MMC), Embedded MMC (eMMC), and Compact Flash (CF) card, etc.

[0124] The memory 1310 or the buffer memory 1340 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the memory 1310 or the buffer memory 1340 may include: a first electrode layer; a second electrode layer; and a selection element layer, which is disposed between the first electrode layer and the second electrode layer to electrically couple or decouple the electrical connection between the first electrode layer and the second electrode layer based on the magnitude of the applied voltage or the applied current relative to the threshold magnitude, wherein the selection element layer has a dopant concentration distribution that decreases from the interface between the selection element layer and the first electrode layer to the interface between the selection element layer and the second electrode layer. In this way, when forming the memory 1310 or the buffer memory 1340, the formation of an undesired interface layer can be suppressed, and / or the formed interface layer can be controlled, thereby effectively reducing Vf, increasing the barrier height, and effectively reducing Ioff. As a result, the electrical characteristics and operating characteristics of the storage system 1300 can be improved and the reliability of the storage system 1300 can be ensured.

[0125] In addition to or excluding the above semiconductor devices, the memory 1310 or the buffer memory 1340 may further include various memories such as non-volatile memories or volatile memories.

[0126] The memory controller 1320 may control the data exchange between the memory 1310 and the interface 1330. For this purpose, the memory controller 1320 may include a processor 1321 that performs operations for processing commands input from the outside of the storage system 1300 through the interface 1330.

[0127] The interface 1330 is used to perform the exchange of commands and data between the storage system 1300 and an external device. In the case where the storage system 1300 is of a card type or a disk type, the interface 1330 may be compatible with the interfaces used in devices having a card type or a disk type, or may be compatible with the interfaces used in devices similar to the above devices. The interface 1330 may be compatible with one or more interfaces of different types from each other.

[0128] Based on the above Figures 5 to 8 features in the examples of the electronic devices or systems in the present document can be implemented in various devices, systems, or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebooks or laptop computers, game consoles, smart televisions, set-top boxes, multimedia servers, digital cameras with or without wireless communication functions, watches or other wearable devices with wireless communication functions.

[0129] Only some embodiments and examples are described. Other embodiments, enhancements, and variations can be made based on the content described and illustrated in this patent document.

Claims

1. An electronic device includes a semiconductor memory configured to include a plurality of memory cells, wherein, Each of the plurality of memory cells includes: A first electrode layer; A second electrode layer; and A select element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple the electrical connection between the first electrode layer and the second electrode layer based on the magnitude of an applied voltage or an applied current relative to a threshold magnitude, Wherein the select element layer is formed by the following steps: Forming a material layer for the select element layer; Doping the material layer with a first dopant by a first ion implantation process; and Doping the material layer with a second dopant by a second ion implantation process to form a select element layer; Wherein the second ion implantation process is performed with a higher energy than the first ion implantation process, Wherein the projected range of the second dopant corresponds to the interface between the first electrode layer and the select element layer Wherein the select element layer has a dopant concentration profile that decreases from the interface between the select element layer and the first electrode layer toward the interface between the select element layer and the second electrode layer.

2. The electronic device according to claim 1, wherein, The first electrode layer includes a lower electrode layer coupled to the lowermost portion of each of the plurality of memory cells, and the second electrode layer includes an upper electrode layer coupled to the uppermost portion of each of the plurality of memory cells.

3. The electronic device according to claim 1, wherein, The first dopant and the second dopant include one or more of B, N, C, P, As, Al, Si, or Ge.

4. The electronic device according to claim 1, wherein, The first dopant and the second dopant are the same.

5. The electronic device according to claim 1, wherein, The first dopant and the second dopant are different from each other.

6. The electronic device according to claim 1, wherein, Each of the plurality of memory cells further includes: a blocking layer disposed between the first electrode layer and the select element layer.

7. The electronic device according to claim 6, wherein, The thickness of the barrier layer is within to and includes one or more materials selected from silicon, oxides, nitrides, and oxynitrides.

8. The electronic device according to claim 1, wherein, Each of the plurality of memory cells further includes a storage layer configured to switch between different resistance states corresponding to different data values based on a voltage or current applied to the storage layer.

9. The electronic device according to claim 1, wherein, The semiconductor memory further includes: A plurality of first interconnects disposed above the substrate and each extending in a first direction; A plurality of second interconnects each extending in a second direction crossing the first direction, Wherein each of the plurality of memory cells is disposed at each intersection of the plurality of first interconnects and the plurality of second interconnects.

10. The electronic device according to claim 1, further comprising a microprocessor, the microprocessor including: A control unit configured to receive a signal including a command from outside the microprocessor and perform extraction, decoding, or control of input or output of signals of the microprocessor; An arithmetic unit configured to perform arithmetic operations based on a result of decoding the command by the control unit; And A storage unit configured to store data for performing the arithmetic operations, data corresponding to a result of performing the arithmetic operations, or an address of data on which the arithmetic operations are performed, Wherein the semiconductor memory is part of the storage unit in the microprocessor.

11. The electronic device according to claim 1, further comprising a processor, the processor including: A core unit configured to perform an operation corresponding to a command based on the command input from outside the processor by utilizing data; A cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data on which the operation is performed; and A bus interface connected between the core unit and the cache memory unit and configured to transfer data between the core unit and the cache memory unit; wherein the semiconductor memory is part of the cache memory unit in the processor.

12. The electronic device according to claim 1, further comprising a processing system, the processing system including: A processor configured to decode a command received by the processor and control an operation on information based on a result of decoding the command; An auxiliary storage device configured to store a program for decoding the command and the information; A main storage device configured to call and store the program and the information from the auxiliary storage device such that the processor can utilize the program and the information to perform the operation when executing the program; and An interface device configured to perform communication between at least one of the processor, the auxiliary storage device, and the main storage device and the outside, wherein the semiconductor memory is part of the auxiliary storage device or the main storage device in the processing system.

13. The electronic device according to claim 1, further comprising a storage system, the storage system including: A memory configured to store data and preserve the stored data regardless of how the power supply is; A memory controller configured to control input of data to the memory and output of data from the memory according to a command input from the outside; A buffer memory configured to buffer data exchanged between the memory and the outside; and An interface configured to perform communication between at least one of the memory, the memory controller, and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the storage system.

14. A method of manufacturing an electronic device, the electronic device including a semiconductor memory including a plurality of memory cells, the method including: Forming a first electrode layer in each of the memory cells over a substrate; Forming a material layer over the first electrode layer to turn on or off the memory cell; Performing a first ion implantation process to implant a first dopant into the material layer, and performing a second ion implantation process to implant a second dopant into the material layer to form a select element layer; and Forming a second electrode layer over the select element layer; wherein the second ion implantation process is performed with higher energy than the first ion implantation process, wherein a projected range of the second dopant corresponds to an interface between the first electrode layer and the select element layer.

15. The method according to claim 14, wherein, Each of the first ion implantation process and the second ion implantation process is performed by using one or more of B, N, C, P, As, Al, Si, or Ge as a dopant.

16. The method according to claim 14, wherein, The step of forming the select element layer includes: forming an interface layer at the interface between the first electrode layer and the select element layer, the interface layer including an oxide, nitride, or oxynitride containing a substance included in the first electrode layer; and removing at least a portion of the interface layer by the second ion implantation process.

17. The method according to claim 14 further comprises: forming a barrier layer between the first electrode layer and the select element layer.

18. The method according to claim 17, wherein, The thickness of the blocking layer is within to and includes one or more materials selected from silicon, oxide, nitride, and oxynitride.

19. The method according to claim 17, wherein, When forming the select element layer, the barrier layer inhibits the formation of an interface layer that includes an oxide, nitride, or oxynitride containing a substance included in the first electrode layer and forms at the interface between the first electrode layer and the select element layer.

20. The method according to claim 14, wherein: The material layer includes one or more materials selected from silicon oxide, silicon nitride, metal oxide, and metal nitride.

21. The method according to claim 20, wherein, Each of the first dopant and the second dopant includes one or more of B, N, C, P, As, Al, Si, or Ge.

22. The method according to claim 20, wherein The first dopant and the second dopant are the same as each other.

23. The method according to claim 20, wherein, The first dopant and the second dopant are different from each other.

24. The method according to claim 14, further comprising: forming a plurality of first interconnects over the substrate, each first interconnect extending in a first direction; and forming a plurality of second interconnects over the memory cells, each second interconnect extending in a second direction intersecting the first direction, wherein the memory cells are disposed at respective intersections of the plurality of first interconnects and the plurality of second interconnects.

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