A method and device for correcting pipeline module capacitance mismatch in pipeline ADC

Abstract

The present invention discloses a method and device for correcting capacitor mismatch of pipeline modules in a pipeline ADC. The present invention uses an accumulated compensation signal to compensate for offset coding to achieve capacitor mismatch correction, which not only reduces the requirements for analog capacitor matching but also facilitates implementation using digital circuits.

Description

Technical Field

[0001] The present invention relates to a method and device for correcting capacitance mismatch of pipeline modules in a pipeline ADC, and belongs to the field of integrated circuits. Background Art

[0002] The conversion speed and accuracy requirements for analog-to-digital converters (ADCs) vary across different applications. For example, wireless communications require higher conversion rates and accuracy, often employing pipeline ADCs. While pipeline ADCs are widely used in wireless communication systems, the integrated circuit manufacturing and production processes can lead to capacitance mismatches within the pipeline modules, which can degrade ADC performance. Summary of the Invention

[0003] The present invention provides a method and device for correcting capacitor mismatch of pipeline modules in a pipeline ADC, which solves the problems disclosed in the background art.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A method for correcting capacitance mismatch of pipeline modules in a pipeline ADC, comprising:

[0006] If the signal D of the current cycle i and the signal D of the current cycle C Satisfy any preset mismatch requirement, according to the signal D of the current cycle i 、Signal D of the current cycle C and the preset rules matching the mismatch requirements to obtain the accumulated signal; wherein, the signal D i is the digital code output by the analog-to-digital converter in pipeline module i, where pipeline module i is a pipeline module with capacitor mismatch; signal D C Signal D e The signal after compensation and correction by the compensation signal of the previous cycle, signal D e Signal D i+1 ,…, signal D N and signal D L The weighted sum of signal D n is the digital code output by the analog-to-digital converter in pipeline module n, where pipeline module n is the pipeline module downstream of pipeline module i, i+1≤n≤N, N is the total number of pipeline modules in the pipeline ADC, and signal D L The digital code output by the sub-ADC connected in series downstream of the pipeline module N;

[0007] The compensation signal of the previous cycle is accumulated according to the accumulated signal to obtain the compensation signal of the current cycle, which is used to compensate the signal D of the next cycle. e Perform compensation correction.

[0008] Mismatch requirements include:

[0009] Signal D i is 1100, and signal D C Greater than 1023 or less than 0;

[0010] Signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C Greater than 1023 or less than -1024;

[0011] Signal D i is 0100, and signal D C Greater than 0 or less than -1024.

[0012] Rules that match the mismatch requirement include:

[0013] If the signal D i is 1100, and signal D C If it is greater than 1023, the accumulated signal adopts the preset signal -A;

[0014] If the signal D i is 1100, and signal D C If it is less than 0, the accumulated signal adopts the preset signal A;

[0015] If the signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C If it is greater than 1023, the accumulated signal adopts the preset signal -A;

[0016] If the signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C If it is less than -1024, the accumulated signal adopts the preset signal A;

[0017] If the signal D i is 0100, and signal D C If it is greater than 0, the accumulated signal adopts the preset signal -A;

[0018] If the signal D i is 0100, and signal D C If it is less than -1024, the accumulated signal adopts the preset signal A.

[0019] The preset signal -A is -1, and the preset signal A is 1.

[0020] A device for correcting capacitance mismatch of pipeline modules in a pipeline ADC, comprising an adder, a plurality of correction modules connected in parallel, and a first selection module;

[0021] The correction unit includes a second selection module and an accumulator;

[0022] The input terminal of the second selection module inputs the signal D of the current cycle i and the signal D of the current cycle C ; The second selection module is used to select the signal D in the current cycle i and the signal D of the current cycle C When any of the preset mismatch requirements are met, the signal D of the current cycle i 、Signal D of the current cycle C and a preset rule matching the mismatch requirement to obtain an accumulated signal;

[0023] Among them, signal D i is the digital code output by the analog-to-digital converter in pipeline module i, where pipeline module i is a pipeline module with capacitor mismatch; signal D C Signal D e The signal after compensation and correction by the compensation signal of the previous cycle, signal D e Signal D i+1 , ..., signal D N and signal D L The weighted sum of signal D n is the digital code output by the analog-to-digital converter in pipeline module n, where pipeline module n is the pipeline module downstream of pipeline module i, i+1≤n≤N, N is the total number of pipeline modules in the pipeline ADC, and signal D L The digital code output by the sub-ADC connected in series downstream of the pipeline module N;

[0024] The output end of the accumulator is connected to the input end of the first selection module; the accumulator is used to accumulate the accumulated signal and the compensation signal of the previous cycle;

[0025] The input terminal of the first selection module also inputs the signal D of the current cycle i The output of the first selection module is connected to the input of the adder; the first selection module is used to select the signal D according to the current cycle. i , select the output of the adapted correction module as the current cycle compensation signal;

[0026] The input of the adder also inputs the signal D of the current cycle e The output end of the adder is connected to the input end of the second selection module and the digital correction splicing module of the pipeline ADC.

[0027] The number of correction modules is not greater than the number of pipeline ADC input signal segments affected by capacitor mismatch.

[0028] The second selection module includes a first sub-selection module and a second sub-selection module;

[0029] The first sub-selection module inputs the current cycle signal D C The output of the first sub-selection module is connected to the input of the second sub-selection module, and the input of the second sub-selection module also inputs the signal D of the current cycle. i , the output end of the second sub-selection module is connected to the accumulator.

[0030] The beneficial effects achieved by the present invention are as follows: the present invention uses an accumulated compensation signal to compensate for the offset coding and realizes capacitance mismatch correction, which not only reduces the requirements for analog capacitance matching but also facilitates implementation using a digital circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is the block diagram of the 14-bit pipeline ADC;

[0032] Figure 2 This is the structural diagram of 3.5-bit Stage 1;

[0033] Figure 3 This is the structural diagram of MDAC in Stage 1;

[0034] Figure 4 The ideal transfer curve and the transfer curve with capacitor mismatch in Stage 1;

[0035] Figure 5 The pipeline ADC quantization coding and capacitor mismatch lead to missing and repeated codes;

[0036] Figure 6 It is the capacitor mismatch correction model of Stage 1 in pipeline ADC;

[0037] Figure 7 The ideal transfer curve and the transfer curve with capacitor mismatch in Stage 1 after quantization;

[0038] Figure 8 This is a device for Stage 1 capacitor mismatch correction. DETAILED DESCRIPTION

[0039] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0040] like Figure 1As shown in the figure, the basic structure of a 14-bit pipeline ADC includes a front-end sample-and-hold circuit S / H, pipeline modules Stage 1 to Stage 5, a Flash ADC module Stage 6, and a digital correction and splicing circuit DCC. Each pipeline module includes a sub-analog-to-digital converter Flash ADC, a sub-digital-to-analog converter Sub-DAC, and a gain margin amplifier x4.

[0041] The S / H samples and holds the analog input signal before outputting it to the subsequent pipeline modules for conversion. Stages 1 through 5 have similar structures and functions. Each stage operates as follows: the residual output signal amplified by the previous stage is quantized by the Flash ADC to produce a 4-bit digital codeword. These digital codewords are then converted to corresponding analog signals by the Sub-DAC. This codeword is then subtracted from the output signal of the previous stage and multiplied by 4 to produce the residual output signal of the current stage.

[0042] From above Figure 1 It can be seen that S / H and Stage 1 to Stage 6 are cascaded in sequence according to the flow direction of the input signal. Any two adjacent stages can work simultaneously under the control of two-phase non-overlapping clocks. The working status of S / H and Stage 1 to Stage 6 is shown in Table 1 below.

[0043] Table 1 S / H and the working status of each stage

[0044]

[0045] For S / H, Stage1~Stage6, there are two working phases corresponding to each clock cycle, that is, in the Φ1 phase of Cycle1, the working states of S / H, Stage1~Stage6 are: sampling, quantization, sampling, quantization, sampling, quantization, sampling; in the Φ2 phase of Cycle1, the working states of S / H, Stage1~Stage6 are: holding, sampling, quantization, sampling, quantization, sampling, quantization, sampling, quantization.

[0046] Therefore, in the digital circuit, D1 (the output of the Flash ADC in Stage 1) needs to be delayed by 3 clock cycles, D2 (the output of the Flash ADC in Stage 2) by 2.5 clock cycles, D3 (the output of the Flash ADC in Stage 3) by 2 clock cycles, D4 (the output of the Flash ADC in Stage 4) by 1.5 clock cycles, D5 (the output of the Flash ADC in Stage 5) by 1 clock cycle, and D6 (the output of Stage 6) by 0.5 clock cycles. These signals are then offset and added together to obtain the quantized output of the pipeline ADC. Since digital circuit delay alignment is not the focus of this article, the subsequent formula derivations will be understood as having completed the delay alignment operation.

[0047] The formula used for offset addition can be expressed as:

[0048] D=D1*2 11 +D2*2 9 +D3*2 7 +D4*2 5 +D5*2 3 +D6*2 0

[0049] Where D is the quantized output of the pipeline ADC.

[0050] Stage 1 to Stage 5 are usually implemented using switched capacitor circuits. The conversion errors introduced by their non-ideal factors limit the performance of the pipeline ADC. Non-ideal factors mainly include capacitor mismatch, limited DC gain of the op amp, and op amp offset. The following describes the performance degradation of the pipeline ADC caused by capacitor mismatch in Stage 1. The structure of the 3.5-bit Stage 1 is as follows Figure 2 shown.

[0051] Figure 2 Vin1 is the output signal of the S / H hold state. Vin1 is quantized by the Flash ADC to obtain a 4-bit digital codeword. These digital codewords are simultaneously converted into corresponding analog signals by the Sub-DAC, and then subtracted from Vin1 and finally multiplied by 4 to obtain the residual output signal Vres1 of this stage. The Sub-DAC, adder and operational amplifier in Stage1 are combined into MDAC, and its structure is as follows: Figure 3 shown.

[0052] The working principle of the MDAC in Stage 1 is as follows: in phase period Φ2, the feedback capacitor C1 and sampling capacitors C3~C5 are all connected to the signal input end to complete the sampling operation of the input signal. In phase period Φ1, the sampling capacitors C2~C4 are connected to the output of the Sub-DAC, and the feedback capacitor C1 is connected to the output of the op amp. At this time, the MDAC is in the amplification state.

[0053] The 3.5-bit Stage 1 outputs nine digital codewords: 1100, 1101, 1110, 1111, 0000, 0001, 0010, 0011, and 0100.

[0054] When the 3.5-bit Stage 1 outputs the digital codeword 0100, during the phase period Φ1, that is, Stage 1 is in the sampling phase, the charges of C1 to C5 can be expressed by the following formula:

[0055]

[0056] Among them, Q C1 , Q C2 , Q C3 , Q C4 , Q C5 are the charges of C1 to C5 respectively, where the charges of capacitors C1, C3, C3, and C5 are equal, and the charge of C2 is 0.

[0057] In phase cycle Φ2, that is, Stage 1 is in the amplification stage, capacitors C2 to C5 discharge, and all the charges are transferred to capacitor C1. Switches SW7, SW8, SW9, and SW10 are connected to the reference voltage Vref (the reference voltage of the analog circuit, which can be 0.9V, 1.2V, 1.8V, etc., depending on the specific circuit), which is expressed by the following formula:

[0058]

[0059] By analogy, the digital codeword output by Stage 1 and Vres1 can be expressed as:

[0060]

[0061] Further simplifying the above formula, it can be expressed as:

[0062]

[0063] Among them, when there is no capacitance imbalance, that is, C1=C2=C3=C4=C 15 ,but Equal and 0, when there is an offset in capacitance, that is, C1≠C2≠C3≠C4≠C5, then Not 0. When When it is not 0, it will affect the full swing range of pipeline ADC but have little impact on other performances. Therefore, the present invention mainly solves The impact of non-zero on pipeline ADC.

[0064] According to the above formula, the ideal transfer curve of Stage 1 and the transfer curve with capacitor offset are as follows: Figure 4 As shown. The ideal transfer curve of Stage1 divides the input signal Vin1 into 9 segments. When the input signal is between -Vref and -7 / 8Vref, the output range of Vres1 is between 0 and 1 / 2Vref. When the input signal is between -7 / 8Vref and 7 / 8Vref, the output range of Vres1 is between -1 / 2Vref and 1 / 2Vref. When the input signal is between 7 / 8Vref and Vref, the output range of Vres1 is between -1 / 2Vref and 0. Within each range, the transfer curve is linear and has the same slope. When the capacitor is mismatched, the transfer curve will shift up or down, resulting in repeated codes and missing codes in the noise output code. The phenomenon is as follows Figure 5 shown.

[0065] like Figure 5 As shown, capacitor mismatch can lead to missing and repeated codes, which degrades the performance of pipeline ADCs. Because errors in the front-end of a pipeline ADC are quantified by the back-end, capacitor mismatch in Stage 1 can be represented by digital codewords from Stages 2 to 6, capacitor mismatch in Stage 2 can be represented by digital codewords from Stages 3 to 6, capacitor mismatch in Stage 3 can be represented by digital codewords from Stages 4 to 6, and so on. In actual engineering applications, only the impact of capacitor mismatch in the first three stages on pipeline ADC performance is typically considered. Correcting capacitor mismatch in Stage 1 requires first correcting capacitor mismatches in Stages 2 and 3, and correcting capacitor mismatch in Stage 2 requires first correcting capacitor mismatch in Stage 3. In engineering, the order of capacitor mismatch correction is Stage 3 first, then Stage 2, and finally Stage 1.

[0066] The correction principles and methods for all stages are the same. Based on the above analysis, the specific methods for correcting the capacitor mismatch of pipeline modules in pipeline ADCs include:

[0067] Step 1: If the signal D of the current cycle i and the signal D of the current cycle C Satisfy any preset mismatch requirement, according to the signal D of the current cycle i 、Signal D of the current cycleC and the preset rules matching the mismatch requirements to obtain the accumulated signal; wherein, the signal D i is the digital code output by the analog-to-digital converter in pipeline module i, where pipeline module i is a pipeline module with capacitor mismatch; signal D C Signal D e The signal after compensation and correction by the compensation signal of the previous cycle, signal D e Signal D i+1 ,…, signal D N and signal D L The weighted sum of signal D n is the digital code output by the analog-to-digital converter in pipeline module n, where pipeline module n is the pipeline module downstream of pipeline module i, i+1≤n≤N, N is the total number of pipeline modules in the pipeline ADC, and signal D L The digital code output by the sub-ADC connected in series downstream of the pipeline module N;

[0068] Step 2: Accumulate the compensation signal of the previous cycle according to the accumulated signal to obtain the compensation signal of the current cycle, which is used to compensate the signal D of the next cycle. e Perform compensation correction.

[0069] The above method uses the accumulated compensation signal to compensate for the offset coding and realizes the capacitance mismatch correction, which not only reduces the requirements for analog capacitance matching but also is easy to realize using digital circuits.

[0070] The above mismatch requirements include:

[0071] a. Signal D i is 1100, and signal D C Greater than 1023 or less than 0;

[0072] b. Signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C Greater than 1023 or less than -1024;

[0073] c. Signal D i is 0100, and signal D C Greater than 0 or less than -1024.

[0074] As long as signal D i and signal D C If any one of the three conditions is met, there is a capacitance mismatch in pipeline module i.

[0075] If the signal D i is 1100, and signal D CIf it is greater than 1023, the accumulated signal adopts the preset signal -A, and accumulates the signal -A with the compensation signal of the previous cycle to obtain the compensation signal of the current cycle.

[0076] If the signal D i is 1100, and signal D C If it is less than 0, the accumulated signal adopts the preset signal A, and accumulates the signal A with the compensation signal of the previous cycle to obtain the compensation signal of the current cycle.

[0077] If the signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C If it is greater than 1023, the accumulated signal adopts the preset signal -A, and accumulates the signal -A and the compensation signal of the previous cycle to obtain the compensation signal of the current cycle.

[0078] If the signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C If it is less than -1024, the accumulated signal adopts the preset signal A, and accumulates the signal A with the compensation signal of the previous cycle to obtain the compensation signal of the current cycle.

[0079] If the signal D i is 0100, and signal D C If it is greater than 0, the accumulated signal adopts the preset signal -A, and accumulates the signal -A with the compensation signal of the previous cycle to obtain the compensation signal of the current cycle.

[0080] If the signal D i is 0100, and signal D C If it is less than -1024, the accumulated signal adopts the preset signal A, and the signal -A is accumulated with the compensation signal of the previous cycle to obtain the compensation signal of the current cycle; wherein, the preset signal -A is generally -1, and the preset signal A is generally 1.

[0081] Based on the above method, a corresponding device can be constructed, including an adder, a plurality of correction modules connected in parallel, and a first selection module, wherein the number of correction modules is no greater than the number of pipeline ADC input signal segments affected by capacitor mismatch. Generally, the number of correction modules is equal to the number of pipeline ADC input signal segments affected by capacitor mismatch.

[0082] The correction unit includes a second selection module and an accumulator; the input end of the second selection module inputs the signal D of the current cycle i and the signal D of the current cycle C ; The second selection module is used to select the signal D in the current cycle i and the signal D of the current cycleC When any of the preset mismatch requirements are met, the signal D of the current cycle i 、Signal D of the current cycle C and preset rules matching the mismatch requirements to obtain the accumulated signal.

[0083] The second selection module includes a first sub-selection module and a second sub-selection module; the first sub-selection module inputs the current cycle signal D C The output of the first sub-selection module is connected to the input of the second sub-selection module, and the input of the second sub-selection module also inputs the signal D of the current cycle. i , the output end of the second sub-selection module is connected to the accumulator.

[0084] The first sub-selection module is a first-level selection module, which selects the pre-accumulated value for the current cycle accumulator according to the rules; the second sub-selection module is a second-level selection module, which selects the pre-accumulated value for the current cycle accumulator according to the current cycle signal D i Select the pre-accumulated value output by the first sub-selection module as 0 as the input of the accumulator, for example, D i =1100, Acc1 accumulates the output of S11, Acc2-8 accumulates 0; D i Equal to 1101, Acc1 accumulates 0, Acc2 accumulates the output of S11, Acc3-8 accumulate 0; and so on.

[0085] The output end of the accumulator is connected to the input end of the first selection module; the accumulator is used to accumulate the accumulated signal and the compensation signal of the previous cycle.

[0086] The input terminal of the first selection module also inputs the signal D of the current cycle i The output of the first selection module is connected to the input of the adder; the first selection module is used to select the signal D according to the current cycle. i , select the output of the adapted correction module as the compensation signal for the current period.

[0087] The input of the adder also inputs the signal D of the current cycle e The output end of the adder is connected to the input end of the second selection module and the digital correction splicing module of the pipeline ADC.

[0088] Taking Stage 1 capacitor mismatch correction as an example, the pipeline ADC is simplified, as shown in the following example: Figure 6 As shown in the figure, Stage 2 to Stage 6 form the Backend ADC, whose output digital codeword can be expressed as:

[0089] D e =D2*2 9 +D3*2 7 +D4*2 5 +D5*23 +D6*2 0

[0090] The pipeline ADC output is expressed as:

[0091] D=D1*2 11 +D e

[0092] After quantizing the transmission curve of Stage 1 into digital code, the result is as follows: Figure 7 As shown, from Figure 7 It can be seen that:

[0093] 1) For input signals between -Vref and -7 / 8Vref, when there is no capacitor mismatch, signal D e The value range is between 0 and 1023. When there is a capacitor mismatch, the signal D e The value of exceeds the range of 0 to 1023;

[0094] 2) When the input signal is between -7 / 8Vref and 7 / 8Vref, the signal D is e The value range is between -1024 and 1023. When there is a capacitor mismatch, the signal D e The value exceeds the range of -1024 to 1023;

[0095] 3) When the input signal is between 7 / 8Vref and Vref, the signal D is e The value range is between -1024 and 0. When there is a capacitor mismatch, the signal D e The value exceeds the range between -1024 and 0.

[0096] The Stage 1 capacitor mismatch correction device is as follows Figure 8 As shown, it includes an adder, a first selection module ACC, and a correction unit. Vin1 has eight transmission curves that may be affected by capacitor mismatch. There are eight correction units, namely S1 to S8, corresponding to the correction values of the eight capacitor mismatch segments. All correction units are connected in parallel. Each correction unit includes a second selection module and an accumulator. The second selection module includes a first sub-selection module and a second sub-selection module. Taking the first correction unit S1 in the figure as an example, it includes a first sub-selection module S11, a second sub-selection module S21, and an accumulator ACC1.

[0097] In different cases in the figure, the output of each sub-selection module is:

[0098] S11 output: When the signal Dc input is greater than 1023, S11 outputs -1; when the signal Dc input is less than 0, S11 outputs 1; otherwise, S11 outputs 0;

[0099] S12~S17 output: When the signal Dc input is greater than 1023, S11 outputs -1; when the signal Dc input is less than -1024, S11 outputs 1; otherwise, S11 outputs 0;

[0100] S18 output: When the signal Dc input is greater than 0, S11 outputs -1; when the signal Dc input is less than -1024, S11 outputs 1; otherwise, S11 outputs 0;

[0101] S21 output: When signal D1 = 1100, ACC1 accumulates S21 and outputs the value of S11, otherwise it accumulates 0;

[0102] S22 output: When signal D1=1101, ACC2 accumulates S22 and outputs the value of S12, otherwise it accumulates 0;

[0103] S23 output: When signal D1 = 1110, ACC3 accumulates S23 and outputs the value of S13, otherwise it accumulates 0;

[0104] S24 output: When signal D1=1111, ACC4 accumulates the value of S24 and outputs S14, otherwise it accumulates 0;

[0105] S25 output: When signal D1=0001, ACC5 accumulates S25 and outputs the value of S15, otherwise it accumulates 0;

[0106] S26 output: When signal D1=0010, ACC6 accumulates S26 and outputs the value of S16, otherwise it accumulates 0;

[0107] S27 output: When signal D1=0011, ACC7 accumulates S27 and outputs the value of S17, otherwise it accumulates 0;

[0108] S28 output: When signal D1=0100, ACC8 accumulates the value of S28 and outputs S18, otherwise it accumulates 0.

[0109] Capacitor mismatch correction method description:

[0110] When signal D1 = 1100, S11 outputs -1 when it detects that signal Dc is greater than 1023, and outputs 1 when it detects that signal Dc input is less than 0. Otherwise, S11 outputs 0. S21 selects S11 output to accumulator Acc1 (if D1 ≠ 1100, S21 selects 0 to accumulator Acc1), and then compensates the previous cycle compensation signal Ds1 to signal De, thus completing a correction. The next time D1 = 1100, the above operation is repeated. At this time, Ds1 has been updated, and then the updated Ds1 is compensated to signal De. This process continues until signal Dc stabilizes between greater than or equal to 0 and less than 1023.

[0111] When signal D1 = 1101, S12 outputs -1 when it detects signal Dc is greater than 1023, 1 when it detects signal Dc is less than -1024, and 0 otherwise. S22 selects S12 output and sends it to accumulator Acc2 (if D1 ≠ 1101, S22 selects 0 and sends it to accumulator Acc2). Then, the compensation signal Ds2 from the previous cycle is added to signal De, completing a correction. The next time D1 = 1101, the above operation is repeated, and Ds2 is updated. The updated Ds2 is then added to signal De. This process continues until signal Dc stabilizes between -1024 and 1023.

[0112] The correction methods for similar signals D1=1110, D1=1111, D1=0001, D1=0010, D1=0011 and D1=0100 are the same.

[0113] When signal D1 = 0100, S18 outputs -1 if it detects signal Dc is greater than 0, 1 if it detects signal Dc is less than -1024, and 0 otherwise. S28 selects S18 output and sends it to accumulator Acc8 (if D1 ≠ 0100, S28 selects 0 and sends it to accumulator Acc8). Then, the previous cycle's compensation signal Ds8 is added to signal De, completing a correction. The next time D1 = 0100, the above operation is repeated, and Ds8 is updated. The updated Ds8 is then added to signal De. This process continues until signal Dc stabilizes between -1024 and 0.

[0114] The method for correcting capacitor mismatch in Stage 3 and Stage 2 is similar to that in Stage 1 and will not be described in detail here.

[0115] The method for correcting the capacitance mismatch of the pipeline module in the pipeline ADC can be implemented not only through a digital circuit (ie, the above-mentioned device), but also through a program in an FPGA.

[0116] Therefore, based on the same technical solution, the present invention also discloses a computer-readable storage medium storing one or more programs, wherein the one or more programs include instructions, which, when executed by a computing device, enable the computing device to perform pipeline module capacitance mismatch correction in a pipeline ADC.

[0117] Based on the same technical solution, the present invention also discloses a computing device, including one or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for performing pipeline module capacitance mismatch correction in a pipeline ADC.

[0118] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0119] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0120] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0121] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0122] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the scope of the claims of the present invention to be approved.

Claims

1. A method for correcting capacitance mismatch of pipeline modules in a pipeline ADC, characterized in that: include: If the signal D of the current cycle i and the signal D of the current cycle C Satisfy any preset mismatch requirement, according to the signal D of the current cycle i 、Signal D of the current cycle C and the preset rules matching the mismatch requirements to obtain the accumulated signal; wherein, the signal D i is the digital code output by the analog-to-digital converter in pipeline module i, where pipeline module i is a pipeline module with capacitor mismatch; signal D C Signal D e The signal after compensation and correction by the compensation signal of the previous cycle, signal D e Signal D i+1 ,…, signal D N and signal D L The weighted sum of signal D n is the digital code output by the analog-to-digital converter in pipeline module n, where pipeline module n is the pipeline module downstream of pipeline module i, i+1≤n≤N, N is the total number of pipeline modules in the pipeline ADC, and signal D L The digital code output by the sub-ADC connected in series downstream of the pipeline module N; The compensation signal of the previous cycle is accumulated according to the accumulated signal to obtain the compensation signal of the current cycle, which is used to compensate the signal D of the next cycle. e Perform compensation correction.

2. The method for correcting capacitance mismatch of a pipeline module in a pipeline ADC according to claim 1, wherein: Mismatch requirements include: Signal D i is 1100, and signal D C Greater than 1023 or less than 0; Signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C Greater than 1023 or less than -1024; Signal D i is 0100, and signal D C Greater than 0 or less than -1024.

3. The method for correcting capacitance mismatch of a pipeline module in a pipeline ADC according to claim 1 or 2, wherein: Rules that match the mismatch requirement include: If the signal D i is 1100, and signal D C If it is greater than 1023, the accumulated signal adopts the preset signal -A; If the signal D i is 1100, and signal D C If it is less than 0, the accumulated signal adopts the preset signal A; If the signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C If it is greater than 1023, the accumulated signal adopts the preset signal -A; If the signal D i is 1101 or 1110 or 1111 or 0001 or 0010 or 0011 or 0100, and signal D C If it is less than -1024, the accumulated signal adopts the preset signal A; If the signal D i is 0100, and signal D C If it is greater than 0, the accumulated signal adopts the preset signal -A; If the signal D i is 0100, and signal D C If it is less than -1024, the accumulated signal adopts the preset signal A.

4. The method for correcting capacitance mismatch of a pipeline module in a pipeline ADC according to claim 3, wherein: The preset signal -A is -1, and the preset signal A is 1.

5. A device for correcting capacitance mismatch of pipeline modules in a pipeline ADC, characterized in that: It includes an adder, a plurality of parallel correction modules and a first selection module; The correction unit includes a second selection module and an accumulator; The input terminal of the second selection module inputs the signal D of the current cycle i and the signal D of the current cycle C ; The second selection module is used to select the signal D in the current cycle i and the signal D of the current cycle C When any of the preset mismatch requirements are met, the signal D of the current cycle i 、Signal D of the current cycle C and a preset rule matching the mismatch requirement to obtain an accumulated signal; Among them, signal D i is the digital code output by the analog-to-digital converter in pipeline module i, where pipeline module i is a pipeline module with capacitor mismatch; signal D C Signal D e The signal after compensation and correction by the compensation signal of the previous cycle, signal D e Signal D i+1 , ..., signal D N and signal D L The weighted sum of signal D n is the digital code output by the analog-to-digital converter in pipeline module n, where pipeline module n is the pipeline module downstream of pipeline module i, i+1≤n≤N, N is the total number of pipeline modules in the pipeline ADC, and signal D L The digital code output by the sub-ADC connected in series downstream of the pipeline module N; The output end of the accumulator is connected to the input end of the first selection module; the accumulator is used to accumulate the accumulated signal and the compensation signal of the previous cycle; The input terminal of the first selection module also inputs the signal D of the current cycle i The output of the first selection module is connected to the input of the adder; the first selection module is used to select the signal D according to the current cycle. i , select the output of the adapted correction module as the current cycle compensation signal; The input of the adder also inputs the signal D of the current cycle e The output end of the adder is connected to the input end of the second selection module and the digital correction splicing module of the pipeline ADC.

6. The device for correcting capacitance mismatch of pipeline modules in a pipeline ADC according to claim 5, wherein: The number of correction modules is not greater than the number of pipeline ADC input signal segments affected by capacitor mismatch.

7. The device for correcting capacitance mismatch of pipeline modules in a pipeline ADC according to claim 5, wherein: The second selection module includes a first sub-selection module and a second sub-selection module; The first sub-selection module inputs the current cycle signal D C The output of the first sub-selection module is connected to the input of the second sub-selection module, and the input of the second sub-selection module also inputs the signal D of the current cycle. i , the output end of the second sub-selection module is connected to the accumulator.

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