Dedicated graphics card frame interpolation circuit, method, device, chip, electronic equipment and medium

Abstract

This application discloses a discrete graphics card frame interpolation circuit, method, apparatus, chip, electronic device, and medium, belonging to the field of communication technology. The discrete graphics card frame interpolation circuit includes a system-on-a-chip (SoC) and a discrete graphics chip. The SoC generates first data based on first content to be displayed, and upon receiving a target TE signal from the discrete graphics chip, sends the first data to the discrete graphics chip, wherein the frame rate of the first data is less than the frame rate of the first content. The discrete graphics chip performs frame interpolation processing on the first data to obtain second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content.

Description

Technical Field

[0001] This application belongs to the field of communication technology, specifically relating to a discrete display frame interpolation circuit, method, device, chip, electronic device, and medium. Background Technology

[0002] With the development of terminal technology, users have increasingly higher requirements for the quality of images displayed on electronic devices. Currently, some electronic devices can support high frame rate display of videos, games, and other visuals. However, in the process of displaying videos and games at high frame rates, the high power consumption of electronic devices affects the display frame rate, resulting in lower smoothness of the displayed images. Summary of the Invention

[0003] The purpose of this application is to provide a discrete graphics frame interpolation circuit, method, apparatus, chip, electronic device, and medium.

[0004] In a first aspect, embodiments of this application provide a discrete graphics card frame interpolation circuit, which includes a system-on-a-chip (SoC) and a discrete graphics chip. The SoC generates first data based on first content to be displayed, and upon receiving a target display frame rate synchronization (TE) signal from the discrete graphics chip, sends the first data to the discrete graphics chip, wherein the frame rate of the first data is less than the frame rate of the first content. The discrete graphics chip performs frame interpolation processing on the first data to obtain second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content.

[0005] Secondly, embodiments of this application provide a discrete graphics card frame interpolation method, which includes: generating first data based on first content to be displayed by the electronic device through a system-on-a-chip (SoC) in the electronic device, wherein the frame rate of the first data is less than the frame rate of the first content; sending the first data to the discrete graphics card through the SoC when the SoC receives a target display frame rate synchronization (TE) signal sent by the discrete graphics card in the electronic device; and performing frame interpolation processing on the first data through the discrete graphics card to obtain second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content.

[0006] Thirdly, embodiments of this application provide a discrete graphics card frame interpolation device, which includes a generation module, a transmission module, and a processing module. The generation module is used to generate first data based on first content to be displayed by the electronic device via a system-on-a-chip (SoC), wherein the frame rate of the first data is less than the frame rate of the first content. The transmission module is used to transmit the first data to the discrete graphics chip via the SoC when the SoC receives a target display frame rate synchronization (TE) signal sent by the discrete graphics chip in the electronic device. The processing module is used to perform frame interpolation processing on the first data via the discrete graphics chip to obtain second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content.

[0007] Fourthly, embodiments of this application provide a system-on-a-chip (SoC) comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, the processor is configured to generate first data based on first content to be displayed by the electronic device, wherein the frame rate of the first data is less than the frame rate of the first content, and the communication interface is configured to send the first data to the discrete graphics chip upon receiving a target display frame rate synchronization (TE) signal sent by the discrete graphics chip in the electronic device.

[0008] Fifthly, this application provides a discrete graphics chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The communication interface is used to send a target display frame rate synchronization (TE) signal to a system-on-a-chip (SoC) in an electronic device and to receive first data sent by the SoC. The first data is data generated by the SoC based on first content to be displayed by the electronic device. The frame rate of the first data is less than the frame rate of the first content. The processor is used to perform frame interpolation on the first data to obtain second data. The frame rate of the second data is greater than or equal to the frame rate of the first content.

[0009] In a sixth aspect, embodiments of this application provide an electronic device that includes a discrete graphics interpolation circuit as described in the first aspect, or includes a system-on-a-chip as described in the fourth aspect and a discrete graphics chip as described in the fifth aspect.

[0010] In a seventh aspect, embodiments of this application provide an electronic device including a processor and a memory, the memory storing programs or instructions executable on the processor, the programs or instructions, when executed by the processor, causing the electronic device to perform the steps of the method described in the second aspect.

[0011] Eighthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, cause an electronic device to perform the steps of the method described in the second aspect.

[0012] In a ninth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to cause an electronic device to perform the method described in the second aspect.

[0013] In this embodiment, the system-on-a-chip (SoC) can generate first data based on the first content to be displayed, and the frame rate of the first data is less than the frame rate of the first content. Then, when the SoC receives a target TE signal sent by the discrete graphics chip, the SoC can send the first data to the discrete graphics chip, so that the discrete graphics chip can perform frame interpolation processing on the first data to obtain second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content. In this solution, since the frame rate of the first data generated by the SoC is less than the frame rate of the first content to be displayed, the output frame rate of the SoC is reduced. Then, the discrete graphics chip can perform frame interpolation processing on the first data to obtain second data, thereby increasing or maintaining the frame rate of the content to be displayed by the electronic device. In this way, by reducing the output frame rate of the SoC, the problem of the high power consumption of the SoC affecting the frame interpolation function of the discrete graphics chip is avoided, thereby improving the smoothness of the screen displayed by the electronic device. Attached Figure Description

[0014] Figure 1 This is one of the schematic diagrams of a discrete graphics frame interpolation method provided in the embodiments of this application;

[0015] Figure 2 This is a second schematic diagram of a discrete graphics frame interpolation method provided in an embodiment of this application;

[0016] Figure 3 This is a schematic diagram of a discrete graphics card frame interpolation circuit provided in an embodiment of this application;

[0017] Figure 4 This is a schematic diagram of the architecture of a discrete graphics chip provided in an embodiment of this application;

[0018] Figure 5 This is a signal interaction diagram provided in an embodiment of this application when the discrete graphics card frame interpolation function is not enabled;

[0019] Figure 6 This is a signal interaction diagram provided in an embodiment of this application when the discrete graphics card frame interpolation function is enabled;

[0020] Figure 7 This is a flowchart of a discrete graphics frame interpolation method provided in an embodiment of this application;

[0021] Figure 8 This is a schematic diagram of the structure of a discrete graphics frame interpolation device provided in an embodiment of this application;

[0022] Figure 9This is one of the hardware structure diagrams of an electronic device provided in the embodiments of this application;

[0023] Figure 10 This is a second schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0025] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0026] The discrete graphics frame interpolation method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0027] Currently, some electronic devices can support high frame rate display of videos, games, and other visuals. However, when electronic devices use high frame rate display of videos, games, and other visuals, the high power consumption of the electronic devices affects the display frame rate, resulting in a lower smoothness of the displayed visuals.

[0028] To address the aforementioned technical issues, in this embodiment of the application, the output frame rate of the system-on-a-chip (SoC) can be reduced, and then the frame rate can be interpolated to the target frame rate (greater than or equal to the frame rate of the currently displayed content) by the independent display chip (i.e., discrete graphics chip). In this way, while increasing or maintaining the frame rate of the content displayed by the electronic device, the power consumption of the SoC is reduced to stabilize the output frame rate of the SoC, thereby improving the smoothness of the screen displayed by the electronic device.

[0029] In one scenario, such as Figure 1As shown, the Liquid Crystal Display Module (LCM) has a display frame rate of 90fps, while the source content's frame rate (i.e., the frame rate of the content to be displayed by the electronic device) is 60fps. When it's necessary to increase the frame rate of the content to be displayed by the electronic device, the LCM sends a 90Hz TE signal to the discrete graphics chip for frame synchronization. The discrete graphics chip adjusts the TE signal to 45Hz and sends it to the SoC. Simultaneously, the SoC processes the generated frame data from 60fps to 45fps and transmits it to the discrete graphics chip, enabling the discrete graphics chip to interpolate the 45fps frame data to 90fps frame data and transmit it to the LCM. The LCM then displays the content corresponding to the 90fps frame data. In this way, while increasing the frame rate of the content to be displayed by the electronic device, the SoC's power consumption is reduced to stabilize the SoC's output frame rate, thereby improving the smoothness of the displayed image.

[0030] In another scenario, such as Figure 2 As shown, the LCM's display frame rate is 90fps, while the source video's frame rate (i.e., the frame rate of the content to be displayed on the electronic device) is 60fps. To maintain the same frame rate, the LCM sends a 90Hz TE signal to the discrete graphics chip for frame synchronization. The discrete graphics chip adjusts the TE signal to 30Hz and sends it to the SoC. Simultaneously, the SoC processes the generated frame data from 60fps to 30fps and transmits it to the discrete graphics chip (or the discrete graphics chip adjusts the TE signal to 45Hz and sends it to the SoC, and the SoC processes the generated frame data from 60fps to 45fps and transmits it to the discrete graphics chip; this can be adjusted according to power consumption and effect requirements). This allows the discrete graphics chip to interpolate the 30fps frame data into 60fps frame data and transmit it to the LCM, thus allowing the LCM to display the content corresponding to the 60fps frame data. In this way, while maintaining the frame rate of the content to be displayed on the electronic device, the SoC's power consumption is reduced to stabilize the SoC's output frame rate, thereby improving the smoothness of the displayed image on the electronic device.

[0031] Example 1

[0032] This application provides a discrete graphics card frame interpolation circuit. Figure 3 A schematic diagram of a discrete graphics card frame interpolation circuit provided in an embodiment of this application is shown. Figure 3 As shown, the discrete graphics frame interpolation circuit provided in this application embodiment may include a system-on-a-chip and a discrete graphics chip.

[0033] The system-on-a-chip (SoC) generates first data based on the first content to be displayed, and sends the first data to the discrete graphics chip upon receiving a target TE signal. The frame rate of the first data is less than the frame rate of the first content. The discrete graphics chip performs frame interpolation on the first data to obtain second data, the frame rate of which is greater than or equal to the frame rate of the first content.

[0034] It's important to note that a dedicated external graphics chip, acting as a specialized image processing unit, can deliver enhanced display effects such as higher frame rates, higher resolutions, improved color saturation, and higher contrast. While some electronic devices support high frame rates (e.g., 120 / 90Hz), the actual displayed content doesn't achieve a true high frame rate; it merely relies on the Graphics Processing Unit (GPU) or display driver IC to simply repeat the same frame, resulting in a low frame rate experience. A dedicated graphics chip, however, can use data from two consecutive frames to calculate the motion characteristics of the image and simulate intermediate frames, achieving dynamic frame interpolation and enabling the electronic device to display content at a truly high frame rate.

[0035] Figure 4 The diagram illustrates the architecture of a discrete graphics chip. This chip features two Display Serial Interfaces (DSIs) and transmits data via the Mobile Industry Processor Interface (MIPI) protocol. It can operate in both dual-channel and single-channel MIPI modes. In dual-channel mode, the display content is divided into a User Interface (UI) layer and a multimedia video layer. The UI and video layers are transmitted to the discrete graphics chip via the DSI interfaces, and each layer is processed by its internal functional modules (e.g., frame interpolation, super-resolution, noise reduction, color enhancement) to synthesize frame data. After necessary color processing, this data is transmitted to the Liquid Crystal Display Module (LCM) via the Display Serial Interface-Transmit (DSI-Tx) 0. In single-channel mode, the display content can be synthesized into frame data by the SoC and sent to the discrete graphics chip via DSI 0, allowing the chip to process the data before transmitting it to the LCM.

[0036] In a photography scenario, the content captured by the camera in the electronic device is transmitted to the SoC via the Camera Serial Interface (CSI) 0. The SoC then transmits the captured content to the discrete graphics chip via the DSI interface. After processing, the discrete graphics chip transmits the processed content to the SoC and the display module via the CSI Tx0 and DSI Tx0 interfaces, respectively. The SoC can store the processed content, while the display module can preview and display the processed content in real time.

[0037] The functions of each interface are as follows:

[0038] DSI 0: Output UI or video content;

[0039] Display serial interface - receiver (DSI-Receive, DSI-Rx)0: Receives the content transmitted by DSI 0;

[0040] DSI 1: Output UI or video content;

[0041] DSI Rx1: Receives the content transmitted by DSI 1;

[0042] CSI 0: Receives content captured by the camera;

[0043] CSI 1: Receives the content processed by the discrete graphics chip;

[0044] DSI Tx0: Outputs display content to the display screen;

[0045] CSI Tx0: Outputs the content processed by the discrete graphics chip to the SoC;

[0046] TE: Display frame rate synchronization signal;

[0047] MIPI: A signal transmission protocol;

[0048] General-Purpose Input / Output (GPIO): Transmits other control signals and data signals between the discrete graphics chip and the processor;

[0049] Kernel module (Intellectual Property, IP): The module that processes functions inside the discrete graphics chip (such as frame interpolation, super resolution, noise reduction, color enhancement, UI and video content overlay, etc.).

[0050] Power Management Integrated Circuit (PMIC): This includes battery management chips, discrete graphics power management chips, and other module power management chips / modules.

[0051] Battery: The battery in an electronic device;

[0052] SoC: System-on-a-Chip, which includes a processor core, digital signal processor, storage module, communication interface, power management, radio frequency front-end and other modules.

[0053] Figure 5 The diagram illustrates the signal interaction when the discrete graphics frame interpolation function is not enabled on the electronic device. The display's frame rate is 90fps. When the discrete graphics frame interpolation function is not enabled, the LCM sends a 90Hz TE signal to the discrete graphics chip for frame synchronization. The discrete graphics chip also synchronously generates a 90Hz TE signal and sends it to the SoC. Since the source material is only 60fps, the GPU generates 60fps frame data and passes it to the discrete graphics chip, which then directly transmits it to the display. Therefore, the actual content displayed on the screen is only 60fps, failing to reach the display's 90fps.

[0054] Figure 6 The diagram illustrates the signal interaction when an electronic device enables discrete graphics frame interpolation. The display's frame rate is 90fps. When the electronic device enables discrete graphics frame interpolation (e.g., interpolating 60fps to 90fps), the LCM sends a 90Hz TE signal to the discrete graphics chip for frame synchronization. The discrete graphics chip synchronously generates a 60Hz TE signal and sends it to the SoC. The SoC generates 60fps frame data and passes it to the discrete graphics chip. The discrete graphics chip then interpolates the 60fps to 90fps and transmits it to the display. At this point, the content displayed on the screen achieves a true 90fps.

[0055] Optionally, in this embodiment, the first content mentioned above can be video footage, game footage, etc. The specific content can be determined according to actual usage requirements, and this embodiment does not impose any limitations.

[0056] Optionally, in this embodiment of the application, the system-on-a-chip can perform frame dropping processing on the first content, or perform any other possible processing on the first content to obtain the first data.

[0057] Optionally, in this embodiment of the application, the above-mentioned system-on-a-chip is specifically used to perform frame dropping processing on the first content based on a preset frame rate to obtain the first data of the preset frame rate.

[0058] Optionally, in this embodiment, the preset frame rate is less than the frame rate of the first content. Furthermore, the preset frame rate can be the default value of the electronic device or a value preset by the user. The specific value can be determined according to actual usage needs, and this embodiment does not impose any limitations.

[0059] For example, assuming the preset frame rate is 45fps and the frame rate of the first content is 60fps, the system-on-a-chip (SoC) will discard 1fps of data for every 3fps of data processed. The discarded frame of data does not need to be processed, and the SoC actually processes 45fps of data.

[0060] For example, assuming the preset frame rate is 30fps and the frame rate of the first content is 60fps, the system-on-a-chip (SoC) will discard 1fps of data for every 1fps of data it processes. The discarded frame of data does not need to be processed, and the SoC actually processes 30fps of data.

[0061] In this embodiment, the system-on-a-chip (SoC) can perform frame dropping processing on the first content based on a preset frame rate to obtain the first data at the preset frame rate, thereby reducing the output frame rate of the SoC. This reduces the power consumption of the SoC, stabilizes the output frame rate of the SoC, and avoids the problem of the SoC's high power consumption affecting the discrete graphics card's frame interpolation function, thereby improving the smoothness of the screen displayed on the electronic device.

[0062] Optionally, in this embodiment, the target TE signal may be a single TE signal or may include multiple TE signals. The specific choice can be determined based on actual usage requirements, and this embodiment does not impose any limitations.

[0063] Optionally, in this embodiment, the system-on-a-chip (SoC) is further configured to send a first instruction to the discrete graphics chip, the first instruction including a preset frame rate. The discrete graphics chip is further configured to generate a target TE signal and send the target TE signal to the SoC, the frequency of the target TE signal being equal to the preset frame rate.

[0064] In this embodiment, the system-on-a-chip (SoC) can send a first instruction, including a preset frame rate, to the discrete graphics chip, causing the discrete graphics chip to generate a TE signal with a frequency value equal to the preset frame rate value, and send the TE signal to the SoC. Thus, since the SoC sends data with the preset frame rate to the discrete graphics chip, and the preset frame rate is less than the frame rate of the first content, the electronic device reduces the power consumption of the SoC by lowering its output frame rate, thereby stabilizing the output frame rate of the SoC and improving the smoothness of the screen displayed by the electronic device.

[0065] Optionally, in this embodiment, the first instruction further includes a target frame rate. Specifically, the discrete graphics chip uses the target frame rate to perform frame interpolation on the first data to obtain the second data.

[0066] It is understandable that the system-on-a-chip sends a first instruction to the discrete graphics chip, which includes a preset frame rate and a target frame rate, so that the discrete graphics chip enters the "preset frame rate interpolation to target frame rate" mode. When the discrete graphics chip receives the first data, it can perform frame interpolation processing on the first data to obtain the second data of the target frame rate.

[0067] Optionally, in this embodiment of the application, while performing frame interpolation on the first data, the discrete graphics chip can also perform other processing on the first data (such as super-resolution, noise reduction, color enhancement, etc.) to finally obtain the second data.

[0068] Optionally, in this embodiment, the frame rate of the second data can be preset by the user or be the default value of the electronic device. The specific value can be determined according to actual usage requirements, and this embodiment does not impose any limitations.

[0069] Optionally, in one implementation of this application, when the high frame rate mode is enabled, the frame rate of the second data can be greater than the frame rate of the first content; in another implementation, when the power saving mode is enabled, the frame rate of the second data can be equal to the frame rate of the first content.

[0070] In this embodiment, the discrete graphics chip can perform frame interpolation on the first data whose frame rate is less than that of the first content to obtain the second data whose frame rate is greater than or equal to that of the first content. In this way, while reducing the power consumption of the system-on-a-chip, the frame rate of the content displayed by the electronic device is increased or maintained, thereby improving the smoothness of the screen displayed by the electronic device.

[0071] Optionally, in this embodiment, the target TE signal includes multiple TE signals. Specifically, the system-on-a-chip (SoC) is used to send one frame of data from the first data to the discrete graphics chip upon receiving each TE signal, thereby sending multiple frames of data from the first data to the discrete graphics chip.

[0072] Optionally, in the embodiments of this application, the aforementioned one TE signal is one of a plurality of TE signals.

[0073] Optionally, in this embodiment of the application, when the system-on-a-chip (SoC) receives the first TE signal, the SoC can send the first frame of data from the first data to the discrete graphics chip. When the SoC receives the second TE signal, the SoC can send the second frame of data from the first data to the discrete graphics chip, and so on, until the SoC sends all the frames of data from the first data to the discrete graphics chip.

[0074] Optionally, in this embodiment, the discrete graphics chip processes each frame of data received from the first data, and after processing that frame of data, the discrete graphics chip sends a TE signal to the system-on-a-chip (SoC) to process all frames of data in the first data. It can be understood that each TE signal corresponds to one frame of data in the first data.

[0075] In this embodiment, the discrete graphics chip can send a TE signal to the system-on-a-chip (SoC). Then, the SoC sends a frame of data to the discrete graphics chip. Thus, each time the SoC receives a TE signal, it sends one frame of data from the first data to the discrete graphics chip. Finally, the SoC sends all the frames of data from the first data to the discrete graphics chip, avoiding the situation where the discrete graphics chip receives the next frame of data before it has finished processing the previous frame, thereby ensuring the timing of data processing by the SoC and the discrete graphics chip.

[0076] Optionally, in this embodiment, the discrete graphics frame interpolation circuit further includes a display unit. The discrete graphics chip is also configured to send second data to the display unit upon receiving a first TE signal from the display unit, wherein the frequency of the first TE signal is greater than or equal to the frame rate of the second data. The display unit is configured to display second content based on the second data.

[0077] Optionally, in this embodiment, the first TE signal can be one TE signal or include multiple TE signals. The specific choice can be determined based on actual usage requirements, and this embodiment does not impose any limitations.

[0078] Optionally, in this embodiment of the application, if the first TE signal includes multiple TE signals, then when the discrete graphics chip receives one of the TE signals in the first TE signal, the discrete graphics chip sends one frame of data in the second data to the display unit, so as to send multiple frames of data in the second data to the display unit.

[0079] It should be noted that the method for the discrete graphics chip to send the second data to the display unit can be found in the method for the system-on-a-chip to send the first data to the discrete graphics chip in the above embodiment, and will not be repeated here.

[0080] Optionally, in this embodiment of the application, each TE signal in the first TE signal corresponds to a frame of data in the second data.

[0081] Optionally, in this embodiment of the application, when the second data includes multiple frames of data, the discrete graphics chip can send multiple frames of data to the display unit in sequence, and then the display unit displays the content corresponding to each frame of data in sequence, so as to realize that the display unit displays the second content.

[0082] It should be noted that when the frequency of the first TE signal is equal to the frame rate of the second data, the display unit displays the content corresponding to each frame of the second data it receives. When the frequency of the first TE signal is greater than the frame rate of the second data, the display unit may not receive a frame of the second data after sending one TE signal from the first TE signal. In this case, the display unit can display the content corresponding to the last frame of data received by the display unit.

[0083] It is understandable that, when the second data includes multiple frames of data, for the target frame data in the multiple frames of data, if the display unit does not receive the target frame data, the display unit displays the content corresponding to the last frame data received by the display unit.

[0084] In this embodiment, the display unit can receive the second data sent by the discrete graphics chip and display the second content corresponding to the second data, that is, display high frame rate content or maintain the content displayed by the display unit, thereby avoiding the problem that the system-on-a-chip power consumption is too high and affects the frame interpolation function of the discrete graphics chip, thereby improving the smoothness of the screen displayed by the electronic device.

[0085] Example 2

[0086] This application provides a method for frame interpolation for discrete graphics cards. Figure 7 A flowchart illustrating a discrete graphics frame interpolation method provided in an embodiment of this application is shown. This method can be applied to electronic devices. Figure 7 As shown, the discrete graphics frame interpolation method provided in this application embodiment may include the following steps 201 to 203.

[0087] Step 201: The electronic device generates first data based on the first content to be displayed by the electronic device through the system-on-a-chip in the electronic device.

[0088] In this embodiment of the application, the frame rate of the first data is less than the frame rate of the first content.

[0089] In this embodiment, the electronic device can generate first data based on the first content to be displayed by the electronic device (e.g., video or game screen) through a system-on-a-chip (SoC). The frame rate of the first data is less than the frame rate of the first content, thus reducing the output frame rate of the SoC. Then, when the SoC receives the target TE signal sent by the discrete graphics chip in the electronic device, the electronic device sends the first data to the discrete graphics chip through the SoC, so that the discrete graphics chip performs frame interpolation on the first data to obtain second data. The frame rate of the second data is greater than or equal to the frame rate of the first content, thus increasing the frame rate of the content displayed by the electronic device or maintaining the frame rate of the content displayed by the electronic device.

[0090] It should be noted that for details regarding discrete graphics chips, system-on-a-chip, and the first content, please refer to the relevant descriptions in Embodiment 1 above, which will not be repeated here.

[0091] Optionally, in this embodiment of the application, the electronic device can perform frame dropping processing on the first content through a system-on-a-chip, or it can perform any other possible processing on the first content through a system-on-a-chip to obtain the first data.

[0092] Optionally, in the embodiments of this application, step 201 above can be specifically implemented by step 201a below.

[0093] Step 201a: The electronic device performs frame dropping processing on the first content based on a preset frame rate through a system-on-a-chip to obtain the first data at the preset frame rate.

[0094] In this embodiment of the application, the preset frame rate is less than the frame rate of the first content.

[0095] It should be noted that for details regarding preset frame rate, frame dropping handling, etc., please refer to the relevant descriptions in Embodiment 1 above, which will not be repeated here.

[0096] In this embodiment, the electronic device can use a system-on-a-chip (SoC) to perform frame dropping on the first content based on a preset frame rate to obtain the first data at the preset frame rate, thereby reducing the output frame rate of the SoC. This reduces the power consumption of the SoC, stabilizes its output frame rate, and avoids the problem of high power consumption of the SoC affecting the frame interpolation function of the discrete graphics card, thus improving the smoothness of the screen displayed by the electronic device.

[0097] Step 202: When the system-on-a-chip receives the target TE signal sent by the discrete graphics chip in the electronic device, the electronic device sends the first data to the discrete graphics chip through the system-on-a-chip.

[0098] Optionally, in this embodiment of the application, the discrete graphics chip in the electronic device can send a target TE signal to the system-on-a-chip (SoC) so that the electronic device can send first data to the discrete graphics chip through the SoC.

[0099] Optionally, in this embodiment, the target TE signal may be a single TE signal or may include multiple TE signals. The specific choice can be determined based on actual usage requirements, and this embodiment does not impose any limitations.

[0100] Optionally, in this embodiment of the application, the target TE signal includes multiple TE signals. Step 202 can be specifically implemented through step 202a as described below.

[0101] Step 202a: When the system-on-a-chip receives a TE signal, the electronic device sends one frame of data from the first data to the discrete graphics chip through the system-on-a-chip, so as to send multiple frames of data from the first data to the discrete graphics chip through the system-on-a-chip.

[0102] It should be noted that for details regarding the TE signal, the first data, etc., please refer to the relevant description in Embodiment 1 above, which will not be repeated here.

[0103] In this embodiment, the electronic device sends a TE signal to the system-on-a-chip (SoC) via the discrete graphics chip. Then, the electronic device can send a frame of data to the discrete graphics chip via the SoC. Thus, each time the SoC receives a TE signal, the electronic device sends another frame of data from the first data to the discrete graphics chip via the SoC. Finally, the SoC sends all the frames of data from the first data to the discrete graphics chip, avoiding the situation where the discrete graphics chip receives the next frame of data before it has finished processing the previous frame, thereby ensuring the timing of data processing by the SoC and the discrete graphics chip.

[0104] Step 203: The electronic device performs frame interpolation on the first data through the discrete graphics chip to obtain the second data.

[0105] In this embodiment of the application, the frame rate of the second data is greater than or equal to the frame rate of the first content.

[0106] It should be noted that for details regarding frame interpolation processing, second data, etc., please refer to the relevant descriptions in Embodiment 1 above, which will not be repeated here.

[0107] Optionally, in this embodiment of the application, before step 202 above, the discrete graphics frame interpolation method provided in this embodiment of the application further includes the following steps 301 and 302.

[0108] Step 301: The electronic device sends the first instruction to the discrete graphics chip through the system-on-a-chip.

[0109] In this embodiment of the application, the first instruction includes a preset frame rate.

[0110] Step 302: The electronic device generates the target TE signal through the discrete graphics chip and sends the target TE signal to the system-on-a-chip through the discrete graphics chip.

[0111] In this embodiment of the application, the frequency of the target TE signal is equal to the preset frame rate.

[0112] In this embodiment, the electronic device can send a first instruction, including a preset frame rate, to the discrete graphics chip via the system-on-a-chip (SoC). This causes the electronic device to generate a TE signal with a frequency value equal to the preset frame rate via the discrete graphics chip, and then send the TE signal to the SoC via the discrete graphics chip. In this way, the electronic device can send data with the preset frame rate to the discrete graphics chip via the SoC. Since the preset frame rate is less than the frame rate of the first content, the electronic device reduces the power consumption of the SoC by lowering its output frame rate, thereby stabilizing the output frame rate of the SoC and improving the smoothness of the displayed image.

[0113] Optionally, in this embodiment of the application, the first instruction mentioned above further includes a target frame rate. Step 203 can be specifically implemented through step 203a as described below.

[0114] Step 203a: The electronic device uses a dedicated graphics chip and a target frame rate to perform frame interpolation on the first data to obtain the second data.

[0115] It should be noted that for details regarding the target frame rate, please refer to the relevant description in the above embodiment one, which will not be repeated here.

[0116] In this embodiment of the application, the electronic device can use a discrete graphics chip to perform frame interpolation processing on the first data whose frame rate is less than that of the first content, to obtain the second data whose frame rate is greater than or equal to that of the first content. In this way, the electronic device can improve or maintain the frame rate of the content displayed by the electronic device while reducing the power consumption of the system-on-a-chip, thereby improving the smoothness of the screen displayed by the electronic device.

[0117] This application provides a method for frame interpolation in discrete graphics cards. An electronic device can generate first data based on first content to be displayed by a system-on-a-chip (SoC), where the frame rate of the first data is lower than the frame rate of the first content. Then, when the SoC receives a target TE signal sent by the discrete graphics chip in the electronic device, the electronic device can send the first data to the discrete graphics chip via the SoC, causing the discrete graphics chip to perform frame interpolation processing on the first data to obtain second data, where the frame rate of the second data is greater than or equal to the frame rate of the first content. In this solution, since the frame rate of the first data generated by the SoC is lower than the frame rate of the first content to be displayed by the electronic device, the output frame rate of the SoC is reduced. Then, the discrete graphics chip can perform frame interpolation processing on the first data to obtain second data, thereby increasing or maintaining the frame rate of the content to be displayed by the electronic device. Thus, by reducing the output frame rate of the SoC, the problem of high power consumption of the SoC affecting the frame interpolation function of the discrete graphics card is avoided, thereby improving the smoothness of the displayed image on the electronic device.

[0118] Optionally, in this embodiment of the application, after step 203 above, the discrete graphics frame interpolation method provided in this embodiment of the application further includes the following steps 401 and 402.

[0119] Step 401: When the discrete graphics chip receives the first TE signal sent by the display unit in the electronic device, the electronic device sends the second data to the display unit through the discrete graphics chip.

[0120] In this embodiment of the application, the frequency of the first TE signal is greater than or equal to the frame rate of the second data.

[0121] It should be noted that for details regarding the display unit, the first TE signal, etc., please refer to the relevant descriptions in Embodiment 1 above, which will not be repeated here.

[0122] Step 402: The electronic device displays the second content based on the second data displayed by the display unit.

[0123] It should be noted that for details regarding the second data, second content, etc., please refer to the relevant description in the above embodiment one, which will not be repeated here.

[0124] In this embodiment, the electronic device can receive the second data sent by the discrete graphics chip through the display unit and display the second content corresponding to the second data. That is, the display unit can display high frame rate content or maintain the content displayed by the display unit, thus avoiding the problem that the system-on-a-chip power consumption is too high and affects the frame interpolation function of the discrete graphics chip, thereby improving the smoothness of the screen displayed by the electronic device.

[0125] The discrete graphics frame interpolation method provided in this application can be executed by a discrete graphics frame interpolation device. This application uses the execution of the discrete graphics frame interpolation method by a discrete graphics frame interpolation device as an example to illustrate the discrete graphics frame interpolation device provided in this application.

[0126] Figure 8 A schematic diagram of a possible structure of the discrete graphics frame interpolation device involved in an embodiment of this application is shown. For example... Figure 8 As shown, the discrete graphics frame interpolation device 70 may include: a generation module 71, a sending module 72, and a processing module 73.

[0127] The generation module 71 is used to generate first data based on the first content to be displayed by the electronic device through a system-on-a-chip (SoC), wherein the frame rate of the first data is less than the frame rate of the first content. The sending module 72 is used to send the first data to the discrete graphics chip through the SoC when the SoC receives a target display frame rate synchronization (TE) signal sent by the discrete graphics chip in the electronic device. The processing module 73 is used to perform frame interpolation processing on the first data through the discrete graphics chip to obtain second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content.

[0128] This application provides a discrete graphics card frame interpolation device. Since the frame rate of the first data generated by the system-on-a-chip (SoC) is lower than the frame rate of the first content displayed by the discrete graphics card frame interpolation device, i.e., the output frame rate of the SoC is reduced, the discrete graphics card can then perform frame interpolation processing on the first data to obtain second data, thereby increasing or maintaining the frame rate of the content to be displayed by the discrete graphics card frame interpolation device. In this way, by reducing the output frame rate of the SoC, the problem of high power consumption of the SoC affecting the discrete graphics card frame interpolation function is avoided, thereby improving the smoothness of the image displayed by the discrete graphics card frame interpolation device.

[0129] In one possible implementation, the aforementioned generation module 71 is specifically used to perform frame dropping processing on the first content based on a preset frame rate through a system-on-a-chip to obtain the first data at the preset frame rate.

[0130] In one possible implementation, the transmitting module 72 is further configured to, upon receiving a target TE signal from the discrete graphics chip in the electronic device, send a first instruction to the discrete graphics chip via the system-on-a-chip (SoC) before sending first data to the discrete graphics chip, the first instruction including a preset frame rate. The generating module 71 is further configured to generate the target TE signal via the discrete graphics chip. The transmitting module 72 is further configured to send the target TE signal from the discrete graphics chip to the SoC, the frequency of which is equal to the preset frame rate.

[0131] In one possible implementation, the first instruction mentioned above also includes a target frame rate. Specifically, the processing module 73 is used by the discrete graphics chip to perform frame interpolation processing on the first data using the target frame rate to obtain the second data.

[0132] In one possible implementation, the target TE signal includes multiple TE signals. Specifically, the transmitting module 72 is used to transmit one frame of data from the first data to the discrete graphics chip via the system-on-a-chip (SoC) each time the SoC receives a TE signal, thereby transmitting multiple frames of data from the first data to the discrete graphics chip via the SoC.

[0133] In one possible implementation, the aforementioned discrete graphics frame interpolation device 70 further includes a display module. The aforementioned transmitting module 72 is further configured to, after performing frame interpolation processing on the first data via the discrete graphics chip to obtain the second data, transmit the second data to the display unit via the discrete graphics chip when the discrete graphics chip receives a first TE signal transmitted by the display unit in the electronic device, wherein the frequency of the first TE signal is greater than or equal to the frame rate of the second data. The display module is configured to display the second content based on the second data via the display unit.

[0134] The discrete graphics frame interpolation device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc., and this application embodiment does not specifically limit the scope.

[0135] The discrete graphics frame interpolation device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit it.

[0136] The discrete graphics frame interpolation device provided in this application embodiment can implement all the processes implemented in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0137] This application embodiment also provides a system-on-a-chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to generate first data based on first content to be displayed by the electronic device. The frame rate of the first data is less than the frame rate of the first content. The communication interface is used to send the first data to the discrete graphics chip when it receives a target TE signal sent by the discrete graphics chip in the electronic device.

[0138] Optionally, in this embodiment of the application, the processor is specifically used to perform frame dropping processing on the first content based on a preset frame rate to obtain the first data of the preset frame rate.

[0139] Optionally, in this embodiment, the communication interface is further configured to send a first instruction to the discrete graphics chip, the first instruction including a preset frame rate. The communication interface is also configured to receive a target TE signal sent by the discrete graphics chip, the frequency of which is equal to the preset frame rate.

[0140] Optionally, in this embodiment, the target TE signal includes multiple TE signals. Specifically, the communication interface is used to send one frame of data from the first data to the discrete graphics chip upon receiving each TE signal, thereby sending multiple frames of data from the first data to the discrete graphics chip.

[0141] The system-on-a-chip provided in this application embodiment can implement all the processes implemented by the system-on-a-chip in the method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0142] This application embodiment also provides a discrete graphics chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The communication interface is used to send a target TE signal to a system-on-a-chip (SoC) in an electronic device and to receive first data sent by the SoC. The first data is data generated by the SoC based on first content to be displayed by the electronic device. The frame rate of the first data is less than the frame rate of the first content. The processor is used to perform frame interpolation processing on the first data to obtain second data. The frame rate of the second data is greater than or equal to the frame rate of the first content.

[0143] Optionally, in this embodiment, the communication interface is further configured to receive a first instruction sent by the system-on-a-chip, the first instruction including a preset frame rate. The processor is further configured to generate a target TE signal. The communication interface is further configured to send the target TE signal to the system-on-a-chip, the frequency of the target TE signal being equal to the preset frame rate.

[0144] Optionally, in this embodiment, the first instruction further includes a target frame rate. Specifically, the processor is used to perform frame interpolation on the first data using the target frame rate to obtain the second data.

[0145] Optionally, in this embodiment, the target TE signal includes multiple TE signals. Specifically, the communication interface is used to receive one frame of data from the first data sent by the system-on-a-chip (SoC) each time a TE signal is sent, thereby receiving multiple frames of data from the first data sent by the SoC.

[0146] Optionally, in this embodiment of the application, the communication interface is further configured to send second data to the display unit when a first TE signal is received from the display unit in the electronic device, wherein the frequency of the first TE signal is greater than or equal to the frame rate of the second data.

[0147] The discrete graphics chip provided in this application embodiment can implement all the processes implemented by the discrete graphics chip in the method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0148] Optionally, such as Figure 9As shown, this application embodiment also provides an electronic device 800, including a processor 801, a memory 802, and a program or instructions stored in the memory 802 and executable on the processor 801. When the program or instructions are executed by the processor 801, they implement the various steps of the above-described discrete graphics frame interpolation method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0149] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0150] Figure 10 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0151] The electronic device 1000 includes, but is not limited to, components such as: radio frequency unit 1001, network module 1002, audio output unit 1003, input unit 1004, sensor 1005, display unit 1006, user input unit 1007, interface unit 1008, memory 1009, and processor 1010.

[0152] Those skilled in the art will understand that the electronic device 1000 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1010 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 10 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0153] The processor 1010 is configured to generate first data based on first content to be displayed by the electronic device through a system-on-a-chip (SoC) in the electronic device, wherein the frame rate of the first data is less than the frame rate of the first content; when the SoC receives a target TE signal sent by the discrete graphics chip in the electronic device, the SoC sends the first data to the discrete graphics chip; and the discrete graphics chip performs frame interpolation processing on the first data to obtain second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content.

[0154] This application provides an electronic device in which the frame rate of the first data generated by the system-on-a-chip (SoC) is lower than the frame rate of the first content displayed by the electronic device. That is, the output frame rate of the SoC is reduced. Then, the discrete graphics chip can perform frame interpolation on the first data to obtain second data, so as to increase or maintain the frame rate of the content displayed by the electronic device. In this way, by reducing the output frame rate of the SoC, the problem of the high power consumption of the SoC affecting the frame interpolation function of the discrete graphics chip is avoided, thereby improving the smoothness of the screen displayed by the electronic device.

[0155] Optionally, in this embodiment of the application, the processor 1010 is specifically used to perform frame dropping processing on the first content based on a preset frame rate through a system-on-a-chip to obtain the first data of the preset frame rate.

[0156] Optionally, in this embodiment, the processor 1010 is further configured to, before sending first data to the discrete graphics chip via the system-on-a-chip (SoC) when the SoC receives a target TE signal sent by the discrete graphics chip in the electronic device, send a first instruction to the discrete graphics chip via the SoC, the first instruction including a preset frame rate. The processor 1010 is also configured to generate the target TE signal via the discrete graphics chip and send the target TE signal to the SoC via the discrete graphics chip, wherein the frequency of the target TE signal is equal to the preset frame rate.

[0157] Optionally, in this embodiment, the first instruction further includes a target frame rate. The processor 1010 is specifically configured to use a discrete graphics chip to perform frame interpolation processing on the first data using the target frame rate to obtain the second data.

[0158] Optionally, in this embodiment, the target TE signal includes multiple TE signals. The processor 1010 is specifically configured to, upon receiving a TE signal, send one frame of data from the first data to the discrete graphics chip via the system-on-a-chip, thereby sending multiple frames of data from the first data to the discrete graphics chip via the system-on-a-chip.

[0159] Optionally, in this embodiment, the processor 1010 is further configured to, after performing frame interpolation processing on the first data via the discrete graphics chip to obtain the second data, send the second data to the display unit via the discrete graphics chip when the discrete graphics chip receives a first TE signal sent by the display unit in the electronic device, wherein the frequency of the first TE signal is greater than or equal to the frame rate of the second data. The display unit 1006 is configured to display the second content based on the second data.

[0160] The electronic device provided in this application embodiment can implement the various processes implemented in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0161] For details on the beneficial effects of the various implementation methods in this embodiment, please refer to the beneficial effects of the corresponding implementation methods in the above method embodiments. To avoid repetition, these will not be repeated here.

[0162] It should be understood that, in this embodiment, the input unit 1004 may include a graphics processing unit (GPU) 10041 and a microphone 10042. The GPU 10041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1006 may include a display panel 10061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 1007 includes a touch panel 10071 and at least one of other input devices 10072. The touch panel 10071 is also called a touch screen. The touch panel 10071 may include a touch detection device and a touch controller. Other input devices 10072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0163] The memory 1009 can be used to store software programs and various data. The memory 1009 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1009 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1009 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0164] The processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into the processor 1010.

[0165] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, the electronic device implements the various processes of the above-described discrete graphics frame interpolation method embodiments and achieves the same technical effect. To avoid repetition, these will not be described again here.

[0166] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0167] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to enable an electronic device to perform the various processes of the discrete graphics frame interpolation method embodiment described above, and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0168] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0169] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0170] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A discrete graphics frame interpolation circuit, characterized in that, The discrete graphics frame interpolation circuit includes a system-on-a-chip and a discrete graphics chip; The system-on-a-chip (SoC) is used to generate first data based on the first content to be displayed, and to send the first data to the discrete graphics chip upon receiving the target display frame rate synchronization (TE) signal sent by the discrete graphics chip. The frame rate of the first data is less than the frame rate of the first content. The discrete graphics chip is used to perform frame interpolation on the first data to obtain second data. The frame rate of the second data is greater than or equal to the frame rate of the first content. The system-on-a-chip is also used to send a first instruction to the discrete graphics chip, the first instruction including a preset frame rate; The first instruction also includes a target frame rate; the discrete graphics chip is specifically used to perform frame interpolation processing on the first data using the target frame rate to obtain the second data; The discrete graphics frame interpolation circuit is applied to the electronic device; when the electronic device is in high frame rate mode, the frame rate of the second data is greater than the frame rate of the first content; when the electronic device is in power saving mode, the frame rate of the second data is equal to the frame rate of the first content. The discrete display frame interpolation circuit also includes a display unit; The discrete graphics chip is also used to send the second data to the display unit when it receives the first TE signal sent by the display unit, wherein the frequency of the first TE signal is greater than the frame rate of the second data. The display unit is used to display second content based on the second data; Wherein, after the display unit sends one of the first TE signals, if the display unit does not receive one frame of data in the second data, the display unit displays the content corresponding to the last frame of data received before sending one of the first TE signals; The target TE signal includes multiple TE signals; the system-on-a-chip is specifically used to send one frame of data from the first data to the discrete graphics chip each time a TE signal is received, so as to send multiple frames of data from the first data to the discrete graphics chip.

2. The circuit according to claim 1, characterized in that, The system-on-a-chip is specifically used to perform frame dropping processing on the first content based on a preset frame rate, so as to obtain the first data of the preset frame rate.

3. The circuit according to claim 1 or 2, characterized in that, The discrete graphics chip is also used to generate the target TE signal and send the target TE signal to the system-on-a-chip, wherein the frequency of the target TE signal is equal to the preset frame rate.

4. A method for frame interpolation on a dedicated graphics card, characterized in that, Applied to electronic devices, the method includes: The system-on-a-chip in the electronic device generates first data based on the first content to be displayed by the electronic device, wherein the frame rate of the first data is less than the frame rate of the first content; When the system-on-a-chip receives the target display frame rate synchronization TE signal sent by the discrete graphics chip in the electronic device, the system-on-a-chip sends the first data to the discrete graphics chip. The discrete graphics chip is used to perform frame interpolation on the first data to obtain the second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content. Before sending the first data to the discrete graphics chip via the system-on-a-chip when the system-on-a-chip receives the target TE signal sent by the discrete graphics chip in the electronic device, the method further includes: The system-on-a-chip sends a first instruction to the discrete graphics chip, the first instruction including a preset frame rate; The first instruction also includes the target frame rate; The step of performing frame interpolation processing on the first data through the discrete graphics chip to obtain the second data includes: Using the discrete graphics chip and the target frame rate, the first data is subjected to frame interpolation to obtain the second data; Specifically, when high frame rate mode is enabled, the frame rate of the second data is greater than the frame rate of the first content; when power saving mode is enabled, the frame rate of the second data is equal to the frame rate of the first content. After performing frame interpolation processing on the first data using the discrete graphics chip to obtain the second data, the method further includes: When the discrete graphics chip receives a first TE signal sent by the display unit in the electronic device, the second data is sent to the display unit through the discrete graphics chip, wherein the frequency of the first TE signal is greater than the frame rate of the second data. The second content is displayed based on the second data generated by the display unit. Wherein, after the display unit sends one of the first TE signals, if the display unit does not receive one frame of data in the second data, the display unit displays the content corresponding to the last frame of data received before sending one of the first TE signals; The target TE signal includes multiple TE signals; When the system-on-a-chip (SoC) receives the target TE signal sent by the discrete graphics chip in the electronic device, sending the first data to the discrete graphics chip via the SoC includes: When the system-on-a-chip receives a TE signal, it sends one frame of the first data to the discrete graphics chip, so as to send multiple frames of the first data to the discrete graphics chip through the system-on-a-chip.

5. The method according to claim 4, characterized in that, The step of generating first data based on the first content to be displayed by the electronic device through the system-on-a-chip in the electronic device includes: The system-on-a-chip performs frame dropping processing on the first content based on a preset frame rate to obtain the first data at the preset frame rate.

6. The method according to claim 4 or 5, characterized in that, After sending the first instruction to the discrete graphics chip via the system-on-a-chip, the method further includes: The target TE signal is generated by the discrete graphics chip and sent to the system-on-a-chip via the discrete graphics chip. The frequency of the target TE signal is equal to the preset frame rate.

7. A discrete graphics frame interpolation device, characterized in that, The discrete display frame interpolation device includes: a generation module, a sending module, and a processing module; The generation module is used to generate first data based on the first content to be displayed by the electronic device through a system-on-a-chip in the electronic device, wherein the frame rate of the first data is less than the frame rate of the first content; The sending module is used to send the first data to the discrete graphics chip through the system-on-a-chip when the system-on-a-chip receives the target display frame rate synchronization TE signal sent by the discrete graphics chip in the electronic device; The processing module is used to perform frame interpolation processing on the first data through the discrete graphics chip to obtain the second data, wherein the frame rate of the second data is greater than or equal to the frame rate of the first content. The sending module is further configured to, when the system-on-a-chip receives the target TE signal sent by the discrete graphics chip in the electronic device, send a first instruction to the discrete graphics chip through the system-on-a-chip before sending the first data through the system-on-a-chip, the first instruction including a preset frame rate; The first instruction also includes the target frame rate; The processing module is specifically used to perform frame interpolation processing on the first data using the discrete graphics chip and the target frame rate to obtain the second data; Specifically, when high frame rate mode is enabled, the frame rate of the second data is greater than the frame rate of the first content; when power saving mode is enabled, the frame rate of the second data is equal to the frame rate of the first content. The discrete display frame interpolation device further includes: a display module; The sending module is further configured to, after performing frame interpolation processing on the first data through the discrete graphics chip to obtain the second data, send the second data to the display unit through the discrete graphics chip when the discrete graphics chip receives the first TE signal sent by the display unit in the electronic device, wherein the frequency value of the first TE signal is greater than the frame rate value of the second data. The display module is used to display second content based on the second data through the display unit; Wherein, after the display unit sends one of the first TE signals, if the display unit does not receive one frame of data in the second data, the display unit displays the content corresponding to the last frame of data received before sending one of the first TE signals; The target TE signal includes multiple TE signals; The transmitting module is specifically used to transmit one frame of the first data to the discrete graphics chip through the system-on-a-chip when the system-on-a-chip receives a TE signal, so as to transmit multiple frames of the first data to the discrete graphics chip through the system-on-a-chip.

8. A system-on-a-chip (SoC), the SoC including a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to generate first data based on first content to be displayed by an electronic device, the frame rate of the first data being less than the frame rate of the first content, and the communication interface being configured to send the first data to the discrete graphics chip upon receiving a target display frame rate synchronization (TE) signal sent by the discrete graphics chip in the electronic device; The target TE signal includes multiple TE signals; the communication interface is specifically used to send one frame of data from the first data to the discrete graphics chip each time a TE signal is received, so as to send multiple frames of data from the first data to the discrete graphics chip.

9. The system-on-a-chip according to claim 8, characterized in that, The processor is specifically used to perform frame dropping processing on the first content based on a preset frame rate to obtain the first data of the preset frame rate.

10. The system-on-a-chip according to claim 8 or 9, characterized in that, The communication interface is also used to send a first instruction to the discrete graphics chip, the first instruction including a preset frame rate; the communication interface is also used to receive the target TE signal sent by the discrete graphics chip, the frequency of the target TE signal being equal to the preset frame rate.

11. A discrete graphics chip, the discrete graphics chip comprising a processor and a communication interface, the communication interface being coupled to the processor, the communication interface being configured to send a target display frame rate synchronization (TE) signal to a system-on-a-chip (SoC) in an electronic device, and to receive first data sent by the SoC, the first data being data generated by the SoC based on first content to be displayed by the electronic device, the frame rate of the first data being less than the frame rate of the first content, the processor being configured to perform frame interpolation processing on the first data to obtain second data, the frame rate of the second data being greater than or equal to the frame rate of the first content; The communication interface is also used to receive a first instruction sent by the system-on-a-chip, the first instruction including a preset frame rate; the first instruction also including a target frame rate; the processor is specifically used to perform frame interpolation processing on the first data using the target frame rate to obtain the second data; The communication interface is also used to send the second data to the display unit when a first TE signal is received from the display unit in the electronic device, wherein the frequency of the first TE signal is greater than the frame rate of the second data. The target TE signal includes multiple TE signals; the communication interface is specifically used to receive one frame of data from the first data sent by the system-on-a-chip when each TE signal is sent, so as to receive multiple frames of data from the first data sent by the system-on-a-chip.

12. The discrete graphics chip according to claim 11, characterized in that, The processor is also used to generate the target TE signal; the communication interface is also used to send the target TE signal to the system-on-a-chip, wherein the frequency of the target TE signal is equal to the preset frame rate.

13. An electronic device, characterized in that, It includes the discrete graphics frame interpolation circuit as described in any one of claims 1 to 3, or the system-on-a-chip as described in any one of claims 8 to 10 and the discrete graphics chip as described in any one of claims 11 to 12.

14. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor causing the electronic device to perform the steps of the discrete graphics frame interpolation method as described in any one of claims 4 to 6.

15. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, cause the electronic device to perform the steps of the discrete graphics frame interpolation method as described in any one of claims 4 to 6.

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