Chip packaging method, device, computer equipment and storage medium

Abstract

The application relates to a chip packaging method, a device, computer equipment and a storage medium. The chip packaging method comprises the following steps: obtaining a model of a target packaging structure; the model comprises a plurality of chip positions; obtaining performance parameters of chips to be used, grouping the chips to be used according to the performance parameters, and obtaining a plurality of chip groups; according to a preset placement rule, sequentially introducing the chips belonging to the chip groups into the chip positions, and obtaining running parameters of the chips in different chip positions; adjusting the chip positions of the chips introduced by the chip groups until the running parameters meet preset conditions, and obtaining a current corresponding relationship between the chip positions and the chip groups; and packaging the chips to be used based on the current corresponding relationship and the target packaging structure. Through the chip packaging method, the chips can be packaged based on the corresponding relationship between the chip groups and the chip positions in the chip packaging process, and the overall performance of a module under the packaging structure is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a chip packaging method and device, computer equipment and storage medium. BACKGROUND

[0002] When multiple chips are packaged into a module, the chips contained in the module should theoretically have the same performance, but due to the slight fluctuations in the chip manufacturing process, the performance of the chips in the same batch will also have slight deviations.

[0003] In the implementation process, the inventor found that the traditional chip packaging technology has at least the following problems: the traditional chip packaging technology has the problem of poor overall performance. SUMMARY

[0004] Therefore, it is necessary to provide a chip packaging method, device, computer equipment and storage medium capable of improving the overall performance to solve the above technical problems.

[0005] To achieve the above purpose, on the one hand, the embodiments of the present application provide a chip packaging method, comprising the steps of:

[0006] Obtaining a model of a target packaging structure; wherein the model comprises a plurality of chip positions;

[0007] Obtaining performance parameters of the chips to be used, and grouping the chips to be used according to the performance parameters to obtain a plurality of chip groups;

[0008] According to a preset placement rule, the chips belonging to each chip group are sequentially imported into each chip position, and the running parameters of each chip in different chip positions are obtained;

[0009] Adjusting the chip positions of the imported chips of each chip group until the running parameters meet the preset conditions, and obtaining the current correspondence between each chip position and each chip group;

[0010] Packaging the chips to be used based on the current correspondence and the target packaging structure.

[0011] In one of the embodiments, the performance parameters include threshold voltage and on-resistance;

[0012] The step of grouping the chips to be used according to the performance parameters to obtain a plurality of chip groups comprises:

[0013] According to the threshold voltage and a first preset range, a plurality of threshold voltage intervals are obtained;

[0014] According to the on-resistance and a second preset range, a plurality of on-resistance intervals are obtained;

[0015] The chips to be used are grouped based on the threshold voltage intervals and the on-resistance intervals, and a plurality of chip groups are obtained.

[0016] In one of the embodiments, the number of the chip groups is the product of the number of the threshold voltage intervals and the number of the on-resistance intervals.

[0017] In one of the embodiments, the method further comprises the steps of:

[0018] Obtaining the parasitic parameters of each loop in the target packaging structure;

[0019] Determining the first preset range and / or the second preset range according to the parasitic parameters.

[0020] In one of the embodiments, the preset placement rule comprises: in a chip position with a small thermal resistance, chips of each chip group are introduced in turn according to the order of the threshold voltage from low to high and / or the order of the on-resistance from large to small; in a chip position with a small packaging resistance, chips of each chip group are introduced in turn according to the order of the on-resistance from large to small; in a chip position with a large packaging inductance, chips of each chip group are introduced in turn according to the order of the threshold voltage from low to high and / or the order of the on-resistance from large to small.

[0021] In one of the embodiments, the operating parameters comprise the current non-uniformity and the junction temperature difference value.

[0022] In the step of obtaining the operating parameters of each chip in different chip positions, the current non-uniformity of each chip in different chip positions is obtained based on the following formula:

[0023]

[0024] wherein y is the non-uniformity; I max is the maximum current of the chip; I min is the minimum current of the chip.

[0025] The step of obtaining the operating parameters of each chip in different chip positions comprises:

[0026] The maximum junction temperature value of the chip and the minimum junction temperature value of the chip are obtained, and the difference between the maximum junction temperature value and the minimum junction temperature value is determined as the junction temperature difference value.

[0027] In one of the embodiments, the step of obtaining the operating parameters of each chip in different chip positions comprises:

[0028] The operating parameters are obtained by using a circuit simulation software.

[0029] In one aspect, the embodiment of the present application further provides a chip packaging device, comprising:

[0030] The model establishing module is configured to obtain a model of the target packaging structure, wherein the model comprises a plurality of chip positions;

[0031] The grouping module is configured to obtain performance parameters of the chips to be used, and group the chips to be used according to the performance parameters, to obtain a plurality of chip groups;

[0032] The obtaining module is configured to sequentially import the chips belonging to the chip groups into the chip positions according to a preset placement rule, and obtain running parameters of the chips in different chip positions;

[0033] The adjusting module is configured to adjust the chip positions of the chips imported by the chip groups until the running parameters meet preset conditions, and obtain a current correspondence between the chip positions and the chip groups;

[0034] The packaging module is configured to package the chips to be used based on the current correspondence and the target packaging structure.

[0035] In one aspect, the embodiment of the present application further provides a computer device, comprising a memory and a processor, the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0036] In another aspect, the embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of any of the above methods.

[0037] One of the above technical solutions has the following advantages and beneficial effects:

[0038] The chip packaging method comprises the following steps: obtaining performance parameters of the chips to be used, and grouping the chips to be used according to the performance parameters, to obtain a plurality of chip groups; sequentially importing the chips belonging to the chip groups into the chip positions according to a preset placement rule, and obtaining running parameters of the chips in different chip positions; adjusting the chip positions of the chips imported by the chip groups until the running parameters meet preset conditions, and obtaining a current correspondence between the chip positions and the chip groups; and packaging the chips to be used based on the current correspondence and the target packaging structure. Through the chip packaging method, the chips can be packaged based on the correspondence between the chip groups and the chip positions in the chip packaging process, the influence of the packaging structure on the running parameters of the chips is considered, and the overall performance of the module under the packaging structure is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:

[0040] Figure 1FIG1 is a first schematic flow chart of a chip packaging method in one embodiment;

[0041] Figure 2 A flowchart illustrating the steps of grouping chips to be used according to performance parameters to obtain multiple chip groups in one embodiment;

[0042] Figure 3 A 3D model of a target package structure in one embodiment;

[0043] Figure 4 Schematic diagram of package parasitic parameters of a certain phase in a three-phase inverter circuit package structure in one embodiment;

[0044] Figure 5 is a structural block diagram of a chip packaging device in one embodiment;

[0045] Figure 6 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0047] In one embodiment, Figure 1 As shown, a chip packaging method is provided, comprising the steps of:

[0048] S110, obtaining a model of a target package structure; wherein the model includes a plurality of chip positions;

[0049] Specifically, the model of the target package structure can be obtained by any means in the art, for example, the model of the target package structure can be drawn using three-dimensional modeling software. The model can be a 3D model, etc.

[0050] S120, obtaining performance parameters of the chips to be used, and grouping the chips to be used according to the performance parameters to obtain multiple chip groups;

[0051] Among them, the performance parameters are the actual inherent parameters of the chip.

[0052] Specifically, the performance parameters of the chips to be used can be obtained by any means known in the art. For example, the chips can be subjected to sufficient incoming material testing to obtain the performance parameters. In one embodiment, the step of obtaining the operating parameters of each chip at different chip positions includes: obtaining the operating parameters using circuit simulation software.

[0053] The chips to be used can be classified according to the performance parameters by any classification manner in the art. For example, the chips with performance parameters exceeding a certain value are classified as one class, and the chips with performance parameters lower than a certain value are classified as another class.

[0054] In S130, the chips belonging to the chip groups are introduced into the chip positions according to the preset placement rules, and the running parameters of the chips in different chip positions are obtained.

[0055] The preset placement rules can be determined according to actual conditions.

[0056] Specifically, the chips of different chip groups are introduced into the chip positions one by one, so that the chips of different chip groups are placed in the chip positions. After the chips of different chip groups are introduced, the running parameters of the packaging structure are obtained.

[0057] In S140, the chip positions introduced by the chip groups are adjusted until the running parameters meet the preset conditions, and the current correspondence between the chip positions and the chip groups is obtained.

[0058] Specifically, the chip positions introduced by the chip groups are adjusted, that is, the correspondence between the chip groups and the chip positions is adjusted.

[0059] In S150, the chips to be used are packaged based on the current correspondence and the target packaging structure.

[0060] Specifically, when the running parameters meet the preset conditions, it is proved that the current correspondence between the chip groups and the chip positions can make the running parameter difference between the chips within an acceptable range, thereby improving the overall performance of the chips in the packaging structure.

[0061] The step of packaging the chips to be used can adopt any packaging manner in the art. According to the current correspondence, any chip belonging to a chip group is placed in the corresponding chip position.

[0062] The chip packaging method described above obtains the performance parameters of the chips to be used, groups the chips to be used according to the performance parameters, and obtains a plurality of chip groups. Then, the chips belonging to the chip groups are introduced into the chip positions according to the preset placement rules, and the running parameters of the chips in different chip positions are obtained. Next, the chip positions introduced by the chip groups are adjusted until the running parameters meet the preset conditions, and the current correspondence between the chip positions and the chip groups is obtained. Finally, the chips to be used are packaged based on the current correspondence and the target packaging structure. Through the chip packaging method described above, the chips can be packaged based on the correspondence between the chip groups and the chip positions in the chip packaging process. The influence of the packaging structure on the running parameters of the chips is considered, and the overall performance of the module in the packaging structure is further improved.

[0063] In one embodiment, the performance parameter includes threshold voltage and on-resistance;

[0064] As shown in Figure 2 , grouping the chips to be used according to the performance parameter includes:

[0065] S210, obtaining a plurality of threshold voltage intervals according to the threshold voltage and a first preset range;

[0066] S220, obtaining a plurality of on-resistance intervals according to the on-resistance and a second preset range;

[0067] S230, grouping the chips to be used based on each threshold voltage interval and each on-resistance interval, to obtain a plurality of chip groups.

[0068] Specifically, the first preset range and the second preset range can be the same or different. For the threshold voltage, for example, the threshold voltage is between 2-3.2V, and the first preset range is 0.4V for binning, then the binning is performed according to the ranges of 2-2.4V, 2.4-2.8V, and 2.8-3.2V. The division of the on-resistance interval can refer to the division of the threshold voltage interval. In one embodiment, the number of chip groups is the product of the number of threshold voltage intervals and the number of on-resistance intervals. If the number of threshold voltage intervals is 5 and the number of on-resistance intervals is 3, the number of chip groups is at most 15.

[0069] In one embodiment, it further includes the steps of:

[0070] Obtaining the parasitic parameters of each loop in the target packaging structure;

[0071] Determining the first preset range and / or the second preset range according to the parasitic parameters.

[0072] Specifically, the parasitic parameter extraction software can be used to obtain the parasitic parameters. The parasitic parameters can include parasitic resistance, parasitic inductance, parasitic capacitance, and parasitic conductance, etc. Figure 3 For a 3D model of the target packaging structure in one embodiment (P, N, G, KS are segments or pin needles in the figure), after importing the 3D model, assigning materials, and other settings in the parasitic parameter extraction software, the parasitic parameters of each loop of the chip in the packaging structure can be calculated. For example, for a three-phase inverter circuit packaging containing SiC Mosfet, the parasitic parameter composition of one phase of the packaging is as shown in Figure 4 The parasitic parameter extraction software can calculate the parasitic parameters of each chip to the terminal (P, N, AC in Figure 4 , and the parasitic parameters of the chip pin (HG, HKS, LG, LKS of Figure 4 ). Figure 4The middle MOSFET (such as MOSFET_H1, MOSFET_H2) is a chip, and L (such as L_HG1, L_HG2) and R (R_HG1, R_HG2) represent the inductance and resistance of each loop, respectively.

[0073] In one embodiment, the preset placement rule comprises: in the chip position with small thermal resistance, the chips of each chip group are introduced in turn according to the order from low to high threshold voltage and / or from large to small on-resistance; in the chip position with small package resistance, the chips of each chip group are introduced in turn according to the order from large to small on-resistance; and in the chip position with large package inductance, the chips of each chip group are introduced in turn according to the order from low to high threshold voltage and / or from large to small on-resistance.

[0074] Specifically, the chip with low threshold voltage and large on-resistance is preferably placed in the position with small thermal resistance; the chip with large on-resistance is preferably placed in the position with small package resistance; and the chip with low threshold voltage and large on-resistance is preferably placed in the position with large package inductance.

[0075] Through the above preset placement rule, the number of simulation can be effectively reduced, and the required current corresponding relationship can be quickly obtained.

[0076] In one embodiment, the operating parameter comprises current unevenness and junction temperature difference value.

[0077] In the step of obtaining the operating parameter of each chip in different chip positions, the current unevenness of each chip in different chip positions is obtained based on the following formula:

[0078]

[0079] Wherein, y is the unevenness; I max is the maximum current of the chip; I min is the minimum current of the chip.

[0080] The step of obtaining the operating parameter of each chip in different chip positions comprises:

[0081] The maximum junction temperature value of the chip and the minimum junction temperature value of the chip are obtained, and the difference between the maximum junction temperature value and the minimum junction temperature value is determined as the junction temperature difference value.

[0082] Specifically, whether the chip position of the chip group is qualified is determined by whether the current non-uniformity meets the corresponding preset condition and whether the junction temperature difference meets the corresponding preset condition. In a specific example, the preset range of the current non-uniformity is within 0.1-10%, and the preset range of the junction temperature difference is between 0.1-5°C. For example, the chip group bin3 is placed at the chip position 1, the chip group bin5 is placed at the chip position 2, and the chip group bin6 is placed at the chip position 3, and the current non-uniformity and the junction temperature difference both meet the preset condition, so that in the packaging process, the chip of the chip group bin3 placed at the chip position 1 is placed at the chip position 2, the chip group bin5 is placed at the chip position 3, and the chip group bin6 is placed at the chip position 3. It should be noted that only three chip positions are listed in the above embodiment, but in actual situations, there can be multiple chip positions and multiple chip groups.

[0083] It should be understood that, although Figures 1-2 the steps in the flowchart are shown in a sequential order following the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated herein, the execution of the steps is not strictly limited in order, and the steps can be executed in other orders. Moreover, Figures 1-2 at least part of the steps in the flowchart can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the sub-steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or sub-steps or stages of other steps.

[0084] In an embodiment, as shown in Figure 5 , a chip packaging device is provided, comprising:

[0085] a model establishing module configured to obtain a model of a target packaging structure; wherein the model comprises a plurality of chip positions;

[0086] a grouping module configured to obtain performance parameters of chips to be used, and group the chips to be used according to the performance parameters to obtain a plurality of chip groups;

[0087] an obtaining module configured to sequentially introduce chips belonging to the chip groups into the chip positions according to a preset placement rule, and obtain running parameters of the chips at different chip positions;

[0088] an adjusting module configured to adjust the chip positions of the chips introduced by the chip groups until the running parameters meet preset conditions, and obtain a current correspondence between the chip positions and the chip groups;

[0089] a packaging module configured to package the chips to be used based on the current correspondence and the target packaging structure.

[0090] In one of the embodiments, the grouping module further comprises:

[0091] a threshold voltage interval division module, configured to obtain a plurality of threshold voltage intervals according to the threshold voltage and a first preset range;

[0092] a conduction resistance interval division module, configured to obtain a plurality of conduction resistance intervals according to the conduction resistance and a second preset range;

[0093] a chip grouping module, configured to group the chips to be used based on the threshold voltage intervals and the conduction resistance intervals, to obtain a plurality of chip groups.

[0094] In one of the embodiments, the chip packaging apparatus further comprises:

[0095] a parasitic parameter acquisition module, configured to acquire the parasitic parameters of the loops in the target packaging structure;

[0096] a range confirmation module, configured to determine the first preset range and / or the second preset range according to the parasitic parameters.

[0097] The specific limitations of the chip packaging apparatus can refer to the limitations of the chip packaging method described above, which will not be repeated here. Each module in the above chip packaging apparatus can be realized by software, hardware and their combinations. Each module described above can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in the form of software, so as to call and execute the operations corresponding to each module by the processor.

[0098] In one embodiment, a computer device is provided, which can be a terminal, and its internal structure diagram can be as shown in Figure 6 The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is configured to communicate with external terminals through network connection. The computer program is executed by the processor to implement a chip packaging method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0099] Those skilled in the art can understand that,Figure 6 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0100] In one embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:

[0101] Obtaining a model of a target packaging structure; wherein the model comprises a plurality of chip positions;

[0102] Obtaining performance parameters of chips to be used, and grouping the chips to be used according to the performance parameters to obtain a plurality of chip groups;

[0103] According to a preset placement rule, chips belonging to each chip group are sequentially imported into each chip position, and running parameters of each chip in different chip positions are obtained;

[0104] Adjusting the chip positions of the imported chips of each chip group until the running parameters meet a preset condition, and obtaining a current correspondence between each chip position and each chip group;

[0105] Packaging the chips to be used based on the current correspondence and the target packaging structure.

[0106] In one embodiment, when the processor executes the step of grouping the chips to be used according to the performance parameters to obtain a plurality of chip groups, the processor further implements the following steps:

[0107] According to the threshold voltage and a first preset range, a plurality of threshold voltage intervals are obtained;

[0108] According to the on-resistance and a second preset range, a plurality of on-resistance intervals are obtained;

[0109] Grouping the chips to be used based on each threshold voltage interval and each on-resistance interval to obtain a plurality of chip groups.

[0110] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0111] Obtaining parasitic parameters of each loop in the target packaging structure;

[0112] Determining the first preset range and / or the second preset range according to the parasitic parameters.

[0113] In one embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0114] obtaining a model of a target packaging structure; wherein the model comprises a plurality of chip positions;

[0115] obtaining performance parameters of the chips to be used, and grouping the chips to be used according to the performance parameters to obtain a plurality of chip groups;

[0116] According to the preset placement rule, the chips belonging to each chip group are sequentially imported into each chip position, and operating parameters of each chip in different chip positions are obtained;

[0117] The chip positions imported by each chip group are adjusted until the operating parameters all meet preset conditions, and a current correspondence between each chip position and each chip group is obtained;

[0118] Based on the current correspondence and the target packaging structure, the chips to be used are packaged.

[0119] In one embodiment, when the step of grouping the chips to be used according to the performance parameters to obtain a plurality of chip groups is executed by the processor, the following steps are also implemented:

[0120] According to the threshold voltage and the first preset range, a plurality of threshold voltage intervals are obtained;

[0121] According to the on-resistance and the second preset range, a plurality of on-resistance intervals are obtained;

[0122] Based on each threshold voltage interval and each on-resistance interval, the chips to be used are grouped to obtain a plurality of chip groups.

[0123] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented:

[0124] Obtaining parasitic parameters of each loop in the target packaging structure;

[0125] According to the parasitic parameters, the first preset range and / or the second preset range are determined.

[0126] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0127] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A chip packaging method, characterized in that: Including steps: Acquire a model of a target package structure; wherein the model includes a plurality of chip positions; Acquiring performance parameters of chips to be used, and grouping the chips to be used according to the performance parameters to obtain multiple chip groups; the performance parameters are actual inherent parameters of the chips to be used; According to a preset placement rule, chips belonging to each chipset are sequentially introduced at each chip position, and operating parameters of each chip at different chip positions are obtained; the operating parameters include current unevenness and junction temperature difference; Adjusting the chip positions imported by each of the chipsets until the operating parameters all meet preset conditions, and obtaining a current correspondence between each of the chip positions and each of the chipsets; Based on the current corresponding relationship and the target packaging structure, packaging the chip to be used; The performance parameters include threshold voltage and on-resistance; The step of grouping the chips to be used according to the performance parameters to obtain a plurality of chip groups includes: obtaining a plurality of threshold voltage intervals according to the threshold voltage and a first preset range; obtaining a plurality of on-resistance intervals according to the on-resistance and a second preset range; and grouping the chips to be used based on the threshold voltage intervals and the on-resistance intervals to obtain a plurality of chip groups. The method further comprises the steps of: obtaining parasitic parameters of each loop in the target package structure; determining the first preset range and / or the second preset range according to the parasitic parameters; The preset placement rule includes: at chip locations with low thermal resistance, chips of each chipset are sequentially introduced in order of threshold voltage from low to high and / or on-resistance from large to small; at chip locations with low package resistance, chips of each chipset are sequentially introduced in order of on-resistance from large to small; at chip locations with high package inductance, chips of each chipset are sequentially introduced in order of threshold voltage from low to high and / or on-resistance from large to small; The parasitic parameters include parasitic resistance, parasitic inductance, parasitic capacitance and parasitic conductance; the parasitic parameters are obtained through parasitic parameter extraction software; the parasitic parameter extraction software is used to calculate the parasitic parameters of each chip to terminal and chip pin.

2. The chip packaging method according to claim 1, wherein: The number of the chip groups is a product of the number of the threshold voltage intervals and the number of the on-resistance intervals.

3. The chip packaging method according to claim 1, wherein: In the step of obtaining the operating parameters of each chip when it is at a different chip position, the current unevenness when each chip is at a different chip position is obtained based on the following formula: Where y is the uneven flow; I max is the maximum current of the chip; I min is the minimum current of the chip; The step of obtaining the operating parameters of each chip when it is in different chip positions includes: A maximum junction temperature value of the chip and a minimum junction temperature value of the chip are obtained, and the junction temperature difference is determined by the difference between the maximum junction temperature value and the minimum junction temperature value.

4. The chip packaging method according to claim 1, wherein: The step of obtaining the operating parameters of each chip when it is in different chip positions includes: The operating parameters are obtained using circuit simulation software.

5. A chip packaging device, characterized in that: include: A model building module, configured to obtain a model of a target package structure; wherein the model includes a plurality of chip positions; a grouping module, configured to obtain performance parameters of chips to be used, and group the chips to be used according to the performance parameters to obtain a plurality of chip groups; the performance parameters are actual inherent parameters of the chips to be used; an acquisition module, configured to sequentially import chips belonging to each chipset at each chip position according to a preset placement rule, and acquire operating parameters of each chip at different chip positions; the operating parameters including current unevenness and junction temperature difference; an adjusting module, configured to adjust the chip positions imported by each of the chipsets until the operating parameters all meet preset conditions, and obtain a current correspondence between each of the chip positions and each of the chipsets; A packaging module, configured to package the chip to be used based on the current corresponding relationship and the target packaging structure; The performance parameters include threshold voltage and on-resistance; The grouping module is further configured to obtain a plurality of threshold voltage intervals based on the threshold voltage and the first preset range; obtain a plurality of on-resistance intervals based on the on-resistance and the second preset range; and group the chips to be used based on the threshold voltage intervals and the on-resistance intervals to obtain a plurality of chip groups. The device further comprises: A parasitic parameter acquisition module, configured to acquire parasitic parameters of each loop in the target package structure; a range confirmation module, configured to determine the first preset range and / or the second preset range according to the parasitic parameter; The preset placement rule includes: at chip locations with low thermal resistance, chips of each chipset are sequentially introduced in order of threshold voltage from low to high and / or on-resistance from large to small; at chip locations with low package resistance, chips of each chipset are sequentially introduced in order of on-resistance from large to small; at chip locations with high package inductance, chips of each chipset are sequentially introduced in order of threshold voltage from low to high and / or on-resistance from large to small; The parasitic parameters include parasitic resistance, parasitic inductance, parasitic capacitance and parasitic conductance; the parasitic parameters are obtained through parasitic parameter extraction software; the parasitic parameter extraction software is used to calculate the parasitic parameters of each chip to terminal and chip pin.

6. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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