Display panel and display device using the same

Abstract

The present disclosure relates to a display panel and a display device using the same, and includes a second pixel area in which pixels having a resolution or pixel per inch (PPI) lower than that of a first pixel area are arranged. A data voltage of pixel data to be written to the pixels in the second pixel area is applied to a first gate electrode of a driving element arranged in the second pixel area. A compensation voltage for increasing the illumination of the second pixel area is applied to a second gate electrode of the driving element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0126163, filed on September 28, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display panel having locally different resolutions or pixels per inch (PPI) and a display device using the display panel. Background Art

[0004] According to the material of the light-emitting layer, electroluminescent display devices are roughly divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include self-luminous organic light-emitting diodes (hereinafter referred to as "OLED"), and have the advantages of fast response speed and large luminous efficiency, illumination and viewing angle. In the organic light-emitting display device, OLED is formed in each pixel. The organic light-emitting display device has a fast response speed, excellent luminous efficiency, illumination and viewing angle, and has excellent contrast and color reproducibility because it can represent black grayscale in full black.

[0005] The multimedia functions of mobile terminals have been improved. For example, cameras are built into smartphones by default, and the resolution of cameras is increasing to the level of conventional digital cameras. The front camera of smartphones limits screen design, making screen design difficult. In order to reduce the space occupied by the camera, screen designs including notches or perforations are adopted in smartphones, but the screen size is still limited due to the camera, making it impossible to achieve a full-screen display. Summary of the invention

[0006] In order to realize a full-screen display, a sensing area in which low-resolution pixels are arranged may be provided in the screen of the display panel. Since the number of pixels lit in such a sensing area is relatively small, the pixels in the sensing area may be driven by a relatively high voltage for the purpose of illumination uniformity across the entire screen. In this case, since the data voltage needs to be higher in order to increase the illumination of the low-resolution area, the voltage range needs to be extended, so the data voltage margin may be reduced, and the cost of the circuit for generating the gamma reference voltage may increase.

[0007] The object of the present disclosure is to address the above-mentioned needs and / or problems.

[0008] The present disclosure provides a display panel capable of realizing a full screen display and achieving uniform illumination over the entire screen without reducing a data voltage margin, and a display device using the same.

[0009] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0010] A display panel according to an embodiment of the present disclosure includes a first pixel area in which pixels are arranged and a second pixel area in which pixels having a lower resolution or pixels per inch (PPI) than that of the first pixel area are arranged.

[0011] Each pixel in the first pixel region includes a first driving element configured to drive a light emitting element. Each pixel in the second pixel region includes a second driving element configured to drive a light emitting element.

[0012] The second driving element includes a first gate electrode and a second gate electrode. A data voltage of pixel data to be written into the pixels of the second pixel area is applied to the first gate electrode of the second driving element.

[0013] A compensation voltage for increasing the illuminance of the second pixel area is applied to the second gate electrode of the second driving element.

[0014] A display device according to an embodiment of the present disclosure includes: a display panel; a data driver configured to convert pixel data of an input image into a data voltage and provide the data voltage to a data line connected to pixels in a first pixel area and a second pixel area; and an illumination compensation unit configured to generate a compensation voltage.

[0015] In the present disclosure, since the sensor is provided on the screen displaying the image, a full screen display can be realized.

[0016] In the present disclosure, a driving element for driving a light-emitting element in a low-resolution or low-PPI area is implemented as a transistor with a dual-gate structure, and a compensation voltage for increasing the illumination of the pixel is applied to the second gate electrode of the driving element, thereby improving the illumination uniformity on a screen having different resolutions or PPIs for each area.

[0017] In the present disclosure, by not expanding the voltage range of the data voltage applied to pixels in low resolution or low PPI areas to ensure voltage margin, the illumination deviation of the sub-pixels can be optically compensated with high resolution, thereby improving the accuracy of optical compensation and ensuring the variable range of the data voltage used to compensate for image quality according to changes over time.

[0018] The effects that can be achieved by the present disclosure are not limited to the above effects. That is, according to the following description, those skilled in the art to which the present disclosure belongs can clearly understand other purposes that are not mentioned. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1 is a cross-sectional view schematically showing a display panel according to an embodiment of the present disclosure;

[0021] Figure 2 is a plan view showing an area in which a sensor module is provided in a screen of a display panel;

[0022] Figure 3 is a diagram showing the arrangement of pixels in a first pixel region;

[0023] Figure 4 is a diagram showing the arrangement of pixels in the second pixel area;

[0024] Figures 5 to 7 is a circuit diagram showing various pixel circuits suitable for use with the present disclosure;

[0025] Figure 8 Is shown driving Figure 7 A waveform diagram of the method of the pixel circuit shown in ;

[0026] Fig. 9 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0027] Fig.10 is a diagram showing an example in which a display device according to an embodiment of the present disclosure is applied to a mobile device;

[0028] Fig.11 is a diagram showing an illumination difference between a first pixel region and a second pixel region when the data voltage ranges applied to pixels in the first pixel region and the second pixel region of the screen are the same;

[0029] Fig.12 is a diagram showing an example in which the luminance difference between a first pixel region and a second pixel region is reduced by extending a data voltage range applied to pixels in a second pixel region of a screen;

[0030] Fig.13 is a circuit diagram schematically showing a dual-gate structure of a driving element according to a first embodiment of the present disclosure;

[0031] Fig.14 It is shown Fig.13 A cross-sectional view of the cross-sectional structure of the first driving element shown in ;

[0032] Fig.15 It is shown Fig.13 A cross-sectional view of the cross-sectional structure of the second driving element shown in ;

[0033] Fig.16 It shows that Fig.13 The first drive element shown is applied to Figure 7 A circuit diagram of an example of a pixel circuit shown;

[0034] Fig.17 It shows that Fig.13 The second drive element shown is applied to Figure 7 A circuit diagram of an example of a pixel circuit shown;

[0035] Fig.18 is a circuit diagram schematically showing a dual-gate structure of a driving element according to a second embodiment of the present disclosure;

[0036] Fig.19 It is shown Fig.18 A cross-sectional view of the cross-sectional structure of the second driving element and the switching element shown in ;

[0037] Fig. 20 It shows that Fig.18 The second driving element and the switching element shown are applied to Figure 7 A circuit diagram of an example of a pixel circuit shown;

[0038] Fig.21 is a plan view showing power lines and auxiliary data lines on a display panel;

[0039] Fig. 22 is a circuit diagram showing an example in which an optimized compensation voltage is applied differently for each color of sub-pixels arranged in a second pixel region;

[0040] Fig.23 is a diagram showing an output voltage range of a data driver and a compensation voltage for each color;

[0041] Fig.24 is a plan view showing power lines on a display panel and auxiliary data lines separated for each color;

[0042] Fig.25 is a diagram showing an effect of improving luminance in a second pixel region by using an output voltage of a data driver having a secured voltage margin and a compensation voltage applied to a display panel;

[0043] Fig.26 is a diagram showing an example in which a compensation voltage is transmitted to a data driver through an independent path;

[0044] Fig. 27 and Fig.28 is a diagram showing an example in which a compensation voltage is output from a channel of a data driver;

[0045] Fig.29 is a flowchart illustrating a method of compensating for illumination of a screen according to a first embodiment of the present disclosure;

[0046] Fig.30 is a flowchart illustrating a method of compensating for illumination of a screen according to a second embodiment of the present disclosure;

[0047] Fig.31 is a flowchart illustrating a method of compensating for illumination of a screen according to a third embodiment of the present disclosure;

[0048] Fig.32 is a flowchart illustrating a method of compensating for illumination of a screen according to a fourth embodiment of the present disclosure; and

[0049] Fig.33 is a diagram showing an example of a histogram calculation result of pixel data. DETAILED DESCRIPTION

[0050] Reference is made to the following detailed description of the embodiments together with the attached Figure 1 The advantages and features of the present disclosure and the methods for achieving these advantages and features will become apparent. However, the present disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. However, this embodiment is provided to complete the present disclosure and to fully inform the scope of the invention to those of ordinary skill in the art to which the present disclosure belongs, and the present disclosure is limited only by the scope of the claims.

[0051] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the accompanying drawings for explaining the embodiments of the present disclosure are exemplary, and thus the present disclosure is not limited to the matters shown. The same reference numerals used herein refer to the same parts. In addition, when describing the present disclosure, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present disclosure, its detailed description will be omitted.

[0052] When terms such as "including", "having" and "comprising" are used herein, other parts may be added unless "only" is used. In the case of expressing a component in the singular, it includes the case of including the plural unless otherwise specifically stated.

[0053] When interpreting a part, interpret it as including a margin of error even if it is not explicitly described.

[0054] In the case of describing a positional relationship, for example, if the positional relationship of two parts is described using terms such as "on", "above", "below", or "beside", one or more other parts may be located between the two parts unless "just" or "directly" is used.

[0055] In the description of the embodiments, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical spirit of the present disclosure, the first component mentioned below may be the second component.

[0056] Like reference numerals used herein refer to like parts.

[0057] The features of the various embodiments may be coupled or combined with each other in part or in whole, and may be variously interlocked and driven technically, and the embodiments may be implemented independently of each other or together in an associated relationship.

[0058] In the display device of the present disclosure, the pixel circuit may include a plurality of transistors. The transistor may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor, a low temperature polysilicon (LTPS) TFT including LTPS, etc. Each of the transistors may be implemented as a p-channel TFT or an n-channel TFT.

[0059] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers flow from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage is lower than the drain voltage, so that electrons can flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor (PMOS), because the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0060] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, and the transistor is turned off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH / VEH, and the gate-off voltage may be a gate low voltage VGL / VEL. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage VGL / VEL, and the gate-off voltage may be a gate high voltage VGH / VEH.

[0061] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0062] Reference Figure 1 and Figure 2 The display panel 100 includes a screen for reproducing an input image. The screen may be divided into a first pixel area DA and a second pixel area CA having different resolutions.

[0063] Each of the first pixel area DA and the second pixel area CA includes a pixel array in which pixels to which pixel data of an input image is written are arranged. The second pixel area CA may be a pixel area having a resolution lower than that of the first pixel area DA. The pixel array of the first pixel area DA may include pixels arranged with a high pixel per inch (PPI). The pixel array of the second pixel area CA may include pixels arranged with a low PPI.

[0064] like Figure 2 As shown in FIG. 1 , one or more sensor modules SS1 and SS2 facing the second pixel area CA may be disposed at a lower portion of the display panel 100. For example, various sensors such as an imaging module including an image sensor, an infrared sensor module, and an illumination sensor module may be disposed at a lower portion of the first pixel area DA of the display panel 100. The second pixel area CA may include a light-transmitting portion to increase transmittance of light guided to the sensor module.

[0065] Since the first pixel area DA and the second pixel area CA include pixels, an input image may be displayed in the first pixel area DA and the second pixel area CA.

[0066] Each of the pixels in the first pixel area DA and the second pixel area CA includes sub-pixels having different colors to reproduce the colors in the image. The sub-pixels include a red sub-pixel (hereinafter referred to as an "R sub-pixel"), a green sub-pixel (hereinafter referred to as a "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as a "B sub-pixel"). Although not shown, each of the pixels may also include a white sub-pixel (hereinafter referred to as a "W sub-pixel"). Each of the sub-pixels may include a pixel circuit that drives a light-emitting element.

[0067] The image quality compensation algorithm for compensating the illumination and color coordinates of the pixels may be applied to the second pixel area CA having a lower PPI than that of the first pixel area DA.

[0068] In the display device of the present disclosure, since the pixels are arranged in the second pixel area CA where the sensor is arranged, the display area of ​​the screen is not limited by the imaging module such as the camera. Therefore, the display device of the present disclosure can realize a full-screen display.

[0069] The display panel 100 has a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 may include a circuit layer 12 disposed on a substrate 10 and a light emitting element layer 14 disposed on the circuit layer 12. A polarizing plate 18 may be disposed on the light emitting element layer 14, and an encapsulating glass 20 may be disposed on the polarizing plate 18.

[0070] The circuit layer 12 may include pixel circuits connected to wirings such as data lines, gate lines, and power lines, and gate drivers connected to the gate lines. The circuit layer 12 may include transistors implemented as thin film transistors (TFTs) and circuit elements such as capacitors. The wirings and circuit elements of the circuit layer 12 may be implemented with multiple insulating layers, two or more metal layers separated by insulating layers therebetween, and an active layer including a semiconductor material.

[0071] The light-emitting element layer 14 may include a light-emitting element driven by a pixel circuit. The light-emitting element may be implemented with an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL, but is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL move to the light-emitting layer EML to form excitons, and as a result, visible light is emitted from the light-emitting layer EML. The light-emitting element layer 14 may be disposed on pixels that selectively emit red wavelengths, green wavelengths, and blue wavelengths, and may also include a color filter array.

[0072] The light emitting element layer 14 may be covered by a passivation layer, and the passivation layer may be covered by an encapsulation layer. The passivation layer and the encapsulation layer may have a structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked into multiple layers, the movement path of moisture or oxygen becomes longer than the movement path in a single layer, thereby effectively blocking the penetration of moisture / oxygen that affects the light emitting element layer 14.

[0073] The polarizing plate 18 may be adhered to the encapsulation layer. The polarizing plate 18 improves the outdoor visibility of the display device. The polarizing plate 18 reduces the light reflected from the surface of the display panel 100 and blocks the light reflected from the metal of the circuit layer 12 to improve the brightness of the pixel. The polarizing plate 18 may be implemented as a polarizing plate in which a linear polarizing plate and a phase delay film are bonded, or as a circular polarizing plate.

[0074] Figure 3 is a diagram showing an example of pixel arrangement in the first pixel area DA. Figure 4 is a diagram showing an example of a light-transmitting portion and pixels in the second pixel area CA. Figure 3 and Figure 4 , the wiring connected to the pixels is omitted.

[0075] Reference Figure 3 , the first pixel area DA includes pixels PIX1 and PIX2 arranged with a high PPI. Each of the pixels PIX1 and PIX2 can be implemented as a real type pixel, in which an R sub-pixel, a G sub-pixel, and a B sub-pixel of three primary colors constitute one pixel. Each of the pixels PIX1 and PIX2 may also include a W sub-pixel omitted from the drawings.

[0076] Using the sub-pixel rendering algorithm, each pixel in the pixel can be composed of two sub-pixels. For example, the first pixel PIX1 can be composed of an R sub-pixel and a first G sub-pixel, and the second pixel PIX2 can be composed of a B sub-pixel and a second G sub-pixel. Insufficient color representation in each of the first pixel PIX1 and the second pixel PIX2 can be compensated by the average value of the corresponding color data between adjacent pixels.

[0077] The pixels in the first pixel area DA may be defined as unit pixel groups PG1 and PG2 having a predetermined size. The unit pixel groups PG1 and PG2 are pixel areas of a predetermined size including four sub-pixels. The unit pixel groups PG1 and PG2 are repeatedly arranged in a first direction (X axis), in a second direction (Y axis) perpendicular to the first direction, and in an inclined direction (θx axis and θy axis) between the first direction and the second direction. θx and θy respectively represent directions of inclined axes formed by rotating the X axis and the Y axis by 45°.

[0078] The unit pixel groups PG1 and PG2 may be a parallelogram-shaped pixel region PG1 or a rhombus-shaped pixel region PG2. The unit pixel groups PG1 and PG2 should be interpreted as including a rectangular shape, a square shape, or the like.

[0079] The sub-pixels of the unit pixel groups PG1 and PG2 include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, including two sub-pixels of any one of the first color sub-pixel to the third color sub-pixel. For example, the unit pixel groups PG1 and PG2 may include one R sub-pixel, two G sub-pixels, and one B sub-pixel. In the sub-pixels in the unit pixel groups PG1 and PG2, the luminous efficiency of the light-emitting element may be different for each color. In view of this, the size of the sub-pixel may vary for each color. For example, among the R sub-pixel, the G sub-pixel, and the B sub-pixel, the B sub-pixel may be the largest, and the G sub-pixel may be the smallest.

[0080] Reference Figure 4 , the second pixel area CA includes pixel groups PG spaced apart by a predetermined distance and a light-transmitting portion AG disposed between adjacent pixel groups PG. External light is received by the lens of the sensor module through the light-transmitting portion AG. The light-transmitting portion AG may include a transparent medium having a high transmittance without metal, so that light can be incident with minimal light loss. In other words, the light-transmitting portion AG may be formed of a transparent insulating material without including metal lines or pixels. Due to the light-transmitting portion AG, the PPI of the second pixel area CA is lower than the PPI of the first pixel area DA.

[0081] The pixel group PG of the second pixel area CA may include one or two pixels. Each pixel in the pixel group may include two to four sub-pixels. For example, one pixel in the pixel group may include an R sub-pixel, a G sub-pixel, and a B sub-pixel, or may include two sub-pixels and may further include a W sub-pixel. Figure 4 In the example, the first pixel PIX1 is composed of an R sub-pixel and a G sub-pixel, and the second pixel PIX2 is composed of a B sub-pixel and a G sub-pixel, but the present disclosure is not limited thereto.

[0082] exist Figure 4 , the shape of the light-transmitting portion AG is shown as a circle, but is not limited thereto. For example, the light-transmitting portion AG may be designed in various shapes such as a circle, an ellipse, and a polygon.

[0083] Due to process deviation and element characteristic deviation caused in the manufacturing process of the display panel, there may be differences in the electrical characteristics of the driving element between pixels, and this difference may increase as the driving time of the pixel passes. In order to compensate for the deviation of the electrical characteristics of the driving element between pixels, an internal compensation technology or an external compensation technology may be applied to the organic light emitting display device.

[0084] The internal compensation technology senses the threshold voltage of the driving element of each sub-pixel by using an internal compensation circuit implemented in each pixel circuit, and compensates the gate-source voltage Vgs of the driving element by the threshold voltage. The external compensation technology senses the current or voltage of the driving element in real time by using an external compensation circuit, which changes according to the electrical characteristics of the driving element. The external compensation technology modulates the pixel data (digital data) of the input image with almost the same deviation (or change) of the electrical characteristics of the driving element sensed for each pixel, thereby compensating the deviation (or change) of the electrical characteristics of the driving element in each pixel in real time.

[0085] Figures 5 to 7 is a circuit diagram showing various pixel circuits suitable for use with the present disclosure.

[0086] Reference Figure 5 The pixel circuit includes a light emitting element OLED, a driving element DT for supplying current to the light emitting element OLED, a switching element M01 for connecting the data line DL in response to a scan pulse SCAN, and a capacitor Cst connected to the gate of the driving element DT. The driving element DT and the switching element M01 may be implemented with n-channel transistors.

[0087] The pixel driving voltage ELVDD is applied to the first electrode of the driving element DT through the power line PL. The driving element DT drives the light emitting element OLED by providing a current to the light emitting element OLED according to the gate-source voltage Vgs. When the forward voltage between the anode electrode and the cathode electrode is greater than or equal to the threshold voltage, the light emitting element OLED is turned on and emits light. The capacitor Cst is connected between the gate electrode and the source electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0088] Figure 6 is an example of a pixel circuit connected to an external compensation circuit.

[0089] Reference Figure 6 The pixel circuit further includes a second switch element M02 connected between the reference voltage line REFL and the second electrode (or source) of the driving element DT. In the pixel circuit, the driving element DT and the switch elements M01 and M02 may be implemented as n-channel transistors.

[0090] The second switching element M02 applies a reference voltage Vref in response to a scan pulse SCAN or a separate sensing pulse SENSE. The reference voltage VREF is applied to the pixel circuit through a reference voltage line REFL.

[0091] In the sensing mode, the current flowing through the channel of the driving element DT or the voltage between the driving element DT and the light-emitting element OLED is sensed by the reference line REFL. The current flowing through the reference line REFL is converted into a voltage by an integrator and converted into digital data by an analog-to-digital converter (ADC). The digital data is sensing data including information about the threshold voltage or mobility of the driving element DT. The sensing data is transmitted to the data operation unit. The data operation unit can receive the sensing data from the ADC and add or multiply the compensation value selected based on the sensing data to the pixel data to compensate for the driving deviation and degradation of the pixel.

[0092] Figure 7 is a circuit diagram showing an example of a pixel circuit to which an internal compensation circuit is applied. Figure 8 Is shown driving Figure 7 2 is a waveform diagram of the method of the pixel circuit shown in FIG.

[0093] Reference Figure 7 and Figure 8 The pixel circuit includes a light emitting element OLED, a driving element DT for supplying current to the light emitting element OLED, and a switching circuit for switching voltages applied to the light emitting element OLED and the driving element DT.

[0094] The switching circuit is connected to the power lines PL1, PL2 and PL3, the data line DL and the gate lines GL1, GL2 and GL3 to which the pixel driving voltage ELVDD, the low potential power supply voltage ELVSS and the initialization voltage Vini are applied, and switches the voltage applied to the light emitting element OLED and the driving element DT in response to the scanning pulses SCAN(N-1) and SCAN(N) and the light emitting pulse (EM pulse) EM(N).

[0095] The switching circuit includes an internal compensation circuit that samples a threshold voltage Vth of the driving element DT using a plurality of switching elements M1 to M6 to store the threshold voltage in a capacitor Cst1 and compensates a gate voltage of the driving element DT by the threshold voltage Vth of the driving element DT. Each of the driving element DT and the switching elements M1 to M6 may be implemented with a p-channel TFT.

[0096] like Figure 8 As shown in , the driving period of the pixel circuit can be divided into an initialization period Tini, a sampling period Tsam, and a light emission period Tem.

[0097] The N-th scan pulse SCAN(N) is generated as the gate-on voltage VGL during the sampling period Tsam and is applied to the first gate line GL1. The (N-1)-th scan pulse SCAN(N-1) is generated as the gate-on voltage VGL during the initialization period Tini before the sampling period and is applied to the second gate line GL2. The EM pulse EM(N) is generated as the gate-off voltage VGH during the initialization period Tini and the sampling period Tsam and is applied to the third gate line GL3.

[0098] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated as the gate-on voltage VGL, and the voltage of each of the Nth scan pulse SCAN(N) and the EM pulse EM(N) is the gate-off voltage VGH. During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as a pulse of the gate-on voltage VGL, and the voltage of each of the (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) is the gate-off voltage VGH. During at least a portion of the light emission period Tem, the EM pulse EM(N) is generated as the gate-on voltage VGL, and the voltage of each of the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) is the gate-off voltage VGH.

[0099] During the initialization period Tini, the fifth switching element M5 is turned on in response to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to initialize the pixel circuit. During the sampling period Tsam, the first switching element M1 and the second switching element M2 are turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N), so that the data voltage Vdata compensated by the threshold voltage of the driving element DT is stored in the capacitor Cst1. At the same time, the sixth switching element M6 is turned on during the sampling period Tsam to reduce the voltage of the fourth node n4 to the reference voltage Vref, thereby suppressing the light emission of the light emitting element OLED.

[0100] During the light emission period Tem, the third switching element M3 and the fourth switching element M4 are turned on, so that the light emitting element OLED emits light. During the light emission period Tem, in order to accurately represent the illumination of low grayscale, the voltage level of the EM pulse EM(N) can be reversed between the gate-on voltage VGL and the gate-off voltage VGH at a predetermined duty cycle. In this case, the third switching element M3 and the fourth switching element M4 can be repeatedly turned on / off at the duty cycle of the EM pulse EM(N) during the light emission period Tem.

[0101] The anode electrode of the light emitting element OLED is connected to the fourth node n4 between the fourth switching element M4 and the sixth switching element M6. The fourth node n4 is connected to the anode of the light emitting element OLED, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode electrode of the light emitting element OLED is connected to the VSS line PL3 to which the low potential power supply voltage ELVSS is applied. The light emitting element OLED emits light by the current Ids flowing according to the gate-source voltage Vgs of the driving element DT. The current path of the light emitting element OLED is switched by the third switching element M3 and the fourth switching element M4.

[0102] The capacitor Cst1 is connected between the VDD line PL1 and the second node n2. The data voltage Vdata compensated by the threshold voltage Vth of the driving element DT is charged into the capacitor Cst1. Since the data voltage Vdata is compensated by the threshold voltage Vth of the driving element DT in each sub-pixel, the deviation of the electrical characteristics of the driving element DT is compensated in the sub-pixel.

[0103] The first switch element M1 is turned on in response to the gate-on voltage VGL of the N-th scan pulse SCAN(N) to connect the second node n2 to the third node n3. The second node n2 is connected to the gate electrode of the driving element DT, the first electrode of the capacitor Cst1, and the first electrode of the first switch element M1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switch element M1, and the first electrode of the fourth switch element M4. The gate electrode of the first switch element M1 is connected to the first gate line GL1 to receive the N-th scan pulse SCAN(N). The first electrode of the first switch element M1 is connected to the second node n2, and the second electrode of the first switch element M1 is connected to the third node n3.

[0104] Since the first switching element M1 is turned on only in a very short horizontal period 1H, in which the Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL in one frame period, leakage current may occur in the off state. In order to suppress the leakage current in the first switching element M1, the first switching element M1 may be implemented with a transistor having a dual-gate structure in which two transistors are connected in series.

[0105] The second switching element M2 is turned on in response to the gate-on voltage VGL of the N-th scan pulse SCAN(N) to provide the data voltage Vdata to the first node n1. The gate electrode of the second switching element M2 is connected to the first gate line GL1 to receive the N-th scan pulse SCAN(N). The first electrode of the second switching element M2 is connected to the first node n1. The second electrode of the second switching element M2 is connected to the data line DL to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the second switching element M2, the second electrode of the third switching element M3, and the first electrode of the driving element DT.

[0106] The third switch element M3 is turned on in response to the gate-on voltage VGL of the EM pulse EM(N) to connect the VDD line PL1 to the first node n1. The gate electrode of the third switch element M3 is connected to the third gate line GL3 to receive the EM pulse EM(N). The first electrode of the third switch element M3 is connected to the VDD line PL1. The second electrode of the third switch element M3 is connected to the first node n1.

[0107] The fourth switch element M4 is turned on in response to the gate-on voltage VGL of the EM pulse EM(N) to connect the third node n3 to the anode electrode of the light emitting element OLED. The gate electrode of the fourth switch element M4 is connected to the third gate line GL3 to receive the EM pulse EM(N). The first electrode of the fourth switch element M4 is connected to the third node n3, and the second electrode thereof is connected to the fourth node n4.

[0108] The fifth switch element M5 is turned on in response to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to connect the second node n2 to the Vini line PL2. The gate electrode of the fifth switch element M5 is connected to the second gate line GL2 to receive the (N-1)th scan pulse SCAN(N-1). The first electrode of the fifth switch element M5 is connected to the second node n2, and the second electrode thereof is connected to the Vini line PL2. In order to suppress leakage current in the fifth switch element M5, the fifth switch element M5 is implemented using a transistor having a dual-gate structure in which two transistors are connected in series.

[0109] The sixth switching element M6 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. The gate electrode of the sixth switching element M6 is connected to the first gate line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the sixth switching element M6 is connected to the Vini line PL2, and the second electrode thereof is connected to the fourth node n4.

[0110] In another embodiment, the gate electrodes of the fifth switching element M5 and the sixth switching element M6 may be commonly connected to the second gate line GL2 to which the (N-1)th scan pulse SCAN(N-1) is applied. In this case, the fifth switching element M5 and the sixth switching element M6 may be simultaneously turned on in response to the (N-1)th scan pulse SCAN(N-1).

[0111] The driving element DT drives the light emitting element OLED by controlling a current flowing through the light emitting element OLED according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0112] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated as the gate-on voltage VGL. The Nth scan pulse SCAN(N) and the EM pulse EM(N) maintain the gate-off voltage VGH during the initialization period Tini. Therefore, during the initialization period Tini, the fifth switching element M5 is turned on, so that the second node n2 and the fourth node n4 are initialized to Vini. A holding period may be set between the initialization period Tini and the sampling period Tsam. During the holding period, the scan pulses SCAN(N-1) and SCAN(N) and the EM pulse EM(N) are the gate-off voltage.

[0113] During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL. The pulse of the Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata of the Nth pixel line. The (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) maintain the gate-off voltage VGH during the sampling period Tsam. Therefore, the first switching element M1 and the second switching element M2 are turned on during the sampling period Tsam.

[0114] During the sampling period Tsam, the gate voltage DTG of the driving element DT rises due to the current flowing through the first switching element M1 and the second switching element M2. When the driving element DT is turned off, the gate voltage DTG is Vdata-|Vth|. In this case, the voltage of the first node n1 is also Vdata-|Vth|. During the sampling period Tsam, the gate-source voltage Vgs of the driving element DT is expressed as |Vgs|=Vdata-(Vdata-|Vth|)=|Vth|.

[0115] During the light emission period Tem, the EM pulse EM(N) may be generated as the gate-on voltage VGL. During the light emission period Tem, the voltage of the EM pulse EM(N) may be reversed at a predetermined duty cycle. Therefore, during at least a portion of the light emission period Tem, the EM pulse EM(N) may be generated as the gate-on voltage VGL.

[0116] When the EM pulse EM(N) is the gate-on voltage VGL, current flows between ELVDD and the light-emitting element OLED, so that the light-emitting element OLED can emit light. During the light emission period Tem, the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) maintain the gate-off voltage VGH. During the light emission period Tem, the third switching element M3 and the fourth switching element M4 are turned on according to the gate-on voltage of the EM pulse EM(N). When the EM pulse EM(N) is the gate-on voltage VGL, the third switching element M3 and the fourth switching element M4 are turned on, so that current flows through the light-emitting element OLED. At this time, the Vgs of the driving element DT is expressed as |Vgs|=VDD-(Vdata-|Vth|), and the current flowing through the light-emitting element OLED is K(VDD-Vdata) 2 K is a constant value determined by the charge mobility, parasitic capacitance, channel capacity, etc. of the driving element DT.

[0117] Fig. 9 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0118] Reference Fig. 9 According to an embodiment of the present disclosure, a display device includes: a display panel 100 and display panel drivers 110 and 120 for writing pixel data of an input image into pixels P of the display panel 100; a timing controller 130 for controlling the display panel driver; and a power supply unit 150 for generating power required to drive the display panel 100.

[0119] The display panel 100 includes a pixel array that displays an input image on a screen. As described above, the pixel array may be divided into a first pixel area DA and a second pixel area CA, the second pixel area CA having a resolution or PPI lower than that of the first pixel area DA. Since the first pixel area DA includes pixels P with high resolution and high PPI and is therefore larger in size than the second pixel area CA, most of the image information is displayed on the first pixel area DA. Each of the sub-pixels of the pixel array may be displayed by using a pixel array such as Figures 5 to 7 The pixel circuit in the device is used to drive the light-emitting element OLED.

[0120] The touch sensor may be provided on the screen of the display panel 100. The touch sensor may be provided on the screen of the display panel in an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor incorporated in a pixel array.

[0121] The display panel 100 may be implemented as a flexible display panel in which pixels P are arranged on a flexible substrate such as a plastic substrate or a metal substrate. In a flexible display, the size and shape of the screen may be changed by rolling, folding or bending the flexible display panel. The flexible display may include a slidable display, a rollable display, a bendable display, a foldable display, etc.

[0122] The display panel driver may drive the pixels P by applying an internal compensation technique and / or an external compensation technique.

[0123] The display panel driver reproduces an input image on the screen of the display panel 100 by writing pixel data of the input image into sub-pixels. The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer 112 disposed between the data driver 110 and the data lines DL.

[0124] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. In the low-speed drive mode, the input image is analyzed, and when the input image does not change within a preset time period, the power consumption of the display device can be reduced. In the low-speed drive mode, when a still image is input for a specific time period or longer, the refresh rate of the pixel P is reduced to control the data write period of the pixel P to be longer, thereby reducing power consumption. The low-speed drive mode is not limited to when a still image is input. For example, when the display device is operating in a standby mode, or when a user command or an input image is not input to the display panel drive circuit for a predetermined time period or longer, the display panel drive circuit can operate in a low-speed drive mode.

[0125] The data driver 110 converts the pixel data of the input image as digital data into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as a "DAC") to generate a data voltage Vdata. The data driver 110 may include a voltage divider circuit that outputs the gamma compensation voltage. The voltage divider circuit divides the gamma reference voltage from the power supply unit 150 to generate a gamma compensation voltage for each grayscale, and provides the generated gamma compensation voltage to the DAC. The DAC may convert the pixel data or the compensation data into a gamma compensation voltage, and output the data voltage and the compensation voltage. The data voltage output from the channel of the data driver 110 may be provided to the data line DL of the display panel 100 through the demultiplexer 112.

[0126] The demultiplexer 112 distributes the data voltage Vdata output through the channels of the data driver 110 to the plurality of data lines DL in a time division manner. The number of channels of the data driver 110 can be reduced due to the demultiplexer 112. The demultiplexer 112 can be omitted. In this case, the channels of the data driver 110 are directly connected to the data lines DL.

[0127] The gate driver 120 may be implemented in a gate-in-panel (GIP) circuit directly formed on the bezel region BZ of the display panel 100 together with the TFT array of the pixel array. The gate driver 120 outputs a gate signal to the gate line GL under the control of the timing controller 130. The gate driver 120 may shift the gate signal using a shift register to sequentially provide the signal to the gate line GL. The voltage of the gate signal swings between a gate-off voltage VGH and a gate-on voltage VGL. The gate signal may include Figures 5 to 7 The scan pulses, EM pulses, sensing pulses, etc. are shown.

[0128] The gate driver 120 may be disposed on each of the left and right frames of the display panel 100 so as to provide a gate signal to the gate line GL in a dual feeding method. In the dual feeding method, the gate drivers 120 on both sides are synchronized so that the gate signal can be applied to both ends of one gate line at the same time. In another embodiment, the gate driver 120 may be disposed on one of the left and right frames of the display panel 100 so as to provide a gate signal to the gate line GL in a single feeding method.

[0129] The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs a scan pulse and a sensing pulse, and shifts the scan pulse and the sensing pulse according to a shift clock. The second gate driver 122 outputs a pulse of an EM signal, and shifts the EM pulse according to a shift clock. In the case of a model without a frame, at least some of the switching elements constituting the first gate driver 121 and the second gate driver 122 may be distributedly arranged in a pixel array.

[0130] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from a host system. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, and the like. One period of the vertical synchronization signal Vsync is a frame period. One period of the horizontal synchronization signal Hsync and the data enable signal DE is a horizontal period 1H. The pulse of the data enable signal DE is synchronized with a row of data of a pixel P to be written into a pixel line. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0131] The timing controller 130 transmits the pixel data of the input image to the data driver 120 and synchronizes the data driver 110, the demultiplexer 112, and the gate driver 120. The timing controller 130 may include a data operation unit that receives the sensing data obtained from the pixel P from the display panel driver to which the external compensation technology is applied and modulates the pixel data. In this case, the timing controller 130 transmits the pixel data modulated by the data operation unit to the data driver 110.

[0132] The timing controller 130 may multiply the input frame frequency by i (i is a positive integer greater than 0) to control the operation timing of the display panel drivers 110, 112, and 120 at a frame frequency of the input frame frequency×i Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system, and 50 Hz in the Phase-Alternating Line (PAL) system. The timing controller 130 may reduce the frame frequency to a frequency between 1 Hz and 30 Hz so as to reduce the refresh rate of the pixel P in the low-speed driving mode.

[0133] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a switch control signal for controlling the operation timing of the demultiplexer 112, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync and DE received from the host system.

[0134] The gate timing control signal may include a start pulse, a shift clock, etc. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-off voltage VGH / VEH or a gate-on voltage VGL / VEL by a level converter omitted in the figure, and may be provided to the gate driver 120. The level converter may convert a low-level voltage of the gate timing control signal into a gate-on voltage VGL, and may convert a high-level voltage of the gate timing control signal into a gate-off voltage VGH.

[0135] The power supply unit 150 may include a charge pump, a regulator, a buck converter, a boost converter, a programmable gamma IC (P-GMA IC), etc. The power supply unit 150 generates the power required to drive the display panel driver and the display panel 100 by adjusting the DC (direct current) input voltage from the host system. The power supply unit 150 can output DC voltages such as a gamma reference voltage, a gate cut-off voltage VGH / VEH, a gate-on voltage VGL / VEL, a pixel driving voltage ELVDD, a low potential power supply voltage ELVSS, an initialization voltage Vini, and a reference voltage VREF. The programmable gamma IC can change the gamma reference voltage according to the register setting value. The gamma reference voltage is provided to the data driver 110. The gate cut-off voltage VGH / VEH and the gate-on voltage VGL / VEL are provided to the level converter and the gate driver 120. The pixel driving voltage ELVDD, the low potential power supply voltage ELVSS, the initialization voltage Vini, and the reference voltage VREF are provided to the pixel circuit through the power line. The pixel driving voltage ELVDD is set to a voltage higher than the low potential power voltage ELVSS, the initialization voltage Vini, and the reference voltage VREF.

[0136] The host system can be a main circuit board of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a home theater system, a mobile device, or a wearable device. Fig.10 As shown, the timing controller 130, the data driver 110 and the power supply unit 150 may be integrated into one driver integrated circuit (D-IC). Fig.10 , reference numeral '200' denotes a host system.

[0137] like Fig.11 and Fig.12 As shown, the data voltage Vdata output from the data driver 110 is determined to be at the minimum grayscale voltage V 0 With the maximum grayscale voltage V 255 The gamma compensation voltage corresponding to the grayscale of the pixel data is within the data voltage range between . The minimum grayscale voltage V 0 is the black grayscale voltage corresponding to the grayscale value 0, and the maximum grayscale voltage V 255 is a white grayscale voltage corresponding to a grayscale value of 255. The output voltage range of the data driver 110 is greater than the data voltage range. Therefore, the data driver 110 can adjust the data voltage Vdata within the voltage margin Vm for optical compensation or to compensate for degradation of the driving element DT or the light emitting element OLED. In the data voltage applied to the gate electrode of the driving element DT implemented as a p-channel transistor, as shown in FIG. Fig.11 and Fig.12 As shown, the high gray voltage is set to a voltage lower than the low gray voltage. Among the data voltages applied to the gate electrode of the driving element DT implemented as an n-channel transistor, the high gray voltage is set to a voltage higher than the low gray voltage.

[0138] The PPI of the second pixel area CA is lower than the PPI of the first pixel area DA. Fig.11 As shown, if the data voltage Vdata applied to the pixel P of the second pixel area CA is equal to the data voltage Vdata applied to the pixel P of the first pixel area DA under the same grayscale, the illuminance L2 of the second pixel area CA is lower than the illuminance L1 of the first pixel area DA. Therefore, a illuminance difference between the first pixel area DA and the second pixel area CA may be caused, so that the illuminance difference may be visually recognized for each area on the screen of the display device.

[0139] exist Fig.12 In the figure, "Vrange (D-IC output)" is an output voltage range between a minimum voltage and a maximum voltage output from the data driver 110. A voltage margin Vm may be ensured within the voltage range of the data driver 110 for optical compensation, for compensating for illumination deviation between pixels P, and for compensating for a threshold voltage shift of a transistor with the lapse of driving time.

[0140] In order to compensate for the illumination difference between the first pixel area DA and the second pixel area CA, the data voltage Vdata applied to the pixel P in the second pixel area CA under high illumination may be set to a higher voltage ( Vdata = 1.0 V) than the data voltage Vdata applied to the pixel P in the first pixel area DA. Fig.12 is the lower voltage). Fig.12As shown, when the data voltage range of the pixel P applied to the second pixel area CA is extended to Vdata+Vdata', the voltage margin Vm is reduced by the extension amount within the output voltage range Vrange (D-IC output), making it difficult to ensure the voltage for optical compensation and unable to cope with the degradation of the transistor as the driving time passes.

[0141] The data voltage Vdata is determined according to the gamma compensation voltage. Therefore, in order to expand the data voltage range, it is necessary to increase the output voltage of the programmable gamma IC within the output voltage range of the data driver 110.

[0142] In the present disclosure, the driving element DT is implemented in a dual-gate structure in each sub-pixel, and the compensation voltage Vdata' is applied to the second gate electrode of the driving element DT in the second pixel area. Since the compensation voltage Vdata' cannot further improve the illumination of the pixel using only the limited data voltage Vdata, the amount of current flowing through the driving element DT can be increased to further improve the illumination of the pixel. Therefore, in the present disclosure, the compensation voltage Vdata' is applied to the second gate electrode of the driving element set in the second pixel area CA, thereby compensating for the illumination difference between the first pixel area DA and the second pixel area CA without expanding the data voltage range of the data driver 110, and achieving uniform illumination across the entire screen.

[0143] The present disclosure includes an illumination compensation unit for compensating the illumination of the second pixel area CA by outputting a compensation voltage Vdata′. The power supply unit 150 or the data driver 110 may include the illumination compensation unit.

[0144] Fig.13 is a circuit diagram showing a driving element having a dual gate structure according to a first embodiment of the present disclosure. Fig.14 is a cross-sectional view illustrating a cross-sectional structure of a first driving element DT1 disposed in the first pixel area DA. Fig.15 is a cross-sectional view showing a cross-sectional structure of a second driving element DT2 disposed in the second pixel area CA. Each sub-pixel in the first pixel area DA may include Fig.13 and Fig.14 Each sub-pixel in the second pixel area CA may include Fig.13 and Fig.15 The second driving element DT2 is shown.

[0145] Reference Figures 13 to 15 The driving elements DT1 and DT2 in the first pixel area DA and the second pixel area CA may be implemented as transistors having a double gate structure having a first gate electrode and a second gate electrode.

[0146] The first driving element DT1 disposed in the first pixel area DA includes a first gate electrode GE1 to which a data voltage Vdata is applied and a second gate electrode GE2 to which a DC voltage such as a pixel driving voltage ELVDD is applied. Fig.14 As shown, the second gate electrode GE2 is disposed in the lower portion of the first driving element DT1 and overlaps with the first gate electrode GE1, wherein the semiconductor channel ACT and the insulating layers BUF and GI are interposed between the first gate electrode GE1 and the second gate electrode GE2. The second gate electrode GE2 also serves as a light shielding layer to block external light so that the light does not irradiate the semiconductor channel ACT of the first driving element DT1. In addition, a DC voltage such as a pixel driving voltage ELVDD is applied to the second gate electrode GE2 of the first driving element DT1 to shield ions affecting the semiconductor channel ACT of the driving element DT, thereby suppressing changes in the threshold voltage Vth of the driving element DT.

[0147] Reference Fig.14 , the first driving element DT1 includes a second gate electrode GE2 disposed on a substrate SUBS, a semiconductor channel ACT formed on a buffer layer BUF, a first electrode SE connected to a source region of the semiconductor channel ACT, a second electrode DE connected to a drain region of the semiconductor channel ACT, and a first gate electrode GE1 overlapping the semiconductor channel ACT and the second gate electrode GE2 on a gate insulating layer GI. The buffer layer BUF is an insulating layer disposed on the substrate SUBS to cover the second gate electrode GE2. The gate insulating layer GI is an insulating layer disposed on the buffer layer BUF to cover the semiconductor channel ACT and the first electrode SE and the second electrode DE.

[0148] The power line PL may be disposed on the buffer layer BUF. A DC voltage such as a pixel driving voltage ELVDD may be applied to the power line PL. The power line PL may be applied to the second gate electrode GE2 of the first driving element DT1 through a first contact hole CH1 penetrating the buffer layer BUF.

[0149] The data voltage Vdata is Figure 5 and Figure 6 The first switching element M01 in the pixel circuit shown is applied to the first gate electrode GE1 of the driving element DT1, DT2. Figure 7 In the case of the pixel circuit shown, the data voltage Vdata is applied to the first gate electrode GE1 of the driving elements DT1 and DT2 through the second switching element M2, the first and second electrodes of the driving elements DT1 and DT2, and the first switching element M1.

[0150] The second driving element DT2 disposed in the second pixel area CA includes a first gate electrode GE1 to which a data voltage Vdata is applied and a second gate electrode GE2 to which a compensation voltage Vdata' is applied. The compensation voltage Vdata' increases the mobility of carriers flowing through the semiconductor channel ACT of the second driving element DT2 to increase the brightness of the light emitting element OLED, thereby increasing the illumination of the second pixel area CA. The compensation voltage Vdata' may be a specific voltage selected as a voltage for increasing the illumination of the second pixel area CA, or a voltage that varies according to the illumination characteristics of the second pixel area CA or the grayscale of the pixel data.

[0151] The compensation voltage Vdata' may vary according to the illuminance characteristics and grayscale distribution characteristics of the input image. For example, based on the analysis result of the input image, as the average illuminance of the image to be displayed in the second pixel area CA increases, the timing controller 130 may control the illuminance compensation unit to increase the grayscale value of the compensation voltage Vdata' to further increase the illuminance of the pixel, and as the average illuminance of the second image decreases, the timing controller 130 may control the illuminance compensation unit to reduce the grayscale value of the compensation voltage Vdata'. In addition, as the pixel data having a high grayscale value in the grayscale distribution of the pixel data to be displayed in the second pixel area CA increases, the timing controller 130 may control the illuminance compensation unit to increase the grayscale value of the compensation voltage Vdata', and as the pixel data having a low grayscale value increases, the timing controller 130 may control the illuminance compensation unit to reduce the grayscale value of the compensation voltage Vdata'.

[0152] The compensation voltage Vdata' may be a specific voltage selected from the voltages output by the programmable gamma IC of the power supply unit 150. In this case, the compensation voltage Vdata' may be set to a voltage independent of the output voltage range Vrange (D-IC output) of the data driver 110 or the data voltage range.

[0153] The compensation voltage Vdata' may be output from the data driver 110. In this case, the voltage range of the compensation voltage Vdata' may be smaller than the data voltage range set within the output voltage range Vrange (D-IC output) of the data driver 110. For example, when the data voltage range of the data voltage Vdata is 0V to 5V, the voltage range of the compensation voltage Vdata' may be set to 0V to 3V.

[0154] The timing controller 130 may generate compensation data having a grayscale value selected based on a result of analyzing the luminance characteristic of the input image or the grayscale characteristic of the pixels in the second pixel area CA. The data driver 110 may convert the compensation data received as digital data into a gamma compensation voltage and output the compensation voltage Vdata'. In this case, the compensation voltage Vdata' may be adaptively changed according to the luminance characteristic and / or the grayscale distribution characteristic of the input image.

[0155] In the second driving element DT2, as Fig.15 As shown, the second gate electrode GE2 is disposed in the lower portion of the second driving element DT2 and overlaps with the first gate electrode GE1, wherein the semiconductor channel ACT and the insulating layers BUF and GI are interposed between the first gate electrode GE1 and the second gate electrode GE2. The second gate electrode GE2 increases the carrier mobility of the second driving element DT2 to improve the illumination of the second pixel area CA, and also serves as a light shielding layer to block external light so that the light does not irradiate the semiconductor channel ACT of the second driving element DT2.

[0156] Reference Fig.15 The second driving element DT2 includes a second gate electrode GE2 arranged on the substrate SUBS, a semiconductor channel ACT formed on the buffer layer BUF, a first electrode SE connected to the source region of the semiconductor channel ACT, a second electrode DE connected to the drain region of the semiconductor channel ACT, and a first gate electrode GE1 overlapping the semiconductor channel ACT and the second gate electrode GE2 on the gate insulating layer GI.

[0157] The power line PL may be disposed on the buffer layer BUF. The auxiliary data line DL' to which the compensation voltage Vdata' is applied may be disposed on the buffer layer BUF. The auxiliary data line DL' may be connected to the second gate electrode GE2 of the second driving element DT2 through the second contact hole CH2 penetrating the buffer layer BUF.

[0158] Figures 13 to 15 The driver elements DT1 and DT2 shown can be applied to Figures 5 to 7 The pixel circuit shown. Fig.16 It shows that Fig.13 The first drive element shown is applied to Figure 7 A circuit diagram of an example of a pixel circuit is shown. Fig.17 It shows that Fig.13 The second drive element shown is applied to Figure 7 A circuit diagram of an example of a pixel circuit is shown.

[0159] like Fig.16As shown, in the sub-pixels PIX1 to PIXn of the first pixel area DA, the pixel driving voltage ELVDD may be applied to the second gate electrode of the driving element DT1. The pixel driving voltage ELVDD may be commonly applied to all driving elements DT1 in the first pixel area DA through the power line PL.

[0160] like Fig.17 As shown, in the sub-pixels PIX1 to PIXm of the second pixel area CA, the compensation voltage Vdata' may be applied to the second gate electrode of the driving element DT2. The compensation voltage Vdata' may be commonly applied to all driving elements DT2 in the second pixel area CA through the auxiliary data line DL'.

[0161] exist Fig.16 In the example of , the first driving elements DT1 are commonly connected to the power line PL, so that the second gate electrodes GE2 of the first driving elements DT1 are grouped together to receive the same DC voltage. Fig.17 In the example of , the second driving elements DT2 are commonly connected to the auxiliary data line DL', so that the second gate electrodes GE2 of the second driving elements DT2 are grouped together to receive the same voltage. Fig.16 and Fig.17 As shown, the second gate electrodes of the driving elements are grouped together for each region, but the present disclosure is not limited thereto. For example, in the second pixel region CA, the auxiliary data line DL' may be divided into two or more lines and may be separated for each color of the sub-pixel.

[0162] Fig.18 is a circuit diagram schematically showing a dual gate structure of a driving element according to a second embodiment of the present disclosure. Fig.19 It is shown Fig.18 FIG. 2 is a cross-sectional view of the cross-sectional structure of the second driving element DT2 and the switching element MS. Fig.18 and Fig.19 In, with Fig.21 Substantially the same components of the illustrated embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0163] Reference Fig.18 and Fig.19 , a DC voltage such as the pixel driving voltage ELVDD may be applied to the second gate electrode GE2 of the first driving element DT1 through the first contact hole CH1.

[0164] The data voltage Vdata is Figure 5 and Figure 6 The first switching element M01 in the pixel circuit shown is applied to the first gate electrode GE1 of the driving element DT1, DT2. Figure 7In the case of the pixel circuit shown, the data voltage Vdata is applied to the first gate electrode GE1 of the driving elements DT1 and DT2 through the second switching element M2, the first and second electrodes of the driving elements DT1 and DT2, and the first switching element M1.

[0165] Each sub-pixel in the second pixel area CA further includes a switching element MS for switching the compensation voltage Vdata' applied to the second gate electrode GE2 of the second driving element DT2. The switching element MS is turned on in response to a pulse of the selection signal SEL. When the switching element MS is turned on, the data line DL is connected to the second gate electrode GE2 of the second driving element DT2, so that the compensation voltage Vdata is applied to the second gate electrode GE2. Under the control of the timing controller 130, the gate driver 120 may output a pulse of the selection signal SEL to provide the selection signal SEL to the gate line connected to the gate electrode of the switching element MS.

[0166] exist Fig.18 and Fig.19 In the example of , the switch element MS is connected to the data line DL to apply the data voltage Vdata as the compensation voltage Vdata' to the second gate electrode GE2 of the second driving element DT2, but the present disclosure is not limited thereto. For example, the switch element MS may be connected to the auxiliary data line DL' to which the compensation voltage Vdata' is applied from the power supply unit 150 or the data driver 110, so that the compensation voltage Vdata' from the auxiliary data line DL' may be applied to the second gate electrode GE2 of the second driving element DT2. Therefore, the compensation voltage Vdata' may be the same as the data voltage Vdata, or may be a specific voltage or a variable voltage.

[0167] Reference Fig.19 , the second driving element DT2 includes a second gate electrode GE2 disposed on the substrate SUBS, a semiconductor channel ACT formed on the buffer layer BUF, a first electrode SE connected to a source region of the semiconductor channel ACT, a second electrode DE connected to a drain region of the semiconductor channel ACT, and a first gate electrode GE1 overlapping the semiconductor channel ACT and the second gate electrode GE2 on the first gate insulating layer GI1. The buffer layer BUF is an insulating layer disposed on the substrate SUBS to cover the second gate electrode GE2. The first gate insulating layer GI1 is an insulating layer disposed on the buffer layer BUF to cover the semiconductor channel ACT and the first electrode SE and the second electrode DE.

[0168] The switching element MS includes a semiconductor channel ACT disposed on a first gate insulating layer GI1, a first electrode SE connected to a source region of the semiconductor channel ACT, a second electrode DE connected to a drain region of the semiconductor channel ACT, and a gate electrode GE overlapping the semiconductor channel ACT on a second gate insulating layer GI2. The second gate insulating layer GI2 is an insulating layer disposed on the first gate insulating layer GI1 to cover the first gate electrode GE1 of the driving element DT2, the semiconductor channel ACT of the switching element MS, and the first electrode SE and the second electrode DE.

[0169] The data line DL may be connected to the second electrode DE of the switching element MS through a third contact hole CH3 penetrating the second gate insulating layer GI2. The first electrode SE of the switching element MS is connected to the auxiliary data line DL' through a fourth contact hole CH4 penetrating the first gate insulating layer GI1. The auxiliary data line DL' is connected to the second gate electrode GE2 of the driving element DT2 through a fifth contact hole CH5 penetrating the buffer layer BUF.

[0170] The data voltage Vdata is Figure 5 and Figure 6 The first switching element M01 in the pixel circuit shown is applied to the first gate electrode GE1 of the driving element DT1, DT2. Figure 7 In the case of the pixel circuit shown, the data voltage Vdata is applied to the first gate electrode GE1 of the driving elements DT1 and DT2 through the second switching element M2, the first and second electrodes of the driving elements DT1 and DT2, and the first switching element M1.

[0171] Fig.18 and Fig.19 The driver elements DT1 and DT2 shown can be applied to Figures 5 to 7 The pixel circuit shown. Fig. 20 It shows that Fig.18 The second driving element DT2 shown is applied to Figure 7 A circuit diagram of an example of a pixel circuit is shown.

[0172] like Fig.16 As shown, a DC voltage such as a pixel driving voltage ELVDD may be applied to the second gate electrode of the driving element DT1 disposed in the sub-pixels PIX1 to PIXn of the first pixel area DA.

[0173] In the sub-pixels PIX1 to PIXm of the second pixel area CA, as shown in FIG. Fig. 20As shown, the compensation voltage Vdata' can be applied to the second gate electrode of the driving element DT2 through the seventh switching element M7. The seventh switching element M7 includes a gate electrode connected to the gate line to which the selection signal SEL is applied, a first electrode connected to the data line DL, and a second electrode connected to the second gate electrode GE2 of the driving element DT2.

[0174] Fig.21 1 is a plan view showing the power lines PL and the auxiliary data lines DL′ on the display panel 100 .

[0175] Reference Fig.21 , the display device may include a plurality of driver ICs S-IC. The data driver 110 may be integrated in each driver IC S-IC. The driver IC S-IC may be attached to the display panel 100 in the form of a chip on film (COF) or a chip on glass (COG). Fig.21 In FIG. 1 , “GIP” is a circuit region including the gate driver 120 .

[0176] In the driving IC S-IC, the channels connected to the data lines in the first pixel area and the channels connected to the data lines in the second pixel area output the data voltage Vdata. Since the illumination of the second pixel area CA is increased by the individual compensation voltage Vdata' applied to the sub-pixels of the second pixel area CA, there is no need to increase the channel voltage of the second pixel area of ​​the driving IC S-IC. Therefore, the channels of the driving IC S-IC have the output voltage range Vrange set to be substantially the same regardless of the area, so that a sufficient voltage margin Vm can be ensured in all channels.

[0177] The power line PL is connected to all sub-pixels in the first pixel area DA and the second pixel area CA to provide the pixel driving voltage ELVDD to the pixel circuit. Fig.14 The first contact hole CH1 shown is connected to the second gate electrode GE2 of the first driving element DT1 disposed in the first pixel area DA. Figures 5 to 7 As shown, the power line PL may be applied to the first electrode of the second driving element DT2 in the pixel circuit disposed in the second pixel area CA.

[0178] The auxiliary data line DL' is connected to the sub-pixels of the second pixel area CA. The auxiliary data line DL' is separated from the sub-pixels of the first pixel area DA. The auxiliary data line DL' may be commonly connected to all sub-pixels in the second pixel area CA. The auxiliary data line DL' applies the compensation voltage Vdata' received from the power supply unit 150 or the channel of the driving IC S-IC to the sub-pixels of the second pixel area CA. The auxiliary data line DL' is connected to the sub-pixels of the second pixel area CA by Fig.15The second contact hole CH2 is connected to the second gate electrode GE2 of the second driving element DT2, or through Fig.19 The switching element MS and the contact holes CH3 and CH4 shown are connected to the second gate electrode GE2 of the second driving element DT2.

[0179] For each color, the light emitting element OLED may have different light emitting efficiencies. Therefore, the data voltage Vdata is optimized for each color of the sub-pixel. Fig. 22 and Fig.23 An embodiment is shown in which a voltage applied to the driving element DT2 of the second pixel area CA is divided for each color in consideration of light emitting efficiency and a data voltage of each color of a sub-pixel.

[0180] Fig. 22 is a circuit diagram illustrating an example of differently applying an optimized compensation voltage for each color of sub-pixels arranged in the second pixel area CA. Fig.23 is a graph showing an output voltage range of a data driver and a compensation voltage for each color.

[0181] Reference Fig. 22 and Fig.23 , the first auxiliary data line DLR is connected to the R sub-pixel SPR to apply a compensation voltage +VR for improving the illumination of the R sub-pixel SPR to the R sub-pixel SPR. The compensation voltage +VR is applied to the second gate electrode GE2 of the second driving element DT2 set in the R sub-pixel SPR. The second auxiliary data line DLG is connected to the G sub-pixel SPG to apply a compensation voltage +VG for improving the illumination of the G sub-pixel SPG to the G sub-pixel SPG. The compensation voltage +VG is applied to the second gate electrode GE2 of the second driving element DT2 set in the G sub-pixel SPG. The third auxiliary data line DLB is connected to the B sub-pixel SPB to apply a compensation voltage +VB for improving the illumination of the B sub-pixel SPB to the B sub-pixel SPB. The compensation voltage +VB is applied to the second gate electrode GE2 of the second driving element DT2 set in the B sub-pixel SPB.

[0182] Taking into account the color difference and luminous efficiency of each color, such as Fig.23 As shown, the data voltage Vdata G applied to the G sub-pixel SPG in the RGB sub-pixels is set to the minimum, and the data voltage Vdata B applied to the B sub-pixel SPB is set to the maximum. When the compensation voltage Vdata' is applied as the same voltage to the RGB sub-pixels at the same high grayscale, the luminance of the G sub-pixel SPG with the highest luminous efficiency increases, so that green can be visually recognized in the image reproduced on the screen. Therefore, the compensation voltages +VR, +VG, and +VB can be set to different voltages for each color. For example, as Fig.23As shown, the compensation voltage +VB applied to the B sub-pixel SPB can be set to a voltage greater than the compensation voltages +VR and +VG applied to the R sub-pixel SPR and the G sub-pixel SPG. The compensation voltage +VG applied to the G sub-pixel SPG can be set to a voltage less than the compensation voltages +VR and +VB applied to the R sub-pixel SPR and the B sub-pixel SPB.

[0183] Fig.24 1 is a plan view showing a power line PL and auxiliary data lines DLR, DLG, and DLB separated for each color on the display panel 100. Fig.24 In, with Fig.21 Substantially the same components of the illustrated embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0184] Reference Fig.24 , the first auxiliary data line DLR is connected to the R sub-pixel SPR of the second pixel area CA. The second auxiliary data line DLG is connected to the G sub-pixel SPG of the second pixel area CA. The third auxiliary data line DLB is connected to the B sub-pixel SPB of the second pixel area CA. The auxiliary data lines DLR, DLG and DLB are separated from the sub-pixels of the first pixel area DA.

[0185] The data driver 110 of the present disclosure includes a plurality of first channels for outputting the data voltage Vdata to the data line DL of the first pixel area DA, and a plurality of second channels for outputting the data voltage to the data line DL of the second pixel area CA. The output voltage range Vrange of the first channel and the second channel is set to be the same. Fig.25 As shown, the data voltage ranges Vdata(DA) and Vdata(CA) output from the first channel and the second channel of the data driver 110 are equally set within the output voltage range Vrange. The output voltage ranges Vrange of the first channel and the second channel include a voltage margin Vm greater than the data voltage ranges Vdata(DA) and Vdata(CA) and a voltage margin Vm less than the data voltage ranges Vdata(DA) and Vdata(CA). The voltage margins Vm of the first channel and the second channel are substantially the same.

[0186] Fig.25 is a diagram showing an effect of improving the luminance of the second pixel area CA by using the output voltage range Vrange of the data driver 110 that ensures the voltage margin Vm and the compensation voltage Vdata′ applied to the display panel 100 .

[0187] Reference Fig.25, the output voltage range Vrange of the data driver 110 includes the data voltages Vdata(DA) and Vdata(CA) applied to the sub-pixels of the first pixel area DA and the second pixel area CA and the voltage margin Vm. The data voltage ranges applied to the pixels in the first pixel area DA and the second pixel area CA are set to be substantially the same. Fig.25 , "Vdata(DA)" is a data voltage applied to the sub-pixel of the first pixel area DA. "Vdata(CA)" is a data voltage applied to the sub-pixel of the second pixel area CA.

[0188] The voltage margin Vm can be used as an optical compensation voltage, that is, a voltage that compensates for the shift of the threshold voltage Vth caused by the degradation of the driving elements DT1 and DT2 as the driving time elapses. Since the sufficient and guaranteed voltage margin Vm can optically compensate for the illumination deviation of the sub-pixel at high resolution, the accuracy of optical compensation can be improved, and the variable range of the data voltage for image quality compensation according to time changes can be ensured.

[0189] The present disclosure improves the illumination of the second pixel area CA using the compensation voltage Vdata' applied to the second gate electrode of the second driving element DT2 without reducing the voltage margin Vm in the output voltage range Vrange of the data driver 110. The compensation voltage Vdata' is output from the power supply unit 150 independently of the data driver 110, or is generated as a specific voltage or a variable voltage within the data voltage range.

[0190] Fig.26 is a diagram showing an example of transmitting a compensation voltage to a data driver through an independent path.

[0191] Reference Fig.26 Each channel of the data driver 110 includes: a DAC that converts the pixel data DATA into a gamma compensation voltage GMA to output a data voltage Vdata, and an output buffer AMP that is connected to an output node of the DAC and supplies the data voltage Vdata to the data line DL. The output voltage range Vrange of the data driver 110 and the data voltage Vdata are as follows: Fig.25 shown.

[0192] The compensation voltage Vdata' may be generated from the power supply unit 150 independently of the data driver 110 and applied to the sub-pixels arranged in the second pixel area of ​​the display panel 100. The compensation voltage Vdata' is supplied to the auxiliary data line DL' of the second pixel area CA. The compensation voltage Vdata' may be set to a voltage optimized for each color of the sub-pixel and applied to the sub-pixel of the second pixel area CA through the auxiliary data line separated for each color.

[0193] Fig. 27 and Fig.28 is a diagram showing an example of outputting a compensation voltage from a channel of a data driver.

[0194] Reference Fig. 27 Each channel of the data driver 110 includes: a DAC that converts the pixel data DATA into a gamma compensation voltage GMA to output a data voltage Vdata, and an output buffer AMP that is connected to an output node of the DAC and supplies the data voltage Vdata to the data line DL. The output voltage range Vrange of the data driver 110 and the data voltage Vdata are as follows: Fig.25 shown.

[0195] Some channels of the data driver 110 may convert the compensation data from the timing controller 130 into the compensation voltage Vdata' and may output the compensation voltage Vdata'. The output voltage range Vrange and the data voltage range of these channels are the same as the output voltage range Vrange and the data voltage range of other channels outputting the data voltage Vdata of the pixel data DATA.

[0196] The compensation voltage Vdata' outputted from the channel of the data driver 110 is supplied to the auxiliary data line DL' of the second pixel area CA. The compensation voltage Vdata' may be set to a voltage optimized for each color of the subpixel and applied to the subpixel of the second pixel area CA through the auxiliary data line separated for each color.

[0197] Reference Fig.28 , the demultiplexer 112 may be connected between the channels of the data driver 110 and the data lines DL and DL' to reduce the number of channels of the data driver 110. In this embodiment, the data driver 110 may output the compensation voltage Vdata' together with the data voltage Vdata without increasing the number of channels. The output voltage range Vrange of the data driver 110 and the data voltage Vdata are as follows: Fig.25 shown.

[0198] As an example of the demultiplexer 112, a 1:2 demultiplexer DEMUX may be used. The demultiplexer 112 includes a first 1:2 demultiplexer connected to the data line DL of the first pixel area DA, and a second 1:2 demultiplexer connected to the data line DL and the auxiliary data line DL' of the second pixel area CA. These demultiplexers include a first switching element S1 and a second switching element S2 that are alternately turned on / off under the control of the timing controller 130. When the first switching element S1 is turned on in response to the first control signal DEMUX1, the second switching element S2 is turned off. Subsequently, when the second switching element S2 is turned on in response to the second control signal DEMUX2, the first switching element S1 is turned off.

[0199] The first 1:2 demultiplexer alternately connects one channel of the data driver 110 to two data lines DL. The first 1:2 demultiplexer time-divisionally distributes a data voltage Vdata output from one channel of the data driver 110 to two data lines of the first pixel area DA through first and second switching elements S1 and S2.

[0200] The second 1:2 demultiplexer alternately connects one channel of the data driver 110 to one data line DL and one auxiliary data line DL'. The second 1:2 demultiplexer supplies a data voltage Vdata output from one channel of the data driver 110 to the first data line DL of the second pixel region CA through the first switching element S1, and supplies the data voltage Vdata output from one channel of the data driver 110 to the auxiliary data line DL' of the second pixel region CA through the second switching element S2.

[0201] If the illumination of the second pixel area CA is low or there are few high grayscale pixels in the grayscale distribution of the pixel data of the pixels written in the second pixel area, the illumination difference between the first pixel area DA and the second pixel area CA is almost non-existent, so that the illumination difference between the areas is not visually recognized. Therefore, when there are few high grayscale pixels in the low illumination image or the second pixel area, the present disclosure does not compensate for the illumination of the second pixel area CA, and does not apply the compensation voltage Vdata' to the driving element DT2 provided in the second pixel area CA. In this case, the pixels in the second pixel area CA are driven by the data voltage Vdata, and the compensation voltage Vdata' is not used. Figure 29 to Figure 32 The illumination compensation method may be controlled by the host system 200 or the data operation unit of the timing controller 130.

[0202] Fig.29 is a flowchart illustrating a method of compensating screen illumination according to a first embodiment of the present disclosure.

[0203] Reference Fig.29 , the timing controller 130 stores the pixel data of the input image in the memory. The timing controller 130 analyzes one frame of pixel data (hereinafter, referred to as "one frame of data") in each frame period to analyze the illumination characteristics of the input image (step S291). One frame of data includes pixel data to be written to all pixels in the screen. Therefore, one frame of data includes pixel data of the first pixel area DA and the second pixel area CA of the screen.

[0204] The timing controller 130 can determine the cumulative distribution of each grayscale by calculating a histogram of pixel data of one frame. The histogram is a cumulative distribution function of each grayscale of the pixel data. The timing controller 130 calculates an average picture level (called "APL") based on the histogram and determines the average illumination of each of the first pixel area DA and the second pixel area CA.

[0205] The timing controller 130 compares the average luminance of the first pixel area DA with a preset first threshold value, and compares the average luminance of the second pixel area CA with a preset second threshold value (steps S292 and S293). The first threshold value and the second threshold value may be set based on the results of the image quality experiment, and these threshold values ​​may be the same or different values.

[0206] When the average illuminance of the first pixel area DA is greater than the first threshold value and the average illuminance of the second pixel area CA is greater than the second threshold value, the timing controller 130 compensates for the illuminance of the second pixel area CA by increasing the illuminance of the second pixel area CA so that the illuminance difference between the first pixel area DA and the second pixel area CA is not visually recognized (steps S292, S293 and S294). In this case, the image reproduced on the screen is a bright image with high illuminance. As in the above-mentioned embodiment, the illuminance of the second pixel area CA can be compensated by applying the compensation voltage Vdata' to the second gate electrode GE2 of the driving element DT2 provided in the second pixel area CA. The power supply unit 150 or the data driver 110 outputs the compensation voltage Vdata' under the control of the timing controller 130.

[0207] When the average illumination of the first pixel area DA is less than or equal to the first threshold value or the average illumination of the second pixel area CA is less than or equal to the second threshold value, the timing controller 130 does not compensate for the illumination of the second pixel area CA (step S295). In this case, the image reproduced on the screen is a low illumination image that is relatively dark compared to the high illumination image. In step S295, the power supply unit 150 or the data driver 110 does not output the compensation voltage Vdata' under the control of the timing controller 130. Therefore, in step S295, since the compensation voltage Vdata' is not applied to the second gate electrode GE2 of the driving element DT2 set in the second pixel area CA, the second gate electrode GE2 of the driving element DT2 set in the second pixel area CA can be floated.

[0208] Fig.30 is a flowchart showing a method of compensating screen illuminance according to a second embodiment of the present disclosure. This embodiment can reduce the amount of data calculation for calculating average illuminance.

[0209] Reference Fig.30 , the timing controller 130 analyzes the luminance characteristics of the second pixel area image based on the result of calculating the APL for the pixel data to be written into the second pixel area CA for each frame period (step S301).

[0210] The timing controller 130 compares the average illumination of the second pixel area CA with a preset threshold value (step S302). When the average illumination of the second pixel area CA is greater than the threshold value, the timing controller 130 compensates the illumination of the second pixel area CA by increasing the illumination of the second pixel area CA (steps S302 and S303). In this case, the image reproduced in the second pixel area CA is a bright image with high illumination. As in the above-mentioned embodiment, the illumination of the second pixel area CA can be compensated by applying the compensation voltage Vdata' to the second gate electrode GE2 of the driving element DT2 provided in the second pixel area CA. The power supply unit 150 or the data driver 110 outputs the compensation voltage Vdata' under the control of the timing controller 130.

[0211] When the average illumination of the second pixel area CA is less than or equal to the threshold value, the timing controller 130 does not compensate for the illumination of the second pixel area CA (step S304). In this case, the image reproduced in the second pixel area CA is a low illumination image that is relatively dark compared to the high illumination image. In step S304, the power supply unit 150 or the data driver 110 does not output the compensation voltage Vdata' under the control of the timing controller 130. Therefore, in step S304, since the compensation voltage Vdata' is not applied to the second gate electrode GE2 of the driving element DT2 provided in the second pixel area CA, the second gate electrode GE2 of the driving element DT2 provided in the second pixel area CA can be floated.

[0212] Fig.31 is a flowchart illustrating a method of compensating screen illumination according to a third embodiment of the present disclosure.

[0213] Reference Fig.31 , the timing controller 130 analyzes the luminance characteristics of the input image based on the result of calculating the APL for one frame of data per frame period (step S311).

[0214] The timing controller 130 compares the average luminance of the first pixel area DA with the first threshold value, and compares the average luminance of the second pixel area CA with the second threshold value (steps S312 and S313).

[0215] When the average luminance of the first pixel area DA is greater than the first threshold and the average luminance of the second pixel area CA is greater than the second threshold, the timing controller 130 analyzes the grayscale distribution of the second pixel area CA by using the histogram calculation result (step S314). The timing controller 130 can determine the grayscale distribution characteristics of the pixel data to be written to the second pixel area CA by calculating the accumulated number of pixels of each grayscale in the second pixel area CA.

[0216] The timing controller 130 can determine whether the main gray level of the second pixel area CA is a high gray level by comparing the number of pixels having a high gray level equal to or greater than a predetermined reference value in the pixel data to be written into the second pixel area CA with a preset third threshold value. When the number of pixels having a high gray level equal to or greater than the reference value is greater than the third threshold value, that is, when it is determined that the high gray level is dominant in the graph of the gray distribution characteristics of the second pixel area, the timing controller 130 compensates for the illumination of the second pixel area CA by increasing the illumination of the second pixel area CA (steps S315 and S316). In this case, the image reproduced in the second pixel area CA is an image containing many high-illuminance pixels, such as Fig.33As in the above embodiment, the illuminance of the second pixel region CA may be compensated by applying the compensation voltage Vdata′ to the second gate electrode GE2 of the driving element DT2 provided in the second pixel region CA.

[0217] When the average luminance of the first pixel area DA is less than or equal to the first threshold or the average luminance of the second pixel area CA is less than or equal to the second threshold, the timing controller 130 does not compensate for the luminance of the second pixel area CA (step S317). In addition, even if the average luminance of the second pixel area CA is high, if the high grayscale pixel data is small, the luminance of the second pixel area CA is not compensated (step S317).

[0218] Fig.32 1 is a flowchart showing a method for compensating screen illumination according to a fourth embodiment of the present disclosure. In this embodiment, whether to compensate the illumination of the second pixel area CA is determined based on the grayscale distribution characteristics of the pixel data of the pixels to be written to the second pixel area CA without analyzing the illumination characteristics of the input image.

[0219] Reference Fig.32 , the timing controller 130 analyzes the grayscale distribution of the second pixel area CA by using the histogram calculation result of the pixel data to be written into the second pixel area CA every frame period (step S321).

[0220] like Fig.33 As shown in (c), when the high grayscale pixel data in the pixel data to be written to the pixels of the second pixel area CA is greater than the third threshold value, the timing controller 130 compensates the illumination of the second pixel area CA by increasing the illumination of the second pixel area CA (steps S322 and S323). On the other hand, when the high grayscale pixel data in the pixel data to be written to the pixels of the second pixel area CA is less than or equal to the third threshold value, the timing controller 130 does not compensate the illumination of the second pixel area CA (step S317). In addition, even if the average illumination of the second image CA is high, if the number of high-illuminance pixels is small, the illumination of the second pixel area CA is not compensated (step S324).

[0221] Fig.33 is a diagram showing an example of a histogram calculation result of pixel data. Fig.33 Among them, (a) is an example of a low-grayscale image having multiple cumulative values ​​of pixel data with low grayscale values; (b) is an example of an image having multiple cumulative values ​​of pixel data with intermediate grayscale values; and (c) is an example of a high-grayscale image having multiple cumulative values ​​of pixel data with high grayscale values.

[0222] The objects to be achieved by the present disclosure, means for achieving the objects, and the effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0223] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display panel, comprising: a first pixel region, in which pixels are arranged; as well as a second pixel region in which pixels having a resolution or pixels per inch lower than that of the first pixel region are arranged; Each pixel in the first pixel region includes a first driving element configured to drive a first light emitting element, and Each pixel in the second pixel region includes a second driving element configured to drive a second light emitting element, wherein Each of the first driving element and the second driving element has a double gate structure including a first gate electrode and a second gate electrode, A data voltage of pixel data to be written to the pixels of the first pixel area is applied to the first gate electrode of the first driving element, A pixel driving voltage is applied to the second gate electrode of the first driving element to suppress a change in a threshold voltage of the first driving element, A data voltage of pixel data to be written to the pixels of the second pixel area is applied to the first gate electrode of the second driving element, and A compensation voltage for increasing the illumination of the second pixel region to improve illumination uniformity between the first pixel region and the second pixel region having different resolutions or pixels per inch is applied to the second gate electrode of the second driving element.

2. The display panel according to claim 1, wherein: The first driving element comprises: a first electrode to which a pixel driving voltage is applied; and A second electrode connected to an anode electrode of the first light emitting element.

3. The display panel according to claim 1, further comprising: An auxiliary data line is connected to the second gate electrode of the second driving element and is configured to apply the compensation voltage to the second gate electrode of the second driving element.

4. The display panel according to claim 3, wherein: The auxiliary data line is connected to the second gate electrode of the second driving element through a contact hole penetrating the insulating layer.

5. The display panel according to claim 3, wherein: In the second pixel area, auxiliary data lines connected to pixels are connected to each other.

6. The display panel according to claim 1, wherein: Each pixel in the second pixel area further includes a switching element configured to apply the compensation voltage to a second gate electrode of the second driving element.

7. The display panel according to claim 1, wherein: Each pixel in the first pixel area and the second pixel area includes a plurality of sub-pixels having different colors, The second pixel region includes an auxiliary data line connected to the second gate electrode of the second driving element and configured to apply the compensation voltage to the second gate electrode of the second driving element, and The auxiliary data line is divided for each color of the sub-pixel in the second pixel area and is connected to the second gate electrode of the second driving element provided in the sub-pixel in the second pixel area.

8. A display device comprising: A display panel comprising a first pixel region in which pixels are arranged and a second pixel region in which pixels having a lower resolution or pixels per inch than the resolution or pixels per inch of the first pixel region are arranged; a data driver configured to convert pixel data of an input image into data voltages and to supply the data voltages to data lines connected to pixels in the first pixel region and pixels in the second pixel region; as well as an illumination compensation unit configured to generate a compensation voltage for increasing the illumination of the second pixel region, wherein The compensation voltage is applied to pixels in the second pixel area, Each pixel in the first pixel region includes a first driving element configured to drive a first light emitting element, and Each pixel in the second pixel region includes a second driving element configured to drive a second light emitting element, wherein Each of the first driving element and the second driving element has a double gate structure including a first gate electrode and a second gate electrode, A data voltage of pixel data to be written to the pixels of the first pixel area is applied to the first gate electrode of the first driving element, A pixel driving voltage is applied to the second gate electrode of the first driving element to suppress a change in a threshold voltage of the first driving element, A data voltage of pixel data to be written to the pixels of the second pixel area is applied to the first gate electrode of the second driving element, and A compensation voltage for increasing the illumination of the second pixel region to improve illumination uniformity between the first pixel region and the second pixel region having different resolutions or pixels per inch is applied to the second gate electrode of the second driving element.

9. The display device according to claim 8, wherein: The data driver comprises: a plurality of first channels configured to output data voltages to data lines of the first pixel region; and a plurality of second channels configured to output data voltages to the data lines of the second pixel region, and The first channel and the second channel have the same output voltage range, The voltage ranges of the data voltages output from the first channel and the second channel are the same within the output voltage range, The output voltage ranges of the first channel and the second channel include a voltage margin greater than a voltage range of the data voltage and a voltage margin less than the voltage range of the data voltage, The voltage margins of the first channel and the second channel are the same.

10. The display device according to claim 8, wherein: The compensation voltage is a specific voltage or varies according to the illuminance characteristics and grayscale distribution characteristics of the input image.

11. The display device according to claim 8, wherein: The compensation voltage is commonly applied to pixels arranged in the second pixel area.

12. The display device according to claim 8, wherein: The compensation voltage is divided for each color of sub-pixels arranged in the second pixel area and applied to pixels in the second pixel area.

13. The display device according to claim 12, wherein: The compensation voltage is differently set for each color of sub-pixels arranged in the second pixel area.

14. The display device according to claim 8, wherein: When an average luminance of an input image to be displayed in the first pixel region and the second pixel region is greater than a preset threshold, the compensation voltage is applied to pixels in the second pixel region.

15. The display device according to claim 8, wherein: When the average illuminance of the input image to be displayed in the first pixel area and the second pixel area is greater than a preset threshold, and in the pixel data to be written into the second pixel area, the number of pixels having a high grayscale equal to or greater than a preset reference value is greater than or equal to a predetermined threshold, the compensation voltage is applied to the pixels in the second pixel area.

16. The display device according to claim 8, wherein: When an average luminance of an input image to be displayed in the second pixel area is greater than a preset threshold, the compensation voltage is applied to pixels in the second pixel area.

17. The display device according to claim 8, wherein: When the average illuminance of the input image to be displayed in the second pixel area is greater than a preset threshold, and in the pixel data to be written into the second pixel area, the number of pixels having a high grayscale equal to or greater than a preset reference value is greater than or equal to a predetermined threshold, the compensation voltage is applied to the pixels in the second pixel area.

18. The display device according to claim 8, wherein: When the number of pixels having a high grayscale equal to or greater than a preset reference value in pixel data to be written in the second pixel area is greater than or equal to a predetermined threshold, the compensation voltage is applied to the pixels in the second pixel area.

19. The display device according to claim 9, further comprising: a power supply unit configured to generate a gamma reference voltage, wherein Each of the channels of the data driver includes a digital-to-analog converter configured to convert the pixel data into the data voltage by using a gamma compensation voltage for each grayscale divided from the gamma reference voltage, and The power supply unit or the data driver includes the illumination compensation unit to output the compensation voltage.

Images