scan driver

Abstract

A scan driver is provided. A stage of the scan driver includes a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry terminal, and a second electrode connected to a first node; a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to a second carry terminal, and a second electrode connected to the first node; a third transistor including a gate electrode connected to the first node, and a first electrode connected to a second node; a fourth transistor including a gate electrode connected to the second clock terminal, a first electrode connected to a first power terminal, and a second electrode connected to the second node; a fifth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the first power terminal, and a second electrode connected to the second node; and an output portion outputting a first scan signal and a second scan signal based on a voltage of the first node and a voltage of the second node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0127493, filed with the Korean Intellectual Property Office on September 29, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a scan driver. Background Technology

[0004] With the development of information technology, display devices are increasingly being used as a connection medium between users and information. Examples of such display devices include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0005] Display devices display images by combining light emission based on data voltages written to pixels. A scan driver is used to select pixels for which data voltages are written. When there are many elements in the scan driver, the dead zone where no image is displayed can increase. Summary of the Invention

[0006] Embodiments of the present invention provide a scan driver comprising: a plurality of stages, wherein a first stage of the plurality of stages comprises: a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry terminal, and a second electrode connected to a first node; a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to a second carry terminal, and a second electrode connected to the first node; a third transistor including a gate electrode connected to the first node and a first electrode connected to a second node; a fourth transistor including a gate electrode connected to the second clock terminal, a first electrode connected to a first power terminal, and a second electrode connected to the second node; a fifth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the first power terminal, and a second electrode connected to the second node; and an output section configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal based on the voltage of the first node and the voltage of the second node.

[0007] The output section may include: a sixth transistor, including a gate electrode connected to a second node, a first electrode connected to a first output terminal, and a second electrode connected to a second power terminal; a seventh transistor, including a gate electrode connected to a third node, a first electrode connected to a third clock terminal, and a second electrode connected to the first output terminal; and a first capacitor, including a first electrode connected to a third node and a second electrode connected to the first output terminal.

[0008] The output section may further include: an eighth transistor, including a gate electrode connected to the second node, a first electrode connected to the second output terminal, and a second electrode connected to the second power terminal; a ninth transistor, including a gate electrode connected to the fourth node, a first electrode connected to the fourth clock terminal, and a second electrode connected to the second output terminal; and a second capacitor, including a first electrode connected to the fourth node and a second electrode connected to the second output terminal.

[0009] The output section may further include: a third capacitor, including a first electrode connected to a second node and a second electrode connected to a second power terminal; a tenth transistor, including a gate electrode connected to a first power terminal, a first electrode connected to a first node and a second electrode connected to a third node; and an eleventh transistor, including a gate electrode connected to a first power terminal, a first electrode connected to a first node and a second electrode connected to a fourth node.

[0010] The second electrode of the third transistor can be connected to the second power terminal.

[0011] The second electrode of the third transistor can be connected to the second clock terminal.

[0012] The first stage may also include a twelfth transistor, which includes a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to the second node.

[0013] In the second stage of multiple stages, the first carry terminal can be connected to the second output terminal of the first stage, the second carry terminal can be connected to the first output terminal of the first stage, the first clock terminal can be connected to the fourth clock terminal of the first stage, the second clock terminal can be connected to the third clock terminal of the first stage, the third clock terminal can be connected to the second clock terminal of the first stage, and the fourth clock terminal can be connected to the first clock terminal of the first stage.

[0014] The first carry terminal and the second carry terminal of the first stage can be connected to each other.

[0015] The width-to-length ratio of the channel of the third transistor may be less than or equal to the width-to-length ratio of the channel of the fourth or fifth transistor.

[0016] Embodiments of the present invention provide a scan driver comprising: a plurality of stages, wherein a first stage of the plurality of stages comprises: a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry terminal, and a second electrode connected to a first node; a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to the first node, and a second electrode connected to a second power terminal; a third transistor including a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to the second node; a fourth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the first power terminal, and a second electrode connected to the second node; and an output section configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal based on the voltage of the first node and the voltage of the second node.

[0017] The output section may include: a fifth transistor, including a gate electrode connected to a second node, a first electrode connected to a first output terminal, and a second electrode connected to a second power terminal; a sixth transistor, including a gate electrode connected to a third node, a first electrode connected to a third clock terminal, and a second electrode connected to the first output terminal; and a first capacitor, including a first electrode connected to a third node and a second electrode connected to the first output terminal.

[0018] The output section may further include: a seventh transistor, including a gate electrode connected to the second node, a first electrode connected to the second output terminal, and a second electrode connected to the second power terminal; an eighth transistor, including a gate electrode connected to the fourth node, a first electrode connected to the fourth clock terminal, and a second electrode connected to the second output terminal; and a second capacitor, including a first electrode connected to the fourth node and a second electrode connected to the second output terminal.

[0019] The output section may further include: a ninth transistor, including a gate electrode connected to a first power terminal, a first electrode connected to a first node, and a second electrode connected to a third node; a tenth transistor, including a gate electrode connected to a first power terminal, a first electrode connected to a first node, and a second electrode connected to a fourth node; and a third capacitor, including a first electrode connected to a second node and a second electrode connected to a second power terminal.

[0020] In the second stage of multiple stages, the first carry terminal can be connected to the second output terminal of the first stage, the first clock terminal can be connected to the fourth clock terminal of the first stage, the second clock terminal can be connected to the third clock terminal of the first stage, the third clock terminal can be connected to the second clock terminal of the first stage, and the fourth clock terminal can be connected to the first clock terminal of the first stage.

[0021] Embodiments of the present invention provide a scan driver comprising: a plurality of stages, wherein a first stage of the plurality of stages comprises: a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry terminal, and a second electrode connected to a first node; a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to a first power terminal, and a second electrode connected to a second node; a third transistor including a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to the second node; a fourth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the first power terminal, and a second electrode connected to the second node; and an output section configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal based on the voltage of the first node and the voltage of the second node.

[0022] The output section may include: a fifth transistor, including a gate electrode connected to a second node, a first electrode connected to a first output terminal, and a second electrode connected to a second power terminal; a sixth transistor, including a gate electrode connected to a third node, a first electrode connected to a third clock terminal, and a second electrode connected to the first output terminal; and a first capacitor, including a first electrode connected to a third node and a second electrode connected to the first output terminal.

[0023] The output section may further include: a seventh transistor, including a gate electrode connected to the second node, a first electrode connected to the second output terminal, and a second electrode connected to the second power terminal; an eighth transistor, including a gate electrode connected to the fourth node, a first electrode connected to the fourth clock terminal, and a second electrode connected to the second output terminal; and a second capacitor, including a first electrode connected to the fourth node and a second electrode connected to the second output terminal.

[0024] The output section may further include: a ninth transistor, including a gate electrode connected to a first power terminal, a first electrode connected to a first node, and a second electrode connected to a third node; a tenth transistor, including a gate electrode connected to a first power terminal, a first electrode connected to a first node, and a second electrode connected to a fourth node; and a third capacitor, including a first electrode connected to a second node and a second electrode connected to a second power terminal.

[0025] In the second stage of multiple stages, the first carry terminal can be connected to the second output terminal of the first stage, the first clock terminal can be connected to the fourth clock terminal of the first stage, the second clock terminal can be connected to the third clock terminal of the first stage, the third clock terminal can be connected to the second clock terminal of the first stage, and the fourth clock terminal can be connected to the first clock terminal of the first stage.

[0026] Embodiments of the present invention provide a stage for a scan driver, the stage comprising: a first transistor and a fifth transistor, the first transistor and the fifth transistor being turned on by a first clock signal, wherein the first transistor is connected to a first node and the fifth transistor is connected to a second node; a second transistor and a fourth transistor, the second transistor and the fourth transistor being turned on by a fourth clock signal, wherein the second transistor is connected to the first node and the fourth transistor is connected to the second node; a third transistor connected to the first node and the second node; and an output circuit configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal based on the voltage of the first node and the voltage of the second node.

[0027] The first and fifth transistors can be connected to the first clock terminal, and the second and fourth transistors can be connected to the second clock terminal.

[0028] The third transistor can be connected to the second power terminal, and the fourth transistor can be connected to the first power terminal.

[0029] The output circuit may include a third node disposed between a first pair of transistors connected to a first capacitor, wherein the voltage of the third node may drop below a logic low level when a clock signal applied to the third clock terminal has a logic low level.

[0030] The output circuit may also include a fourth node connected between the second pair of transistors, the voltage of which may drop below the logic low level when the clock signal applied to the fourth clock terminal has a logic low level. Attached Figure Description

[0031] Figure 1 A schematic view is shown for explaining a display device according to an embodiment of the present invention.

[0032] Figure 2 A schematic view is shown to explain pixels according to an embodiment of the present invention.

[0033] Figure 3 A schematic view is shown for explaining a scan driver according to an embodiment of the present invention.

[0034] Figure 4 A schematic view is shown for explaining the levels according to an embodiment of the invention.

[0035] Figure 5 The following is an explanation Figure 4 The sequence diagram of the example driver method at the level.

[0036] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a schematic view used to explain the first frame time period and the second frame time period according to an embodiment of the present invention.

[0037] Figure 11 The following is an explanation Figure 4 A schematic view of example variations of the level.

[0038] Figure 12 A schematic view is shown to explain a scan driver according to another embodiment of the present invention.

[0039] Figure 13 A schematic view is shown for explaining a level according to another embodiment of the invention.

[0040] Figure 14 The following is an explanation Figure 13 The sequence diagram of the example driver method at the level.

[0041] Figure 15 The following is an explanation Figure 13 A schematic view of example variations of the level.

[0042] Figure 16 The following is an explanation Figure 15 The sequence diagram of the example driver method at the level. Detailed Implementation

[0043] Embodiments of the invention will be described more fully below with reference to the accompanying drawings.

[0044] In the specification and drawings, the same or similar elements may be represented by the same reference numerals.

[0045] Furthermore, the thickness of layers, films, panels, areas, etc., may be exaggerated in the accompanying drawings for clarity.

[0046] Figure 1 A schematic view is shown for explaining a display device according to an embodiment of the present invention.

[0047] Reference Figure 1 According to an embodiment of the present invention, the display device 10 may include a timing controller 11, a data driver 12, a scan driver 13, and a pixel unit 14.

[0048] The timing controller 11 can receive external input signals from an external processor. These external input signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, RGB data, etc. The vertical synchronization signal may include multiple pulses and may indicate the end of the previous frame period and the start of the current frame period based on the time point at which each pulse is generated. The interval between adjacent pulses of the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include multiple pulses and may indicate the end of the previous horizontal period and the start of a new horizontal period based on the time point at which each pulse is generated. The interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may indicate the supply of RGB data during a horizontal period. In response to the data enable signal, RGB data may be supplied in pixel rows during a horizontal period. The RGB data corresponding to a frame may be referred to as an input image. When the grayscale of consecutive input images is substantially the same, the timing controller 11 may determine the consecutive input images as still images. When the grayscale of consecutive input images is substantially different, the timing controller 11 may determine the consecutive input images as moving pictures.

[0049] The data driver 12 can provide a data voltage corresponding to the grayscale of the input image to the pixels. For example, the data driver 12 can sample the grayscale using a clock signal and apply the data voltage corresponding to the grayscale to the data lines DL1, DL2, DL3, ..., DLn in units of scan lines. Here, n can be an integer greater than zero.

[0050] The scan driver 13 can receive clock signals, scan start signals, etc. from the timing controller 11 to generate scan signals to be provided to scan lines SL1, SL2, SL3, ..., SLm. Here, m can be an integer greater than zero.

[0051] The pixel unit 14 includes pixels. Each pixel PXij can be connected to a corresponding data line and scan line. Here, i and j can be integers greater than zero. For example, pixel PXij can be a pixel in which the scan transistor is connected to the i-th scan line and the j-th data line.

[0052] Figure 2 A schematic view is shown to explain pixels according to an embodiment of the present invention.

[0053] The gate electrode of the first transistor T1 can be connected to the i-th scan line SLi, the first electrode of the first transistor T1 can be connected to the j-th data line DLj, and the second electrode of the first transistor T1 can be connected to the second electrode of the storage capacitor Cst. The first transistor T1 can be referred to as the scan transistor.

[0054] The gate electrode of the second transistor T2 can be connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 can be connected to the first pixel power line ELVDDL, and the second electrode of the second transistor T2 can be connected to the anode of the light-emitting diode LD. The second transistor T2 can be referred to as the driving transistor.

[0055] The first electrode of the storage capacitor Cst can be connected to the first pixel power line ELVDDL, and the second electrode of the storage capacitor Cst can be connected to the gate electrode of the second transistor T2. For example, the second electrode of the storage capacitor Cst can be connected to the node between the gate electrode of the second transistor T2 and the second electrode of the first transistor T1.

[0056] The anode of the light-emitting diode (LD) can be connected to the second electrode of the second transistor T2, and the cathode of the LD can be connected to the second pixel power line ELVSSL. During the light emission period of the LD, the first pixel power voltage applied to the first pixel power line ELVDDL can be greater than the second pixel power voltage applied to the second pixel power line ELVSSL.

[0057] Here, the first transistor T1 and the second transistor T2 are shown as P-type transistors, but at least one of the first transistor T1 and the second transistor T2 can be replaced with an N-type transistor by inverting the phase of the signal.

[0058] When a scan signal with an on-level (e.g., logic low level) is applied through the i-th scan line SL1, the first transistor T1 is turned on. In this case, the data voltage applied to the j-th data line DLj flows through the first transistor T1 and is stored in the storage capacitor Cst.

[0059] A drive current corresponding to the voltage difference between the first and second electrodes of the storage capacitor Cst flows between the first and second electrodes of the second transistor T2. Therefore, the light-emitting diode LD emits light with a brightness corresponding to the data voltage.

[0060] Next, when a scan signal with a turn-off level (e.g., a logic high level) is applied through the i-th scan line SL1, the first transistor T1 is turned off, and the j-th data line DLj is electrically isolated from the second electrode of the storage capacitor Cst. Therefore, even if the data voltage of the j-th data line DLj changes, the voltage stored in the second electrode of the storage capacitor Cst does not change.

[0061] The embodiments of the present invention can be applied not only to Figure 2 The pixel PXij can also be applied to pixels with another pixel circuit.

[0062] Figure 3A schematic view is shown for explaining a scan driver according to an embodiment of the present invention.

[0063] Reference Figure 3 The scan driver 13a may include multiple levels (ST1a, ST2a, ST3a, ST4a, ...).

[0064] Each of the levels (ST1a, ST2a, ST3a, ST4a, ...) may include a first power terminal IV1, a second power terminal IV2, a first carry terminal IC1, a second carry terminal IC2, a first clock terminal IK1, a second clock terminal IK2, a third clock terminal IK3, a fourth clock terminal IK4, a first output terminal OT1, and a second output terminal OT2.

[0065] The first power terminal IV1 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be connected to the first power line VGLL, and the second power terminal IV2 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be connected to the second power line VGHL. The second power supply voltage of the second power line VGHL can be greater than the first power supply voltage of the first power line VGLL.

[0066] The first carry terminal IC1 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be connected to the second output terminal OT2 of the previous stage. Similarly, the second carry terminal IC2 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be connected to the first output terminal OT1 of the previous stage. However, the first carry terminal IC1 and the second carry terminal IC2 of the first stage ST1a can be connected to each other. For example, the first carry terminal IC1 and the second carry terminal IC2 of the first stage ST1a can be connected together to the scan start line FLML.

[0067] The first clock terminal IK1 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be alternately connected to the first clock line CKL1 or the third clock line CKL3. For example, the first clock terminal IK1 of odd-numbered stages ST1a and ST3a can be connected to the first clock line CKL1, and the first clock terminal IK1 of even-numbered stages ST2a and ST4a can be connected to the third clock line CKL3.

[0068] The second clock terminal IK2 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be alternately connected to the fourth clock line CKL4 or the second clock line CKL2. For example, the second clock terminal IK2 of odd-numbered stages ST1a and ST3a can be connected to the fourth clock line CKL4, and the second clock terminal IK2 of even-numbered stages ST2a and ST4a can be connected to the second clock line CKL2.

[0069] The third clock terminal IK3 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be alternately connected to the second clock line CKL2 or the fourth clock line CKL4. For example, the third clock terminal IK3 of odd-numbered stages ST1a and ST3a can be connected to the second clock line CKL2, and the third clock terminal IK3 of even-numbered stages ST2a and ST4a can be connected to the fourth clock line CKL4.

[0070] The fourth clock terminal IK4 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be alternately connected to the third clock line CKL3 or the first clock line CKL1. For example, the fourth clock terminal IK4 of odd-numbered stages ST1a and ST3a can be connected to the third clock line CKL3, and the fourth clock terminal IK4 of even-numbered stages ST2a and ST4a can be connected to the first clock line CKL1.

[0071] The first output terminal OT1 and the second output terminal OT2 of each stage (ST1a, ST2a, ST3a, ST4a, ...) can be connected to different scan lines. For example, the first output terminal OT1 of the stage (ST1a, ST2a, ST3a, ST4a, ...) can be connected to odd-numbered scan lines (SL1, SL3, SL5, SL7, ...), and the second output terminal OT2 of the stage (ST1a, ST2a, ST3a, ST4a, ...) can be connected to even-numbered scan lines (SL2, SL4, SL6, SL8, ...).

[0072] For example, in the second stage ST2a, the first carry terminal IC1 can be connected to the second output terminal OT2 of the first stage ST1a, the second carry terminal IC2 can be connected to the first output terminal OT1 of the first stage ST1a, the first clock terminal IK1 can be connected to the fourth clock terminal IK4 of the first stage ST1a, the second clock terminal IK2 can be connected to the third clock terminal IK3 of the first stage ST1a, the third clock terminal IK3 can be connected to the second clock terminal IK2 of the first stage ST1a, and the fourth clock terminal IK4 can be connected to the first clock terminal IK1 of the first stage ST1a.

[0073] In another embodiment of the invention, odd-numbered configurations can be replaced by even-numbered configurations, and even-numbered configurations can be replaced by odd-numbered configurations. For example, the first clock terminal IK1 of odd-numbered scan stages ST1a and ST3a can be connected to the third clock line CKL3, and the first clock terminal IK1 of even-numbered scan stages ST2a and ST4a can be connected to the first clock line CKL1.

[0074] Figure 4 A schematic view is shown for explaining the levels according to an embodiment of the invention.

[0075] Reference Figure 4 The first stage ST1a may include multiple transistors T1a, T2a, T3a, T4a, T5a, T6a, T7a, T8a, T9a, T10a, and T11a, as well as multiple capacitors C1a, C2a, and C3a. Other stages (ST2a, ST3a, ST4a, ...) of the scan driver 13a may also have the same or similar configuration as the first stage ST1a.

[0076] The first stage ST1a may include an output section OPPa, which outputs a first scan signal to a first output terminal OT1 and a second scan signal to a second output terminal OT2 based on the voltage of the first node N1a and the voltage of the second node N2a. According to this embodiment, the output section OPPa may include a sixth transistor T6a to an eleventh transistor T11a and a first capacitor C1a to a third capacitor C3a.

[0077] In the first transistor T1a, the gate electrode can be connected to the first clock terminal IK1, the first electrode can be connected to the first carry terminal IC1, and the second electrode can be connected to the first node N1a. The first carry terminal IC1 can be connected to the scan start line FLML. The first clock terminal IK1 can be connected to the first clock line CKL1.

[0078] In the second transistor T2a, the gate electrode can be connected to the second clock terminal IK2, the first electrode can be connected to the second carry terminal IC2, and the second electrode can be connected to the first node N1a. The second electrodes of the first transistor T1a and the second electrodes of the second transistor T2a can be connected to each other. The second carry terminal IC2 can be connected to the scan start line FLML. The second clock terminal IK2 can be connected to the fourth clock line CKL4.

[0079] In the third transistor T3a, the gate electrode can be connected to the first node N1a, the first electrode can be connected to the second node N2a, and the second electrode can be connected to the second power terminal IV2. In this embodiment, the width-to-length ratio of the channel of the third transistor T3a can be less than or equal to the width-to-length ratio of the channel of the fourth transistor T4a or the fifth transistor T5a. The second power terminal IV2 can be connected to the second power line VGHL.

[0080] In the fourth transistor T4a, the gate electrode can be connected to the second clock terminal IK2, the first electrode can be connected to the first power terminal IV1, and the second electrode can be connected to the second node N2a. The second electrode of the fourth transistor T4a can be connected to the first electrode of the third transistor T3a. The first power terminal IV1 can be connected to the first power line VGLL.

[0081] In the fifth transistor T5a, the gate electrode can be connected to the first clock terminal IK1, the first electrode can be connected to the first power terminal IV1, and the second electrode can be connected to the second node N2a. For example... Figure 4 As shown, the first transistor T1a to the fifth transistor T5a may not be included in the output section OPPa.

[0082] In the sixth transistor T6a, the gate electrode can be connected to the second node N2a, the first electrode can be connected to the first output terminal OT1, and the second electrode can be connected to the second power terminal IV2. The first output terminal OT1 can be connected to the first scan line SL1.

[0083] In the seventh transistor T7a, the gate electrode can be connected to the third node N3a, the first electrode can be connected to the third clock terminal IK3, and the second electrode can be connected to the first output terminal OT1. The third clock terminal IK3 can be connected to the second clock line CKL2.

[0084] In the first capacitor C1a, the first electrode can be connected to the third node N3a, and the second electrode can be connected to the first output terminal OT1. The first electrode of the first capacitor C1a can be connected to the gate electrode of the seventh transistor T7a.

[0085] In the eighth transistor T8a, the gate electrode can be connected to the second node N2a, the first electrode can be connected to the second output terminal OT2, and the second electrode can be connected to the second power terminal IV2. The gate electrode of the eighth transistor T8a can be connected to the gate electrode of the sixth transistor T6a. The second output terminal OT2 can be connected to the second scan line SL2.

[0086] In the ninth transistor T9a, the gate electrode can be connected to the fourth node N4a, the first electrode can be connected to the fourth clock terminal IK4, and the second electrode can be connected to the second output terminal OT2. The fourth clock terminal IK4 can be connected to the third clock line CKL3.

[0087] In the second capacitor C2a, the first electrode can be connected to the fourth node N4a, and the second electrode can be connected to the second output terminal OT2. The first electrode of the second capacitor C2a can be connected to the gate electrode of the ninth transistor T9a.

[0088] In the third capacitor C3a, the first electrode can be connected to the second node N2a, and the second electrode can be connected to the second power terminal IV2.

[0089] In the tenth transistor T10a, the gate electrode can be connected to the first power terminal IV1, the first electrode can be connected to the first node N1a, and the second electrode can be connected to the third node N3a.

[0090] In the eleventh transistor T11a, the gate electrode can be connected to the first power terminal IV1, the first electrode can be connected to the first node N1a, and the second electrode can be connected to the fourth node N4a. The tenth transistor T10a and the seventh transistor T7a can be referred to as the first pair of transistors, with the third node N3a between them. The eleventh transistor T11a and the ninth transistor T9a can be referred to as the second pair of transistors, with the fourth node N4a between them.

[0091] According to this embodiment, since two levels can be implemented as one level, the dead zone can be reduced.

[0092] Figure 5 The following is an explanation Figure 4 The sequence diagram of the example driver method at the level.

[0093] A first clock signal CK1 can be applied to a first clock line CKL1, a second clock signal CK2 can be applied to a second clock line CKL2, a third clock signal CK3 can be applied to a third clock line CKL3, and a fourth clock signal CK4 can be applied to a fourth clock line CKL4. The first clock signal CK1 to the fourth clock signal CK4 can be signals with the same frequency but different phases. For example, a first clock signal CK1 at a conduction level (logic low), a second clock signal CK2 at a conduction level, a third clock signal CK3 at a conduction level, and a fourth clock signal CK4 at a conduction level can be supplied sequentially.

[0094] First, a scan start signal FLM with an on level (logic low) can be applied to the scan start line FLML.

[0095] When the first clock signal CK1, which provides a conduction level, is applied at time t1a, the first transistor T1a and the fifth transistor T5a are turned on. When the first transistor T1a is turned on, the first node N1a can be discharged to a logic low level. In this case, because the tenth transistor T10a is turned on, the third node N3a can be discharged to a logic low level, and the seventh transistor T7a can be turned on. In addition, because the eleventh transistor T11a is turned on, the fourth node N4a can be discharged to a logic low level, and the ninth transistor T9a can be turned on.

[0096] When the first node N1a is discharged to a logic low level, the third transistor T3a can be turned on. Accordingly, a current path can be formed connecting the second power line VGHL, the third transistor T3a, the fifth transistor T5a, and the first power line VGLL. In this case, the current flowing through this path can be set to be sufficiently small.

[0097] For example, the width-to-length ratio of the channel of the third transistor T3a can be less than or equal to the width-to-length ratio of the channel of the fifth transistor T5a. When the width-to-length ratio of the channel of the third transistor T3a is less than that of the channel of the fifth transistor T5a, the second node N2a can remain at a logic low level at time t1a because the current flowing into the second node N2a through the third transistor T3a is less than the current output from the second node N2a through the fifth transistor T5a. Even if the width-to-length ratio of the channel of the third transistor T3a is the same as that of the channel of the fifth transistor T5a, the power consumption may not increase and / or drive errors may not occur because the current flowing through the aforementioned current path is sufficiently small.

[0098] When the first clock signal CK1, at time t2a, is supplied with a shutdown level (logic high), the first transistor T1a and the fifth transistor T5a can be turned off. It will be understood that from time t1a to time t2a, the second clock signal CK2 to the fourth clock signal CK4 have shutdown levels. In this situation, since the third transistor T3a remains on, the second node N2a can be charged with the second supply voltage (logic high).

[0099] When the second clock signal CK2, at a conduction level (logic low), is supplied at time t3a, the voltage of the third node N3a, coupled through the first capacitor C1a, can be lower than the logic low level. For example, for a portion of the time period between time t3a and time t4a, the voltage of the third node N3a can drop below the logic low level. Accordingly, a sufficiently high source-gate voltage can be applied to the seventh transistor T7a, and the first scan signal SO1, at a conduction level (logic low), can be output to the first scan line SL1. The pulse width of the first scan signal SO1 can correspond to the pulse width of the second clock signal CK2 at the conduction level.

[0100] In this configuration, the tenth transistor T10a prevents an excessively low voltage from the third node N3a from being applied to the first node N1a. Accordingly, the first node N1a can be kept at a logic low level, and thus it is possible to prevent stress from being applied to other transistors connected to the first node N1a (e.g., T1a, T2a, T3a, or T11a).

[0101] When the third clock signal CK3, at a conduction level (logic low), is supplied at time t4a, the voltage of the fourth node N4a, coupled through the second capacitor C2a, can be lower than the logic low level. For example, for a portion of the time period between time t4a and time t5a, the voltage of the fourth node N4a can drop below the logic low level. Accordingly, a sufficiently high source-gate voltage can be applied to the ninth transistor T9a, and the second scan signal SO2, at a conduction level (logic low), can be output to the second scan line SL2. The pulse width of the second scan signal SO2 can correspond to the pulse width of the third clock signal CK3 at the conduction level.

[0102] In this configuration, the eleventh transistor T11a prevents an excessively low voltage from the fourth node N4a from being applied to the first node N1a. Consequently, the first node N1a can be kept at a logic low level, and therefore, it is possible to prevent stress from being applied to other transistors connected to the first node N1a.

[0103] When the fourth clock signal CK4, at a conduction level (logic low), is supplied at time t5a, the second transistor T2a and the fourth transistor T4a can be turned on. In this case, since the scan start signal FLM is at a shutdown level (logic high), the first node N1a, the third node N3a, and the fourth node N4a can be charged to a logic high level. Additionally, the second node N2a can be discharged to a logic low level first supply voltage through the fourth transistor T4a.

[0104] Embodiments of the present invention provide a scan driver 13a, which includes multiple stages (ST1a, ST2a, ST3a, ST4a, ...), wherein the first stage ST1a includes: a first transistor T1a, including a gate electrode connected to a first clock terminal IK1, a first electrode connected to a first carry terminal IC1, and a second electrode connected to a first node N1a; a second transistor T2a, including a gate electrode connected to a second clock terminal IK2, a first electrode connected to a second carry terminal IC2, and a second electrode connected to the first node N1a; and a third transistor T3a, including a gate electrode connected to the first node N1a and a second electrode connected to a first node N1a. The first electrode is connected to the second node N2a; the fourth transistor T4a includes a gate electrode connected to the second clock terminal IK2, a first electrode connected to the first power terminal IV1, and a second electrode connected to the second node N2a; the fifth transistor T5a includes a gate electrode connected to the first clock terminal IK1, a first electrode connected to the first power terminal IV1, and a second electrode connected to the second node N2a; and the output section OPPa is configured to output a first scan signal SO1 to the first output terminal OT1 and a second scan signal SO2 to the second output terminal OT2 based on the voltage of the first node N1a and the voltage of the second node N2a.

[0105] Figures 6 to 10 This is a schematic view used to explain the first frame time period and the second frame time period according to an embodiment of the present invention.

[0106] The display device 10 can operate in a first display mode including a plurality of first frame periods FP1, or in a second display mode including a plurality of second frame periods FP2. The second frame periods FP2 can be longer than the first frame periods FP1. For example, the second frame period FP2 can be an integer multiple of the first frame periods FP1. For example, the second frame period FP2 can be 2p times the first frame period FP1, and p can be an integer greater than 0. Figure 6 In one embodiment, the second frame time period FP2 is twice the first frame time period FP1.

[0107] The first display mode is suitable for displaying moving images by displaying input images (e.g., frames) at a high frequency, and the second display mode is suitable for displaying still images by displaying input images at a low frequency. When a still image is detected while displaying a moving image, the display device 10 can switch from the first display mode to the second display mode. Conversely, when a moving image is detected while displaying a still image, the display device 10 can switch from the second display mode to the first display mode.

[0108] Reference Figure 6For ease of description, we will mainly describe the j-th data line DLj, the first pixel PX1j, and the second pixel PX2j. The first pixel PX1j can be connected to the j-th data line and the first scan line SL1. The second pixel PX2j can be connected to the j-th data line and the second scan line SL2.

[0109] In each first frame period FP1, the data driver 12 can sequentially apply data voltages corresponding to the scan lines to the data lines. For example, the data driver 12 can sequentially apply data voltages (DT1, DT2, ..., DT(m-1), DTm) to the j-th data line DLj. Assuming the first frame period FP1 is 1 / 60 second, the first data voltage DT1 can be supplied to the first pixel PX1j at 60Hz. Accordingly, the first pixel PX1j emits light with the highest brightness at the time when the first data voltage DT1 is applied, and then the brightness can gradually decrease due to leakage current. (Refer to...) Figure 6 The brightness waveform of the first pixel PX1j corresponding to multiple first frame time periods FP1 is shown as an example. This is... Figure 6 The top curve is shown.

[0110] Each second frame period FP2 may include a first subframe period SFP1 and a second subframe period SFP2. The lengths of the first subframe period SFP1 and the second subframe period SFP2 may be the same. For example, assuming the second frame period FP2 is 1 / 30 of a second, then each of the first subframe period SFP1 and the second subframe period SFP2 may be 1 / 60 of a second.

[0111] For example, in each first subframe period SFP1, the data driver 12 can sequentially apply data voltages corresponding to odd-numbered pixel rows to the data lines. A pixel row can refer to pixels connected to the same scan line. For example, the data driver 12 can sequentially apply data voltages (DT1, DT3, ..., DT(m-1)) to the j-th data line DLj. In each second subframe period SFP2, the data driver 12 can sequentially apply data voltages corresponding to even-numbered pixel rows to the data lines. For example, the data driver 12 can sequentially apply data voltages (DT2, DT4, ..., DTm) to the j-th data line DLj.

[0112] Accordingly, a first data voltage DT1 can be supplied to the first pixel PX1j at 30Hz. Consequently, the first pixel PX1j emits light with the highest brightness at the time the first data voltage DT1 is applied, and then its brightness may gradually decrease due to leakage current. (Refer to...) Figure 6The brightness waveform of the first pixel PX1j corresponding to multiple second frame time periods FP2 is shown as an example. Additionally, a second data voltage DT2 can be applied to the second pixel PX2j at 30Hz. Accordingly, the second pixel PX2j emits light with the highest brightness at the time the second data voltage DT2 is applied, and then its brightness may gradually decrease due to leakage current. (See reference...) Figure 6 The brightness waveform of the second pixel PX2j corresponding to multiple second frame time periods FP2 is shown as an example.

[0113] In this case, since the first pixel PX1j and the second pixel PX2j are positioned adjacent to each other, the first data voltage DT1 and the second data voltage DT2 can be substantially the same or similar in a typical input image.

[0114] Because the time points when the first pixel PX1j and the second pixel PX2j have the highest brightness are alternately located, the user can identify the average brightness waveform (AVG) of the first pixel PX1j and the second pixel PX2j as 60Hz. For example, when the second pixel PX2j emits light with the highest brightness, the first pixel PX1j emits light with a lower brightness, and vice versa. Therefore, even when switching between the first display mode and the second display mode, it is possible to prevent the observation of flickering caused by the difference in brightness waveforms.

[0115] According to this embodiment, each of the first subframe period SFP1 and the second subframe period SFP2 may include a data blanking period (BPC). The data blanking period (BPC) may be the remaining period after the data driver 12 has completed supplying the data voltage in each of the first subframe period SFP1 and the second subframe period SFP2. During the data blanking period (BPC), all or at least a portion of the data driver 12 (e.g., the gamma amplifier or digital logic) is de-energized, thereby reducing power consumption.

[0116] Reference Figure 7 This shows the control signals in the first frame time period FP1.

[0117] During the first frame period FP1, the timing controller 11 may sequentially apply on-level clock signals CK1, CK2, CK3, and CK4. For example, each cycle of the on-level clock signals CK1, CK2, CK3, and CK4 may consist of four horizontal periods.

[0118] Additionally, the timing controller 11 can apply a scan start signal FLM at the on level to the scan start line FLML. In this case, the length of the scan start signal FLM at the on level can be set to overlap with the first clock signal CK1 at the on level and the second clock signal CK2 at the on level. For example, the length of the scan start signal FLM at the on level can be two horizontal time intervals.

[0119] During the first frame period FP1, the scan driver 13a can alternately apply on-level scan signals (SO1, SO2, SO3, SO4, ...) to odd scan lines (SL1, SL3, ...) and even scan lines (SL2, SL4, ...).

[0120] Reference Figure 5 The driving method can generate a first scan signal SO1 at the conduction level corresponding to a second clock signal CK2 at the conduction level. Similarly, a second scan signal SO2 at the conduction level can be generated corresponding to a third clock signal CK3 at the conduction level. Likewise, a third scan signal SO3 at the conduction level can be generated corresponding to a fourth clock signal CK4 at the conduction level. Furthermore, a fourth scan signal SO4 at the conduction level can be generated corresponding to a first clock signal CK1 at the conduction level.

[0121] Data driver 12 can supply data voltage to synchronize with the scan signals (SO1, SO2, SO3, SO4, ...) at various conduction levels. For example, data driver 12 can supply data voltage in the current horizontal period in response to a grayscale latched by a data enable signal DE with a logic high level from the previous horizontal period. The logic high level of the data enable signal DE can correspond to the logic high level of the horizontal synchronization signal Hsync.

[0122] Reference Figure 8 This shows the control signals in the first subframe period SFP1 of the second frame period FP2. Specifically, Figure 8 The control signals for the first subframe period SFP1, excluding the data blank period BPC, are shown.

[0123] During the first subframe period SFP1, the timing controller 11 can maintain the first clock signal CK1 and the third clock signal CK3 at the off level, and can sequentially supply the fourth clock signal CK4 and the second clock signal CK2 at the on level.

[0124] In this embodiment, the period during which the second clock signal CK2 and the fourth clock signal CK4 at the conduction level are applied to the second clock line CKL2 and the fourth clock line CKL4 in the first subframe period SFP1 can be shorter than the period during which the second clock signal CK2 and the fourth clock signal CK4 at the conduction level are applied in the first frame period FP1. For example, each period of the second clock signal CK2 and the fourth clock signal CK4 at the conduction level can be two horizontal time periods.

[0125] During the first subframe period SFP1, the scan driver 13a can apply on-level scan signals (SO1, SO3, ...) to the odd-numbered scan lines (SL1, SL3, ...) and can maintain off-level scan signals (SO2, SO4, ...) in the even-numbered scan lines (SL2, SL4, ...). The on-time of the scan signals (SO1, SO3, ...) can correspond to the on-time of the second clock signal CK2 and the fourth clock signal CK4. The period of applying the on-level scan signals (SO1, SO3, ...) to the odd-numbered scan lines (SL1, SL3, ...) during the first subframe period SFP1 can be shorter than the period of applying the on-level odd-numbered scan signals (SO1, SO3, ...) during the first frame period FP1.

[0126] The data driver 12 can supply data voltage to synchronize with the odd scan signals (SO1, SO3, ...) at each conduction level.

[0127] Reference Figure 9 The diagram shows the control signals in the data blank period BPC of the second frame time period FP2. In the data blank period BPC, there are clock signals CK1, CK2, CK3 and CK4 that can be kept at the off level, scan signals (SO1, SO2, SO3, SO4, ...) at the off level, and scan start signal FLM at the off level.

[0128] As described above, during the data blank period (BPC), all or at least a portion of the data driver 12 (e.g., gamma amplifier or digital logic) is powered off, thereby reducing power consumption.

[0129] Reference Figure 10 This shows the control signals in the second subframe period SFP2 of the second frame period FP2. Specifically, Figure 10 The control signals for the second subframe period SFP2, excluding the data blank period BPC, are shown.

[0130] During the second subframe period SFP2, the timing controller 11 can maintain the second clock signal CK2 and the fourth clock signal CK4 at the off level, and can sequentially supply the first clock signal CK1 and the third clock signal CK3 at the on level.

[0131] In this embodiment, the period during the second subframe period SFP2 when the first clock signal CK1 and the third clock signal CK3 with the conduction level are applied to the first clock line CKL1 and the third clock line CKL3 can be shorter than the period during the first frame period FP1 when the first clock signal CK1 and the third clock signal CK3 with the conduction level are applied. For example, each period of the first clock signal CK1 and the third clock signal CK3 with the conduction level can be two horizontal time periods.

[0132] During the second subframe period SFP2, the scan driver 13a can apply on-level scan signals (SO2, SO4, ...) to even-numbered scan lines (SL2, SL4, ...) and maintain off-level scan signals (SO1, SO3, ...) in odd-numbered scan lines (SL1, SL3, ...). The on-time of the scan signals (SO2, SO4, ...) can correspond to the on-time of the first clock signal CK1 and the third clock signal CK3. The period of applying on-level scan signals (SO2, SO4, ...) to even-numbered scan lines (SL2, SL4, ...) during the second subframe period SFP2 can be shorter than the period of applying on-level even-numbered scan signals (SO2, SO4, ...) during the first frame period FP1.

[0133] The data driver 12 can supply data voltage to synchronize with the even-numbered scan signals (SO2, SO4, ...) at each conduction level.

[0134] Figure 11 The following is an explanation Figure 4 A schematic view of example variations of the level.

[0135] and Figure 4 Compared to the first-level ST1a, Figure 11 The first stage ST1a' also includes a twelfth transistor T12a', and the connection relationship of the third transistor T3a' is different. Since the other components of the first stage ST1a' are the same as those of the first stage ST1a, redundant descriptions are omitted. For example, the configurations of output section OPPa' and output section OPPa can be identical.

[0136] In the third transistor T3a', the gate electrode can be connected to the first node N1a, the first electrode can be connected to the second node N2a, and the second electrode can be connected to the second clock terminal IK2.

[0137] In the twelfth transistor T12a', the gate electrode can be connected to the first node N1a, the first electrode can be connected to the first clock terminal IK1, and the second electrode can be connected to the second node N2a. The gate electrode of the twelfth transistor T12a' can be connected to the gate electrode of the third transistor T3a'. Additionally, the second electrode of the twelfth transistor T12a' can be connected to the first electrode of the third transistor T3a'.

[0138] The first level ST1a' can be connected with Figures 5 to 10 The driving method is the same as the driving method, and therefore its redundant description will be omitted.

[0139] Figure 12 A schematic view is shown to explain a scan driver according to another embodiment of the present invention.

[0140] and Figure 3 Compared to the scan driver 13a, in Figure 12 In the scan driver 13b, each of the stages (ST1b, ST2b, ST3b, ST4b, ...) does not include the second carry terminal IC2.

[0141] Therefore, with Figure 3 Unlike other stages, the carry line used to connect the second carry terminal and the first output terminal OT1 of the previous stage is unnecessary. Accordingly, Figure 12 The scan driver 13b can further reduce the dead zone.

[0142] Figure 13 A schematic view is shown for explaining a level according to another embodiment of the invention.

[0143] Reference Figure 13 The first stage ST1b may include multiple transistors T1b, T2b, T3b, T4b, T5b, T6b, T7b, T8b, T9b, and T10b, as well as multiple capacitors C1b, C2b, and C3b. Other stages (ST2b, ST3b, ST4b, ...) of the scan driver 13b may also have the same or similar configuration as the first stage ST1b.

[0144] The first stage ST1b may include an output section OPPb, which outputs a first scan signal to a first output terminal OT1 and a second scan signal to a second output terminal OT2 based on the voltage of the first node N1b and the voltage of the second node N2b. In this embodiment, the output section OPPb may include a fifth transistor T5b to a tenth transistor T10b and a first capacitor C1b to a third capacitor C3b.

[0145] In the first transistor T1b, the gate electrode can be connected to the first clock terminal IK1, the first electrode can be connected to the first carry terminal IC1, and the second electrode can be connected to the first node N1b. The first clock terminal IK1 can be connected to the first clock line CKL1.

[0146] In the second transistor T2b, the gate electrode can be connected to the second clock terminal IK2, the first electrode can be connected to the first node N1b, and the second electrode can be connected to the second power terminal IV2. The second clock terminal IK2 can be connected to the fourth clock line CKL4. The second power terminal IV2 can be connected to the second power line VGHL.

[0147] In the third transistor T3b, the gate electrode can be connected to the first node N1b, the first electrode can be connected to the first clock terminal IK1, and the second electrode can be connected to the second node N2b. The gate electrode of the third transistor T3b can be connected to the first electrode of the second transistor T2b and the second electrode of the first transistor T1b.

[0148] In the fourth transistor T4b, the gate electrode can be connected to the first clock terminal IK1, the first electrode can be connected to the first power terminal IV1, and the second electrode can be connected to the second node N2b. The first power terminal IV1 can be connected to the first power line VGLL. The first transistors T1b to the fourth transistor T4b may not be included in the output section OPPb.

[0149] In the fifth transistor T5b, the gate electrode can be connected to the second node N2b, the first electrode can be connected to the first output terminal OT1, and the second electrode can be connected to the second power terminal IV2. The first output terminal OT1 can be connected to the first scan line SL1.

[0150] In the sixth transistor T6b, the gate electrode can be connected to the third node N3b, the first electrode can be connected to the third clock terminal IK3, and the second electrode can be connected to the first output terminal OT1. The third clock terminal IK3 can be connected to the second clock line CKL2.

[0151] In the first capacitor C1b, the first electrode can be connected to the third node N3b, and the second electrode can be connected to the first output terminal OT1.

[0152] In the seventh transistor T7b, the gate electrode can be connected to the second node N2b, the first electrode can be connected to the second output terminal OT2, and the second electrode can be connected to the second power terminal IV2. The second output terminal OT2 can be connected to the second scan line SL2. The gate electrode of the seventh transistor T7b and the gate electrode of the fifth transistor T5b can be connected to each other.

[0153] In the eighth transistor T8b, the gate electrode can be connected to the fourth node N4b, the first electrode can be connected to the fourth clock terminal IK4, and the second electrode can be connected to the second output terminal OT2. The fourth clock terminal IK4 can be connected to the third clock line CKL3.

[0154] In the second capacitor C2b, the first electrode can be connected to the fourth node N4b, and the second electrode can be connected to the second output terminal OT2.

[0155] In the ninth transistor T9b, the gate electrode can be connected to the first power terminal IV1, the first electrode can be connected to the first node N1b, and the second electrode can be connected to the third node N3b.

[0156] In the tenth transistor T10b, the gate electrode can be connected to the first power terminal IV1, the first electrode can be connected to the first node N1b, and the second electrode can be connected to the fourth node N4b.

[0157] In the third capacitor C3b, the first electrode can be connected to the second node N2b, and the second electrode can be connected to the second power terminal IV2.

[0158] According to this embodiment, since two levels can be implemented as one level, the dead zone can be reduced.

[0159] Figure 14 The following is an explanation Figure 13 The sequence diagram of the example driver method at the level.

[0160] A first clock signal CK1 can be applied to a first clock line CKL1, a second clock signal CK2 can be applied to a second clock line CKL2, a third clock signal CK3 can be applied to a third clock line CKL3, and a fourth clock signal CK4 can be applied to a fourth clock line CKL4. The first clock signal CK1 to the fourth clock signal CK4 can be signals with the same frequency but different phases. For example, a first clock signal CK1 at a conduction level (logic low), a second clock signal CK2 at a conduction level, a third clock signal CK3 at a conduction level, and a fourth clock signal CK4 at a conduction level can be supplied sequentially.

[0161] First, a scan start signal FLM with an on level (logic low) can be applied to the scan start line FLML.

[0162] When the first clock signal CK1, at time point t1b, is applied, the first transistor T1b and the fourth transistor T4b are turned on. When the first transistor T1b is turned on, the first node N1b can be discharged to a logic low level. In this case, because the ninth transistor T9b is turned on, the third node N3b can be discharged to a logic low level, and the sixth transistor T6b can be turned on. Additionally, because the tenth transistor T10b is turned on, the fourth node N4b can be discharged to a logic low level, and the eighth transistor T8b can be turned on. Furthermore, when the first node N1b is discharged to a logic low level, the third transistor T3b can be turned on.

[0163] Because the first clock signal CK1, which is at a turn-off level (logic high level), is supplied at time t2b, the first transistor T1b and the fourth transistor T4b can be turned off. In this case, because the third transistor T3b remains on, the second node N2b can be charged at a logic high level.

[0164] When the second clock signal CK2, at a conduction level (logic low), is supplied at time t3b, the voltage of the third node N3b, coupled through the first capacitor C1b, can be lower than the logic low level. For example, for the first portion of the time period between time t3b and time t4b, the voltage of the third node N3b can be lower than the logic low level, and for the second portion of the time period between time t3b and time t4b, the voltage of the third node N3b can be maintained at the logic low level. Accordingly, a sufficiently high source-gate voltage can be applied to the sixth transistor T6b, and the first scan signal SO1, at a conduction level (logic low), can be output to the first scan line SL1.

[0165] In this configuration, the ninth transistor T9b prevents an excessively low voltage from the third node N3b from being applied to the first node N1b. Consequently, the first node N1b can be kept at a logic low level, and therefore, it is possible to prevent stress from being applied to other transistors connected to the first node N1b.

[0166] Because a third clock signal CK3 with a conduction level (logic low) is supplied at time point t4b, the voltage of the fourth node N4b coupled through the second capacitor C2b can be lower than the logic low level. For example, for the first part of the time period between time points t4b and t5b, the voltage of the fourth node N4b can be lower than the logic low level, and for the second part of the time period between time points t4b and t5b, the voltage of the fourth node N4b can be maintained at the logic low level. Accordingly, a sufficiently high source-gate voltage can be applied to the eighth transistor T8b, and a second scan signal SO2 with a conduction level (logic low) can be output to the second scan line SL2.

[0167] In this configuration, the tenth transistor T10b prevents an excessively low voltage from the fourth node N4b from being applied to the first node N1b. Consequently, the first node N1b can be kept at a logic low level, and therefore, it is possible to prevent stress from being applied to other transistors connected to the first node N1b.

[0168] When the fourth clock signal CK4, at a logic low level, is supplied at time t5b, the second transistor T2b can be turned on. Accordingly, the first node N1b, the third node N3b, and the fourth node N4b can be charged to the second power supply voltage at a logic high level.

[0169] When the first clock signal CK1 (logic low level) is supplied at time t6b, the fourth transistor T4b can be turned on. Therefore, the second node N2b can be discharged to the first power supply voltage (logic low level) through the fourth transistor T4b.

[0170] Figure 15 The following is an explanation Figure 13 A schematic view of example variations of the level.

[0171] and Figure 13 Compared to the first-level ST1b, Figure 15 The first stage ST1b' has a different connection relationship with the second transistor T2b'. Since the other components of the first stage ST1b' are the same, redundant descriptions are omitted. For example, the output section OPPb' can have the same configuration as the output section OPPb.

[0172] In the second transistor T2b', the gate electrode can be connected to the second clock terminal IK2, the first electrode can be connected to the first power terminal IV1, and the second electrode can be connected to the second node N2b.

[0173] Figure 16 The following is an explanation Figure 15 The sequence diagram of the example driver method at the level.

[0174] Because until Figure 16 The driving method of time point t4b and until Figure 14 The driving method for time point t4b is essentially the same, so repeated descriptions are omitted.

[0175] When the fourth clock signal CK4, representing a logic low level, is supplied at time t5b', the second transistor T2b' can be turned on. Therefore, the second node N2b can be discharged to the first supply voltage (logic low level) through the second transistor T2b'. In other words, at time t5b', the second node N2b can have a logic low level.

[0176] When the first clock signal CK1, which provides the conduction level, is supplied at time point t6b', the first transistor T1b can be turned on. Accordingly, the first node N1b, the third node N3b, and the fourth node N4b can be charged to the logic high level of the scan start signal FLM. In other words, each of the first node N1b, the third node N3b, and the fourth node N4b can have a logic high level.

[0177] Although the invention has been described in conjunction with embodiments thereof, it will be understood that the invention is not limited to the disclosed embodiments, but rather that various changes and modifications can be made by those skilled in the art.

Claims

1. A scan driver comprising: a plurality of stages, wherein a first stage of the plurality of stages comprises: a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry terminal, and a second electrode connected to a first node; a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to a second carry terminal, and a second electrode connected to the first node; a third transistor including a gate electrode connected to the first node, and a first electrode connected to a second node; a fourth transistor including a gate electrode connected to the second clock terminal, a first electrode connected to a first power terminal, and a second electrode connected to the second node; a fifth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the first power terminal, and a second electrode connected to the second node; and an output configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal based on a voltage of the first node and a voltage of the second node. 2.The scan driver of claim 1, wherein the output comprises: a sixth transistor including a gate electrode connected to the second node, a first electrode connected to the first output terminal, and a second electrode connected to a second power terminal; a seventh transistor including a gate electrode connected to a third node, a first electrode connected to a third clock terminal, and a second electrode connected to the first output terminal; and a first capacitor including a first electrode connected to the third node, and a second electrode connected to the first output terminal. 3.The scan driver of claim 2, wherein the output further comprises: an eighth transistor including a gate electrode connected to the second node, a first electrode connected to the second output terminal, and a second electrode connected to the second power terminal; a ninth transistor including a gate electrode connected to a fourth node, a first electrode connected to a fourth clock terminal, and a second electrode connected to the second output terminal; and a second capacitor including a first electrode connected to the fourth node, and a second electrode connected to the second output terminal. 4.The scan driver of claim 3, wherein the output further comprises: a third capacitor including a first electrode connected to the second node, and a second electrode connected to the second power terminal; a tenth transistor including a gate electrode connected to the first power terminal, a first electrode connected to the first node, and a second electrode connected to the third node; and an eleventh transistor including a gate electrode connected to the first power terminal, a first electrode connected to the first node, and a second electrode connected to the fourth node. 5.The scan driver of claim 4, wherein a second electrode of the third transistor is connected to the second power terminal. 6.The scan driver of claim 4, wherein a second electrode of the third transistor is connected to the second clock terminal. 7.The scan driver of claim 6, wherein, the first stage further includes a twelfth transistor including a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to the second node. 8.The scan driver of claim 4, wherein, in a second stage of the plurality of stages, a first carry-in terminal is connected to the second output terminal of the first stage, a second carry-in terminal is connected to the first output terminal of the first stage, a first clock terminal is connected to the fourth clock terminal of the first stage, a second clock terminal is connected to the third clock terminal of the first stage, a third clock terminal is connected to the second clock terminal of the first stage, and a fourth clock terminal is connected to the first clock terminal of the first stage. 9.The scan driver of claim 8, wherein, the first carry-in terminal and the second carry-in terminal of the first stage are connected to each other. 10.The scan driver of claim 1, wherein, a width / length ratio of a channel of the third transistor is less than or equal to a width / length ratio of a channel of the fourth transistor or the fifth transistor. 11.A scan driver comprising: a plurality of stages, wherein a first stage of the plurality of stages includes: a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry-in terminal, and a second electrode connected to a first node; a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to the first node, and a second electrode directly connected to a second power terminal; a third transistor including a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to a second node; a fourth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to a first power terminal, and a second electrode connected to the second node; and an output configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal based on a voltage of the first node and a voltage of the second node. 12.The scan driver of claim 11, wherein, the output includes: a fifth transistor including a gate electrode connected to the second node, a first electrode connected to the first output terminal, and a second electrode connected to the second power terminal; a sixth transistor including a gate electrode connected to a third node, a first electrode connected to a third clock terminal, and a second electrode connected to the first output terminal; and a first capacitor including a first electrode connected to the third node and a second electrode connected to the first output terminal. 13.The scan driver of claim 12, wherein, the output further includes: a seventh transistor including a gate electrode connected to the second node, a first electrode connected to the second output terminal, and a second electrode connected to the second power terminal; an eighth transistor including a gate electrode connected to the fourth node, a first electrode connected to the fourth clock terminal, and a second electrode connected to the second output terminal; and a second capacitor including a first electrode connected to the fourth node and a second electrode connected to the second output terminal.

14. The scan driver of claim 13, wherein the output portion further includes: a ninth transistor including a gate electrode connected to the first power terminal, a first electrode connected to the first node, and a second electrode connected to the third node; a tenth transistor including a gate electrode connected to the first power terminal, a first electrode connected to the first node, and a second electrode connected to the fourth node; and a third capacitor including a first electrode connected to the second node and a second electrode connected to the second power terminal.

15. The scan driver of claim 14, wherein in a second stage of the plurality of stages, a first carry-in terminal is connected to the second output terminal of the first stage, a first clock terminal is connected to the fourth clock terminal of the first stage, a second clock terminal is connected to the third clock terminal of the first stage, a third clock terminal is connected to the second clock terminal of the first stage, and a fourth clock terminal is connected to the first clock terminal of the first stage.

16. A scan driver comprising: a plurality of stages, wherein a first stage of the plurality of stages includes: a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry-in terminal, and a second electrode connected to a first node; a second transistor including a gate electrode connected to a second clock terminal, a first electrode directly connected to a first power terminal, and a second electrode connected to a second node; a third transistor including a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to the second node; a fourth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the first power terminal, and a second electrode connected to the second node; and an output portion configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal based on a voltage of the first node and a voltage of the second node.

17. The scan driver of claim 16, wherein the output portion includes: a fifth transistor including a gate electrode connected to the second node, a first electrode connected to the first output terminal, and a second electrode connected to a second power terminal; a sixth transistor including a gate electrode connected to a third node, a first electrode connected to a third clock terminal, and a second electrode connected to the first output terminal; and a first capacitor including a first electrode connected to the third node and a second electrode connected to the first output terminal.

18. The scan driver of claim 17, wherein the output portion further includes: a seventh transistor including a gate electrode connected to the second node, a first electrode connected to the second output terminal, and a second electrode connected to the second power terminal; an eighth transistor including a gate electrode connected to a fourth node, a first electrode connected to a fourth clock terminal, and a second electrode connected to the second output terminal; and a second capacitor including a first electrode connected to the fourth node and a second electrode connected to the second output terminal.

19. The scan driver of claim 18, wherein the output further includes: a ninth transistor including a gate electrode connected to the first power terminal, a first electrode connected to the first node, and a second electrode connected to the third node; a tenth transistor including a gate electrode connected to the first power terminal, a first electrode connected to the first node, and a second electrode connected to the fourth node; and a third capacitor including a first electrode connected to the second node and a second electrode connected to the second power terminal.

20. The scan driver of claim 19, wherein in a second stage of the plurality of stages, a first carry-in terminal is connected to the second output terminal of the first stage, a first clock terminal is connected to the fourth clock terminal of the first stage, a second clock terminal is connected to the third clock terminal of the first stage, a third clock terminal is connected to the second clock terminal of the first stage, and a fourth clock terminal is connected to the first clock terminal of the first stage.

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