Data protection system for three-dimensional semiconductor devices and method thereof

Abstract

A data protection system and a data protection method for handling erroneous commands are disclosed. The data protection system includes a master device and a slave device. The master device is configured to send commands. The slave device is coupled to the master device. The slave device is configured to receive the commands from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface is electrically connected with the slave interface through one or more bonds and / or through silicon vias and is configured to perform interface functions between the master device and the slave device. An erroneous command represents a command having a parity error or other error. The slave device is further configured to receive the erroneous command and to respond to the erroneous command according to a read operation or a write operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a technology for a three dimensional (3D) semiconductor device, and more particularly, to a data protection system and a data protection method for a 3D semiconductor device. BACKGROUND

[0002] In recent years, a 3D semiconductor technology has emerged. By utilizing this technology, various semiconductor devices including a central processing unit (CPU) and a memory can be integrated into a single chip. The integration of the CPU and the memory is performed by vertically interconnecting the CPU and the memory. The structure of vertically interconnecting the CPU and the memory is generally referred to as a 3D integrated circuit (3D IC). By implementing the 3D IC, the size of an electronic device becomes compact and the production cost can be accordingly reduced. On the other hand, in order to create the 3D IC, interfaces and corresponding interconnections between, for example, the CPU and the memory need to be created and adjusted. Recently, some interfaces and corresponding interconnections have been proposed. However, since the 3D IC integrates the CPU and the memory into one system, the data communication between the CPU and the memory becomes more complex. In addition, the more data is transmitted and received between the CPU and the memory, the higher the possibility of errors occurring in the transmitted and received data. Therefore, a system and a method capable of distinguishing good data from error data and further capable of handling the error data become crucial. However, a reliable system and method to solve this problem are still under development. SUMMARY

[0003] The present disclosure provides a data protection system and a data protection method for a 3D semiconductor device. The data protection system provides reliable data communication between a master device and a slave device.

[0004] In an embodiment, the present disclosure provides a data protection system for handling an error command. The data protection system includes a master device and a slave device. The master device is configured to send a command. The slave device is coupled to the master device and configured to receive the command from the master device. The master device includes a master interface, the slave device includes a slave interface, and the master interface and the slave interface are electrically connected through one or more bonds and / or through silicon vias (TSVs) and configured to perform an interface function between the master device and the slave device. The error command represents the command with a parity error. The slave device is further configured to receive the error command and respond to the error command according to a read operation or a write operation.

[0005] In an embodiment, the present disclosure also provides a data protection method for handling an error command. A master device includes a master interface, a slave device includes a slave interface, and the master interface and the slave interface are electrically connected through one or more bonds and / or through-silicon vias (TSVs) and configured to interface between the master device and the slave device. The data protection method includes sending, by the master interface, a command; and receiving, by the slave interface, the command from the master device. The error command represents the command with a parity error. An operation of receiving the error command by the slave device and responding to the error command is performed according to a read operation or a write operation.

[0006] In order to make the above more comprehensible, several embodiments of the accompanying drawings will be described in detail below. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain principles of the present disclosure.

[0008] Figure 1 a block diagram schematically showing a data protection system including a master device and a slave device according to an embodiment of the present disclosure;

[0009] Figure 2 a block diagram schematically showing a data protection system including a master device and a slave device according to an embodiment of the present disclosure;

[0010] Figure 3 a block diagram schematically showing a data protection system including a master device and a plurality of slave devices according to an embodiment of the present disclosure;

[0011] Figure 4 a design diagram schematically showing a data protection system including a master chip and a slave chip according to an embodiment of the present disclosure;

[0012] Figure 5 a design diagram schematically showing a data protection system including a master chip and a plurality of slave chips according to an embodiment of the present disclosure;

[0013] Figure 6 a 3D diagram schematically showing a data protection system including an example of an interface device structure according to an embodiment of the present disclosure;

[0014] Figure 7 a schematic diagram schematically showing an interface device including a master interface and a plurality of slave interfaces according to an embodiment of the present disclosure;

[0015] Figure 8 a schematic diagram schematically showing an interface device including a master chip and a slave chip during a read operation according to an embodiment of the present disclosure;

[0016] Figure 9 Schematic diagram of a slave interface according to an embodiment of the present disclosure is shown schematically;

[0017] Figure 10 Schematic diagram of a slave interface according to an embodiment of the present disclosure is shown schematically;

[0018] Figure 11 Interface method according to an embodiment of the present disclosure is shown schematically.

[0019] Explanation of symbols

[0020] 100, 200, 300, 400, 500, 600: data protection system

[0021] 101, 111: interface device

[0022] 102, 501-2: master interface

[0023] 103, 103-1-103-N, Glink-3D slaves: slave interface

[0024] 104, 406, 412, 502-3, 502-4, 503-3: through silicon via (TSV)

[0025] 105: master device

[0026] 106: master device

[0027] 107, 115: clock generator

[0028] 108-1-108-M: central processing unit (CPU)

[0029] 110, 110-1-110-N: slave device

[0030] 120, 501-1: master chip

[0031] 130: slave chip

[0032] 402: processor chip

[0033] 404: processor interface

[0034] 408: memory chip

[0035] 410: memory interface

[0036] 414, 506: connector

[0037] 502-1: first slave chip

[0038] 502-2: first slave interface

[0039] 503-1: second slave chip

[0040] 503-2: second slave interface

[0041] 504: TSV connection

[0042] 700, 800: schematic diagram

[0043] 702, 703-1, 703-2, 703-3, 710, 712, 712-1, 712-2, 714, 804: flip-flop FF

[0044] 704, 716: DDR MUX

[0045] 706-1, 706-2, 706-3: bonding member

[0046] 708-1, 708-2, 708-3: bonding member

[0047] 718, 720: buffer

[0048] 801: SRAM

[0049] 802: logic unit

[0050] 900: bonding member diagram

[0051] S1102, S1104, S1106, S1108, S1110, S1112: step

[0052] S1114, S1116, S1118, S1120, S1122, S1124: step

[0053] address wr_data, CS, rx_data command, tx_data command, WR: command

[0054] add_cnt[31:0]: address data block

[0055] add_cnt[63:32]: address data block

[0056] clk, clk_in, clk_out: clock

[0057] CLK, C_LR, RDQS_R, RDQS_F, VDD, VSS: bit

[0058] Glink-3D master: master interface

[0059] Glink-3D slaveK, Glink-3D slaveN: interface

[0060] M_CMD0, M_CMD1: bits

[0061] M_DID0 - M_DID3: bits

[0062] M_PAR: parity bit

[0063] RD: read command

[0064] R_D0 - R_D15: data

[0065] R_LR: lane repair bit

[0066] R_PAR: parity bit

[0067] address rd_data, rx_data, tx_data, tx_data[15:0], tx_data[31:16]: data

[0068] S_CMD0, S_CMD1: bits

[0069] S_DID0 - S_DID3: bits

[0070] slave_ID: slave chip address

[0071] S_PAR: parity bit

[0072] T_D0 - T_D15: bits

[0073] T_PAR: parity bit

[0074] tx_data[31:0]: intentionally erroneous data

[0075] tx_data[127:96]: transmitted data block

[0076] tx_en: enable signal DETAILED DESCRIPTION

[0077] The following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature on top of or in another feature in the description below can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be in direct contact. In addition, the present disclosure can make use of the same reference numbers and / or letters in various instances. Such repetitions are for the purpose of simplicity and clarity and do not themselves indicate a relationship between the various embodiments and / or configurations discussed.

[0078] Moreover, spatial or directional terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used in this specification to describe one element's or feature's relationship to another element or feature as illustrated in the figures. The spatial and directional terms are used for purposes of clarity and convenience in understanding the illustrations of the figures. The spatial and directional terms are not intended to limit the device to the specific orientations or configurations shown in the figures. The device can have other orientations or configurations (rotated 90 degrees or otherwise) and the spatially relative terms used herein are intended to encompass such other orientations and configurations.

[0079] The present disclosure discloses a data protection system and a data protection method for a 3D semiconductor device. The data protection system provides reliable data communication between a master device and a slave device. The reliable data communication is generated by distinguishing correct data from error data. The data protection system also handles error data by a specific method, so that the data protection system can respond properly in the case of error data. By responding to error data properly, reliable data transmission and reception can be maintained and reliable data communication can be achieved accordingly.

[0080] For example, a data protection system for a 3D IC includes a processor and a plurality of memories. Data communication between the processor and the plurality of memories includes write operations and read operations. For example, during a read operation, the processor sends a command to one of the memories, and the memory accordingly receives the command. However, the command received by the memory is not always the same as the command sent by the processor. In the case where the command received by the memory is different from the command sent by the processor, an error has occurred. Therefore, the memory needs a mechanism to check whether the command received by the memory is the same as the command sent by the processor. The checking mechanism is performed, for example, by detecting parity error of the command received by the memory. If there is a parity error in the command received by the memory, the command received by the memory is different from the command sent by the processor. In this case, the memory sends intentional error data to the processor, and the processor receives the same intentional error data as the error data and responds to the intentional error data. Since the processor receives the intentional error data, the processor realizes that an error has occurred in the command received by the memory. By implementing such a case, the processor and the memory perform a corresponding interrupt to the data protection system. On the other hand, in the case where an error has occurred in the command received by the memory but the memory does not send intentional error data to the processor, the processor does not realize that an error has occurred in the command received by the memory. Therefore, when the memory does not send data or intentional error data to the processor in response to the command sent by the processor, the processor loses one data. Therefore, the read operation of the plurality of data in response to the plurality of commands sent by the processor will be erroneous. In particular, a data protection system and a data protection method for a 3D IC in both write operations and read operations will be described in detail as follows.

[0081] Figure 1 A block diagram of a data protection system including a master device and a slave device according to embodiments of the present disclosure is schematically shown. The data protection system 100 is implemented in, for example, the following 3D packaging: chip-on-wafer-on-substrate (CoWoS), system-on-integrated-chip (SoIC), wafer-on-wafer (WoW), and other 3D packaging integration.

[0082] Reference Figure 1The data protection system 100 includes a master chip 120, a slave chip 130, and a clock generator 115. The master chip 120 is coupled to the slave chip 130 through a through-silicon-via (TSV) 104. The master chip 120 includes a master device 105 and a master interface 102 coupled to the master device 105. On the other hand, the slave chip 130 includes a slave device 110 and a slave interface 103 coupled to the slave device 110. The master device 105 is coupled to the slave device 110 through the master interface 102 and the slave interface 103. The master interface 102 and the slave interface 103 are coupled through the TSV 104 and integrated together as an interface apparatus 101. The interface apparatus 101 is adapted to connect the master device 105 and the slave device 110 vertically, which forms a 3D semiconductor device. The structure of the interface apparatus 101 is referred to as Glink-3D. In addition, the clock generator 115 generates a clock for driving the master device 105, the master interface 102, the slave interface 103, and the slave device 110. The clock generated by the clock generator 115 is used in a forward direction and a reverse direction for the master interface 102 and the slave interface 103.

[0083] In an embodiment, the master device 105 and the slave device 110 are implemented as, for example, a processor and a memory, such as a static random access memory (SRAM), respectively. The clock generator 115 is implemented by, for example, an oscillator. The connection between the master interface 102 and the slave interface 103 is implemented by a TSV with a parallel bus for transferring data at a sampling rate of up to 5.0 Gbps or a double data rate (DDR) of 2.5 GHz. The parallel bus is also used to couple between the slave device 110 and the slave interface 103 and also between the master device 105 and the master interface 102. In an embodiment, the latency between the master device 105 and the slave device 110 is set to 1 ns to 2 ns. The data transfer between the master device 105 and the slave device 110 has a low bit error or no bit error (no BER).

[0084] Figure 2 A block diagram of a data protection system including a master device and a slave device is schematically shown according to an embodiment of the present disclosure. Figure 2 The data protection system 200 shown in FIG. 2 is similar to the data protection system 100 shown in FIG. 1. Figure 1 The data protection system 200 shown in FIG. 2 is similar to the data protection system 100 shown in FIG. 1. Figure 1 The data protection system 200 shown in FIG. 2 is similar to the data protection system 100 shown in FIG. 1.

[0085] Figure 3 A block diagram of a data protection system including a master device and a plurality of slave devices is schematically shown according to an embodiment of the present disclosure.Figure 3 The data protection system 300 shown in FIG. 3 is similar to the data protection system 100 shown in FIG. 1. Figure 1 The data protection system 300 shown in FIG. 3 is similar to the data protection system 100 shown in FIG. 1. The difference is that the master device 105 includes a plurality of central processing units (CPUs) 108-1 to 108-M. In addition, the interface device 111 includes the master interface 102 and a plurality of slave interfaces 103-1 to 103-N. Each slave interface 103-1 to 103-N is coupled to each slave device 110-1 to 110-N in a one-to-one relationship. N and M are integers equal to or greater than 1. In addition, the clock generator 115 generates a clock for driving the master device 105 having the plurality of CPUs 108-1 to 108-M, the master interface 102, the plurality of slave interfaces 103-1 to 103-N, and the plurality of slave devices 110-1 to 110-N. The clock generator 115 can be included in the master device 105 as shown in FIG. 2. Figure 2 The data protection system 300 shown in FIG. 3 is similar to the data protection system 100 shown in FIG. 1.

[0086] Figure 4 A design diagram of a data protection system including a master chip and a slave chip according to embodiments of the disclosure is shown schematically. The data protection system 400 is arranged vertically to form a 3D package and includes, for example, a master / processor / chip 1 chip 402 coupled with a master interface 404, a slave / memory / chip 2 chip 408 coupled with a slave memory interface 410. The processor chip 402 and the memory chip 408 are coupled via the processor interface 404 and the memory interface 410 through the plurality of TSVs 406. In addition, the memory chip 408 includes the plurality of TSVs 412 and the plurality of connections 414.

[0087] Figure 5 A design diagram of a data protection system including a master chip and a plurality of slave chips according to embodiments of the disclosure is shown schematically. The data protection system 500 is arranged vertically to form a 3D package and includes, for example, a master chip 501-1 coupled to a master interface 501-2, a plurality of first slave chips 502-1 coupled to a plurality of first slave interfaces 502-2, and a plurality of second slave chips 503-1 coupled to a plurality of second slave interfaces 503-2. The plurality of first slave chips 502-1 includes TSVs 502-4. The master interface 501-2 is coupled to the plurality of first slave interfaces 502-2 through TSVs 502-3 and to the plurality of second slave interfaces 503-2 through TSVs 503-3. In addition, the data protection system includes TSV connections 504 connecting the master interface 501-2 to connections 506.

[0088] In an embodiment, the data protection system (i.e., 500) supports face-to-face interfaces and face-to-back interfaces. For example, the interface between the master chip 501-1 and the first slave chip 502-1 and / or the interface between the master chip 501-1 and the second slave chip 503-1 is a face-to-face interface. And the face-to-back interface is used for the interface between each first slave chip 502-1 and / or the interface between each second slave chip 503-1.

[0089] Figure 6 A 3D diagram of a data protection system including an example of an interface device structure according to an embodiment of the disclosure is schematically shown. The data protection system 600 includes a CPU core chip coupled to a Glink-3D master as a master interface and cache chips coupled to Glink-3D slaves as slave interfaces. The Glink-3D master is coupled to the Glink-3D slaves through TSVs. For example, during a read operation, the CPU core chip sends a command to the cache chips through the Glink-3D master and the Glink-3D slaves. And then, the cache chips receive the command from the CPU core chip. The cache chips generate data according to the command and send the data to the CPU core chip through the Glink-3D slaves and the Glink-3D master. Finally, the CPU core chip receives the data from the cache chips. Moreover, the data communication between the CPU core chip and the cache chips through the Glink-3D master and the Glink-3D slaves is driven by a clock generated by a clock generator (i.e., 115).

[0090] In this embodiment, the Glink-3D master and the Glink-3D slaves have the same structure and are connected in a one-to-one relationship. For example, each Glink-3D master and Glink-3D slave includes a plurality of blocks. Each block is divided into a plurality of cells, for example, 5x5 cells. Each cell of the Glink-3D master is connected to each cell of the Glink-3D slave in a one-to-one relationship through TSVs. This Glink-3D structure is used as a physical layer of, for example, an advance microcontroller bus architecture coherent hub interface (AMBA CHI) protocol. The details of the interface device including the Glink-3D master and the Glink-3D slaves on a 3D semiconductor device and the corresponding implementation will be further explained as follows.

[0091] Figure 7 A schematic diagram of an interface device including a master interface and a plurality of slave interfaces according to embodiments of the disclosure is shown schematically. The schematic diagram 700 can be implemented using a plurality of electronic components (i.e., flip-flops (FFs), multiplexers (MUXs), inverters, and buffers).

[0092] Referring to Figure 7 Glink-3D master is used as the interface of the master chip. Glink-3D slaveK and Glink-3D slaveN are used as the interface of the slaveK chip and the interface of the slaveN chip, respectively. Glink-3D master, Glink-3D slaveK, and Glink-3D slaveN are driven by a clock clk_in generated by a clock generator (i.e., 115). Glink-3D master, Glink-3D slaveK, and Glink-3D slaveN are electrically connected by one or more bonds and / or TSVs. For example, Glink-3D master bonds 706-1 to 706-3 are connected to Glink-3D slaveN bonds 708-1 to 708-3 in a one-to-one relationship using TSVs.

[0093] In this embodiment, Glink-3D master includes FF 702, DDR MUX 704, bonds 706-1 to 706-3, and a read first-in-first-out (FIFO) including a plurality of FFs 703-1 to 703-3. FF 702 is coupled to DDR MUX 704 and receives a command tx_data command from the master chip. The command tx_data command can include a slave_ID used as a slave chip address. DDR MUX 704 is coupled to bond 706-1 and proceeds the command tx_data command to Glink-3D slaveN through bonds 706-1 and 708-1 in a DDR data format. FF 703-1 is coupled to FF 703-2 and bond 706-3. FF 703-3 is coupled to FF 703-2 and the master chip and sends data rx_data to the master chip. FF 702, DDR MUX 704, bond 706-2, and FF 703-3 are driven by a clock generator (i.e., 115) that generates clk_in. FFs 703-1 and 703-2 are driven by a local clock generated by, for example, Glink-3D slaveN through bonds 706-3 and 708-3.

[0094] In this embodiment, Glink-3D slaveN includes junctions 708-1 to 708-3, FFs 710 to 714, DDR MUX 716, and buffers 718 and 720. Junction 708-1 is coupled to junction 706-1 and FF 710 sends command rx_datacommand to the slaveN chip. Junction 708-2 is coupled to junction 706-2 and sends clock clk to the slaveN chip. FF 712 is coupled to DDR MUX 716 and the slaveN chip and receives data tx_data from the slaveN chip. FF 714 is coupled to the slaveN chip and receives enable signal tx_en. Buffer 720 is coupled to DDR MUX 716 and junction 708-3 and sends data tx_data in DDR data format. Buffer 718 is coupled to junction 708-3 and sends local clock to Glink 3D master through junctions 708-3 and 706-3. FFs 710 to 714 and DDR MUX 716 are driven by clock clk. Buffers 718 and 720 are driven by enable signal tx_en. In addition, slaveK chip and corresponding Glink-3D slaveK have the same structure and data communication as slaveN chip and Glink-3D slaveN. The difference between Glink-3D slaveN and Glink-3D slaveK is the generation of local clock.

[0095] Figure 8 A schematic diagram of interface devices including master and slave chips during a read operation is shown schematically in accordance with an embodiment of the present disclosure. Schematic diagram 800 is similar to schematic diagram 700. The difference between schematic diagram 800 and schematic diagram 700 is that schematic diagram 800 shows, for example, one slaveN chip and SRAM 801 with corresponding Glink-3D slaveN. In addition, logic unit 802 and FF 804 are also included.

[0096] Reference is made to Figure 8During a read operation, the master chip sends a command address wr_data including a chip identification (ID) as an address of the slave chip N to the SRAM 801 through the Glink-3D master and the Glink-3D slave N. The logic unit 802 is coupled to the Glink-3D slave N, the SRAM 801, and the FF 804. The FF 804 is coupled to the Glink-3D slave N. The logic unit 902 generates a signal for selecting between a chip select (CS) command, a read (RD) command, or a write (WR) command. The logic unit 802 and the corresponding FF 804 generate an enable signal tx_en. The SRAM 901 generates data tx_data according to the command. The Glink-3D slave N sends the data tx_data to the Glink-3D master in a DDR data format. The master chip reads the data rd_data according to a local clock of the master chip.

[0097] In an embodiment, the data protection system handles an error command. For example, the processor 105 sends a command to the slave N device through the Glink-3D master and the Glink-3D slave N. Since the data communication between the processor 105 and the slave N device can be disturbed by external factors (i.e., noise), the command sent by the processor 105 can be changed. Thus, the slave N device receives a command having a different value from the command sent by the processor 105. The command having a different value from the command sent by the processor 105 is referred to as an error command.

[0098] Figure 9 A binding diagram of an interface device including a master interface and a slave interface according to an embodiment of the present disclosure is schematically shown. The binding diagram 900 shows a mapping of a binding between, for example, the Glink-3D master and the Glink-3D slave N. Each binding in the Glink-3D master is electrically connected to the Glink-3D slave N in a one-to-one relationship through a TSV. The Glink-3D master receives a command from the processor 105. Thus, the Glink-3D master is driven by a clock clk_in generated by the clock generator 115. And then, the Glink-3D slave N sends the command to the slave N device. Thus, the Glink-3D slave N sends a clock clk_out to the slave N. The Glink-3D slave N receives data from the slave N device. And then, the Glink-3D master sends the data to the processor 105.

[0099] In this embodiment, the error command represents a command with parity error. For example, Glink-3D master includes four blocks of data transmitted, two blocks of address data, one block of command data, and four blocks of data received. Each block includes 4x5 (20) junctions. Each junction represents a bit connection. On the other hand, Glink-3D slaveN includes four blocks of data received, two blocks of address data, one block of command data, and four blocks of data transmitted. Each block includes 4x5 (20) junctions. Each junction represents a bit connection. Each junction of Glink-3D master is electrically connected in a one-to-one relationship to each junction of Glink-3D slaveN.

[0100] For example, the command data block of Glink-3D master includes 4 bits of master-to-slave ID (M_DID0 to M_DID3), 2 bits of read / write (R / W) command (M_CMD0, M_CMD1), 1 bit of parity (M_PAR), 2 bits of local clock (RDQS_R, RDQS_F), 1 bit of lane repair (C_LR), 2 bits of voltage (VDD, VSS), 1 bit of clock (CLK), 4 bits of slave-to-master ID (S_DID0 to S_DID3), 2 bits of read / write (R / W) command (S_CMD0, S_CMD1), and 1 bit of parity (S_PAR). On the other hand, the command data block of Glink-3D slaveN is the same as the command data block of Glink-3D master. The command data block of Glink-3D slaveN includes 4 bits of master-to-slave ID (M_DID0 to M_DID3), 2 bits of read / write (R / W) command (M_CMD0, M_CMD1), 1 bit of parity (M_PAR), 2 bits of local clock (RDQS_R, RDQS_F), 1 bit of lane repair (C_LR), 2 bits of voltage (VDD, VSS), 1 bit of clock (CLK), 4 bits of slave-to-master ID (S_DID0 to S_DID3), 2 bits of read / write (R / W) command (S_CMD0, S_CMD1), and 1 bit of parity (S_PAR).

[0101] The one-to-one relationship between each of the Glink-3D master's bindings and, for example, a Glink-3D slaveN is that, for example, the first bit of the master-to-slave ID of the Glink-3D master (MJDID0) is coupled to the first bit of the master-to-slave ID of the Glink-3D slaveN (MJDID0), the second bit of the master-to-slave ID of the Glink-3D master (MJDID1) is coupled to the second bit of the master-to-slave ID of the Glink-3D slaveN (MJDID1), and so on.

[0102] An even parity error occurs, for example, when the parity bit type is odd, in the case where the total number of bits in the command data block is even. For example, the processor 105 sends a command to slaveN. The command can include all blocks (four transmitted data blocks, two address data blocks, one command data block, and four received data blocks). The values of MJDID0 to MJDID3, M_CMD0, M_CMD1, M_PAR of the Glink-3D master are different from the values of MJDID0 to MJDID3, M_CMD0, M_CMD1, M_PAR of the Glink-3D slaveN. The values of MJDID0 to MJDID3, M_CMD0, M_CMD1 of the Glink-3D master are 1, 0, 0, 0, 0, 1, respectively. Since the parity bit type is odd, the value of M_PAR of the Glink-3D master is 1. Thus, the total value (in binary format) of MJDID0 to MJDID3, M_CMD0, M_CMD1, M_PAR of the Glink-3D master is odd 1. On the other hand, the values of MJDID0 to MJDID3, M_CMD0, M_CMD1, M_PAR of the Glink-3D slaveN are 1, 1, 0, 0, 0, 1, 1, respectively. The total value (in binary format) of MJDID0 to MJDID3, M_CMD0, M_CMD1, M_PAR of the Glink-3D slaveN is even 0. Thus, an even parity error occurs, where the even parity error represents an erroneous command received by the slaveN device.

[0103] In this embodiment, the slave N device is also configured to receive an error command and respond to the error command according to the read operation or the write operation. Since the blocks of the Glink-3D master and the Glink-3D slave N during the write operation have different values from the blocks of the Glink-3D master and the Glink-3D slave N during the read operation, the slave N device responds differently between the command sent by the processor 105 during the write operation and the command sent by the processor 105 during the read operation. The different responses of the slave N device between the write operation and the read operation and the corresponding responses from the processor 105 will be further illustrated in the following embodiments. In addition, the slave N device with the corresponding Glink-3D slave N is taken as an example to simplify the description. Other slave devices with the corresponding Glink-3D slaves also perform as the slave N device with the corresponding Glink-3D slave N.

[0104] In another embodiment, during the read operation, the slave device (i.e., the slave N device) is also configured to send data to the master device (i.e., the processor 105) according to the command received from the master device (i.e., the processor 105), and the other slave device (i.e., the slave K device) is also configured to send other data to the master device (i.e., the processor 105) according to the command received from the master device (i.e., the processor 105).

[0105] For example, the ID values of the slave N device and the slave K device are “1000” and “0100”, respectively. The value of the write operation and the read operation is “01”. The parity bit type is even. The processor 105 reads the address 0 of the slave N device or the slave K device. Therefore, for example, during the read operation of the slave N device, all values of the first T_D0 to T_D15 of the address data block of the Glink-3D master including the corresponding parity bit are 0, all values of the second T_D0 to T_D15 of the address data block of the Glink-3D master including the corresponding parity bit are 0, and the values of S_DID0 to S_DID3, S_CMD0, S_CMD1, S_PAR of the command data block of the Glink-3D master are 1, 0, 0, 0, 0, 1, 0. This means that the processor 105 sends the command of the read operation to the address 0 of the slave N device.

[0106] In response to the processor 105 sending a command of a read operation to the slaveN device, the slaveN device sends data to the processor 105. For example, the data has 64 bits, which are divided into 4 blocks. All values of the data of the slaveN device at address 0 including the parity bit are 0. Therefore, all values of the first T_D0 to T_D15 (first main data) of the data block of the Glink-3D slaveN including the corresponding parity bit (first parity bit) are 0, all values of the second T_D0 to T_D15 (second main data) of the data block of the Glink-3D slaveN including the corresponding parity bit (second parity bit) are 0, all values of the third T_D0 to T_D15 (third main data) of the data block of the Glink-3D slaveN including the corresponding parity bit (third parity bit) are 0, and all values of the fourth T_D0 to T_D15 (fourth main data) of the data block of the Glink-3D slaveN including the corresponding parity bit (fourth parity bit) are 0. This means that the slaveN device sends the data at address 0 to the processor 105 in response to the read operation command sent by the processor 105.

[0107] Another example, during a read operation to the slaveK device, all values of the first T_D0 to T_D15 of the address data block of the Glink-3D master including the corresponding parity bit are 0, all values of the second T_D0 to T_D15 of the address data block of the Glink-3D master including the corresponding parity bit are 0, and the values of S_DID0 to S_DID3, S_CMD0, S_CMD1, S_PAR of the command data block of the Glink-3D master are 0, 1, 0, 0, 0, 1, 0. This means that the processor 105 sends a command of a read operation to the slaveK device at address 0.

[0108] In response to the processor 105 sending a command of a read operation to the slaveK device, the slaveK device sends data to the processor 105. For example, the data has 64 bits, which is divided into 4 blocks. All values of the data of the slaveK device at address 0 including the parity bit are 0. Thus, all values of the first T_D0 to T_D15 of the data block of the Glink-3D slaveK including the corresponding parity bit are 0, all values of the second T_D0 to T_D15 of the data block of the Glink-3D slaveK including the corresponding parity bit are 0, all values of the third T_D0 to T_D15 of the data block of the Glink-3D slaveK including the corresponding parity bit are 0, and all values of the fourth T_D0 to T_D15 of the data block of the Glink-3D slaveK including the corresponding parity bit are 0. This means that the slaveK device sends the data at address 0 to the processor 105 in response to the command of the read operation sent by the processor 105.

[0109] In an embodiment, the command has higher protection than the data / other data. The command includes, for example, 1 parity bit for 6 bits of the command. On the other hand, the data includes, for example, 1 parity bit for 16 bits of the data. For example, refer to Figure 9The command data block of the Glink-3D master includes 4 bits of master-to-slave ID (MJDID0 to MJDID3), 2 bits of read / write (R / W) command (M_CMD0, M_CMD1), and 1 bit of parity (M_PAR). The command data block of the Glink-3D master also includes 4 bits of slave-to-master ID (SJDID0 to SJDID3), 2 bits of read / write (R / W) command (S_CMD0, S_CMD1), and 1 bit of parity (S_PAR). That is, for a write operation, the command includes 1 bit of parity (M_PAR), 4 bits of master-to-slave ID (MJDID0 to MJDID3), and 2 bits of read / write (R / W) command (M_CMD0, M_CMD1). And for a read operation, the command includes 1 bit of parity (S_PAR), 4 bits of slave-to-master ID (SJDID0 to SJDID3), and 2 bits of read / write (R / W) command (S_CMD0, S_CMD1). On the other hand, for example, the transmitted data block of the Glink-3D master includes 16 bits of transmitted data (T_D0 to T_D15) and 1 bit of parity (T_PAR). That is, the data includes 1 bit of parity (T_PAR) and 16 bits of transmitted data (T_D0 to T_D15). In other words, the command includes 1 parity check bit and 6 bits of ID and R / W command, and the data / other data includes 1 parity check bit for 16 bits of data. That is, the protection of the command is higher than the protection of the data.

[0110] In an embodiment, the slave device (i.e., slaveN device) sends intentional error data to the master device (i.e., processor 105) in response to an error command received by the slave device (i.e., slaveN device), and the other slave device (i.e., slaveK device) sends other intentional error data to the master device (i.e., processor 105) in response to an error command received by the other slave device (i.e., slaveK device). The data / other data and the intentional error data / other intentional error data include one or more master data and parity check bits. The intentional error data / other intentional error data is generated by inverting the parity check bits of the data / other data.

[0111] For example, during a read operation to the slaveN device, the processor 105 sends a command of the read operation to the address 0 of the slaveN device. Since the data configuration in the Glink-3D master has been set forth, the explanation will not be repeated thereafter. Since the slaveN device receives an error command, the values in the Glink-3D slaveN are different from the values in the Glink-3D master, for example. For example, the values of the SJDID0 to SJDID3, S_CMD0, S_CMD1, S_PAR of the command data block of the Glink-3D slaveN are 0, 1, 0, 0, 0, 1, 1 with a total value (binary format) of 1. Since the parity bit type is even 0, the total value of 1 means that a parity error has occurred. This occurrence of the parity error represents the error command.

[0112] In response to the error command received by the slaveN device, the slaveN device sends intentional error data to the processor 105. The intentional error data includes one or more master data and a parity bit. The intentional error data is generated by inverting the parity bit of the data. The intentional error data includes, for example: all values of the first TJD0 to TJD15 (first master data) of the data block of the Glink-3D slaveN are 0 and the corresponding parity bit (first parity bit) is 1; all values of the second TJD0 to TJD15 (second master data) of the data block of the Glink-3D slaveN are 0 and the corresponding parity bit (second parity bit) is 1; all values of the third TJD0 to TJD15 (third master data) of the data block of the Glink-3D slaveN are 0 and the corresponding parity bit (third parity bit) is 1; and all values of the fourth TJD0 to TJD15 (fourth master data) of the data block of the Glink-3D slaveN are 0 and the corresponding parity bit (fourth parity bit) is 1. That is, the intentional error data includes the master data and the parity bit, and the intentional error data is generated by inverting the parity bit.

[0113] Another example, during a read operation to the slaveK device, the processor 105 sends a command of the read operation to the address 0 of the slaveK device. Since the slaveN device receives an erroneous command, the value in the Glink-3D slaveN, for example, is different from the value in the Glink-3D master. In response to the erroneous command received by the slaveK device, the slaveK device sends other intentional erroneous data to the processor 105. The other intentional erroneous data includes one or more other master data with corresponding parity bits. The other intentional erroneous data is generated by inverting the corresponding parity bits of the other data. The other intentional erroneous data includes, for example: all values of the first T_D0 to T_D15 (first other master data) of the data block of the Glink-3D slaveK are 0 and the corresponding parity bit (first parity bit) is 1; all values of the second T_D0 to T_D15 (second other master data) of the data block of the Glink-3D slaveK are 0 and the corresponding parity bit (second parity bit) is 1; all values of the third T_D0 to T_D15 (third other master data) of the data block of the Glink-3D slaveK are 0 and the corresponding parity bit (third parity bit) is 1; and all values of the fourth T_D0 to T_D15 (fourth other master data) of the data block of the Glink-3D slaveK are 0 and the corresponding parity bit (fourth parity bit) is 1. That is, the other intentional erroneous data includes other master data with corresponding parity bits, and the other intentional erroneous data is generated by inverting the corresponding parity bits.

[0114] Figure 10 A schematic diagram of a DDR configuration of a slave interface according to an embodiment of the disclosure is shown. Figure 10 The shown schematic diagram includes FFs 712-1 and 712-2, a multiplexer 716, a buffer 720, and a junction 708-3. Figure 10 The shown FFs 712-1 and 712-2 represent Figure 7 The shown FF 712, Figure 10 The shown multiplexer 716 represents Figure 7 The shown multiplexer 716, Figure 10 The shown buffer 720 represents Figure 7 The shown buffer 720, and Figure 10 The shown junction 708-3 represents Figure 7 The shown junction 708-3.

[0115] In Figure 9 and Figure 10In the illustrated embodiment, the intentional error data / other intentional error data is sent using a double data rate (DDR) configuration. Since the DDR configuration of the intentional error data is the same as the DDR configuration of the other intentional error data, for brevity purposes, the DDR configuration is only described with respect to the intentional error data. Moreover, where the slave device and the other slave device perform the same processing, hereinafter, the processing is only described with respect to the slave device.

[0116] Referring to Figure 7 , Figure 9 and Figure 10 , the intentional error data (i.e., tx_data[31:0]) is sent to the processor 105 using a DDR configuration via the Glink-3D slaveN and the Glink-3D master. For example, the FF 712-1 delivers tx_data[31:16] and the FF 712-2 delivers tx_data[15:0]. The tx_data[31:16] and the tx_data[15:0] are delivered to the bond 708-3 that is electrically connected to the corresponding bond of the Glink-3D master via the multiplexer 716 and the buffer 720.

[0117] Specifically, the bond 708-3 has 4x5 (20) bonds with mapped data, e.g., T_D0 to T_D15, T_PAR, T_LR, VDD, and VSS. The buffer 720 delivers the tx_data[31:16] and the tx_data[15:0] consecutively. For example, the intentional error data has 0 values except for the parity bit that is inverted. The buffer 720 delivers the tx_data[31:16] to the bond 708-3 with the corresponding lane repair bit and the inverted parity bit. And then, the buffer 720 delivers the tx_data[15:0] to the bond 708-3 with the corresponding lane repair bit and the inverted parity bit. That is, the intentional error data (tx_data[31:0]) is sent to the processor 105 using a DDR configuration.

[0118] In another embodiment, the master device (i.e., the processor 105) is also configured to receive error data or intentional error data from the slave device (i.e., the slaveN device), and / or configured to receive other error data or other intentional error data from the other slave device (i.e., the slaveK device). The one or more master data of the error data / other error data has a different value than the one or more master data of the data / other data. The master device (i.e., the processor 105) handles the intentional error data / other intentional error data in the same manner as the error data / other error data by reporting a failure of a read operation.

[0119] For example, with reference to Figure 9 During a read operation, all values of the first transmitted data (T_DO to T_D15) of the Glink-3D slave N including the parity bit (T_PAR) are 0. In the case where no error has occurred, all values of the first received data (R_DO to R_D15) of the Glink-3D master including the parity bit (R_PAR) are 0. However, in the case where an error has occurred, all values of the first received data (R_DO to R_D14) of the Glink-3D master including the parity bit (R_PAR) except for R_D15 are 0. Since the parity error type is even, the error is detected when the total value of R_DO to R_D15 including R_PAR is odd. That is, for the error data, the value of R_D15 when no error has occurred is different from the value of R_D15 when an error has occurred.

[0120] On the other hand, during a read operation, all values of the first transmitted data (T_DO to T_D15) of the Glink-3D slave N are 0 and the value of the parity bit (T_PAR) is 1 due to the parity error type being even. In other words, in the case where a deliberate error has been generated, all values of the first received data (R_DO to R_D15) of the Glink-3D master are 0 and the value of the parity bit (R_PAR) is 1. The error is detected when the total value of R_DO to R_D15 including R_PAR is odd. That is, for the deliberate error data, when a deliberate error has occurred, the value of T_PAR is inverted, and as a result, the parity error has been detected by the processor 105. Accordingly, the processor 105 reports the error caused by the error data or the deliberate error data as a read operation failure.

[0121] In another embodiment, the command includes one or more address data with corresponding address data parity bits, and read command and identification (ID) data with corresponding read command and ID data parity bits. In the one or more address data with corresponding address data parity bits and / or the read command and ID data with corresponding read command and ID data parity bits, the command has different values from an error command. In response to receiving an error command from the master device (i.e., the processor 105), the slave device / other slave device (i.e., the slaveN device, the slaveK device) does not read data / other data of the slave device / other slave device (i.e., the slaveN device, the slaveK device), and the slave device / other slave device (i.e., the slaveN device, the slaveK device) sends intentional error data / other intentional error data to the master device (i.e., the processor 105).

[0122] For example, referring to Figure 9 , a command in the Glink-3D master includes two address data blocks (add_cnt[31:0], add_cnt[63:32]) and one command data block. Each of the first address data block add_cnt[31:0] and the second address data block add_cnt[63:32] includes transmitted address data (T_D0 to T_D15), parity bits (T_PAR), lane repair bits (T_LR), and VSS and VDD. Since the command data block has been described, the description will not be repeated. On the other hand, a command in the Glink-3D slaveN includes two address data blocks (add_cnt[31:0], add_cnt[63:32]) and one command data block. Each of the first address data block add_cnt[31:0] and the second address data block add_cnt[63:32] includes received address data (R_D0 to R_D15), parity bits (R_PAR), lane repair bits (R_LR), and VSS and VDD.

[0123] During a read operation, when an error occurs, the Glink-3D slaveN receives an error command instead of a command. For example, all values in the first address data T_DO to T_D15 of the first address data block add_cnt[31:0] of the Glink-3D master including the parity bit T_PAR are 0. And all values in the command data block of the Glink-3D master with the corresponding parity bit are 0. On the other hand, all values in the first address data R_DO to R_D14 of the first address data block add_cnt[31:0] of the Glink-3D slaveN including the parity bit R_PAR except R_D15 are 0. And all values in the command data block of the Glink-3D slaveN with the corresponding parity bit are 0. Since the parity bit error type is even, the slaveN device will detect the command received through the Glink-3D slaveN as an error command. That is, in the one or more address data with the corresponding address data parity bit, the command and the error command have different values.

[0124] Another example, all values in the first address data block add_cnt[31:0] and the second address data block add_cnt[63:32] of the Glink-3D master are 0. And all values of the master to slave ID S_DID0 to S_DID3, the read command S_CMD0 and S_CMD1, and the parity bit S_PAR of the Glink-3D master are 0. On the other hand, all values in the first address data block add_cnt[31:0] and the second address data block add_cnt[63:32] of the Glink-3D slaveN are 0. And all values in the master to slave ID S_DID0 to S_DID2, the read command S_CMD0 and S_CMD1, and the parity bit S_PAR of the Glink-3D slaveN except S_DID3 are 0. Since the parity bit error type is even, the slaveN device will detect the command received through the Glink-3D slaveN as an error command. That is, in the read command and ID data with the corresponding read command and ID data parity bit, the command and the error command have different values.

[0125] In response to the erroneous command received by the slaveN device, the slaveN device does not read the data at address 0 sent by the processor 105. As described above, the address received by the slaveN device has changed, which represents an erroneous address, and / or the slave ID received by the slaveN device has changed, which represents an erroneous slave ID. Accordingly, the slaveN device generates intentional erroneous data and sends the intentional erroneous data to the processor 105.

[0126] In another embodiment, the master device (i.e., the processor 105) receives the intentional erroneous data / intentional erroneous data from the slave device / other slave device (i.e., the slaveN device, the slaveK device). For example, in response to the intentional erroneous data sent by the slaveN device over the Glink-3D slaveN, the processor 105 receives the intentional erroneous data over the Glink-3D master.

[0127] In another embodiment, the master device (i.e., the processor 105) further includes a master device interrupt and a master error counter, the slave device (i.e., the slaveN device) further includes a slave device interrupt and a slave device error counter, and the other slave device (i.e., the slaveK device) further includes an other slave device interrupt and an other slave device error counter. In response to the master device (i.e., the processor 105) receiving the intentional erroneous data / intentional erroneous data, the master device (i.e., the processor 105) sets the master device interrupt and increments the master error counter, and the slave device / other slave device (i.e., the slaveN device, the slaveK device) sets the slave device interrupt / other slave device interrupt and increments the slave device error counter / other slave device error counter.

[0128] The master device interrupt / slave device interrupt / other slave device interrupt can be an interrupt to the data protection system, i.e., 300. The master device interrupt / slave device interrupt / other slave device interrupt can be an interrupt to the code currently being executed. The master device interrupt can be used to interrupt the processor 105 from reading data from the slave device. The master device interrupt can be implemented by rebooting the data protection system, i.e., 300, and resetting the read first-in-first-out, i.e., FFs 703-1 to 703-3. The slave device interrupt / other slave device interrupt can be used to interrupt, for example, the slaveN device / slaveK device from reading data at the corresponding address. The master device interrupt / slave device interrupt / other slave device interrupt can be implemented by setting a corresponding interrupt bit / flag. The master error counter can be implemented in response to an interrupt generated by the processor 105. The slave device error counter / other slave device error counter can be implemented in response to an interrupt generated by, for example, the slaveN device / slaveK device. The master error counter / slave device error counter / other slave device error counter can be implemented as a bit / flag.

[0129] For example, during a read operation, the processor 105 sends a read command to the slaveN device to read address 0. However, due to an error, the slaveN device receives an error command. In response, the slaveN device generates intentional error data and sends the intentional error data to the processor 105. The processor 105 receives the intentional error data sent by the slaveN device. The processor 105 identifies that the data received from the slaveN device is erroneous by, for example, checking the parity error. In response, the processor 105 sets the master interrupt flag and increments the corresponding master error counter. Accordingly, the slaveN device sets the slave device interrupt flag and increments the corresponding slave error counter.

[0130] In another embodiment, the command includes one or more write data with corresponding write data parity bits, one or more address data with corresponding address data parity bits, and write command and identification (ID) data with corresponding write command and ID data parity bits. The command has different values from the error command in the one or more write data with corresponding write data parity bits, and / or the one or more address data with corresponding address data parity bits, and / or the write command and ID data with corresponding write command and ID data parity bits. During a write operation, in response to receiving an error command from the master device (i.e., the processor 105), the slave device / other slave device (i.e., the slaveN device, the slaveK device) does not execute the error command to prevent the one or more write data from being written to the slave device / other slave device (i.e., the slaveN device, the slaveK device).

[0131] Referring to Figure 9For example, during a write operation, the processor 105 sends a command to the slaveN device. The command includes: transmitted data blocks tx_data[3l:0] to tx_data[127:96] and corresponding parity bits (T_D0 to T_D15, T_PAR) for each transmitted data block; address data blocks add_cnt[31:0] to add_cnt[63:32] and corresponding parity bits (T_D0 to T_D15, T_PAR) for each address data block; and command data blocks and corresponding parity bits for each write command (M_DID0 to M_DID3, M_CMD0, M_CMD1, M_PAR) and read command (S_DID0 to S_DID3, S_CMD0, S_CMD1, S_PAR) of the Glink-3D master. All values of the transmitted data with corresponding parity bits are 0. All values of the address data with corresponding parity bits are 0. All values of the write commands with corresponding parity bits except M_CMD1 are 0. And all values of the read commands with corresponding parity bits are 0. M_CMD1 has a value of 1 to represent that the processor 105 sends a write command instead of a read command. M_DID0 to M_DID3 have a value of 0 to represent, for example, the slaveN device. T_D0 to T_D15 of the address data blocks have a value of 0 to represent an address 0 of the slaveN device. T_D0 to T_D15 of the transmitted data blocks have a value of 0 to represent that data 0 is to be written to the address 0 of the slaveN device.

[0132] In the case that an error has occurred, the Glink-3D slaveN receives an error command. Since the command sent by the processor 105 has transmitted data with a value of 0, the Glink-3D slaveN receives received data with a value of 0 (i.e., the first received data block except R_D15) when an error has occurred. That is, the Glink-3D slaveN receives an error command with a value of R_D15 of the first received data block that is different from the value of T_D15 of the first transmitted data block. The error can not always occur in the received data, the error can occur in the address data, the write ID, the write command, the parity bits, or a combination thereof.

[0133] In response to the error command received by the slaveN device (i.e., R_D15 of the first received data block that is different from T_D15 of the first transmitted data block), the slaveN device does not execute the command sent by the processor 105. The slaveN device does not write the received data R_D0 to R_D15 of all received data blocks to the address 0 of the slaveN device. By doing so, the command with, for example, the error data can be prevented from being written to the slaveN device.

[0134] In another embodiment, the slaveN device / other slave device further comprises a slave device interrupt / other slave device interrupt and a slave device error counter / other slave device error counter. In response to the slaveN device / other slave device not executing an error command, the slaveN device / other slave device discards the error command, sets the slave device interrupt / other slave device interrupt, and increments the slave device error counter / other slave device error counter.

[0135] For example, the slave device interrupt / other slave device interrupt can be an interrupt to a data protection system. The slave device interrupt / other slave device interrupt can be an interrupt to code currently being executed. The slave device interrupt / other slave device interrupt can be used to interrupt, for example, the slaveN device / slaveK device from writing data to a corresponding address. The slave device interrupt / other slave device interrupt can be implemented by setting a corresponding interrupt bit / flag. The slave device error counter / other slave device error counter can be implemented in response to an interrupt generated by, for example, the slaveN device / slaveK device. The slave device error counter / other slave device error counter can be implemented as a bit / flag.

[0136] The slaveN device discards the command with, for example, the error data R_D15. In response to the slaveN device not executing the command with, for example, the error data R_D15, the slaveN device increments a slave device error counter by, for example, adding one to the slave device error counter. By incrementing the slave device error counter, the slaveN device records the number of errors that occur for a write operation and / or a read operation.

[0137] Figure 11 An interface method according to embodiments of the present disclosure is schematically illustrated.

[0138] In Figure 11 In the illustrated embodiment, a data protection method for handling error commands during, for example, a read operation includes steps S1102-S1124. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected by one or more bonds and / or through silicon vias and are configured to interface between the master device and the slave device.

[0139] In step S1102, a read command is sent to the slaveN device. In step S1104, the read command is received from the processor 105. In step S1106, the slaveN device checks whether an error has occurred by, for example, checking for parity error. If no error has occurred, in step S1108, data on a corresponding address of the slaveN device is read according to the read command. In step S1110, the data read by the slaveN device is sent to the processor 105. In step S1112, the data is read by the processor 105. If an error has occurred in step S1106, in step S1114, the read command is discarded by the slaveN device. In step S1116, intentional error data is generated by the slaveN device. In step S1118, the intentional error data is sent to the processor 105. In step S1120, the intentional error data is received by the processor 105. In step S1122, a slaveN device interrupt is set and a slaveN device error counter is incremented. In step S1124, a processor device interrupt is set and a processor error counter is incremented. That is, during a read operation, the slaveN device and the processor 105 set a corresponding interrupt and increment a corresponding error counter.

[0140] In summary, a data protection system and a data protection method are provided. The data protection system includes a master device and a plurality of slave devices. The master device communicates with the plurality of slave devices through a master interface and a slave interface. During a read operation, in case an error has occurred, a slave device receives an error command. In response to the error command received by the slave device, the slave device does not execute the command and accordingly sets a corresponding interrupt and increments a corresponding error counter. Accordingly, the slave device generates intentional error data and sends the intentional error data to the master device. The master device receives the intentional error data and accordingly sets a corresponding interrupt and increments a corresponding error counter. During a write operation, in case an error has occurred, a slave device receives an error command. In response to the error command received by the slave device, the slave device does not execute the command and accordingly sets a corresponding interrupt and increments a corresponding error counter. That is, during a read operation, by distinguishing the error command, a slave device generates intentional error data. Accordingly, by distinguishing the intentional error data received by the master device, the data protection system implements protection on data transceived between the master device and the plurality of slave devices.

[0141] In another embodiment, a data protection system for handling an error command includes a master device and a slave device. The master device is configured to send a command. The slave device is coupled to the master device and configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface is electrically connected with the slave interface through one or more bonds and / or TSVs and is configured to interface between the master device and the slave device. The error command represents the command with a parity error. The slave device is further configured to receive the error command and respond to the error command according to a read operation or a write operation.

[0142] In another embodiment, the data protection system further includes other slave devices. The other slave devices are coupled to other slave interfaces in a one-to-one relationship and configured to receive the command from the master device. The other slave interfaces are electrically connected to the master interface through the one or more bonds and / or the TSVs. The other slave devices are further configured to receive the error command and respond to the error command according to a read operation or a write operation.

[0143] In another embodiment, during a read operation, the slave device is further configured to send data to the master device according to the command received from the master device. The other slave devices are further configured to send other data to the master device according to the command received from the master device. The command has a higher protection than the data / other data. The slave device sends intentional error data to the master device in response to the error command received by the slave device. The other slave devices send other intentional error data to the master device in response to the error command received by the other slave devices. The data / other data and the intentional error data / other intentional error data include one or more main data and parity bits. The intentional error data / other intentional error data is generated by inverting the parity bits of the data / other data.

[0144] In another embodiment, the intentional error data / other intentional error data is sent using a double data rate (DDR) configuration. In another embodiment, the master device is further configured to receive error data or the intentional error data from the slave device and / or configured to receive other error data or the other intentional error data from the other slave devices. The one or more main data of the error data / other error data have different values from the one or more main data of the data / other data. The master device handles the intentional error data / other intentional error data in the same way as the error data / other error data by reporting a failure of a read operation.

[0145] In another embodiment, the command includes one or more address data with corresponding address data parity bits, and a read command and identification (ID) data with corresponding read command and ID data parity bits. The command has different values than the error command in the one or more address data with corresponding address data parity bits, and / or the read command and ID data with corresponding read command and ID data parity bits. In response to the error command received from the master device, the slave device / the other slave device does not read the data / other data of the slave device / the other slave device, and the slave device / the other slave device sends the intentional error data / other intentional error data to the master device.

[0146] In another embodiment, the master device receives the intentional error data / other intentional error data sent by the slave device / the other slave device. In another embodiment, the master device further includes a master device interrupt and a master error counter. The slave device further includes a slave device interrupt and a slave device error counter. The other slave device further includes an other slave device interrupt and an other slave device error counter. In response to the master device receiving the intentional error data / other intentional error data, the master device sets the master device interrupt and increments the master error counter, and the slave device / the other slave device sets the slave device interrupt / other slave device interrupt and increments the slave device error counter / other slave device error counter.

[0147] In another embodiment, the command includes one or more write data with corresponding write data parity bits, one or more address data with corresponding address data parity bits, and a write command and identification (ID) data with corresponding write command and ID data parity bits. The command has different values than the error command in the one or more write data with corresponding write data parity bits, and / or the one or more address data with corresponding address data parity bits, and / or the write command and ID data with corresponding write command and ID data parity bits. In response to the error command received from the master device, the slave device / the other slave device does not execute the error command to prevent the one or more write data from being written to the slave device / the other slave device during a write operation.

[0148] In another embodiment, the slave device / other slave device further comprises a slave device interrupt / other slave device interrupt and a slave device error counter / other slave device error counter. In response to the slave device / other slave device not executing the error command, the slave device / other slave device discards the error command, sets the slave device interrupt / other slave device interrupt, and increments the slave device error counter / other slave device error counter.

[0149] In another embodiment, a data protection method for handling error commands includes steps. A master device comprises a master interface. A slave device comprises a slave interface. The master interface is electrically connected with the slave interface through one or more bonds and / or TSVs and is configured to interface between the master device and the slave device. The steps are: sending a command by the master interface; and receiving the command by the slave interface from the master device. The error command represents the command with a parity error. An operation of receiving the error command by the slave device and responding to the error command is performed according to a read operation or a write operation.

[0150] In another embodiment, the data protection method further comprises: receiving the error command by other slave device and responding to the error command according to a read operation or a write operation.

[0151] In another embodiment, during a read operation, an operation of sending data to the master device by the slave device according to the command received from the master device is performed, and an operation of sending other data to the master device by the other slave device according to the command received from the master device is performed. The command has higher protection than the data / other data. In response to receiving the error command by the slave device, an operation of sending intentional error data to the master device by the slave device is performed, and in response to receiving the error command by the other slave device, other intentional error data is sent to the master device by the other slave device. The data / other data and the intentional error data / other intentional error data comprise one or more master data and parity check bits. The intentional error data / other intentional error data is generated by inverting the parity check bits of the data / other data.

[0152] In another embodiment, the intentional error data / the other intentional error data is sent using a double data rate (DDR) configuration. In another embodiment, the operation of receiving error data or the intentional error data from the slave device and / or other error data or the other intentional error data from the other slave device is performed by the master device. The one or more master data of the error data / other error data has a different value than the one or more master data of the data / other data. The operation of handling the intentional error data / the other intentional error data in the same manner as handling the error data / the other error data is performed by the master device by reporting a failure of a read operation.

[0153] In another embodiment, the command includes one or more address data with corresponding address data parity bits, and a read command and identification (ID) data with corresponding read command and ID data parity bits. The command has a different value than the error command in the one or more address data with corresponding address data parity bits and / or the read command and ID data with corresponding read command and ID data parity bits. In response to the error command received from the master device, the slave device / the other slave device does not perform the operation of reading the data / other data of the slave device / the other slave device, and the slave device / the other slave device performs the operation of sending the intentional error data / the other intentional error data to the master device.

[0154] In another embodiment, the operation of receiving the intentional error data / the other intentional error data sent by the slave device / the other slave device is performed by the master device. In another embodiment, the master device further includes a master device interrupt and a master error counter. The slave device further includes a slave device interrupt and a slave device error counter. The other slave device further includes an other slave device interrupt and an other slave device error counter. In response to the operation of receiving the intentional error data / the other intentional error data being performed by the master device, the master device interrupt is set and the master error counter is incremented by the master device, and the slave device interrupt / the other slave device interrupt is set and the slave device error counter / the other slave device error counter is incremented by the slave device / the other slave device.

[0155] In another embodiment, the command includes one or more write data with corresponding write data parity bits, one or more address data with corresponding address data parity bits, and a write command and identification (ID) data with corresponding write command and ID data parity bits. The command has different values than the error command in the one or more write data with corresponding write data parity bits, and / or the one or more address data with corresponding address data parity bits, and / or the write command and ID data with corresponding write command and ID data parity bits. In response to the error command received from the master device during a write operation, the slave device / the other slave device does not perform an operation to execute the error command to prevent the one or more write data from being written to the slave device / the other slave device.

[0156] In another embodiment, the slave device / the other slave device further includes a slave device interrupt / the other slave device interrupt and a slave device error counter / the other slave device error counter. In response to the slave device / the other slave device not performing an operation to execute the error command, the slave device / the other slave device performs an operation to discard the error command, set the slave device interrupt / the other slave device interrupt, and increment the slave device error counter / the other slave device error counter.

[0157] The foregoing has outlined rather broadly the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or for achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize from the disclosure that equivalent constructions thereof do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A data protection system for handling erroneous commands, characterized in that, include: The master device is configured to send commands; as well as The slave device, coupled to the master device, is configured to receive the command from the master device, wherein... The master device includes a master interface, the slave device includes a slave interface, and the master interface and the slave interface are electrically connected via one or more bonding elements and / or through-silicon vias (TSVs) and configured to perform interface functions between the master device and the slave device. The erroneous command represents a command with a parity error or other errors. The slave device is also configured to receive the error command and respond to the error command based on a read operation or a write operation. During the read operation, the slave device is also configured to send data to the master device according to a command received from the master device, the command having a higher level of authentication protection than the data. The slave device sends intentionally erroneous data to the master device in response to the erroneous command received by the slave device. The data includes one or more master data bits and a parity check bit; the intentionally erroneous data includes one or more master data bits and a parity check bit. The intentional erroneous data is generated by reversing the parity check bit of the data.

2. The data protection system according to claim 1, characterized in that, It also includes other slave devices, which are coupled to other slave interfaces in a one-to-one relationship and are configured to receive the commands from the master device. The other slave interfaces are electrically connected to the master interface via one or more bonding elements and / or the through-silicon vias. The other slave devices are also configured to receive the error command and respond to the error command in accordance with a read or write operation.

3. The data protection system according to claim 2, characterized in that, During the read operation, the other slave devices are also configured to send additional data to the master device according to the commands received from the master device. The command described therein has a higher level of verification protection than the other data. The other slave device, in response to the erroneous command received by the other slave device, sends other intentionally erroneous data to the master device. The other data mentioned above includes one or more master data bits and parity check bits, and the other intentionally erroneous data includes one or more master data bits and parity check bits. The other intentional erroneous data mentioned above is generated by inverting the parity check bit of the other data.

4. The data protection system according to claim 3, characterized in that, The intentional erroneous data / other intentional erroneous data is transmitted using a double data rate configuration.

5. The data protection system according to claim 3, characterized in that, The master device is also configured to receive erroneous data or the intentional erroneous data from the slave device, and / or to receive other erroneous data or the other intentional erroneous data from the other slave devices. The one or more master data of the erroneous data have values ​​that are different from the one or more master data of the data or the one or more master data of the other data, wherein the one or more master data of the other erroneous data have values ​​that are different from the one or more master data of the data or the one or more master data of the other data. The master device thereunder handles the intentional erroneous data / other intentional erroneous data in the same manner as the erroneous data / other erroneous data by reporting the failure of the read operation.

6. The data protection system according to claim 3, characterized in that, The command includes one or more address data with corresponding address data parity check bits, and a read command and identification data with corresponding read command and identification (ID) data parity check bits. In the one or more address data with corresponding address data parity check bits and / or the read command and identification data with corresponding read command and identification (ID) data parity check bits, the command and the erroneous command have different values. In response to the erroneous command received from the master device, the slave device / other slave device does not read the data / other data of the slave device / other slave device, and the slave device / other slave device sends the intentional erroneous data / other intentional erroneous data to the master device.

7. The data protection system according to claim 3, characterized in that, The master device receives the intentional erroneous data / other intentional erroneous data sent by the slave device / other slave device.

8. The data protection system according to claim 3, characterized in that, The master device also includes a master device interrupt and a master error counter; the slave device also includes a slave device interrupt and a slave device error counter; and the other slave devices also include other slave device interrupts and other slave device error counters. In response to the master device receiving the intentional erroneous data / other intentional erroneous data, the master device sets the master device interrupt and increments the master error counter, and the slave device / other slave device sets the slave device interrupt / other slave device interrupt and increments the slave device error counter / other slave device error counter.

9. The data protection system according to claim 2, characterized in that, The command includes one or more write data with corresponding write data parity bits, one or more address data with corresponding address data parity bits, and write command and identifier data with corresponding write command and identifier (ID) data parity bits. In the one or more write data having corresponding write data parity check bits, and / or the one or more address data having corresponding address data parity check bits, and / or the write command and identifier (ID) data having corresponding write command and identifier (ID) data parity check bits, the command and the error command have different values. During a write operation, in response to an error command received from the master device, the slave device / other slave device does not execute the error command to prevent one or more write data from being written to the slave device / other slave device.

10. The data protection system according to claim 9, characterized in that, The slave device / other slave devices also include slave device interrupt / other slave device interrupt and slave device error counter / other slave device error counter. In response to the slave device / other slave device not executing the erroneous command, the slave device / other slave device discards the erroneous command, sets the slave device interrupt / other slave device interrupt, and increments the slave device error counter / other slave device error counter.

11. A data protection method for handling erroneous commands, wherein a master device includes a master interface, a slave device includes a slave interface, and the master interface and the slave interface are electrically connected via one or more bonding elements and / or through-silicon vias (TSVs) and configured to interface between the master device and the slave device, characterized in that, The data protection method includes: Commands are sent from the main interface; and The command is received from the master device via the slave interface, wherein During a read operation, the slave device sends data to the master device based on the command received from the master device. The erroneous command represents a command with a parity error. Based on a read or write operation, the slave device receives the error command and responds to it. The command has a higher level of verification protection than the data. In response to receiving the erroneous command by the slave device, the slave device performs the operation of sending intentionally erroneous data to the master device. The data includes one or more master data bits and a parity check bit; the intentionally erroneous data includes one or more master data bits and a parity check bit. The intentional erroneous data is generated by reversing the parity check bit of the data.

12. The data protection method according to claim 11, characterized in that, Also includes: The error command is received by other slave devices based on a read operation or a write operation, and the error command is responded to.

13. The data protection method according to claim 12, characterized in that, During the read operation, the other slave devices send additional data to the master device according to the commands received from the master device. The command described therein has a higher level of verification protection than the other data. In response to receiving the erroneous command from the other slave device, the other slave device sends other intentionally erroneous data to the master device. The other data mentioned above includes one or more master data bits and parity check bits, and the other intentionally erroneous data includes one or more master data bits and parity check bits. The other intentional erroneous data mentioned above is generated by inverting the parity check bit of the other data.

14. The data protection method according to claim 13, characterized in that, The intentional erroneous data / other intentional erroneous data is transmitted using a double data rate (DDR) configuration.

15. The data protection method according to claim 13, characterized in that, The master device performs the operation of receiving erroneous data or intentional erroneous data from the slave device and / or receiving other erroneous data or other intentional erroneous data from the other slave devices. The one or more master data of the erroneous data have values ​​that are different from the one or more master data of the data or the one or more master data of the other data, wherein the one or more master data of the other erroneous data have values ​​that are different from the one or more master data of the data or the one or more master data of the other data. The master device performs the operation of handling the intentional erroneous data / other intentional erroneous data in the same manner as handling the erroneous data / other erroneous data by reporting the failure of the read operation.

16. The data protection method according to claim 13, characterized in that, The command includes one or more address data with corresponding address data parity bits, and read command and identifier data with corresponding read command and identifier (ID) data parity bits. In the one or more address data having corresponding address data parity check bits and / or the read command and identifier data having corresponding read command and identifier (ID) data parity check bits, the command and the erroneous command have different values. In response to the erroneous command received from the master device, the slave device / other slave device does not perform the operation of reading the data / other data of the slave device / other slave device, and the slave device / other slave device performs the operation of sending the intentional erroneous data / other intentional erroneous data to the master device.

17. The data protection method according to claim 13, characterized in that, The master device performs the operation of receiving the intentional erroneous data / other intentional erroneous data sent by the slave device / other slave device.

18. The data protection method according to claim 13, characterized in that, The master device also includes a master device interrupt and a master error counter; the slave device also includes a slave device interrupt and a slave device error counter; and the other slave devices also include other slave device interrupts and other slave device error counters. In response to the operation of receiving the intentional erroneous data / other intentional erroneous data by the master device, the master device sets the master device interrupt and increments the master error counter, and the slave device / other slave device sets the slave device interrupt / other slave device interrupt and increments the slave device error counter / other slave device error counter.

19. The data protection method according to claim 12, characterized in that, The command includes one or more write data with corresponding write data parity bits, one or more address data with corresponding address data parity bits, and write command and identifier data with corresponding write command and identifier (ID) data parity bits. In the one or more write data having corresponding write data parity check bits, and / or the one or more address data having corresponding address data parity check bits, and / or the write command and identifier (ID) data having corresponding write command and identifier (ID) data parity check bits, the command and the error command have different values. During a write operation, in response to an error command received from the master device, the slave device / other slave device does not execute the error command to prevent one or more write data from being written to the slave device / other slave device.

20. The data protection method according to claim 19, characterized in that, The slave device / other slave devices also include slave device interrupt / other slave device interrupt and slave device error counter / other slave device error counter. In response to the slave device / other slave device not executing the erroneous command, the slave device / other slave device performs the following operations: discarding the erroneous command, setting the slave device interrupt / other slave device interrupt, and incrementing the slave device error counter / other slave device error counter.

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