Data processing method and device combined with access memory cell array

Abstract

This invention discloses an apparatus including a storage cell array, multiple page registers, and a processing element. The storage cell array is divided into multiple blocks. The multiple page registers are coupled to the edge blocks of the storage cell array, and the multiple page registers access page data based on a page copying method. The processing element is connected to the multiple page registers to process conditionally and / or directly read data from the multiple page registers to perform multiplication and / or accumulation in machine learning of an artificial intelligence system.

Description

Technical Field

[0001] This invention relates to a memory management apparatus, and more particularly to an apparatus for enhancing prefetching in a memory cell array using a low-power, data access page data copying scheme. Furthermore, this invention also relates to a page data copying apparatus for locking data accessed via the page data copying method and for conditionally accessing data. The conditionally accessed data is the preprocessing result of a processing program and is sent to a processing unit to complete the computation of an artificial intelligence system. Background Technology

[0002] Memory types such as Dynamic Random Access Memory (DRAM) are used to store user data, and maximizing access bandwidth is considered one of the important considerations in DRAM design. However, some problems may arise in existing data access methods. For example, there may be issues with prefetch count, total power consumption, normalized access energy efficiency (i.e., energy per bit access), and memory area. More specifically, the conventional cell array architecture of DRAM chips may have reached the limit of prefetch count without a significant increase in memory area. Therefore, a new data access architecture and method are needed to address this problem.

[0003] However, even if the limitation on the maximum number of data prefetches of the memory array can be overcome, the access bandwidth of the chip processing data on another chip is still limited by the inter-chip interface bandwidth. Furthermore, driving the inter-chip interface generates power consumption and heat dissipation issues, further limiting system performance. To address this, by employing the disclosed memory architecture and a special data access scheme, combined with a near-station processing unit, the high bandwidth and short data stream required to solve the problem can be achieved. Summary of the Invention

[0004] As a solution to these problems, the embodiments propose a memory-based device. The device includes a set of page registers connected to edge blocks of a memory cell array, accessing data from the memory cell array based on a page copying method, and a processing block including arithmetic processing elements and page registers, wherein data can be conditionally accessed from the page registers or locally accessed from the page registers, and then the data processed by the arithmetic processing elements can be copied to the page registers of the processing block or page registers in adjacent processing blocks, thereby enabling the feasibility of such operations in an artificial intelligence system.

[0005] The memory cell array may include operations performed by a row decoder and a page register decoder coupled to the memory cell array and via a predetermined decoding sequence of a decoder, and by combining a row decoder and a page register decoder for matrix-vector multiplication, matrix-matrix multiplication, or in-situ convolution in an arithmetic processing element. The page register, arithmetic processing element, and memory cell array may be integrated in the same semiconductor chip or may be integrated in at least two different semiconductor chips coupled to each other. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a memory module data access device according to an embodiment of the present invention.

[0007] Figure 2 Is with Figure 1 A schematic diagram of the bit line sensing amplifier block and the memory cell array block in the memory module.

[0008] Figure 3 yes Figure 1 A schematic diagram of the storage unit 1T1C of the memory module.

[0009] Figure 4 yes Figure 1 A schematic diagram of the bit line sensing amplifier of the memory module shown.

[0010] Figure 5 This is a schematic diagram of the page data copying method in the embodiment.

[0011] Figure 6A and 6B This is a schematic diagram of data copying in the bit-line open array of traditional 1T1C and 2T2C architecture memory.

[0012] Figure 6C This is a schematic diagram of data replication in the T1C cell array of Embodiment 1.

[0013] Figure 7A and 7B This is a schematic diagram of data copying in an open bitline array of another traditional storage block.

[0014] Figure 8 This is a schematic diagram illustrating the data copying operation of an open bitline array.

[0015] Figure 9 This is a schematic diagram illustrating the application of array data access methods to chip peripheral devices.

[0016] Figure 10A This is a schematic diagram of an artificial intelligence accelerator coupled to a central processing unit to process machine learning.

[0017] Figure 10BThis is a schematic diagram of an artificial intelligence accelerator coupled to a central processing unit and a large-capacity memory to process machine learning.

[0018] Figure 11 This is a schematic diagram of an AI accelerator implemented on an example chip.

[0019] Figure 12 This is a schematic diagram of a page register used for conditional access storage of data.

[0020] Figure 13 This is a schematic diagram illustrating the substitution of multiplication and addition when multiplying vectors in an embodiment.

[0021] Figure 14A and 14B This is a schematic diagram of the convolution operation process in the embodiment.

[0022] The reference numerals in the attached figures are explained as follows:

[0023] 100: Memory Module

[0024] 101: Storage

[0025] 102: Secondary semiconductor chip

[0026] 110: Word Line Decoder

[0027] 120: Memory cell array

[0028] 130: Page Register

[0029] 150: Peripheral Circuits

[0030] 152: Access Circuit

[0031] BL, BLF: Bit lines

[0032] WL: Word Line

[0033] Capacitor

[0034] SEN, SENf: Drive signals

[0035] BLSA: Bit Line Sensing Amplifier Detailed Implementation

[0036] Figure 1 This is a schematic diagram of a data access (e.g., read / write / move) device for a memory module 100 according to an embodiment of the present invention. The data access device may include at least a portion (e.g., a portion or all) of the memory module 100. The data access device may include a portion of the memory architecture of the memory module 100. For example, the data access device may include a combination of a portion of the memory architecture and associated control mechanisms. Alternatively, the data access device may include the entire memory module 100.

[0037] like Figure 1 As shown, the memory module 100 may include a memory bank 101 and a secondary semiconductor chip 102. The memory bank 101 may include a word line decoder 110, a memory cell array 120 with multiple memory cells, such as M×N memory cells (M and N are positive integers), and multiple bit lines and multiple word lines coupled to the memory cell array 120, such as N bit lines {BL(1),BL(2),...,BL(N)} and M word lines {WL(1),WL(2),...,WL(M)} coupled to (M×N) memory cells, but the present invention is not limited thereto. According to some embodiments, in addition to the word line driver, the word line decoder 110 may also be located in the secondary semiconductor chip 102. For example, the front end of the word line decoder 110 may be located in the secondary semiconductor chip 102, and the back end of the word line decoder 110 (which may include the word line driver) may be located in the memory bank 101.

[0038] The memory bank 101 may further include multiple bit-line sense amplifiers (BLSAs), each coupled to the memory cell array 120 via multiple bit lines, such as the N BLSAs of the page register 130, and multiple main data lines connected to the N BLSAs of the page register 130. These main data lines can serve as external data interfaces for the memory bank 101. For example, a secondary semiconductor chip 102 may be electrically connected to the memory bank 101, but the invention is not limited thereto. Furthermore, the secondary semiconductor chip 102 may include peripheral circuitry 150, which may include access circuitry 152. For example, the secondary semiconductor chip 102 may include multiple secondary amplifiers located within the access circuitry 152.

[0039] The memory cell array 120 can be used to store data for a host system, and the memory module 100 can be installed in the host system. The host system can be a multifunction mobile phone, tablet computer, desktop computer, or laptop computer. Multiple bit lines, such as N bit lines {BL(1), BL(2), ..., BL(N)}, and multiple word lines, such as M word lines {WL(1), WL(2), ..., WL(M)}, can be used to perform access control of the memory cell array 120. According to an embodiment, multiple bit line sense amplifiers BLSA can be used to sense multiple bit line signals from multiple memory cells, such as (M×N) memory cells, and convert the multiple bit line signals into multiple amplified signals respectively.

[0040] Some implementation details regarding the access control of the memory cell array 120 are described below. According to some embodiments, the word line decoder 110 can decode its access control signals, such as row select signals, to determine whether to select (activate) a column of memory cells corresponding to word line WL(m) (e.g., m may represent an integer falling within the interval [0, M]), wherein the word line decoder 110 can act as a row decoder within the access control range of the memory cell array 120.

[0041] Reference Figure 1 The device may include a memory bank 101 in the memory module 100, but the invention is not limited thereto; the device may also include a secondary semiconductor chip 102. According to some embodiments, in addition to the memory bank 101, the memory module 100 may include at least a portion (e.g., a portion or all) of the secondary semiconductor chip 102. One or more circuits having any function outside the memory module 100 may be integrated into the secondary semiconductor chip 102.

[0042] According to some embodiments, Figure 1 The architecture shown may vary. For example, the memory cell array 120 may be divided into multiple memory cell array blocks according to a predetermined bit line length to improve access speed, and the bit line sense amplifiers (BLSAs), such as the N bit line sense amplifiers (BLSAs) in the page register 130, may be divided into multiple bit line sense amplifier block BLSAs and correspondingly coupled to multiple memory cell array blocks to perform related sensing operations.

[0043] Figure 2 Is with Figure 1 A schematic diagram showing the interleaving of the bit line sense amplifier block (BLSA) and the memory cell array block in the memory module. Figure 2 Can be used as Figure 1 Examples of memory cell array blocks and bit line sense amplifier blocks (BLSAs) in the illustrated architecture are shown. Furthermore, any two memory cell array blocks can be identical or similar, and any two bit line sense amplifier blocks (BLSAs) can be identical or similar.

[0044] Figure 3 yes Figure 1 A schematic diagram of a 1T1C (one transistor, one capacitor) memory cell (e.g., a DRAM cell) in a memory module 100. The memory cell can be any one of multiple memory cells in a memory cell array 120. (See reference...) Figure 3The memory cell can be coupled to a switch of a word line, such as word line WL(m), or a bit line, such as bit line BL(n). The switch can be a transistor, such as a metal-oxide-semiconductor field-effect transistor. The memory cell may also include a capacitor Cap. The capacitor Cap can be used to store charge, and different states of the charge can indicate bit information (e.g., 0 or 1), but the invention is not limited thereto. Some embodiments may also utilize 2T2C (two transistors, two capacitors) memory cells to increase reliability. The structure and function of a typical 2T2C memory cell are well known to those skilled in the art.

[0045] Figure 4 yes Figure 1 A schematic diagram of the bit line sense amplifier (BLSA) of the memory module 100 shown. Figure 4 As shown, the bit line sense amplifier (BLSA) can be a latch comprising two cross-connected inverters. Specifically, the two cross-connected inverters can each be coupled to two bit lines (BL_0 and BL_1) from a plurality of bit lines. The two bit lines can be coupled to different memory cells. Each inverter can be driven by a set of drive signals, such as drive signals SENf and SEN.

[0046] The bit line sense amplifier (BLSA) can operate according to the drive signals SENf and SEN, respectively acquiring their respective bit signals (voltages). The memory bank 101 in the memory module 100 can select any one of multiple memory cells based on the signal from the access word line decoder 110. For example, in the first read phase, the BLSA can acquire the bit information of the first memory cell out of two memory cells via BL_0, for example, amplifying the bit signal of the first memory cell. As another example, in the second read phase, the BLSA can acquire the bit signal of the second memory cell out of two memory cells via BL_1, and amplify the bit signal of the second memory cell.

[0047] Bit-line sense amplifiers (BLSAs) are controlled by two drive signals, SENf and SEN. A BLSA application moves one page of data at a time. A page of data is defined as the data stored across all memory cells initiated by the same word line. Therefore, BLSA applications do not require row select lines and data lines, saving cost and reducing chip area and complexity. By sequentially initiating adjacent BLSA blocks, the data present in the first BLSA is copied to the next sequential BLSA. In embodiments, a page of data can be transferred from a source location to a target location in any direction perpendicular to the word line.

[0048] For example, the latch voltage can be transferred to the bit lines in the second block by activating the bit line sense amplifier (BLSA) between the first and second blocks. The embodiment can also use the bit line sense amplifier (BLSA) between the second and third blocks to transfer the voltage of the bit lines in the second block to transfer the latch voltage to the bit lines in the third block. Using this method of sequentially activating the bit line sense amplifier (BLSA), the voltage can be sequentially transferred from one block to adjacent blocks until the target location is reached. The source voltage can be read by activating the appropriate word line, or the source voltage can be provided by the data access circuitry 152 and the voltage can be loaded onto the bit lines.

[0049] Therefore, the embodiment can activate the word line at the source location, load the voltage of the memory cell at the source location onto the corresponding bit line, and activate the latch voltage of the adjacent bit line sense amplifier (BLSA). The voltage can be sequentially transferred from block to adjacent block until the target location is reached. The target location can be the data access circuit 152 or another memory cell array block.

[0050] Figure 5 This is a schematic diagram of the page data copying method in the embodiment. Figure 5 The upper half of the diagram shows a functional schematic of a portion of the example memory bank. Memory cell array blocks are marked with dashed lines and numbered 0 to 4, and each memory cell array block portion includes a word line. Bit line sense amplifier blocks BLSA_0 to BLSA_3 are located between each memory cell array block, and each bit line sense amplifier BLSA is connected to the adjacent memory cell array block via a bit line.

[0051] like Figure 5 As shown, after BLSA_0 boots (i.e., SENf is 0v, SEN is VDD), page data is read from the cells of the open word line and copied from memory cell array block 0 to memory cell array block 1 (circle 1). Then, after BLSA_1 boots, page data is copied from memory cell array block 1 to memory cell array block 2 (circle 2). Next, after BLSA_2 boots, page data is copied from memory cell array block 2 to memory cell array block 3 (circle 3). Finally, after BLSA_3 boots, page data is copied from memory cell array block 3 to memory cell array block 4 (circle 4).

[0052] Figure 6A and 6B This is a schematic diagram of data copying in a bit-line open array of traditional 1T1C and 2T2C memory architectures. The data copying method disclosed in the embodiments cannot be used in... Figure 6A Implemented in the conventional open bitline array shown (e.g. from) Figure 6A (The memory cell array block 2 is copied to memory cell array block 3). To solve this problem... Figure 6B This is a schematic diagram of the structural modification of an open bit line array by electrically connecting the first bit line and the second bit line in each memory cell. Figure 6B The structure ensures that regardless of whether the data is stored on the bit line BLF or BL, the data stored in the previous bit line sense amplifier BLSA can be used in the subsequent adjacent bit line sense amplifier BLSA. Figure 6C This is a schematic diagram of data replication in a 1T1C cell array (modified from a conventional 1T1C open bitline array).

[0053] Figure 7A and 7B This illustrates data replication in an open bitline array of another traditional storage block. (Compared to...) Figure 6A and 6B As with the previous embodiments, the data copying method disclosed in the embodiments cannot be used in... Figure 7A Implemented in the conventional open bitline array shown (e.g. from) Figure 7A (The memory cell array block 2 is copied to memory cell array block 3). To solve this problem... Figure 7B This is a schematic diagram of the structural modifications made to the open bit-line array. Figure 7B In this configuration, each bit-line sense amplifier (BLSA) is connected to four transistors, each transistor having a first terminal, a second terminal, and a control terminal. The first bit line in a memory block is coupled to the first terminal of the first transistor, the second terminal of the first transistor, a first node, the first terminal of the second transistor, the second terminal of the second transistor, and the first bit line in the adjacent memory block, as shown below. Figure 7B As shown, the second bit line in the memory block is coupled to the first terminal of the third transistor, the second terminal of the third transistor, the second node, the first terminal of the fourth transistor, the second terminal of the fourth transistor, and the second bit line in the adjacent memory block. The bit line sense amplifier BLSA is coupled to the first node and the second node. This ensures that each of the four transistors is electrically connected to the bit lines BLF and BL in the adjacent memory cell array, ensuring that the data voltage can be transmitted correctly.

[0054] Figure 8 This is a schematic diagram illustrating the data copying operation of an open bitline array. Time progresses from top to bottom in the diagram, and data is copied from left to right. Figure 8In this process, after the memory cells in block 2 of the memory cell array are precharged, the word lines are activated, data is read and amplified from the memory cells, and data A is latched into the appropriate bit line sense amplifier (BLSA). The word lines are then turned off. When a subsequent bit line sense amplifier (BLSA) is activated, data A is copied from the current bit line sense amplifier (BLSA) to the next bit line sense amplifier (BLSA). The bit line sense amplifier (BLSA) activation process continues, transferring data A from one bit line sense amplifier (BLSA) to the next bit line sense amplifier (BLSA), finally reaching the target location.

[0055] Some advantages of this page copying method include:

[0056] 1. Obtain the maximum data prefetch that the DRAM array can provide;

[0057] 2. It eliminates the need for a data line sensing amplifier and saves power consumption from unnecessary line select line decoders;

[0058] 3. Energy is saved due to the inherent voltage half-amplitude of the landing lines BL and BLF;

[0059] 4. Applying the bit line before word line (BL-before-WL) page data writing method can achieve fast and low-power data writing.

[0060] Figure 9 This is a schematic diagram illustrating the application of the array data access method to chip peripheral devices. This method is a long-range, wide-bus, energy-efficient data transmission approach. Figure 9 and Figure 8 Similar, but different Figure 9 This includes the voltage value transmitted by the cross-line sense amplifier (BLSA). For example... Figure 9 As shown, since the bit line sense amplifier BLSA amplifies the read value 1 or 0, and since the circuit is precharged to 1 / 2 of VDD, the maximum amplitude of the transmission voltage is 1 / 2.

[0061] This method offers advantages over complementary metal-oxide-semiconductor (CMOS) methods that use half-amplitude voltages to copy or move data to the edge regions of the chip. Compared to conventional small-amplitude intermediate frequency (IF) voltages, this method does not consume DC current from the receiver and is as stable as differential IF voltages (which require a reference voltage or half-amplitude IF voltage).

[0062] In short, after selecting a word line and loading the charge of the memory cell onto the bit line, the signals on these bit lines in the first memory cell array block can be amplified and latched by activating the bit line sense amplifier (BLSA) between the first memory cell array block and its adjacent blocks, thus allowing the latched voltage to be transferred to the bit lines in the second memory cell array block. Similarly, a latch between the second and third memory cell array blocks can be used to further transfer the voltage to the third memory cell array block. The voltage can be sequentially transferred from one block to subsequent adjacent blocks, eventually reaching the target location. This can serve as a method for writing page data in a memory chip, where page data can be sequentially transferred from the page register to adjacent blocks, then from that block to subsequent adjacent blocks, and finally to the target block. Activating the word line of the target block of the memory cell array involves writing data in the form of voltage to the target word line in the target block.

[0063] The page copying method described in this embodiment can be applied to AI accelerators. Like most neural networks, Convolutional Neural Networks (CNNs) are computationally intensive and power-intensive processors. The data transmission power required accounts for 90-99% of the total power consumption and runtime of the neural network; therefore, it is necessary to reduce the amount of data transmitted and / or the distance of data transmission.

[0064] Convolutional neural networks (CNNs) differ from many types of neural networks because they are not fully interconnected. Therefore, the input image is typically divided into multiple windows, at least until it approaches or reaches the output layer. For this reason, most processing layers in a CNN can use a single window at a time until the window outputs a single result. While a CNN can process multiple windows in parallel or simultaneously, the processing of each window by each layer does not involve the processing of any other window. This individual processing of a window is called localized data flow. The same localized data flow can also be applied separately to each channel in a multi-channel CNN, for example, processing the RGB colors in an RGB color input image separately.

[0065] like Figure 10A As shown, AI accelerators can be coupled to and operate in conjunction with a central processing unit. Furthermore, as... Figure 10BAs shown, the AI ​​accelerator can also be coupled to and operate in conjunction with a central processing unit and a large-capacity main memory to handle, for example, machine learning involving large amounts of data. In some embodiments, page registers, arithmetic processing elements, and memory cell arrays are integrated into the same semiconductor chip. In other embodiments, page registers, arithmetic processing elements, and memory cell arrays are integrated into at least two different semiconductor chips, and the semiconductor chips are coupled to each other.

[0066] Figure 11 This is a schematic diagram of an AI accelerator implemented on an example chip. Figure 11 The chip shown can be applied to artificial intelligence accelerators that utilize localized data streams. For example... Figure 11 As shown, the chip can be divided into multiple units, each unit including two memory cell arrays and a processing block. Each unit can be used to independently process a single data window. Each memory cell array can be a dynamic random access memory array; however, the embodiments are not limited to dynamic random access memory.

[0067] like Figure 11 As shown, the processing block comprises multiple page registers connected in the middle to an arithmetic processing element. The other side of each page register is coupled to the edge block of one of the corresponding memory cell arrays. The page registers are used to access data from the coupled memory cell arrays using the previously described page copying method. The arithmetic processing element processes conditional access data from the page registers. The arithmetic processing element can perform data accumulation on different channels separately.

[0068] Page registers and the processing blocks closest to the page registers can be designated as cache memory for computation. Each memory cell array includes column decoders and row decoders coupled to the memory cell array. Convolutional operations of the convolutional neural network can be performed in conjunction with operations executed within the processing blocks using a predetermined decoding sequence from the decoders.

[0069] like Figure 11 As shown, the embodiment utilizes a page copying method to access data pages from the top of the storage cell array and stores them in a page register adjacent to the processing element. The processing element processes the conditional access data stored in the page register and stores the result in another page register. The stored result data is then stored in the storage cell array using the page copying method, and the embodiment can repeat the data stream multiple times as needed to complete the processing of the localized data stream without requiring any long-distance data transmission.

[0070] The purpose of the conditional access data stream described above is to further reduce the energy and complexity consumed by data transmission and movement by using addition instead of multiplication in the processing at each layer. This can be accomplished by using page data registers, such as... Figure 12 As shown, the embodiment can conditionally access X (e.g., feature image data) based on W (e.g., weight data).

[0071] like Figure 13 As shown, multiplying one 8-bit data by another 8-bit data can be represented as multiplying an 8-element vector X0 to X7 by another 8-element vector W0 to W7, with the product being a 16-bit vector data. The embodiment can control... Figure 12 The page register conditionally accesses bit-by-bit multiplication data to calculate, such as Figure 13 The data shown is a 16-bit vector. For example, the data for bit A3 requires the sum of X3×W0, X2×W1, X1×W2, and X0×W3, where X3×W0 represents the product of X3 and W0.

[0072] Subsequently, the embodiment can copy the data accumulated as the multiplication result of the processing block to the page register of the in-situ processing block or to the page register of an adjacent processing block. Since data transfer accounts for 90% to 99% of the power consumed by a convolutional neural network, this method of combining page copying with conditional access can significantly save power.

[0073] In short, conditional access data involves accessing Xi (page data stored in a row of the memory cell array) by activating a selection bit, denoted as Wj, such that the accessed data is Xi × Wj (i.e., Xi AND Wj) instead of the original Xi, and the sum of the conditional access data, Xi × Wj, is equal to the product of two vectors X and W in a given permutation. Furthermore, conditional access data involves accessing Xi (page data stored in a row of the memory cell array) by activating multiple selection bits (Wj, Wj+1, Wj+2, ...). The result can be represented as (Xi × Wj, Xi × Wj+1, Xi × Wj+2, ...), where the sum of these conditional access data in a given permutation is equal to the product of two vectors X and W.

[0074] Figure 14A and 14B Explain the process of convolution operation. Figure 14A In this embodiment, a 3×3×3 filter is used and applied to the three channels of the input data. On the right side of the figure, because the filter for one channel is 3×3, the feature map pixel data for one channel is multiplied by one of the nine pixel data points in the 3×3 matrix, resulting in nine images. The pixel data is then stored in a storage cell array, or, through some access method (e.g., a page copying scheme), in the cache memory of the nearest processing element block.

[0075] Figure 14BThis is a schematic diagram of the sum of pixel-by-pixel multiplication data stored in the corresponding memory cell array location. The embodiment skips column and / or row data access to facilitate the operation processing of the convolution window.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An apparatus, characterized in that, include: The storage unit array is divided into multiple blocks; Multiple page registers are connected to the edge blocks of the multiple blocks of the storage unit array. The multiple page registers access page data based on the page copying method; and A processing element is connected to the plurality of page registers, wherein data conditionally and / or directly read from the plurality of page registers is processed to perform multiplication and / or accumulation in machine learning of an artificial intelligence system. The page copying method described herein performs inter-block data transfer by sequentially activating bitline sensing amplifiers.

2. The apparatus of claim 1, wherein the memory cell array includes a row decoder and a page register decoder, both coupled to the memory cell array, and matrix-vector multiplication, matrix-matrix multiplication, or in-place convolution is performed by combining arithmetic performed in the computational processing element in the order of the row decoder and the page register decoder.

3. The apparatus according to claim 1, wherein the arithmetic processing element performs data accumulation on different channels respectively.

4. The apparatus of claim 1, wherein the memory cell array block adjacent to the page register is a cache memory designated to store intermediate data during operation.

5. The apparatus according to claim 1, characterized in that, It works in conjunction with a central processing unit to process machine learning.

6. The apparatus of claim 1, wherein the page register, the arithmetic processing element, and the memory cell array are integrated on the same semiconductor chip.

7. The apparatus of claim 1, wherein the page register, the arithmetic processing element and the memory cell array are integrated in at least two different semiconductor chips and the at least two different semiconductor chips are coupled to each other.

8. The apparatus of claim 1, wherein the edge block of the storage cell array is adjacent to the peripheral block of the storage cell array.

9. The apparatus of claim 1, wherein the storage cell array is a dynamic random access memory array.

10. The apparatus of claim 1, wherein the data Xi accessed by page copying is latched in the page registers of the plurality of page registers, and the accessed data is XiWj by activating the row selection bit of the page register, denoted as Wj, and the sum of the conditionally accessed data XiWj in a particular permutation is equal to the product of two vectors X and W.

11. The apparatus of claim 1, wherein the data Xi accessed by page copying is latched in the page registers of the plurality of page registers, and by activating a plurality of selection bits, the plurality of selection bits being represented as vectors W(Wj, Wj+1, Wj+2, ...) and the plurality of selection bits being coupled to the same page register, the accessed data is represented as vector XiW or (Xi×Wj, Xi×Wj+1, Xi×Wj+2, ...), the sum of the plurality of data in a particular permutation being equal to the product of two vectors X and W.

12. The apparatus of claim 1, wherein the data accumulated by the arithmetic processing element is copied to a plurality of page registers in an adjacent processing block.

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