Memory device and method of operating the memory device

Abstract

A memory device and a method of operating the memory device are provided. The memory device may include: a peripheral circuit configured to perform a plurality of programming cycles and program a page selected from the plurality of pages, wherein the peripheral circuit may count the number of memory cells in a part of the memory cells included in the selected page whose threshold voltage has increased to a first target voltage, and may perform a current sensing check operation to determine whether a verification operation performed in a previous programming cycle has passed or failed; and a control logic circuit configured to control the peripheral circuit such that the current sensing check operation is performed when the number of memory cells whose threshold voltage has increased to the first target voltage is equal to or greater than a reference number of memory cells.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0126702, filed with the Korean Intellectual Property Office on September 29, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate to a memory device and a method of operating a memory device, and more particularly to a memory device capable of performing a programming operation and a method of operating the memory device. Background Art

[0004] Memory devices may include volatile memory devices and non-volatile memory devices; in volatile memory devices, data stored is lost when power is interrupted; in non-volatile memory devices, data stored is retained even when power is interrupted.

[0005] Examples of volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM). Examples of non-volatile memory devices may include read-only memory (ROM), programmable read-only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), NAND flash memory, and the like.

[0006] A memory device may include a memory cell array, peripheral circuits, and control logic circuits.

[0007] The memory cell array may include a plurality of memory cells, and each of the memory cells may store data. A scheme for storing one bit of data in one memory cell is referred to as a single-level cell (SLC) scheme, and a scheme for storing two or more bits of data in one memory cell is referred to as a multi-level cell (MLC) scheme. Depending on the number of bits stored in each memory cell, the MLC scheme may be classified into a triple-level cell (TLC) scheme and a quad-level cell (QLC) scheme. In the TLC scheme, three bits of data may be stored in one memory cell, and in the QLC method, four bits of data may be stored in one memory cell. Summary of the Invention

[0008] Various embodiments of the present disclosure relate to a memory device and a method of operating the memory device, which can shorten the operation time by performing a current sensing check operation because, during a programming operation performed on a selected page, the number of memory cells that have passed a verification operation among the memory cells having the lowest target voltage has reached a reference number of memory cells.

[0009] Embodiments of the present disclosure may provide a memory device. The memory device may include a plurality of pages, each including a plurality of memory cells, a peripheral circuit, and a control logic circuit. The peripheral circuit is configured to perform a plurality of programming cycles and program a selected page from the plurality of pages. The peripheral circuit counts the number of memory cells among a part of the memory cells included in the selected page whose threshold voltage has increased to a first target voltage. The peripheral circuit performs a current sensing check operation to determine whether a verification operation performed in a previous programming cycle has passed or failed. The control logic circuit is configured to control the peripheral circuit such that the current sensing check operation is performed when the number of memory cells whose threshold voltage has increased to the first target voltage is equal to or greater than a reference number of memory cells.

[0010] Embodiments of the present disclosure may provide a method of operating a memory device. The method may include: performing a sub-programming operation of applying a programming voltage to a plurality of memory cells included in a selected page, performing a verification operation for verifying a threshold voltage of a selected memory cell having the lowest target voltage among the plurality of memory cells, and comparing the number of passing bits detected in the verification operation with a reference number of passing bits. When the number of passing bits is less than the reference number of passing bits, a current sensing check operation for determining whether the verification operation has passed or failed is skipped in a next programming cycle, and when the number of passing bits is equal to or greater than the reference number of passing bits, a current sensing check operation is performed from the next programming cycle.

[0011] Embodiments of the present disclosure may provide a method of operating a memory device. The method may include: performing a plurality of programming cycles to increase a threshold voltage of memory cells in a selected page, wherein in each of the plurality of programming cycles, when the number of memory cells whose threshold voltage has increased to a target voltage is less than a reference number of memory cells, a current sensing check operation for determining a result of a verification operation in a previous programming cycle is skipped, and when the number of memory cells whose threshold voltage has increased to the target voltage is equal to or greater than the reference number of memory cells, a current sensing check operation is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0015] Figure 4 is a block diagram illustrating a plurality of pages included in a memory block.

[0016] Figure 5 is a diagram illustrating a threshold voltage distribution of memory cells.

[0017] Figure 6 is a block diagram illustrating a verification detector according to an embodiment of the present disclosure.

[0018] Figure 7A and Figure 7B is a block diagram illustrating a first embodiment in which a verification detector can determine pass bits in verification data.

[0019] Figure 8 is a block diagram illustrating a second embodiment in which a verification detector can determine pass bits in verification data.

[0020] Figure 9A and Figure 9B is a block diagram illustrating a third embodiment in which a verification detector can determine pass bits in verification data.

[0021] Figure 10 is a block diagram illustrating a current sense check detector according to an embodiment of the present disclosure.

[0022] Figure 11A and Figure 11B is a block diagram illustrating a method in which a current sense check detector can determine pass or fail in a verification operation depending on check data.

[0023] Figure 12 is a block diagram illustrating a current sense check controller according to an embodiment of the present disclosure.

[0024] Figure 13 is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0025] Figure 14A and Figure 14B is a diagram illustrating a programming operation according to a first embodiment of the present disclosure.

[0026] Figure 15 is a diagram illustrating a programming operation according to a second embodiment of the present disclosure.

[0027] Figure 16 FIG. is a diagram illustrating a programming operation according to a third embodiment of the present disclosure.

[0028] Figure 17 FIG. is a diagram illustrating a programming operation according to a fourth embodiment of the present disclosure.

[0029] Figure 18 FIG. is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0030] Figure 19 FIG. is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0031] Figure 20 FIG. is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0032] Figure 21 FIG. is a diagram illustrating a programming operation according to a fifth embodiment of the present disclosure.

[0033] Figure 22 FIG. is a diagram illustrating a programming operation according to a sixth embodiment of the present disclosure.

[0034] Figure 23 FIG. is a block diagram illustrating a memory card system applying a memory device according to an embodiment of the present disclosure.

[0035] Figure 24 FIG. is a block diagram illustrating a solid state drive (SSD) system applying a memory device according to the present disclosure. DETAILED DESCRIPTION

[0036] Figure 1 FIG. is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0037] Referring Figure 1 , the memory system 1000 may include a storage device 1100 and a memory controller 1200. The storage device 1100 may include a plurality of memory devices MD, and these memory devices MD may be coupled to the memory controller 1200 through input / output lines.

[0038] The memory controller 1200 may perform communication between the host 1500 and the memory device MD. The memory controller 1200 may generate a command CMD for controlling the memory device MD in response to a request RQ from the host 1500. In addition, even if no request RQ is received from the host 1500, the memory controller 1200 may perform background operations for improving the performance of the memory system 1000.

[0039] The host 1500 may generate requests RQ for various operations and output the generated requests RQ to the memory system 1000. For example, the request RQ may include a program request for controlling a programming operation, a read request for controlling a read operation, an erase request for controlling an erase, etc.

[0040] The host 1500 may communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0041] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0042] Referring to Figure 2 , the memory device MD may include: a memory cell array 110 that stores data; a peripheral circuit 200 that performs a programming operation, a read operation, or an erase operation; and a control logic circuit 180 that controls the peripheral circuit 200.

[0043] The memory cell array 110 may include a plurality of planes PL1 to PLk (where k is a positive integer), and each of the planes PL1 to PLk may include a plurality of memory blocks BLK1 to BLKi. Each of the memory blocks BLK1 to BLKi may include a plurality of memory cells, and the memory cells may be implemented in a two-dimensional (2D) structure in which the memory cells are horizontally arranged on a substrate, or may be implemented in a three-dimensional (3D) structure in which the memory cells are vertically stacked on a substrate.

[0044] The peripheral circuit 200 may include a voltage generator 120, a row decoder 130, a page buffer group 140, an input / output circuit 150, a verify detector 160, and a current sense check (CSC) detector 170.

[0045] The voltage generator 120 may generate and output an operation voltage Vop required for various operations in response to a voltage code VCD. For example, the voltage generator 120 may generate and output a program voltage, a verify voltage, a read voltage, a pass voltage, an erase voltage, etc., each having various levels.

[0046] The row decoder 130 may select one memory block from among a plurality of memory blocks BLK1 to BLKi included in the memory cell array 110 in response to a row address RADD, and transfer an operation voltage Vop, and may transfer the operation voltage Vop to the selected memory block.

[0047] The page buffer group 140 may be coupled to the memory cell array 110 through bit lines. For example, the page buffer group 140 may include a plurality of page buffers coupled to corresponding bit lines. The plurality of page buffers may be simultaneously operated in response to a page buffer control signal PBSIG, and may temporarily store data during a programming operation or a read operation. A verify operation performed during a programming operation and a verify operation performed during an erase operation may be performed in a manner similar to a read operation. For example, the page buffer may output verify data V_DATA or check data C_DATA sensed from a memory cell during a programming operation. The verify data V_DATA may be data in units of chunks included in a selected page, and the check data C_DATA may be data of a selected page included in a selected memory block in each selected plane. Accordingly, the check data C_DATA may include the verify data V_DATA.

[0048] The input / output circuit 150 may be coupled to a memory controller (e.g., Figure 1 1200) through input / output lines. The input / output circuit 150 may receive / output a command CMD, an address ADD, and data DATA through the input / output lines. For example, the input / output circuit 150 may receive the command CMD and the address ADD through the input / output lines, and transfer the command CMD and the address ADD to the control logic circuit 180. The input / output circuit 150 may transfer the data DATA received from the memory controller 1200 to the page buffer group 140 through the input / output lines. In addition, during a read operation, the input / output circuit 150 may output the read data DATA received from the page buffer group 140 to the memory controller 1200 through the input / output lines.

[0049] The verify detector 160 may output a check start signal CSS or a check delay signal CDS during a programming operation depending on the number of memory cells whose threshold voltages have reached a selected target voltage. For example, the verify detector 160 may receive verify data V_DATA from the page buffer bank 140 in response to a verify signal VFS, may compare the number of passed bits in the verify data V_DATA with a reference number of passed bits, and may output a check start signal CSS or a check delay signal CDS based on the result of the comparison. For example, the verify detector 160 may receive verify data V_DATA from a selected memory block included in a selected plane and may count the number of passed bits included in the received verify data V_DATA. That is, in order to quickly determine the programming state of selected memory cells in an initial stage of a programming operation, the verify detector 160 may receive verify data V_DATA from any one of the plurality of planes PL1 to PLk and may count the number of passed bits included in the verify data V_DATA. The verify data V_DATA may be a part of data sensed from a selected page in a selected memory block included in a selected plane. For example, the verify data V_DATA may be data divided into chunks in a data slice of a selected page. Here, the term "chunk" may be a unit smaller than a page. For example, assuming that the capacity of one page is 10 kilobytes (KB), the capacity of one chunk may be set to 1 KB. In this case, the verify detector 160 may receive 1 KB of verify data V_DATA from the page buffer bank 140 and may count the number of passed chunk bits included in the received verify data V_DATA. When counting the number of passed chunk bits, the verify detector 160 may compare the number of passed chunk bits with a reference number of passed chunk bits and may output a check start signal CSS or a check delay signal CDS based on the result of the comparison. For example, when the number of passed chunk bits is equal to or greater than the reference number of passed chunk bits, the verify detector 160 may output a check start signal CSS, and when the number of passed chunk bits is less than the reference number of passed chunk bits, the verify detector 160 may output a check delay signal CDS.

[0050] The current sensing check detector 170 may determine whether a verification operation has passed or failed. For example, the current sensing check detector 170 may receive check data C_DATA from the page buffer bank 140 in response to a check enable signal CHS, may compare the number of failed page bits included in the check data C_DATA with the allowable number of failed page bits, and may output a check pass signal CPS or a check fail signal CFA based on the result of the comparison. For example, when the number of failed page bits is less than the allowable number of failed page bits, the current sensing check detector 170 may output a check pass signal CPS. When the number of failed page bits is equal to or greater than the allowable number of failed page bits, the current sensing check detector 170 may output a check fail signal CFA. When at least one of the plurality of planes PL1 to PLk has passed the verification operation, the current sensing check detector 170 may determine that the programming operation has passed and output a check pass signal CPS even if the verification operation on the remaining planes has failed. For example, when all of the planes PL1 to PLk have passed the verification operation, the current sensing check detector 170 may output a check pass signal CPS, and even if one of the planes PL1 to PLk has passed the verification operation, the current sensing check detector 170 may output a check pass signal CPS.

[0051] The control logic circuit 180 may output a voltage code VCD, a row address RADD, a page buffer control signal PBSIG, a verification signal VFS, and a check enable signal CHS in response to a command CMD and an address ADD. For example, the control logic circuit 180 may include software that executes an algorithm in response to the command CMD, and hardware that outputs various signals depending on the address ADD and the algorithm. Also, the control logic circuit 180 may include a current sensing check (CSC) controller 190 that can control a current sensing check operation depending on the programming state of a memory cell during a programming operation.

[0052] The current sensing check (CSC) controller 190 may output a verification signal VFS for activating the verification detector 160 during a programming operation. In addition, the current sensing check (CSC) controller 190 may output a check enable signal CHS for activating the current sensing check (CSC) detector 170 in response to a check start signal CSS or a check delay signal CDS. Also, the current sensing check controller 190 may determine whether a programming operation performed on a selected page has been completed in response to a check pass signal CPS or a check fail signal CFA.

[0053] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure, where is illustrated by way of example Figure 2The i-th memory block BLKi among a plurality of memory blocks BLK1 to BLKi.

[0054] Referring to Figure 3 , the i-th memory block BLKi may include a plurality of strings ST1 to STj (where j is a positive integer). The first to j-th strings ST1 to STj may be coupled between bit lines BL1 to BLj and a source line SL. For example, the first string ST1 may be coupled between the first bit line BL1 and the source line SL, the second string ST2 may be coupled between the second bit line BL2 and the source line SL, and the j-th string STj may be coupled between the j-th bit line BLj and the source line SL.

[0055] Each of the first to j-th strings ST1 to STj may include a source select transistor SST, a plurality of memory cells C1 to Cn, and a drain select transistor DST. Although not illustrated in the figure, each of the first to j-th strings ST1 to STj may further include dummy cells between the memory cells C1 to Cn and the source select transistor SST or the drain select transistor DST. The configuration of the j-th string STj will be described in detail by way of example below.

[0056] Depending on the voltage applied to the source select line SSL, the source select transistor SST included in the j-th string STj may electrically couple or decouple the source line SL and the first memory cell C1 from each other. The gates of the first to n-th memory cells C1 to Cn may be respectively coupled to the first to n-th word lines WL1 to WLn. Depending on the voltage applied to the drain select line DSL, the drain select transistor DST may electrically couple or decouple the j-th bit line BLj and the n-th memory cell Cn from each other. The gates of the source select transistors SST included in different strings ST1 to STj may be commonly coupled to the source select line SSL, the gates of the first to n-th memory cells C1 to Cn may be coupled to the first to n-th word lines WL1 to WLn, and the gates of the drain select transistors DST may be commonly coupled to the drain select line DSL. A group of memory cells coupled to the same word line may be referred to as a page (PG), and programming operations and read operations may be performed on a page (PG) basis.

[0057] The programming operation according to this embodiment may be performed in an incremental step pulse programming (ISPP) manner with a gradually increasing programming voltage. During the programming operation performed in the ISPP manner, multiple programming cycles may be executed until the threshold voltage of the selected memory cell increases to the target voltage, and the programming voltage may be gradually increased whenever each programming cycle is executed. In each programming cycle, a sub-programming operation for increasing the threshold voltage of the selected memory cell and a verification operation for determining whether the threshold voltage of the selected memory cell has increased to the target voltage may be executed. In the sub-programming operation, the programming voltage may be applied to the selected word line, and in the verification operation, the verification voltage may be applied to the selected word line. Depending on the data sensed from the memory cell during the verification operation, a determination of whether the verification operation has passed or failed may be made during the sub-programming operation of the next programming cycle. During the sub-programming operation, the operation of determining whether the verification operation has passed or failed may be a current sensing check operation.

[0058] In this embodiment, when the number of memory cells in the memory cell having the lowest target voltage whose threshold voltage has increased to the target voltage is equal to or greater than a specific number of memory cells, the current sensing check operation may be performed. That is, since the current sensing check operation is performed on the selected pages of the selected memory blocks included in all the selected planes, it may take a long time. Therefore, in this embodiment, the time required for the programming operation may be shortened by skipping the current sensing check operation in some programming cycles.

[0059] Figure 4 is a block diagram illustrating a plurality of pages included in a memory block.

[0060] Referring to Figure 4 , the memory block may include a plurality of pages PG1 to PGn (where n is a positive integer). Since each of the plurality of pages PG1 to PGn includes a plurality of memory cells capable of storing data, the storage capacity CAPpg of each of the pages PG1 to PGn may be determined depending on the number of memory cells. Recently, as the number of memory cells included in each of the pages PG1 to PGn has increased, the page storage capacity CAPpg has increased.

[0061] As described above, the programming operation is performed on a page basis, and as the page storage capacity CAPpg increases, a chunk unit may be used to easily process data. For example, each page may be divided into first to mth chunks CHK1 to CHKm. The first to mth chunks CHK1 to CHKm may be divided depending on a unified capacity or various capacities. The page buffer group (e.g., Figure 1140) can receive / output data on a per-chunk basis or can receive / output data independent of chunks. When the first page PG1 is the selected page, during the verification operation performed in the programming operation, data in all memory cells included in the first page PG1 can be stored in the page buffer so that the page buffer can output data on a per-chunk basis.

[0062] Figure 5 is a diagram illustrating the threshold voltage distribution of memory cells.

[0063] Referring to Figure 5 , depending on the number of bits stored in each memory cell, the programming operation can be classified into various schemes. For example, a scheme in which three-bit data is stored in one memory cell is called a triple-level cell (TLC) scheme, and a scheme in which four-bit data is stored in one memory cell is called a quad-level cell (QLC) scheme.

[0064] In the TLC scheme, the state of each memory cell can be identified as an erased state ER or any one of seven programming states P1 to P7. In the QLC scheme, the state of each memory cell can be identified as an erased state ER or any one of 15 programming states P1 to P15.

[0065] The number of bits that can be stored in one memory cell can be 5 or more, and the present embodiment does not limit the number of bits to be stored in each memory cell.

[0066] Figure 6 is a block diagram illustrating a verification detector according to an embodiment of the present disclosure.

[0067] Referring to Figure 6 , the verification detector 160 can include a pass bit counter 160a and a first comparator 160b. When the verification signal VFS is input, the pass bit counter 160a can receive verification data V_DATA from the page buffer group (e.g., Figure 2 140) and can count the number of pass chunk bits P_BIT included in the received verification data V_DATA. For example, the verification data V_DATA can be data of a selected chunk in a selected page included in a selected memory block of a selected plane. When the number of all pass chunk bits P_BIT has been counted, the pass bit counter 160a can transfer the number of pass chunk bits P_BIT to the first comparator 160b.

[0068] The first comparator 160b may store a preset reference number NBref of passed chunk bits and may compare the number P_BIT of passed chunk bits with the reference number NBref of passed chunk bits. Then, the first comparator 160b may output a check start signal CSS or a check delay signal CDS based on the result of the comparison. For example, when the number P_BIT of passed chunk bits is equal to or greater than the reference number NBref of passed chunk bits, the first comparator 160b may output a check start signal CSS. When the number P_BIT of passed chunk bits is less than the reference number NBref of passed chunk bits, the first comparator 160b may output a check delay signal CDS. In addition, even when the number P_BIT of chunk bits of all chunks in the selected page is equal to or greater than the reference number NBref of passed chunk bits, the first comparator 160b may output a check start signal CSS.

[0069] The operation of the verification detector 160 based on the number P_BIT of passed chunk bits will be described below.

[0070] Figure 7A and Figure 7B is a diagram illustrating a first embodiment in which the verification detector determines passed bits in verification data.

[0071] Referring to Figure 6 、 Figure 7A and Figure 7B In the first embodiment, the verification detector 160 may receive only the verification data V_DATA of one selected chunk. Then, depending on the comparison result between the number P_BIT of passed chunk bits included in the verification data V_DATA and the reference number NBref of passed chunk bits, the verification detector 160 may output a check start signal CSS or a check delay signal CDS.

[0072] Referring to Figure 6 and Figure 7A To better understand this embodiment, assume that the reference number NBref of passed chunk bits is 63 and may be set to different values depending on the memory device. When the number P_BIT of passed chunk bits is 40, the first comparator 160b may output a check delay signal CDS because the number P_BIT of passed chunk bits is less than the reference number NBref of passed chunk bits.

[0073] Referring to Figure 6 and Figure 7B When the number P_BIT of passed chunk bits is 65, the first comparator 160b may output a check start signal CSS because the number P_BIT of passed chunk bits is equal to or greater than the reference number NBref of passed chunk bits.

[0074] Figure 8 It is a block diagram illustrating a second embodiment in which a verification detector determines pass bits in verification data.

[0075] Referring to Figure 6 and Figure 8 In the second embodiment, the verification detector 160 may sequentially receive verification data pieces V_DATA on a block basis, and may compare the number P_BIT of block bits included in the received verification data V_DATA of each block with a reference number NBref of pass block bits. That is, the verification detector 160 may determine whether a block in which the number P_BIT of pass block bits is equal to or greater than the reference number NBref of pass block bits has been detected among a plurality of blocks included in the selected page, and when a block in which the number P_BIT of pass block bits is equal to or greater than the reference number NBref of pass block bits has been detected, the verification detector 160 may stop receiving the verification data V_DATA.

[0076] For example, the verification detector 160 may receive verification data V_DATA from the first block CHK1, and may count the number P_BIT of pass block bits included in the verification data V_DATA. When the number P_BIT of pass block bits in the first block CHK1 is detected as 50 or more than 50 bits, the number P_BIT of pass block bits is less than the reference number NBref of pass block bits, and thus the verification detector 160 may receive verification data V_DATA from the second block CHK2. When the number P_BIT of pass block bits in the second block CHK2 is detected as 45 bits, the number P_BIT of pass block bits is less than the reference number NBref of pass block bits, and thus the verification detector 160 may receive verification data V_DATA from the third block CHK3. When the number P_BIT of pass block bits in the third block CHK3 is detected as 63 bits, the number P_BIT of pass block bits is equal to the reference number NBref of pass block bits, and thus the verification detector 160 may output a check start signal CSS without receiving verification data V_DATA from the fourth block to the mth block CHK4 to CHKm. That is, when the number P_BIT of pass block bits is equal to or greater than the reference number NBref of pass block bits, the verification detector 160 may output a check start signal CSS, and may stop the operation of comparing the number P_BIT of pass block bits with the reference number NBref of pass block bits.

[0077] Figure 9A and Figure 9B It is a block diagram illustrating a third embodiment in which a verification detector determines pass bits in verification data.

[0078] Referring toFigure 6 , Figure 9A and Figure 9B , in the third embodiment, the verification detector 160 may sequentially receive verification data pieces V_DATA from the first block to the m-th block CHK1 to CHKm, may accumulate the comparison result between the number P_BIT of passed block bits included in the verification data V_DATA and the reference number Nbref of passed block bits, and output a check start signal CSS or a check delay signal CDS depending on the accumulated value.

[0079] Referring to Figure 6 and Figure 9A , the verification detector 160 may receive verification data V_DATA from the first block CHK1 and may count the number P_BIT of passed block bits included in the received verification data V_DATA. When the number P_BIT of passed block bits in the first block CHK1 is 1, 1 is less than the reference number NBref of passed block bits, and thus the verification detector 160 may receive verification data V_DATA from the second block CHK2. When the number P_BIT of passed block bits in the second block CHK2 is 2, the verification detector 160 may calculate the value obtained by summing '1' (which is the number P_BIT of passed block bits in the first block CHK1) and '2' (which is the number P_BIT of passed block bits in the second block CHK2). When the calculated value is 3, 3 is less than the reference number NBref of passed block bits, and thus the verification detector 160 may receive verification data V_DATA from the third block CHK3. When the number P_BIT of passed block bits in the third block CHK3 is 1, the verification detector 160 may calculate the new value obtained by summing '3' (which is the previously calculated value) and '1' (which is the number P_BIT of passed block bits in the third block CHK3). In this way, assuming that the value obtained by summing the number P_BIT of passed block bits in the first block to the m-th block CHK1 to CHKm is 61, 61 is less than the reference number NBref of passed block bits, and thus the verification detector 160 may output a check delay signal CDS.

[0080] Referring to Figure 6 and Figure 9B, when the number of passing chunk bits P_BIT counted in the first to fourth chunks CHK1 to CHK4 are 20, 5, 30, and 10 respectively, the value obtained by summing all the numbers of passing chunk bits P_BIT can be 65. In this case, since the calculated value is greater than the reference number NBref of passing chunk bits, the verification detector 160 can output a check start signal CSS without receiving verification data V_DATA from the fifth to the m-th chunks CHK5 to CHKm.

[0081] Figure 10 is a block diagram illustrating a current sensing check detector according to an embodiment of the present disclosure.

[0082] Referring to Figure 10 , the current sensing check detector 170 may include a failure bit counter 170a and a second comparator 170b.

[0083] The failure bit counter 170a may receive check data C_DATA from a selected plane in response to a check enable signal CHS, may count the number of failure bits included in the check data C_DATA, and may output the number of failure page bits Pa_BIT. For example, the failure bit counter 170a may sequentially receive pieces of check data C_DATA from the plane on which a programming operation is performed, and may output the number of failure page bits Pa_BIT included in each piece of check data C_DATA in the pieces of check data C_DATA. For example, the check data C_DATA may include verification data received from chunks included in a selected page. The failure bit counter 170a may output the number of failure page bits Pa_BIT in the check data C_DATA received from the selected pages of each plane.

[0084] The second comparator 170b may compare the number of failure page bits Pa_BIT with a preset allowable number Nall of failure page bits, and may output a check pass signal CPS or a check fail signal CFA depending on the result of the comparison. The allowable number of failure page bits represents the maximum number of correctable errors included in a page. When the number of failure page bits Pa_BIT is less than or equal to the allowable number Nall of failure page bits, the second comparator 170b may output a check pass signal CPS. Alternatively, when the number of failure page bits Pa_BIT is greater than the allowable number Nall of failure page bits, the second comparator 170b may output a check fail signal CFA.

[0085] The operation of the current sensing check detector 170 will be described in detail below.

[0086] Figure 11A and Figure 11BIt is a block diagram illustrating a method in which a current sensing inspection detector determines pass or fail in a verification operation depending on inspection data.

[0087] Referring to Figure 10 and Figure 11A , the current sensing inspection detector 170 can receive inspection data C_DATA from all planes on which a programming operation is performed, and can compare the number Pa_BIT of failed page bits included in the inspection data C_DATA with the allowable number Nall of failed page bits. For example, the current sensing inspection detector 170 can sequentially receive verification data slices V_DATA of selected pages included in a selected memory block of the first plane PL1, and can count the number Pa_BIT of failed page bits in all received verification data slices V_DATA. Here, all verification data slices V_DATA received from the selected pages of the selected plane can be the inspection data C_DATA. When the number Pa_BIT of failed page bits included in the inspection data C_DATA received from the first plane PL1 is less than or equal to the allowable number Nall of failed page bits, the current sensing inspection detector 170 can determine that the current sensing inspection operation on the first plane PL1 has passed. In this way, the current sensing inspection detector 170 can receive inspection data slices C_DATA from the first plane to the k-th plane PL1 to PLk respectively, and can determine whether the current sensing inspection operation on each plane has passed or failed. As Figure 11A shown in

[0088] Referring to Figure 10 and Figure 11B , when all current sensing inspection operations on the first plane to the k-th plane PL1 to PLk are determined to have passed, the current sensing inspection detector 170 can output an inspection pass signal CPS.

[0089] Figure 12 It is a block diagram illustrating a current sensing inspection controller according to an embodiment of the present disclosure.

[0090] Referring to Figure 12 , the current sensing inspection controller 190 can include a programming loop controller 190a and a detector 190b.

[0091] Depending on the result of a verification operation or a current sensing check operation performed on the selected page, the programming loop controller 190a may output a verification signal VFS or a check enable signal CHS. For example, in response to a pass signal PS or a fail signal FA input during the verification operation or the current sensing check operation, the programming loop controller 190a may output a verification signal VFS or a check enable signal CHS.

[0092] In response to a check start signal CSS or a check delay signal CDS that may be input during an operation of determining the number of memory cells in the first programming state, the detector 190b may output a pass signal PS or a fail signal FA. Then, in response to a check pass signal CPS or a check fail signal CFA that may be input during the verification operation for each programming state, the detector 190b may output a pass signal PS or a fail signal FA.

[0093] Figure 13 is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0094] Referring to Figure 13 During the programming operation according to the present embodiment, a current sensing check operation for determining whether the verification operation has passed or failed may be skipped until the number of memory cells whose threshold voltage has increased to the target voltage in the selected memory cells with the lowest target voltage reaches a preset number of memory cells. Since the number of memory cells whose threshold voltage has increased to the target voltage in the memory cells with the lowest target voltage has reached the preset number of memory cells, a current sensing check operation may be performed. The programming operation according to the present embodiment will be described in detail below.

[0095] In step S131, a value n indicating the order of the target voltage may be set to 1. For example, in a triple-level cell (TLC) scheme in which three-bit data is stored in one memory cell, there may be seven different target voltages to distinguish programming states. In a quad-level cell (QLC) scheme in which four-bit data is stored in one memory cell, there may be 15 different target voltages (see Figure 5 for TLC or QLC). In the TLC or QLC scheme, the lowest target voltage may be the first target voltage, and the programming operation may start from the first target voltage. Therefore, in step S131, '1' may be set as the initial value of n. When the programming operation is performed, in the TLC scheme, n may change from 1 to 7, and in the QLC scheme, n may change from 1 to 15.

[0096] In step S132, a sub-programming operation may be performed on the selected memory cell. The sub-programming operation may be an operation of applying a programming voltage to the selected word line to increase the threshold voltage of the selected memory cell. When the sub-programming operation is first performed, a starting programming voltage may be applied to the selected word line. Among the programming voltages applied to the selected word line, the starting programming voltage may be the lowest voltage.

[0097] After the programming voltage has been applied for a predetermined period of time, a verification operation for the nth target voltage PVn may be performed in step S133. The verification operation may be performed by applying the nth verification voltage to the selected word line.

[0098] After the verification operation in step S133 has been performed for a predetermined period of time, an operation of determining whether a bit of a memory cell whose threshold voltage has increased to the nth target voltage has been detected may be performed in step S134. Since n is 1, the number of memory cells whose threshold voltage has increased to the first target voltage having the lowest level among the plurality of target voltages may be counted in step S134, and pass or fail may be determined by comparing the counted number with a reference number of the memory cells. For example, Figure 6 the verification detector 160 shown in may determine pass or fail by comparing the number P_BIT of passed chunk bits included in the verification data V_DATA with a reference number NBref of passed chunk bits. When the number P_BIT of passed chunk bits is less than the reference number NBref of passed chunk bits, the programming voltage may be increased, and the sub-programming operation in step S132 may be performed using the increased programming voltage. That is, when step S134 fails, the next programming cycle may be executed. Steps S132 to S134 may be repeated while gradually increasing the programming voltage until step S134 passes. When the number P_BIT of passed chunk bits is equal to or greater than the reference number NBref of passed chunk bits, step S134 may pass.

[0099] When step S134 has passed, the next programming cycle may be executed, and then a current sense check (CSC) operation may be performed in step S136. For example, when the sub-programming operation in step S135 is performed, the current sense check operation in step S136 may be performed. The sub-programming operation and the current sense check operation S136 will be described in detail below.

[0100] When step S134 has passed, the sub-programming operation can be executed in step S135. The sub-programming operation can be an operation of applying a programming voltage to the selected word line to increase the threshold voltage of the selected memory cell, and can be executed in a manner similar to step S132. In step S135, a programming voltage higher than the programming voltage used in step S132 can be used.

[0101] While the sub-programming operation in step S135 is being executed, a current sensing check operation S136 corresponding to the verification operation of the previous programming cycle can be executed. For example, when the number of error bits detected in the verification operation of the previous programming cycle is greater than the allowable number of error bits, the current sensing check operation in step S136 can fail. Alternatively, when the number of error bits is less than or equal to the allowable number of error bits, the current sensing check operation S136 can pass.

[0102] When the current sensing check (CSC) operation fails (in the case of "fail"), the verification operation for the nth target voltage PVn can be executed in step S137. The verification operation can be executed by applying the nth verification voltage to the selected word line.

[0103] After the verification operation has been executed in step S137, the sub-programming operation S135 and the current sensing check operation S136 corresponding to the next programming cycle can be executed. The sub-programming operation S135 can be executed using a programming voltage higher than the programming voltage in the previous programming cycle. Then, the current sensing check operation S136 can determine whether the verification operation executed in step S137 has passed or failed.

[0104] When it is determined that the verification operation has passed in the current sensing check operation S136 (in the case of "pass"), it is determined in step S138 whether the nth target voltage PVn is the last target voltage of the programming operation. The last target voltage can be the highest target voltage in the programming operation. For example, when the programming operation in the TLC scheme is executed, each memory cell in the selected memory cells can be programmed to the first target voltage to the seventh target voltage. When the first target voltage PV1 is the lowest voltage and the seventh target voltage PV7 is the highest voltage, the seventh target voltage PV7 can be the last target voltage.

[0105] When the nth target voltage PVn is the last target voltage (in the case of "yes"), the programming operation performed on the selected page can be terminated.

[0106] When the n-th target voltage PVn is not the last target voltage (in the case of "No"), the verification operation for the n-th target voltage PVn can be skipped in step S139, and the next target voltage can be selected in step S140. For example, n can be changed to n + 1 in step S140, and the verification operation S137 for the changed n-th target voltage PVn can be executed.

[0107] Steps S135 to S140 can be repeated until all the current sensing check operations for the target voltages up to the last target voltage pass in step S138.

[0108] Figure 14A and Figure 14B is a diagram illustrating a programming operation according to a first embodiment of the present disclosure, and shows an embodiment of a flowchart based on Figure 13 of.

[0109] Referring to Figure 14A , in the first programming loop LP1, a sub-programming operation using the first programming voltage 1Vpgm and a first verification operation using the first verification voltage V1 can be executed. During the first verification operation using the first verification voltage V1, it can be determined whether the number of memory cells whose threshold voltage has increased to the first verification voltage V1 has been detected as equal to or greater than the reference number of memory cells. When it is determined in the first programming loop LP1 that the number of memory cells whose threshold voltage has increased to the first verification voltage V1 is less than the reference number of memory cells (X), the second programming loop LP2 can be executed without performing the current sensing check (CSC) operation.

[0110] In the second programming loop LP2, a sub-programming operation using the second programming voltage 2Vpgm, which is a step voltage higher than the first programming voltage 1Vpgm, and a first verification operation using the first verification voltage V1 can be executed. When it is determined in the second programming loop LP2 that the number of memory cells whose threshold voltage has increased to the first verification voltage V1 is equal to or greater than the reference number of memory cells (O), the current sensing check (CSC) operation can be executed starting from the third programming loop LP3.

[0111] In the third programming loop LP3, a sub-programming operation using a third programming voltage 3Vpgm that is a step voltage higher than the second programming voltage 2Vpgm, a first verification operation using a first verification voltage V1, and a second verification operation using a second verification voltage V2 can be performed. A current sensing check (CSC) operation for the first verification operation of the second programming loop LP2 can be performed during the sub-programming operation of the third programming loop LP3. When it is determined during the current sensing check (CSC) operation that the first verification operation of the second programming loop LP2 has passed, the first verification operation can be skipped starting from the fourth programming loop LP4. In the above-described manner, the remaining programming loops, i.e., the fourth programming loop to the nth programming loop LP4 to LPn, can be performed, and when the seventh verification operation performed in the nth programming loop has passed, the programming operation for the selected page can be terminated.

[0112] Figure 14B is a diagram illustrating an embodiment in which the number of memory cells that have passed the first verification operation gradually increases compared to the embodiment in which Figure 14A the number of memory cells that have passed the first verification operation gradually increases compared to the embodiment in which

[0113] Referring to Figure 14B , when the number of memory cells that have passed the first verification operation of the first programming loop to the third programming loop LP1 to LP3 is detected to be less than the reference number (X) of memory cells and the number of memory cells that have passed the first verification operation of the fourth programming loop LP4 is detected to be equal to or greater than the reference number (O) of memory cells, a current sensing check (CSC) operation can be performed starting from the fifth programming loop LP5.

[0114] That is, in the first embodiment described with reference to Figure 14A and Figure 14B , the current sensing check (CSC) operation can be skipped until the number of memory cells that have passed the first verification operation using the first verification voltage V1 is detected to be equal to or greater than the reference number of memory cells, and the verification operation using a verification voltage higher than the verification voltage V1 can also be skipped.

[0115] Figure 15 is a diagram illustrating a programming operation according to a second embodiment of the present disclosure.

[0116] Referring to Figure 15, in the second embodiment, the current sensing check (CSC) operation and the verification operation using the next verification voltage can be skipped until the number of memory cells that have passed the first verification operation using the first verification voltage V1 is detected to be equal to or greater than the reference number of memory cells. For example, when in the first programming cycle LP1 and the second programming cycle LP2, the number of memory cells that have passed the first verification operation is detected to be less than the reference number of memory cells, and in the third programming cycle LP3, the number of memory cells that have passed the first verification operation is detected to be equal to or greater than the reference number of memory cells, the current sensing check (CSC) operation and the second verification operation using the second verification voltage V2 can be performed starting from the fourth programming cycle LP4. For example, in the fourth programming cycle LP4, the current sensing check (CSC) operation for the first verification operation can be performed during the sub-programming operation using the fourth programming voltage 4Vpgm. After the sub-programming operation has been performed, the first verification operation to the third verification operation using the first verification voltage to the third verification voltage V1 to V3 can be performed.

[0117] During the current sensing check (CSC) operation performed in the fourth programming cycle LP4, when the first verification operation of the third programming cycle LP3 is determined to have passed, the first verification operation can be skipped starting from the fifth programming cycle LP5.

[0118] Figure 16 FIG. is a diagram illustrating a programming operation according to a third embodiment of the present disclosure.

[0119] Referring to Figure 16 , in the third embodiment, since the current sensing check (CSC) operation for the first verification operation has passed, the verification operation using a verification voltage higher than the first verification voltage V1 can be performed. For example, when in the third programming cycle LP3, the number of memory cells that have passed the first verification operation is detected to be equal to or greater than the reference number of memory cells, the current sensing check (CSC) operation can be performed starting from the fourth programming cycle LP4. When the CSC operation for the first verification operation performed in the fourth programming cycle LP4 has failed, the sub-programming operation and the first verification operation can be performed in the fourth programming cycle LP4. When the CSC operation for the first verification operation performed in the fifth programming cycle LP5 has passed, the first verification operation can be skipped in the fifth programming cycle LP5. Moreover, the second verification operation using the second verification voltage V2 can be performed. Therefore, during the current check sensing (CSC) operation in the sixth programming cycle LP6, it can be determined whether the second verification operation has passed or failed.

[0120] Figure 17 FIG. is a diagram illustrating a programming operation according to a fourth embodiment of the present disclosure.

[0121] Reference Figure 17 , in the initial stage of the programming operation, it may be difficult to sufficiently increase the threshold voltage of the memory cell to the target voltage. Therefore, the verification operation can be skipped in some of the programming cycles that can be performed in the initial stage of the programming operation. For example, in the first programming cycle LP1 and the second programming cycle LP2, only the sub-programming operation can be performed without performing the verification operation. In this way, the interval in which the verification operation is skipped and the programming voltage is only applied to the selected word line is called a blind interval (BLD). The blind interval BLD can be set differently depending on the programming speed of the memory cell. As Figure 17 shown, when the first programming cycle LP1 and the second programming cycle LP2 are included in the blind interval BLD, the first verification operation using the first verification voltage V1 can be performed starting from the third programming cycle LP3. In the third programming cycle LP3, when the number of memory cells that have passed the first verification operation is detected to be less than the reference number of memory cells (X), even in the fourth programming cycle LP4, the current sense check (CSC) operation can be skipped.

[0122] When it is determined in the fourth programming cycle LP4 that the number of memory cells that have passed the first verification operation is detected to be equal to or greater than the reference number of memory cells (O), the current sense check (CSC) operation can be performed starting from the fifth programming cycle LP5. For example, in the fifth programming cycle LP5, the sub-programming operation using the fifth programming voltage 5Vpgm, the first verification operation using the first verification voltage V1, and the second verification operation using the second verification voltage V2 can be performed. During the sub-programming operation, the current sense check (CSC) operation for the first verification operation performed in the fourth programming cycle LP4 can be performed.

[0123] Figure 18 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0124] Reference Figure 18 , in the memory device MD according to an embodiment of the present disclosure, components other than the current sense check (CSC) detector 170 can be configured in the same manner as the memory device MD shown in Figure 2 . Therefore, in the description of the memory device MD of Figure 18 , the description of the components that are the same as those of the memory device MD of Figure 2 will be omitted here.

[0125] In addition to the current sense check operation that determines whether the verification operation has passed or failed, Figure 18 the current sense check detector 170 shown in Figure 2Verify the function of the verification detector 160. For example, the current sensing check detector 170 can count the number of failed memory cells during a programming operation and can perform a current sensing check operation depending on the result of the count.

[0126] The function of the current sensing check detector 170 will be described below. That is, the current sensing check detector 170 can receive check data C_DATA from the page buffer bank 140 in response to a check enable signal CHS, can compare the number of failed bits included in the check data C_DATA with a reference number of failed bits, and can determine whether to perform a current sensing check operation based on the result of the comparison. Here, the check data C_DATA can be chunk data.

[0127] When the number of failed chunk bits is less than or equal to the reference number of failed chunk bits, the current sensing check detector 170 can perform a current sensing check operation. When the number of failed chunk bits is greater than the reference number of failed chunk bits, in the current programming cycle, the current sensing check detector 170 can skip the current sensing check operation.

[0128] When it is determined to perform a current sensing check operation, the current sensing check detector 170 can perform a current sensing check operation to determine whether the verification operation has passed or failed. For example, the current sensing check detector 170 can receive check data C_DATA from the page buffer bank 140 in response to a check enable signal CHS and can compare the number of failed page bits included in the check data C_DATA with an allowable number of failed page bits. Then, the current sensing check detector 170 can output a check pass signal CPS or a check fail signal CFA based on the result of the comparison. For example, the current sensing check detector 170 can output a check pass signal CPS when the number of failed page bits is less than or equal to the allowable number of failed page bits, and can output a check fail signal CFA when the number of failed page bits is greater than the allowable number of failed page bits. When at least one of the multiple planes PL1 to PLk has passed the verification operation, even if the verification operations for the remaining planes have failed, the current sensing check detector 170 can determine that the programming operation has passed and output a check pass signal CPS. For example, the current sensing check detector 170 can output a check pass signal CPS when all of the planes PL1 to PLk have passed the verification operation, and can also output a check pass signal CPS even if one of the planes PL1 to PLk has passed the verification operation.

[0129] The following will describe Figure 18 each embodiment of the programming operation of the memory device MD shown in

[0130] Figure 19It is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0131] Referring to Figure 19 , during the programming operation according to the present embodiment, the current sensing check operation for determining whether the verification operation has passed or failed can be skipped until the number of memory cells whose threshold voltage is lower than the target voltage in the selected memory cells with the lowest target voltage becomes less than or equal to a preset number of memory cells. Since the number of memory cells whose threshold voltage has increased to the target voltage in the memory cells with the lowest target voltage has reached the preset number of memory cells, the current sensing check operation can be performed. The programming operation according to the present embodiment will be described in detail below.

[0132] In step S191, the value n indicating the order of the target voltage can be set to 1. For example, in a triple-level cell (TLC) scheme in which three-bit data is stored in one memory cell, there may be seven different target voltages in order to distinguish the programming states. In a quad-level cell (QLC) scheme in which four-bit data is stored in one memory cell, there may be 15 different target voltages (see Figure 5 for TLC or QLC). In the TLC or QLC scheme, the lowest target voltage can be the first target voltage, and the programming operation can start from the first target voltage. Therefore, in step S191, '1' can be set as the initial value of n. When the programming operation is performed, in the TLC scheme, n can change from 1 to 7, and in the QLC scheme, n can change from 1 to 15.

[0133] In step S192, a sub-programming operation can be performed on the selected memory cells. The sub-programming operation can be an operation of applying a programming voltage to the selected word line to increase the threshold voltage of the selected memory cells. When the sub-programming operation is first performed, the starting programming voltage can be applied to the selected word line. Among the programming voltages applied to the selected word line, the starting programming voltage can be the lowest voltage.

[0134] After the programming voltage has been applied for a predetermined period of time, a verification operation for the nth target voltage PVn can be performed in step S193. The verification operation can be performed by applying the nth verification voltage to the selected word line.

[0135] After the verification operation in step S193 has been performed for a predetermined period of time, an operation of determining whether the bits of the memory cells whose threshold voltage has increased to the nth target voltage have been detected can be performed in step S194. For example, a current sensing check detector (e.g., Figure 18The 170) can count the number of bits of memory cells whose threshold voltage is lower than the nth target voltage. Since n is 1, in step S194, memory cells whose threshold voltage has increased to the first target voltage with the lowest level among the multiple target voltages can be detected, and pass or fail can be determined by comparing the number of detected memory cells with the reference number of memory cells. For example, the current sense check detector 170 can compare the number of failed block bits included in the check data C_DATA with the reference number of failed block bits, and then can determine pass or fail. When the number of failed block bits is greater than the reference number of failed block bits, the programming voltage can be increased, and the sub-programming operation S192 can be performed using the increased programming voltage. That is, when step S194 fails, the next programming cycle can be executed. Steps S192 to S194 can be repeated while gradually increasing the programming voltage until step S194 passes. When the number of failed block bits is less than or equal to the reference number of failed block bits, step S194 can pass.

[0136] When step S194 has passed, the next programming cycle can be executed, and then the current sense check detector 170 can perform a current sense check (CSC) operation in step S196. For example, when the sub-programming operation S195 is executed, the current sense check operation S196 can be executed. The sub-programming operation S195 and the current sense check operation S196 will be described in detail below.

[0137] When step S194 has passed, the sub-programming operation can be performed in step S195. The sub-programming operation can be an operation of applying a programming voltage to the selected word line to increase the threshold voltage of the selected memory cells, and can be performed in a similar manner to step S192. In step S195, a programming voltage higher than the programming voltage used in step S192 can be used.

[0138] While performing the sub-programming operation S195, a current sense check operation S196 corresponding to the verification operation of the previous programming cycle can be performed. For example, when the number of error bits detected in the verification operation of the previous programming cycle is greater than the allowable number of error bits, the current sense check operation S196 can fail. Otherwise, when the number of error bits is less than or equal to the allowable number of error bits, the current sense check operation S196 can pass.

[0139] When the current sense check (CSC) operation fails (in the case of "fail"), a verification operation for the nth target voltage PVn can be performed in step S197. The verification operation can be performed by applying the nth verification voltage to the selected word line.

[0140] After the verification operation has been performed in step S197, the sub-programming operation S195 and the current sensing check operation S196 corresponding to the next programming cycle can be performed. The sub-programming operation S195 can be performed using a programming voltage higher than the programming voltage in the previous programming cycle, and the current sensing check operation S196 can determine whether the verification operation performed in step S197 has passed or failed.

[0141] When it is determined in the current sensing check operation S196 that the verification operation has passed (in the case of "passed"), it can be determined in step S198 whether the n-th target voltage PVn is the last target voltage of the programming operation. The last target voltage can be the highest target voltage in the programming operation. For example, when the programming operation in the TLC scheme is performed, each memory cell in the selected memory cells can be programmed to the first target voltage to the seventh target voltage. When the first target voltage PV1 is the lowest voltage and the seventh target voltage PV7 is the highest voltage, the seventh target voltage PV7 can be the last target voltage.

[0142] When the n-th target voltage PVn is the last target voltage (in the case of "yes"), the programming operation performed on the selected page can be terminated.

[0143] When the n-th target voltage PVn is not the last target voltage (in the case of "no"), the verification operation for the n-th target voltage PVn can be skipped in step S199, and the next target voltage can be selected in step S200. For example, n can be changed to n + 1 in step S200, and the verification operation S197 for the changed n-th target voltage PVn can be performed.

[0144] Steps S195 to S200 can be repeated until all the current sensing check operations for the target voltages up to the last target voltage pass in step S198.

[0145] Figure 20 FIG. is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0146] Referring to Figure 20 , during the programming operation according to the present embodiment, while performing the sub-programming operation, an operation of determining the number of passing bits to determine the time point at which the current sensing check operation is to be started can be performed. The programming operation according to the present embodiment will be described in detail below.

[0147] In step S201, the value n indicating the order of the target voltage can be set to 1. For example, in a triple-level cell (TLC) scheme where three-bit data is stored in one memory cell, there may be seven different target voltages in order to distinguish the programming states. In a quad-level cell (QLC) scheme where four-bit data is stored in one memory cell, there may be 15 different target voltages (see Figure 5 for TLC or QLC). In the TLC or QLC scheme, the lowest target voltage can be the first target voltage, and the programming operation can start from the first target voltage. Therefore, in step S201, '1' can be set as the initial value of n. When the programming operation is executed, in the TLC scheme, n can change from 1 to 7, and in the QLC scheme, n can change from 1 to 15.

[0148] In step S202, a sub-programming operation can be performed on the selected memory cell. The sub-programming operation can be an operation of applying a programming voltage to the selected word line to increase the threshold voltage of the selected memory cell. When the sub-programming operation is first executed, the starting programming voltage can be applied to the selected word line. Among the programming voltages applied to the selected word line, the starting programming voltage can be the lowest voltage.

[0149] After the programming voltage has been applied for a predetermined period in step S202, a verification operation for the nth target voltage PVn can be performed in step S203. The verification operation can be executed by applying the nth verification voltage to the selected word line.

[0150] After the verification operation S203 has been executed, the next programming operation can be performed. Then, an operation S205 of determining the number of passing bits can be performed together with the sub-programming operation S204, and a current sense check (CSC) operation S207 can be selectively executed depending on the determination result in step S205. For example, when the sub-programming operation is executed in step S204, an operation S205 of determining the number of failing bits and a current sense check operation S207 can be performed. The sub-programming operation S204, the operation S205 of determining the number of failing bits, and the current sense check operation S207 will be described in detail below.

[0151] The sub-programming operation S204 can be an operation of applying a programming voltage to the selected word line to increase the threshold voltage of the selected memory cell, and can be executed in a manner similar to step S202. In step S204, a programming voltage higher than the programming voltage used in step S202 can be used.

[0152] While performing the sub-programming operation S204, an operation S205 of comparing the number of failed bits detected in the verification operation of the previous programming cycle with the reference number of failed bits can be performed. For example, in the operation S205 of comparing the number of failed bits with the reference number of failed bits, an operation of determining whether bits of memory cells having a threshold voltage lower than the n-th target voltage are detected can be performed in step S205. Since n is 1, in step S205, the number of memory cells whose threshold voltage is lower than the first target voltage having the lowest level among the multiple target voltages can be counted, and pass or fail can be determined by comparing the counted number with the reference number of memory cells. For example, Figure 18 the current sense check detector 170 shown in Figure 18 can compare the number of failed chunk bits included in the chunk data with the reference number of failed chunk bits, and then can determine pass or fail. When the number of failed chunk bits is greater than the reference number of failed chunk bits, the programming voltage can be increased. Then, the sub-programming operation S204 can be performed again using the increased programming voltage. That is, when step S205 fails, the current sense check operation S207 can be skipped, and the next programming cycle can be performed. Even if step S205 fails, the sub-programming operation can be performed in step S204. Therefore, the verification operation S206 for the sub-programming operation can be performed. That is, when step S205 fails, the verification operation is performed in step S206, and the sub-programming operation S204 can be performed again after step S206.

[0153] Steps S204 to S206 can be repeated while gradually increasing the programming voltage until step S205 passes.

[0154] In step S205, when it is determined that the number of failed chunk bits is less than or equal to the reference number of failed chunk bits (in the case of "pass"), the current sense check operation S207 can be performed. For example, when the number of error bits detected in the verification operation of the previous programming cycle is greater than the allowable number of error bits, the current sense check operation S207 can fail. However, when the number of error bits is less than the allowable number of error bits, the current sense check operation S207 can pass.

[0155] When the current sense check (CSC) operation fails (in the case of "fail"), the verification operation for the n-th target voltage PVn can be performed in step S206. The verification operation can be performed by applying the n-th verification voltage to the selected word line.

[0156] After the verification operation has been performed in step S206, the sub-programming operation S204 corresponding to the next programming cycle, the operation S205 of determining the number of failed bits, and the current sensing check operation S207 can be performed. The sub-programming operation S204 can be performed using a programming voltage higher than the programming voltage in the previous programming cycle. The step S205 of determining the number of passed bits indicates that the corresponding operation has passed in the previous step, and thus the passed state can be continuously maintained while performing subsequent operations.

[0157] The current sensing check operation S207 can determine whether the verification operation performed in step S206 in the previous cycle has passed or failed.

[0158] When the verification operation is determined to have passed in the current sensing check operation S207 (in the case of "passed"), it can be determined in step S208 whether the nth target voltage PVn is the last target voltage of the programming operation. The last target voltage can be the highest target voltage in the programming operation. For example, when the programming operation in the TLC scheme is performed, each memory cell in the selected memory cells can be programmed to the first target voltage to the seventh target voltage. When the first target voltage PV1 is the lowest voltage and the seventh target voltage PV7 is the highest voltage, the seventh target voltage PV7 can be the last target voltage.

[0159] When the nth target voltage PVn is the last target voltage (in the case of "yes"), the programming operation performed on the selected page can be terminated. When the nth target voltage PVn is not the last target voltage (in the case of "no"), the verification operation for the nth target voltage PVn can be skipped in step S209, and the next target voltage can be selected in step S210. For example, n can be changed to n + 1 in step S210, and the verification operation S206 for the changed nth target voltage PVn can be performed.

[0160] Steps S204 to S210 can be repeated until all the current sensing check operations for the target voltages up to the last target voltage pass in step S208.

[0161] Figure 21 FIG. is a diagram illustrating a programming operation according to a fifth embodiment of the present disclosure.

[0162] Referring to Figure 21 In the first programming cycle LP1, the sub-programming operation using the first programming voltage 1Vpgm and the first verification operation using the first verification voltage V1 can be performed. The first verification operation can include the operation of sensing the threshold voltage of the selected memory cells using the first verification voltage V1.

[0163] In the second programming loop LP2, a sub-programming operation using a second programming voltage 2Vpgm that is a step voltage higher than the first programming voltage 1Vpgm, and a first verification operation using a first verification voltage V1 can be performed.

[0164] Starting from the second programming loop LP2, an operation PV1 for determining whether the number of memory cells whose threshold voltage has increased to the first verification voltage V1 has been detected to be equal to or greater than a reference number of memory cells can be performed. For example, while the sub-programming operation of the second programming loop LP2 is being performed, an operation PV1 for determining whether the number of memory cells whose threshold voltage is lower than the first verification voltage V1 has been detected to be less than or equal to a reference number of memory cells can be performed. When it is determined that the number of memory cells whose threshold voltage is lower than the first verification voltage V1 is greater than the reference number of memory cells (X), the remaining operations of the second programming loop LP2 can be performed without performing a current sense check (CSC) operation. For example, after the sub-programming operation has been performed, a first verification operation using the first verification voltage V1 can be performed.

[0165] In the third programming loop LP3, a sub-programming operation using a third programming voltage 3Vpgm that is a step voltage higher than the second programming voltage 2Vpgm, a first verification operation using the first verification voltage V1, and a second verification operation using a second verification voltage V2 can be performed. While the sub-programming operation of the third programming loop LP3 is being performed, an operation PV1 for determining whether the number of memory cells whose threshold voltage is lower than the first verification voltage V1 has been detected to be less than or equal to a reference number of memory cells can be performed. When it is determined that the number of memory cells whose threshold voltage is lower than the first verification voltage V1 is greater than the reference number of memory cells (O), a current sense check (CSC) operation can be performed starting from the third programming loop LP3. For example, during the operation PV1 for determining whether the number of memory cells whose threshold voltage is lower than the first verification voltage V1 has been detected to be less than or equal to a reference number of memory cells, the number of failed bits in the corresponding block can be counted. In addition, in the current sense check (CSC) operation, it can be determined on a plane basis whether the verification operation has passed or failed.

[0166] That is, the current sense check (CSC) operation performed in the third programming loop LP3 can be an operation for determining whether the first verification operation of the second programming loop LP2 has passed or failed. When it is determined in the current sense check (CSC) operation that the first verification operation of the second programming loop LP2 has passed, the first verification operation can be skipped starting from the fourth programming loop LP4.

[0167] In the above-described manner, the remaining programming loops can be executed, i.e., the fourth programming loop to the nth programming loop LP4 to LPn. Then, when the seventh verification operation performed in the nth programming loop has passed, the programming operation for the selected page can be terminated.

[0168] Figure 22 FIG. is a diagram illustrating a programming operation according to a sixth embodiment of the present disclosure.

[0169] Referring to Figure 22 , in the first programming loop LP1, a sub-programming operation using a first programming voltage of 1 Vpgm and a first verification operation using a first verification voltage V1 can be performed. The first verification operation can include an operation of sensing the threshold voltage of the selected memory cell using the first verification voltage V1.

[0170] In the second programming loop LP2, a sub-programming operation using a second programming voltage of 2 Vpgm, which is a step voltage higher than the first programming voltage 1 Vpgm, and a first verification operation using the first verification voltage V1 can be performed.

[0171] From the second programming loop LP2, an operation PV1 of determining whether the number of memory cells whose threshold voltage has increased to the first verification voltage V1 has been detected to be equal to or greater than a reference number of memory cells can be performed. For example, while the sub-programming operation in the second programming loop LP2 is being performed, an operation PV1 of determining whether the number of memory cells whose threshold voltage is lower than the first verification voltage V1 has been detected to be less than or equal to the reference number of memory cells can be performed. When it is determined that the number of memory cells whose threshold voltage is lower than the first verification voltage V1 is greater than the reference number of memory cells (X), the remaining operations of the second programming loop LP2 can be performed without performing a current sense check (CSC) operation. For example, after the sub-programming operation has been performed, a first verification operation using the first verification voltage V1 can be performed.

[0172] In the third programming loop LP3, a sub-programming operation using a third programming voltage of 3 Vpgm, which is a step voltage higher than the second programming voltage 2 Vpgm, a first verification operation using the first verification voltage V1, and a second verification operation using a second verification voltage V2 can be performed. While the sub-programming operation in the third programming loop LP3 is being performed, an operation PV1 of determining whether the number of memory cells whose threshold voltage is lower than the first verification voltage V1 is greater than the reference number of memory cells can be performed. When it is determined that the number of memory cells whose threshold voltage is lower than the first verification voltage V1 is less than or equal to the reference number of memory cells (O), the first verification operation can be performed only up to the third programming loop LP3. Then, the first verification operation using the first verification voltage V1 can be skipped starting from the fourth programming loop LP4.

[0173] When the number of memory cells whose threshold voltage is lower than the first verification voltage V1 in the third programming cycle LP3 is less than or equal to the reference number of memory cells (O), a current sensing check (CSC) operation can be performed starting from the fourth programming cycle LP4.

[0174] In the above manner, the remaining programming cycles, i.e., the fourth programming cycle to the nth programming cycle LP4 to LPn, can be performed, and when the seventh verification operation performed in the nth programming cycle has passed, the programming operation of the selected page can be terminated.

[0175] Figure 23 is a block diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0176] Referring to Figure 23 , the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0177] The memory controller 2100 is coupled to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control the programming operation, read operation, or erase operation of the memory device 2200, or can control the background operation of the memory device 2200. The memory controller 2100 can provide an interface between the memory device 2200 and the host. The memory controller 2100 can run firmware for controlling the memory device 2200. The memory device 2200 can be operated in the same manner as the memory device MD described above with reference to Figure 2 or Figure 18 described.

[0178] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a specific communication protocol. In an embodiment, the memory controller 2100 may communicate with an external device through at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WIFI, Bluetooth, and Non-Volatile Memory Express (NVMe) protocol. In an embodiment, the connector 2300 may be defined by at least one of the above various communication protocols.

[0179] In an embodiment, the memory device 2200 may be implemented as any one of various non-volatile memory devices, such as Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM).

[0180] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card, such as Personal Computer Memory Card International Association (PCMCIA), CompactFlash card (CF), SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), SD card (SD, miniSD, microSD or SDHC), Universal Flash Storage (UFS), etc.

[0181] Figure 24 is a block diagram of a Solid State Drive (SSD) system applying a memory device according to the present disclosure.

[0182] Referring to Figure 24 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 may exchange signals with the host 3100 through a signal connector 3001 and may receive a power supply voltage through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0183] According to an embodiment of the present disclosure, flash memories 3221 to 322n may be configured in the same manner as the memory device MD described with reference to Figure 2 or Figure 18 described.

[0184] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100. In an embodiment, the signal may be a signal based on an interface between the host 3100 and the SSD 3200. For example, such a signal may be a signal defined by at least one of various interfaces, such as a Universal Serial Bus (USB), a Multimedia Card (MMC), an Embedded MMC (eMMC), a Peripheral Component Interconnect (PCI), a PCI-Express (PCI-E), an Advanced Technology Attachment (ATA), a Serial ATA (SATA), a Parallel ATA (PATA), a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), FireWire, a Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and a Non-Volatile Memory Express (NVMe) interface.

[0185] The auxiliary power supply 3230 may be coupled to the host 3100 through a power connector 3002. The auxiliary power supply 3230 may be supplied with power from the host 3100 and may be charged. When the power supply from the host 3100 is not performed smoothly, the auxiliary power supply 3230 may supply power to the SSD 3200. In an embodiment, the auxiliary power supply 3230 may be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 may be located on a main board and may also supply auxiliary power to the SSD 3200.

[0186] The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as a DRAM, an SDRAM, a DDR SDRAM, and an LPDDR SDRAM, or a non-volatile memory such as a FRAM, a ReRAM, an STT-MRAM, and a PRAM.

[0187] The present disclosure may shorten the time required for a programming operation of a memory device.

Claims

1. A memory device, comprising: A plurality of pages, each of the plurality of pages including a plurality of memory cells; Peripheral circuitry that performs a plurality of programming cycles and programs a selected page from the plurality of pages, wherein the peripheral circuitry counts the number of memory cells among a portion of the memory cells included in the selected page whose threshold voltage has increased to a first target voltage, and performs a current sensing check operation to determine whether a verification operation performed in a previous programming cycle has passed or failed; And Control logic circuitry that controls the peripheral circuitry such that: When the number of memory cells whose threshold voltage has increased to the first target voltage is less than a reference number of memory cells, it delays performing the current sensing check operation, and When the number of memory cells whose threshold voltage has increased to the first target voltage is equal to or greater than the reference number of memory cells, it performs the current sensing check operation.

2. The memory device according to claim 1, wherein the peripheral circuitry includes: A verification detector that compares the number of memory cells whose threshold voltage has increased to the first target voltage with the reference number of memory cells, and outputs a check start signal or a check delay signal based on the result of the comparison; And A current sensing check detector that delays the current sensing check operation for determining whether the verification operation performed in the previous programming cycle has passed or failed until a check enable signal is output from the control logic circuitry, and when the check enable signal is output, the current sensing check detector performs the current sensing check operation.

3. The memory device according to claim 2, wherein the verification detector includes: A first bit counter that verifies the memory cells in the selected page on a block basis, counts the number of memory cells whose threshold voltage has increased to the first target voltage, and outputs the number of passed block bits that have been counted; and A first comparator that compares the number of passed block bits with a reference number of passed block bits, and when the number of passed block bits is equal to or greater than the reference number of passed block bits, the first comparator outputs the check start signal, and when the number of passed block bits is less than the reference number of passed block bits, the first comparator outputs the check delay signal.

4. The memory device according to claim 3, wherein: The first bit counter receives verification data from one block selected from a plurality of blocks included in the selected page, and outputs the number of passed block bits included in the verification data, and When the number of passed block bits is equal to or greater than the reference number of passed block bits, the first comparator outputs the check start signal, and when the number of passed block bits is less than the reference number of passed block bits, the first comparator outputs the check delay signal.

5. The memory device according to claim 3, wherein: the first bit counter sequentially receives verification data slices included in a plurality of chunks included in the selected page, and sequentially outputs the number of passing chunk bits included in the verification data slices, and the first comparator compares the sequentially received number of passing chunk bits with the reference number of passing chunk bits, and outputs the check start signal or the check delay signal based on the result of the comparison.

6. The memory device according to claim 5, wherein: the first comparator compares the number of passing chunk bits corresponding to the plurality of chunks respectively with the reference number of passing chunk bits, and then outputs the check start signal or the check delay signal, and when each of the numbers of passing chunk bits is equal to or greater than the reference number of passing chunk bits, the first comparator outputs the check start signal, and subsequently stops the operation of comparing the number of passing chunk bits with the reference number of passing chunk bits.

7. The memory device according to claim 5, wherein the first comparator compares a value obtained by summing the numbers of passing chunk bits of the plurality of chunks with the reference number of passing chunk bits, and then outputs the check start signal or the check delay signal.

8. The memory device according to claim 2, wherein the current sensing check detector includes: a second bit counter that, in response to the check enable signal, receives data sensed from the selected page, counts the number of failing bits included in the sensed data, and outputs the number of failing page bits; and a second comparator that compares the number of failing page bits with the allowable number of failing page bits, and outputs a check pass signal or a check fail signal based on the result of the comparison.

9. The memory device according to claim 8, wherein: when the number of failing page bits is less than or equal to the allowable number of failing page bits, the second comparator outputs the check pass signal, and when the number of failing page bits is greater than the allowable number of failing page bits, the second comparator outputs the check fail signal.

10. The memory device according to claim 8, wherein, When the selected page is included in each of a plurality of planes, when, in all of the planes, the number of failing page bits of the selected page is less than or equal to the allowable number of failing page bits, the second comparator outputs the check pass signal, and when, in at least one of the planes, the number of failing page bits of the selected page is greater than the allowable number of failing page bits, the second comparator outputs the check fail signal.

11. The memory device according to claim 1, wherein the control logic circuit includes: A current sensing check controller selectively outputs a check enable signal for performing the current sensing check operation depending on the number of memory cells whose threshold voltage is lower than the first target voltage, and controls the programming cycle of the selected page depending on the result of the verification operation or the current sensing check operation on the selected page.

12. The memory device according to claim 11, wherein the current sensing check controller comprises: A programming cycle controller that outputs a verification signal or the check enable signal depending on the result of the verification operation or the current sensing check operation for each programming cycle performed on the selected page; And A detector that outputs a pass signal when the number of memory cells whose threshold voltage is lower than the first target voltage is less than or equal to the reference number of memory cells, or when the verification operation has passed, and outputs a fail signal when the number of memory cells whose threshold voltage is lower than the first target voltage is greater than the reference number of memory cells, or when the verification operation has failed.

13. The memory device according to claim 1, wherein the peripheral circuit includes a current sensing check detector, The current sensing check detector compares the number of memory cells whose threshold voltage has increased to the first target voltage with the reference number of memory cells, and outputs a check start signal or a check delay signal based on the result of the comparison, or The current sensing check detector delays the current sensing check operation for determining whether the verification operation performed in the previous programming cycle has passed or failed until the check enable signal is output from the control logic circuit, and when the check enable signal is output, the current sensing check detector performs the current sensing check operation.

14. A method of operating a memory device, comprising: Performing a sub-programming operation of applying a programming voltage to a plurality of memory cells included in a selected page; Performing a verification operation for verifying the threshold voltage of a selected memory cell having the lowest target voltage selected from the plurality of memory cells; And Comparing the number of pass bits detected in the verification operation with a reference number of pass bits, When the number of pass bits is less than the reference number of pass bits, skipping a current sensing check operation for determining whether the verification operation has passed or failed in the next programming cycle, and When the number of pass bits is equal to or greater than the reference number of pass bits, performing the current sensing check operation starting from the next programming cycle.

15. The method according to claim 14, wherein the number of pass bits is the number of memory cells among the selected memory cells having the lowest target voltage whose threshold voltage has increased to the target voltage.

16. The method according to claim 14, wherein, When the number of passed bits is less than the reference number of passed bits, a programming voltage higher than the programming voltage is used to perform the next programming cycle.

17. The method according to claim 14, wherein before the next programming cycle is performed or during a sub-programming operation of the next programming cycle, a comparison of the number of passed bits detected in the verification operation with the reference number of passed bits is performed.

18. The method according to claim 14, wherein, When the current sensing check operation is performed, the current sensing check operation is performed during the sub-programming operation.

19. The method according to claim 14, wherein When the current sensing check operation is performed, a comparison of the number of passed bits detected in the verification operation with the reference number of passed bits is skipped.

20. A method of operating a memory device, comprising: Performing a plurality of programming cycles to increase the threshold voltages of memory cells in a selected page, wherein in each of the plurality of programming cycles, when the number of memory cells whose threshold voltages have increased to a target voltage is less than a reference number of memory cells, a current sensing check operation for determining the result of the verification operation of the previous programming cycle is skipped, and when the number of memory cells whose threshold voltages have increased to the target voltage is equal to or greater than the reference number of memory cells, the current sensing check operation is performed.

21. The method according to claim 20, wherein, When the number of memory cells whose threshold voltages have increased to the target voltage is less than the reference number of memory cells, the corresponding programming cycle includes: Applying a programming voltage to a word line coupled to the selected page to increase the threshold voltage of the memory cells; and Comparing the number of memory cells whose threshold voltages have increased to the target voltage with the reference number of memory cells.

22. The method according to claim 20, wherein When the number of memory cells whose threshold voltages have increased to the target voltage is equal to or greater than the reference number of memory cells, the corresponding programming cycle includes: Applying a programming voltage to a word line coupled to the selected page to increase the threshold voltage of the memory cells, and performing the current sensing check operation; and Performing a verification operation to sense whether the threshold voltages of all the memory cells have increased to the target voltage.

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