Storage device, system, and storage device operating method

Abstract

The present application discloses a memory device, a system, and an operating method for the memory device, belonging to the field of memory technology. In the process of erasing a memory block, the method applies a first voltage to the first end of a memory string, and applies a second voltage less than the first voltage to a word line coupled to a first memory cell of the memory string. Since the voltage difference between the first voltage and the second voltage is greater than or equal to the tunneling voltage of the first memory cell, invalid data stored therein can be erased. In addition, a third voltage less than the first voltage is configured for the word line coupled to a second memory cell of the memory string. Since the voltage difference between the first voltage and the third voltage is less than the tunneling voltage of the second memory cell, valid data stored therein is protected from being erased, thereby eliminating the need to migrate valid data, saving time for migrating valid data back and forth, and improving the erasing efficiency of the memory block.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage device, a system, and an operating method of the storage device. Background Art

[0002] With the development of semiconductor technology, three-dimensional (3D) memory devices have gained widespread application. In related technologies, a 3D memory device stores data, such as photos, in its memory blocks. When a photo in a memory block is to be deleted, the 3D memory device erases the corresponding data in the memory block. The data to be erased in the memory block is invalid data, while the remaining data to be retained is valid data.

[0003] During the data erasure process, the 3D storage device first migrates valid data in the storage block to the selected over-provisioning block, then erases the data in the storage block, and finally migrates the valid data in the over-provisioning block back to the original storage location.

[0004] This erasing method based on storage blocks requires migrating valid data in the storage blocks back and forth, which increases the time required to erase data and reduces data erasure efficiency. Therefore, an operating method that can improve erasure efficiency is urgently needed. Summary of the Invention

[0005] The present invention provides a memory device, a system, and a method for operating the memory device, which can improve the data erasure efficiency of the memory device. The technical solution is as follows:

[0006] In a first aspect, a memory device is provided, the memory device comprising a memory array and a peripheral circuit;

[0007] The memory array includes a memory string and a plurality of word lines, the memory string includes at least one first memory cell and at least one second memory cell, the first memory cell is a memory cell in the memory string storing invalid data, and the second memory cell is a memory cell in the memory string storing valid data;

[0008] The plurality of word lines are respectively coupled to the memory array;

[0009] The peripheral circuit is coupled to the plurality of word lines and is configured to:

[0010] Applying a first voltage to a first end of the memory string, where the first end is an end coupled to a bit line contact corresponding to the memory string or an end coupled to a source contact corresponding to the memory string;

[0011] Applying a second voltage to a word line coupled to the first memory cell, wherein the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage;

[0012] A third voltage is configured for a word line coupled to the second memory cell, where the third voltage is lower than the first voltage, and a voltage difference between the first voltage and the third voltage is lower than a second tunneling voltage.

[0013] In a possible implementation, the peripheral circuit is further configured as follows:

[0014] The third voltage is applied to the coupled word line of the second memory cell.

[0015] In a possible implementation, the peripheral circuit is further configured as follows:

[0016] The word line coupled to the second memory cell is floated.

[0017] In a possible implementation, the memory string further includes at least one first selection transistor, where the first selection transistor is close to the first end; and the peripheral circuit is further configured as follows:

[0018] A fourth voltage is applied to the selection line coupled to the first selection transistor, where the fourth voltage is lower than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfies a voltage difference condition for band-to-band tunneling.

[0019] In a possible implementation, the first end is coupled to a bit line contact corresponding to the memory string, the bit line contact is an N-type doped conductive structure, and a doping concentration of impurities is greater than or equal to a first concentration.

[0020] In one possible implementation, the first concentration is 5*10^8.

[0021] In a possible implementation manner, the first end is coupled to a source contact portion corresponding to the memory string.

[0022] In one possible implementation, the memory string further includes at least one first selection transistor, the first selection transistor being close to the first end, the first end being coupled to a source contact corresponding to the memory string, the source contact being a P-type doped conductive structure; and the peripheral circuit is further configured as follows:

[0023] A fifth voltage is applied to the selection line coupled to the first selection transistor, where the fifth voltage is lower than the first voltage.

[0024] In a possible implementation manner, the first storage unit is close to the first end, and the second storage unit is far from the first end.

[0025] In a possible implementation, the memory string further includes at least one second selection transistor, where the at least one second selection transistor is located away from the first end; and the peripheral circuit is further configured to:

[0026] A sixth voltage is configured for the selection line coupled to the second selection transistor. The sixth voltage is lower than the first voltage, and a voltage difference between the first voltage and the sixth voltage is lower than a third tunneling voltage.

[0027] In a possible implementation, the first storage unit is far away from the first end, and the second storage unit is close to the first end; and the peripheral circuit is further configured as follows:

[0028] Before the channel voltage of the memory string reaches a seventh voltage, applying an eighth voltage to the word line coupled to the second memory cell, wherein the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage;

[0029] After the channel voltage of the memory string reaches the seventh voltage, the step of configuring a third voltage for the word line coupled to the second memory cell is performed.

[0030] In a possible implementation, the memory string further includes at least one second selection transistor, where the at least one second selection transistor is located away from the first end; and the peripheral circuit is further configured to:

[0031] Before the channel voltage of the memory string reaches the seventh voltage, applying a ninth voltage to the selection line coupled to the second selection transistor, wherein the seventh voltage is greater than the ninth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the ninth voltage is less than a third tunneling voltage;

[0032] After the channel voltage of the storage string reaches the seventh voltage, a sixth voltage is configured for the selection line coupled to the second selection transistor, the sixth voltage is less than the first voltage, and a voltage difference between the first voltage and the sixth voltage is less than a third tunneling voltage.

[0033] In a second aspect, a system is provided, the system comprising a memory device configured to store data, the memory device comprising a memory array and a peripheral circuit;

[0034] The memory array includes a memory string and a plurality of word lines, the memory string includes at least one first memory cell and at least one second memory cell, the first memory cell is a memory cell in the memory string storing invalid data, and the second memory cell is a memory cell in the memory string storing valid data;

[0035] The plurality of word lines are respectively coupled to the plurality of memory cells of the memory string;

[0036] The peripheral circuit is coupled to the memory array and is configured to:

[0037] Applying a first voltage to a first end of the memory string, where the first end is an end coupled to a bit line contact corresponding to the memory string or an end coupled to a source contact corresponding to the memory string;

[0038] Applying a second voltage to a word line coupled to the first memory cell, wherein the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage;

[0039] A third voltage is configured for a word line coupled to the second memory cell, where the third voltage is lower than the first voltage, and a voltage difference between the first voltage and the third voltage is lower than a second tunneling voltage.

[0040] In a possible implementation, the peripheral circuit is further configured as follows:

[0041] The third voltage is applied to the coupled word line of the second memory cell.

[0042] In a possible implementation, the peripheral circuit is further configured as follows:

[0043] The word line coupled to the second memory cell is floated.

[0044] In a possible implementation, the memory string further includes at least one first selection transistor, where the first selection transistor is close to the first end; and the peripheral circuit is further configured as follows:

[0045] A fourth voltage is applied to the selection line coupled to the first selection transistor, where the fourth voltage is lower than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfies a voltage difference condition for band-to-band tunneling.

[0046] In a possible implementation, the first end is coupled to a bit line contact corresponding to the memory string, the bit line contact is an N-type doped conductive structure, and a doping concentration of impurities is greater than or equal to a first concentration.

[0047] In one possible implementation, the first concentration is 5*10^8.

[0048] In a possible implementation manner, the first end is coupled to a source contact portion corresponding to the memory string.

[0049] In one possible implementation, the memory string further includes at least one first selection transistor, the first selection transistor being close to the first end, the first end being coupled to a source contact corresponding to the memory string, the source contact being a P-type doped conductive structure; and the peripheral circuit is further configured as follows:

[0050] A fifth voltage is applied to the selection line coupled to the first selection transistor, where the fifth voltage is lower than the first voltage.

[0051] In a possible implementation manner, the first storage unit is close to the first end, and the second storage unit is far from the first end.

[0052] In a possible implementation, the memory string further includes at least one second selection transistor, where the at least one second selection transistor is located away from the first end; and the peripheral circuit is further configured to:

[0053] A sixth voltage is configured for the selection line coupled to the second selection transistor. The sixth voltage is lower than the first voltage, and a voltage difference between the first voltage and the sixth voltage is lower than a third tunneling voltage.

[0054] In a possible implementation, the first storage unit is far away from the first end, and the second storage unit is close to the first end; and the peripheral circuit is further configured as follows:

[0055] Before the channel voltage of the memory string reaches a seventh voltage, applying an eighth voltage to the word line coupled to the second memory cell, wherein the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage;

[0056] After the channel voltage of the memory string reaches the seventh voltage, the step of configuring a third voltage for the word line coupled to the second memory cell is performed.

[0057] In a possible implementation, the memory string further includes at least one second selection transistor, where the at least one second selection transistor is located away from the first end; and the peripheral circuit is further configured to:

[0058] Before the channel voltage of the memory string reaches the seventh voltage, applying a ninth voltage to the selection line coupled to the second selection transistor, wherein the seventh voltage is greater than the ninth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the ninth voltage is less than a third tunneling voltage;

[0059] After the channel voltage of the storage string reaches the seventh voltage, a sixth voltage is configured for the selection line coupled to the second selection transistor, the sixth voltage is less than the first voltage, and a voltage difference between the first voltage and the sixth voltage is less than a third tunneling voltage.

[0060] In a possible implementation, the system further includes a host and a memory controller;

[0061] The host is configured to send data to the storage device or receive data from the storage device;

[0062] The memory controller is coupled to the host and the memory device and is configured to control the memory device.

[0063] In a third aspect, a method for operating a memory device is provided, wherein the memory device includes a memory array, the memory array includes memory strings and a plurality of word lines, the memory strings include at least one first memory cell and at least one second memory cell, the first memory cell being a memory cell in the memory string storing invalid data, the second memory cell being a memory cell in the memory string storing valid data, the plurality of word lines being coupled to the plurality of memory cells in the memory strings, respectively; the method comprising:

[0064] Applying a first voltage to a first end of the memory string, where the first end is an end coupled to a bit line contact corresponding to the memory string or an end coupled to a source contact corresponding to the memory string;

[0065] Applying a second voltage to a word line coupled to the first memory cell, wherein the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage;

[0066] A third voltage is configured for a word line coupled to the second memory cell, where the third voltage is lower than the first voltage, and a voltage difference between the first voltage and the third voltage is lower than a second tunneling voltage.

[0067] In a possible implementation manner, configuring a third voltage for a word line coupled to the second memory cell includes:

[0068] The third voltage is applied to the coupled word line of the second memory cell.

[0069] In a possible implementation manner, configuring a third voltage for a word line coupled to the second memory cell includes:

[0070] The word line coupled to the second memory cell is floated.

[0071] In a possible implementation, the storage string further includes at least one first selection tube, the first selection tube being close to the first end; and the method further includes:

[0072] A fourth voltage is applied to the selection line coupled to the first selection transistor, where the fourth voltage is lower than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfies a voltage difference condition for band-to-band tunneling.

[0073] In a possible implementation, the first end is coupled to a bit line contact corresponding to the memory string, the bit line contact is an N-type doped conductive structure, and a doping concentration of impurities is greater than or equal to a first concentration.

[0074] In one possible implementation, the first concentration is 5*10^8.

[0075] In a possible implementation manner, the first end is coupled to a source contact portion corresponding to the memory string.

[0076] In one possible implementation, the memory string further includes at least one first selection transistor, the first selection transistor being close to the first end, the first end being coupled to a source contact corresponding to the memory string, the source contact being a P-type doped conductive structure; and the method further includes:

[0077] A fifth voltage is applied to the selection line coupled to the first selection transistor, where the fifth voltage is lower than the first voltage.

[0078] In a possible implementation manner, the first storage unit is close to the first end, and the second storage unit is far from the first end.

[0079] In a possible implementation, the storage string further includes at least one second selection tube, and the at least one second selection tube is away from the first end; and the method further includes:

[0080] A sixth voltage is configured for the selection line coupled to the second selection transistor. The sixth voltage is lower than the first voltage, and a voltage difference between the first voltage and the sixth voltage is lower than a third tunneling voltage.

[0081] In a possible implementation, the first storage unit is far away from the first end, and the second storage unit is close to the first end; the method further includes:

[0082] Before the channel voltage of the memory string reaches a seventh voltage, applying an eighth voltage to the word line coupled to the second memory cell, wherein the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage;

[0083] After the channel voltage of the memory string reaches the seventh voltage, the step of configuring a third voltage for the word line coupled to the second memory cell is performed.

[0084] In a possible implementation, the storage string further includes at least one second selection tube, and the at least one second selection tube is away from the first end; and the method further includes:

[0085] Before the channel voltage of the memory string reaches the seventh voltage, applying a ninth voltage to the selection line coupled to the second selection transistor, wherein the seventh voltage is greater than the ninth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the ninth voltage is less than a third tunneling voltage;

[0086] After the channel voltage of the storage string reaches the seventh voltage, a sixth voltage is configured for the selection line coupled to the second selection transistor, the sixth voltage is less than the first voltage, and a voltage difference between the first voltage and the sixth voltage is less than a third tunneling voltage.

[0087] The technical solution provided by the present application is that, during the process of erasing a storage block, a first voltage is applied to the first end of the storage string, and a second voltage less than the first voltage is applied to the word line coupled to the first storage cell of the storage string. Since the voltage difference between the first voltage and the second voltage is greater than or equal to the tunneling voltage of the first storage cell, invalid data stored therein can be erased. In addition, a third voltage less than the first voltage is configured for the word line coupled to the second storage cell of the storage string. Since the voltage difference between the first voltage and the third voltage is less than the tunneling voltage of the second storage cell, the valid data stored therein is protected from being erased, and there is no need to migrate the valid data, which saves time for migrating the valid data back and forth and improves the erasing efficiency of the storage block. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Figure 1 is a schematic diagram of a system provided in an embodiment of the present application;

[0089] Figure 2 is a schematic diagram of a memory card provided in an embodiment of the present application;

[0090] Figure 3 is a schematic diagram of a solid-state drive provided by an embodiment of the present application;

[0091] Figure 4 is a block diagram of a storage device provided in an embodiment of the present application;

[0092] Figure 5 is a structural diagram of a storage device provided in an embodiment of the present application;

[0093] Figure 6This is a schematic diagram of the structure of a storage block provided in an embodiment of the present application;

[0094] Figure 7 is a cross-sectional side view of a storage string provided in an embodiment of the present application;

[0095] Figure 8 is a schematic diagram of a peripheral circuit provided in an embodiment of the present application;

[0096] Figure 9 is a flowchart of a method for operating a memory device provided in an embodiment of the present application;

[0097] Figure 10 This is a schematic diagram of the distribution of storage units in a storage string provided in an embodiment of the present application;

[0098] Figure 11 This is a schematic diagram of voltage waveforms during data erasure under scenario 1.1 provided in an embodiment of the present application;

[0099] Figure 12 1.2 is a schematic diagram of voltage waveforms during data erasure in a scenario 1.2 provided in an embodiment of the present application;

[0100] Figure 13 2.1.1 is a schematic diagram of voltage waveforms during data erasure in accordance with an embodiment of the present application;

[0101] Figure 14 2.1.2 is a schematic diagram of voltage waveforms during data erasure in accordance with an embodiment of the present application;

[0102] Figure 15 2.2.1 is a schematic diagram of voltage waveforms during data erasure in accordance with an embodiment of the present application;

[0103] Figure 16 2.2.2 is a schematic diagram of voltage waveforms during data erasure in accordance with an embodiment of the present application;

[0104] Figure 17 This is a flow chart of another method for operating a memory device provided in an embodiment of the present application:

[0105] Figure 18 This is a schematic diagram of voltage waveforms during data erasure under situation 3 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0106] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0107] In this application, the terms "first," "second," and the like are used to distinguish identical or similar items having substantially the same role and function. It should be understood that "first," "second," and "nth" do not have a logical or temporal dependency, nor do they limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," and the like to describe various elements, these elements should not be limited by these terms.

[0108] These terms are simply used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of various examples. Both the first element and the second element can be elements, and in some cases, can be separate and different elements.

[0109] Here, at least one refers to one or more than one, for example, at least one element can be one element, two elements, three elements, or any other integer greater than or equal to one. At least two refers to two or more than two, for example, at least two elements can be two elements, three elements, or any other integer greater than or equal to two.

[0110] Figure 1 is a schematic diagram of a system provided in an embodiment of the present application. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device.

[0111] like Figure 1 As shown, system 100 includes a host 101 and a storage subsystem 102. Host 101 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 101 may be configured to send data to storage device 103. Alternatively, host 101 may be configured to receive data from storage device 103.

[0112] The storage subsystem 102 includes one or more storage devices 103 and a memory controller 104. The storage device 103 may be any memory disclosed herein. Alternatively, the storage device 103 may be a NAND flash memory device, such as a three-dimensional (3D) NAND flash memory device.

[0113] According to some embodiments, memory controller 104 is coupled to host 101 and memory device 103 and is configured to control memory device 103. Memory controller 104 may manage data stored in memory device 103 and communicate with host 101.

[0114] In one possible embodiment, the memory controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0115] In one possible implementation, the memory controller 104 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0116] The memory controller 104 may be configured to control operations of the memory device 103, such as read, erase, and program operations. The memory controller 104 may also be configured to manage various functions related to data stored or to be stored in the memory device 103, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In one possible embodiment, the memory controller 104 is further configured to process error correction code (ECC) for data read from or written to the memory device 103.

[0117] The memory controller 104 may also perform any other suitable functions, such as formatting the memory device 103. The memory controller 104 may communicate with an external device (e.g., the host 101) according to a specific communication protocol. For example, the memory controller 104 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0118] The memory controller 104 and the one or more memory devices 103 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the system 100 can be implemented and packaged into different types of terminal electronic products.

[0119] Figure 2 is a schematic diagram of a memory card provided in an embodiment of the present application, such as Figure 2 As shown, the memory controller 104 and the single memory device 103 may be integrated into a memory card 200. The memory card 200 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 200 may also include a computer that connects the memory card 200 to a host (e.g., Figure 11 A memory card connector 201 is coupled to the host 101 in the memory card connector.

[0120] Figure 3 is a schematic diagram of a solid-state drive provided by an embodiment of the present application, such as Figure 3 As shown, the memory controller 104 and the plurality of memory devices 103 may be integrated into a solid state drive (SSD) 300. The solid state drive 300 may also include a computer that connects the solid state drive 301 to a host (eg, Figure 1 In one embodiment, the solid-state drive 310 has a storage capacity and / or an operating speed greater than that of the memory card 200.

[0121] Figure 4 This is a block diagram of a memory device provided in an embodiment of the present application. The memory device 103 includes a memory array 301 and a peripheral circuit 302, wherein the memory array 301 is used to store data, and the peripheral circuit 302 is used to control the memory array 301 to implement the operation method of the memory device provided below.

[0122] To further illustrate the internal structure of the storage array 301, see Figure 5 This is a schematic diagram of the structure of a storage device provided in the embodiment of the application. Figure 5 As shown, the memory array 301 includes a plurality of memory strings 11, which are arranged in an array above a substrate (not shown) of the memory array 301, and each memory string 11 extends vertically above the substrate.

[0123] Each memory string 11 includes a plurality of memory cells 111 connected in series, and the plurality of memory cells 111 are stacked vertically above the substrate of the memory array 301. In different memory strings 11, memory cells at the same or similar heights from the substrate support surface are in the same layer.

[0124] The memory cell 111 includes a source S, a drain D, a control gate (CG), and a storage layer. The control gate of the memory cell 111 is also referred to as the gate G. The storage layer is used to store electrons. The number of electrons stored in the storage layer determines the data stored in the memory cell, thereby enabling the memory cell 11 to store data. Optionally, the memory cell 111 includes a floating gate field-effect transistor (FFET) or a charge trap field-effect transistor (CFET). A floating gate field-effect transistor is a special field-effect transistor that includes a source, a drain, a control gate, and a floating gate (FG). The floating gate is also referred to as a floating gate. The floating gate is a unit for storing electrons and serves as the storage layer of the memory cell 111. A charge trap field-effect transistor, also referred to as a charge trap device, includes a source, a drain, a control gate, and a charge trap layer. The charge trap layer is a unit for storing electrons and serves as the storage layer of the memory cell 111.

[0125] In some embodiments, each memory cell 111 is a single-level cell having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range.

[0126] In some embodiments, each memory cell 111 is a cell capable of storing more than a single bit of data in more than four memory states. For example, two bits can be stored per cell (also known as a multi-level cell), three bits can be stored per cell (also known as a triple-level cell), or four bits can be stored per cell (also known as a quad-level cell). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0127] Continue to refer Figure 5 , multiple memory cells 111 in the same layer of multiple memory strings 11 share the same word line (WL).

[0128] Each memory string 11 also includes an upper select transistor 112 and a lower select transistor 113, which are used to activate the selected memory string when erasing or programming memory cells. Each memory string 11 has at least one upper select transistor 112, also known as a top select gate (TSG). Each memory string 11 has at least one upper select transistor 112, which is vertically stacked above the memory cells 111 in the memory string 11. Each memory string 11 has at least one lower select transistor 113, also known as a bottom select gate (BSG). Each memory string 11 has at least one lower select transistor 113, which is vertically stacked below the memory cells 111 in the memory string 11 and above the substrate.

[0129] Multiple upper select transistors in the same layer of multiple memory strings 11 share the same drain select line (DSL). Multiple lower select transistors in the same layer of multiple memory strings 11 share the same source select line (SSL). In some embodiments, each memory string 11 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the TSG) or a deselect voltage (e.g., 0V) to the gate of the corresponding TSG via one or more DSLs. And / or, in some embodiments, each memory string 11 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the BSG) or a deselect voltage (e.g., 0V) to the gate of the corresponding BSG via one or more SSLs.

[0130] Each memory string 11 further includes a dummy cell 114. There is at least one dummy cell 114 in each memory string 11. Multiple dummy cells 114 in the same layer of multiple memory strings 11 share the same dummy word line (DWL).

[0131] One end of each memory string 11 is directly or indirectly connected to a bit line (BL), and the other end of each memory string 11 is indirectly connected to a source line (SL). The end of the memory string 11 that is directly or indirectly connected to the bit line can be called a drain end, and the end that is indirectly connected to the source line can be called a source end.

[0132] All memory strings 11 that share a set of word lines in the memory array 302 are referred to as a memory block 11A. The memory block 11A is the smallest physical addressing unit for erasing data. To further illustrate the structure of the memory block 11A, for example, see Figure 6 The schematic diagram of the structure of a storage block provided by an embodiment of the present application is shown in FIG. Figure 5The memory block 11A shown includes n memory strings 11, each memory string 11 includes m memory cells 111, and the m WLs arranged along the Z direction: WL_1 to WL_m are respectively connected to the memory cells 111 located in the same layer. The j DSLs arranged along the Y direction: DSL_1 to DSL_j are respectively connected to a layer of TSG, and the j SSLs arranged along the Y direction: SSL_0 to SSL_j are respectively connected to a layer of BSG. The n BLs arranged along the X direction: BL_1 to BL_n are respectively connected. Each memory string 11 shares the same source line contact connected to the source line, thereby realizing that each memory string 11 shares the same source line. The source line contact can also be called the array common source (ACS). Multiple virtual memory cells in the same layer of multiple memory strings 11 share the same pseudo word line DWL. Wherein, n and m are both integers greater than 1, Figure 6 Where i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n.

[0133] It should be appreciated that in some examples, erase operations may be performed at a half-block level, at a quarter-block level, or at a level having any suitable number or fraction of a block.

[0134] The memory string 11 also includes a channel, see Figure 7 The embodiment of the present application provides a cross-sectional side view of a storage string, as shown in FIG. Figure 7 As shown, the memory string 11 further includes a channel 115 that vertically passes through the memory string 11. The channels of the devices in the memory string 11 are connected in series to form the channel 115, and the control lines connected to the devices are formed on the periphery of the channel 115. One end of the channel 115 is connected to a bit line through a bit line contact 116, and the other end is coupled to a source contact 304 in the substrate 303. The source contact 304 is coupled to the source line contact. In some embodiments, the source contact 304 is a part of the substrate 303, such as Figure 7 In another possible implementation, the source contact portion 304 serves as a substrate of the memory device.

[0135] The devices in the memory string 11 include a memory cell 111, an upper select transistor 112, a lower select transistor 113, and a dummy memory cell 114. The control line of the memory cell 111 is the word line connected to the memory cell 111, the control line of the upper select transistor 112 is the drain select line connected to the upper select transistor 112, the control line of the lower select transistor 113 is the source select line connected to the lower select transistor 113, and the control line of the dummy memory cell 114 is the dummy word line connected to the dummy cell 114. The peripheral circuit 302 is used to provide appropriate voltages to the control lines of the devices in the memory string of the memory array 301 when reading, writing, or erasing data in the memory array 301, so as to complete the data reading, writing, or erasing.

[0136] Return Reference Figure 5 , the peripheral circuit 302 may be coupled to the memory array 301 through the bit lines, word lines, source lines, DSL, SSL lines, and DWLs. The peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell and sensing a voltage signal and / or a current signal from each target memory cell through the bit lines, word lines, source lines, DSL, SSL lines, and DWLs.

[0137] The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 8 The schematic diagram of a peripheral circuit provided by the embodiment of the present application is shown in FIG. Figure 8 The peripheral circuit 302 shown includes a page buffer / sense amplifier 804, a column decoder / bit line (BL) driver 806, a row decoder / word line (WL) driver 808, a voltage generator 810, a control logic unit 812, a register 814, an interface 816, and a data bus 818. In some examples, the peripheral circuit 302 also includes Figure 8 8. The page buffer / sense amplifier 804 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic unit 812. In one example, the page buffer / sense amplifier 804 may store a page of program data (write data) to be programmed into one page of the memory array 301. In another example, the page buffer / sense amplifier 804 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 111 coupled to the selected word line. In yet another example, the page buffer / sense amplifier 804 may also sense a low-power signal from a bit line representing a data bit stored in the memory cell 111 and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 806 may be configured to be controlled by the control logic unit 812 and to select one or more memory strings 11 by applying a bit line voltage generated from the voltage generator 810.

[0138] The row decoder / word line driver 808 may be configured to be controlled by the control logic unit 812 and select / deselect the word line 1620 of the memory block 11A of the memory array 301. The row decoder / word line driver 808 may also be configured to use the word line voltage (V WL) to drive the word lines. In some embodiments, the row decoder / word line driver 808 can also select / deselect and drive the DSL and SSL. As described in detail below, the row decoder / word line driver 808 is configured to perform an erase operation on the memory cells 111 coupled to the selected word line(s). The voltage generator 810 can be configured to be controlled by the control logic unit 812 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0139] The control logic unit 812 may be coupled to each of the peripheral circuits 302 described above and configured to control the operation of each peripheral circuit 302. The registers 814 may be coupled to the control logic unit 812 and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 302. The interface 816 may be coupled to the control logic unit 812 and function as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 812, as well as to buffer status information received from the control logic unit 812 and relay it to the host. The interface 816 may also be coupled to the column decoder / bitline driver 806 via the data bus 1618 and function as a data I / O interface and data buffer to buffer data and relay it to or from the memory array 301.

[0140] The following is a further introduction to the erasing principle of the storage cells in the storage block:

[0141] A bitline voltage is applied to the bitline of the memory string where the memory cell is located, generating holes at one end of the memory string close to the bitline. The holes are then transferred to the channel of the memory string, causing the channel voltage to increase. An erase voltage is applied to the wordline coupled to the memory cell. The erase voltage is less than the channel voltage, and the voltage difference between them is greater than the tunneling voltage of the memory cell. This voltage difference causes a tunneling effect between the channel of the memory cell and the gate of the memory cell. As a result, the holes in the channel of the memory cell tunnel to the storage layer of the memory cell, eliminating the electrons in the storage layer, thereby erasing the memory cell.

[0142] Based on the above introduction, the following Figure 9 The flowchart of a method for operating a memory device provided in an embodiment of the present application is shown, which introduces the process of erasing a memory string.

[0143] 901. Apply a first voltage to a first end of a memory string.

[0144] The memory string is any memory string in any memory block to be erased in the memory device. Optionally, the first voltage has a value range of 10V to 30V or 15V to 25V.

[0145] The two ends of the memory string are respectively coupled to the bit line contact and source contact corresponding to the memory string. For the convenience of description, the two ends of the memory string are respectively referred to as the first end and the second end. The first end is coupled to the bit line contact corresponding to the memory string, or coupled to the source contact corresponding to the memory string. The second end is the other end of the memory string other than the first end. For example, if the first end is coupled to the bit line contact, the second end is coupled to the source contact; if the first end is coupled to the source contact, the second end is coupled to the bit line contact.

[0146] A first voltage is applied to the first end of the memory string to generate holes at the first end. Initially, the voltage of the channel is less than the first voltage, so that the holes move from the first end of the memory string to the channel of the memory string, and move along the channel to the second end of the memory string. As the holes move in the channel, the holes are distributed to various positions of the channel of the memory string, so that the voltage of the entire channel gradually reaches the first voltage. In addition, a first voltage is also applied to the second end of the memory string, so that the voltages at both ends of the channel of the memory string are the same to prevent the channel of the memory string from being turned on.

[0147] 902. Apply a second voltage to a word line coupled to a first memory cell, where the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage.

[0148] The first storage cell is a storage cell in the storage string that stores invalid data. There is at least one first storage cell in the storage string, and the invalid data is data that is specified to be erased by the user. Optionally, the second voltage has a value range of 0V to 3V, and the first tunneling voltage is a tunneling voltage of the first storage cell. The first tunneling voltage is the minimum voltage that can erase the data stored in the first storage cell, and the value range of the first tunneling voltage is 15V to 30V.

[0149] As the holes move in the channel, the voltage of the channel of the first storage cell gradually reaches the first voltage. Since the voltage difference between the first voltage and the second voltage is greater than or equal to the first tunneling voltage, and the first tunneling voltage is the minimum voltage that can erase the data stored in the first storage cell, the voltage difference is sufficient to cause a tunneling effect between the channel of the first storage cell and the gate of the first storage cell, thereby erasing the data stored in the first storage cell.

[0150] 903. Configure a third voltage for the word line coupled to the second memory cell, where the third voltage is lower than the first voltage, and a voltage difference between the first voltage and the third voltage is lower than a second tunneling voltage.

[0151] The second storage cell is a storage cell in the storage string that stores valid data. There is at least one second storage cell in the storage string, and the valid data is the data stored in the storage string other than invalid data. Optionally, the third voltage has a value range of 10V to 25V, the second tunneling voltage is the tunneling voltage of the second storage cell, and the second tunneling voltage is the minimum voltage capable of erasing the data stored in the second storage cell. The value range of the second tunneling voltage is 15V to 30V.

[0152] In one possible implementation, the third voltage is configured for the word line coupled to the second storage cell by applying the third voltage to the word line coupled to the second storage cell; or by floating the word line coupled to the second storage cell. Floating the word line coupled to the second storage cell places the word line in a floating state. When the word line is in the floating state, if the channel voltage increases, the voltage jump across the capacitor causes the voltage of the word line to increase, such as to the third voltage. For example, the word line can be floated by disconnecting the word line from a power source.

[0153] As holes move in the channel, the voltage of the channel of the second memory cell gradually reaches the first voltage. Since the voltage difference between the first voltage and the third voltage is less than the second tunneling voltage, and the second tunneling voltage is the minimum voltage capable of erasing the data stored in the second memory cell, the voltage difference is insufficient to cause a tunneling effect between the channel of the second memory cell and the gate of the second memory cell, thereby protecting the data stored in the second memory cell from being erased.

[0154] It should be noted that there is no specific order in which steps 901-903 are executed. For example, steps 901-903 may be executed simultaneously, or step 901 may be executed first, followed by steps 902 and 903 simultaneously. Alternatively, step 903 may be executed first, then step 902, and then step 901. The present embodiment of the present application does not limit the order in which steps 901-903 are executed.

[0155] The method provided by the embodiment of the present application, in the process of erasing a storage block, applies a first voltage to the first end of the storage string, and applies a second voltage less than the first voltage to the word line coupled to the first storage cell of the storage string. Since the voltage difference between the first voltage and the second voltage is greater than or equal to the tunneling voltage of the first storage cell, the invalid data stored therein can be erased. In addition, a third voltage less than the first voltage is configured for the word line coupled to the second storage cell of the storage string. Since the voltage difference between the first voltage and the third voltage is less than the tunneling voltage of the second storage cell, the valid data stored therein can be protected from being erased, and there is no need to migrate the valid data, which saves the time for migrating the valid data back and forth and improves the erasing efficiency of the storage block.

[0156] In one possible embodiment, the first storage unit of the storage string is close to the first end, and the second storage unit is far from the first end. In another possible embodiment, the first storage unit of the storage string is far from the first end, and the second storage unit is close to the first end.

[0157] Based on the different distributions of the first memory cells in the memory string, holes are controlled to move from different directions in the memory string toward the channel of the memory string. For example, by applying a first voltage to a first end close to the first memory cell, holes are controlled to move from the first end close to the first memory cell toward the channel of the memory string. For another example, by applying a first voltage to a first end far from the first memory cell, holes are controlled to move from the first end far from the first memory cell toward the channel of the memory string.

[0158] The following describes the process of controlling the movement of holes toward the channel of the memory string from the end closest to the first memory cell in the memory string:

[0159] Since the first end of the storage string may be coupled to the bit line contact corresponding to the storage string, or may be coupled to the source contact corresponding to the storage string, accordingly, there are two cases for the storage string, namely, Case 1 and Case 2 below.

[0160] Case 1: The first memory cell in the memory string is close to the first end, the second memory cell is far from the first end, and the first end is coupled to the bit line contact corresponding to the memory string.

[0161] by Figure 10 Taking the distribution diagram of the memory cells in a memory string provided by the embodiment of the present application as an example, when the first end is coupled to the bit line contact corresponding to the memory string, the memory string that satisfies Case 1 is, for example, Figure 7Memory string 1001 is shown. The first memory cell in memory string 1001 is located in an adjacent layer and is close to the bit line contact coupled to memory string 1001, serving as the upper memory cell of memory string 1001. The second memory cell in memory string 1001 is located in an adjacent layer and is close to the source contact coupled to memory string 1001, serving as the lower memory cell of memory string 1001.

[0162] Case 2: The first memory cell in the memory string is close to the first end, the second memory cell is far away from the first end, and the first end is coupled to the source contact portion corresponding to the memory string.

[0163] When the first end is coupled to the source contact portion corresponding to the memory string, illustratively, structure 2 is Figure 10 In the illustrated memory string 1002, the first memory cell in the memory string 1002 is located in an adjacent layer and is close to the source contact coupled to the memory string 1002, serving as the lower memory cell of the memory string 1002. The second memory cell in the memory string 1002 is located in an adjacent layer and is close to the bit line contact coupled to the memory string 1002, serving as the upper memory cell of the memory string 1002.

[0164] The process of controlling the movement of holes along the channel from the first end to the second end of the memory string varies depending on the situation of the memory string. Here, taking situation 1 as an example, the process of controlling the movement of holes along the channel from the first end to the second end of the memory string is described as follows:

[0165] For case 1, when the first storage cell is close to the first end, and the first end is close to the bit line contact corresponding to the storage string, if the bit line contact is an N-type doped conductive structure, and the impurity doping concentration is greater than or equal to the first concentration, by applying a first voltage to the bit line contact, the holes are controlled to move from the first end of the storage string to the channel of the storage string.

[0166] A doped conductive structure is an impurity semiconductor obtained by doping an intrinsic semiconductor with a certain impurity. For example, an impurity semiconductor obtained by doping with a pentavalent impurity element is an N-type impurity semiconductor, i.e., an N-type doped conductive structure. Meanwhile, an impurity semiconductor obtained by doping with a trivalent impurity element is a P-type impurity semiconductor, i.e., a P-type doped conductive structure.

[0167] Based on the different doping concentrations of impurities, doped conductive structures are classified into heavily doped conductive structures, medium doped conductive structures, and lightly doped conductive structures. A heavily doped conductive structure is a hybrid conductive structure having an impurity doping concentration greater than or equal to a first concentration. For example, an N-type doped conductive structure having a doping concentration greater than or equal to the first concentration is an N-type heavily doped conductive structure, and a P-type doped conductive structure having a doping concentration greater than or equal to the first concentration is a P-type heavily doped conductive structure. A medium doped conductive structure is a hybrid conductive structure having an impurity doping concentration less than the first concentration and greater than a second concentration. For example, an N-type doped conductive structure having a doping concentration less than the first concentration and greater than the second concentration is an N-type medium doped conductive structure, and a P-type doped conductive structure having a doping concentration less than the first concentration and greater than the second concentration is a P-type medium doped conductive structure. A lightly doped conductive structure is a hybrid conductive structure having an impurity doping concentration less than or equal to the second concentration. For example, an N-type doped conductive structure having a doping concentration less than or equal to the second concentration is an N-type lightly doped conductive structure, and a P-type doped conductive structure having a doping concentration less than or equal to the second concentration is a P-type lightly doped conductive structure. In addition, for the convenience of description, the medium-doped conductive structure and the lightly-doped conductive structure are both referred to as ordinary doped conductive structures. For example, the N-type medium-doped conductive structure and the N-type lightly-doped conductive structure are both referred to as N-type ordinary doped conductive structures, and the P-type medium-doped conductive structure and the P-type lightly-doped conductive structure are both referred to as P-type ordinary doped conductive structures.

[0168] The second concentration is less than the first concentration. In one possible embodiment, the first concentration is 5*10^8. The second concentration can be set according to the application scenario. Here, the embodiment of the present application does not limit the second concentration.

[0169] If the first storage cell is close to the first end, the first end is coupled to the bit line contact, and the bit line contact is an N-type heavily doped conductive structure, the source contact portion coupled to the storage string may be made of different materials, for example, the source contact portion is an N-type heavily doped conductive structure or a P-type doped conductive structure (such as a P-type heavily doped conductive structure).

[0170] Based on source contacts made of different materials, Case 1 can be further expanded into the following Case 1.1 and Case 1.2.

[0171] Case 1.1: The bit line contact coupled to the first end is an N-type heavily doped conductive structure, the source contact coupled to the storage string is an N-type heavily doped conductive structure, the first storage cell is close to the first end, and the second storage cell is away from the first end and close to the source contact.

[0172] Case 1.2: The bit line contact coupled to the first end is an N-type heavily doped conductive structure, the source contact coupled to the storage string is a P-type heavily doped conductive structure, the first storage cell is close to the first end, and the second storage cell is away from the first end and close to the source contact.

[0173] In one possible implementation, the memory string further includes at least one first selection transistor, which is located near the first end. For example, if the first end is coupled to the bit line contact, the first selection transistor is also an upper selection transistor. If the first end is coupled to the source contact, the first selection transistor is also a lower selection transistor.

[0174] For each of Cases 1.1 and 1.2, a first voltage is applied to the bit line contact to control the first select transistor of the memory string to generate gate-induced drain leakage (GIDL). GIDL generates electron-hole pairs between the gate and drain of the first select transistor. The hole in the electron-hole pair moves toward and enters the channel of the memory string. The hole refers to the effect of losing an electron from a covalent bond and leaving a vacancy in the covalent bond.

[0175] For example, a first voltage is applied to the bit line connected to the bit line contact, and a first voltage is applied to the source line, so that the voltages at both ends of the channel of the memory string are the same, thereby preventing the channel of the memory string from being turned on. A fourth voltage is applied to the select line coupled to the first select transistor, where the fourth voltage is less than the first voltage, and the voltage difference between the first voltage and the fourth voltage meets the voltage difference condition for band-to-band tunneling (B2B). Then, the voltage difference formed between the gate and drain of the first select transistor causes B2B to occur between the gate and drain of the first select transistor, generating electron-hole pairs, and the holes in the electron-hole pairs move toward the channel of the memory string and enter the channel of the memory string.

[0176] In one possible embodiment, before the channel voltage of the memory string increases to a tenth voltage, an eleventh voltage is configured for the select line coupled to the first select transistor, wherein the channel voltage of the memory string is the voltage of the channel of the memory string, the tenth voltage is less than the first voltage and greater than the fourth voltage, and the voltage difference between the tenth voltage and the fourth voltage is less than or equal to a fourth tunneling voltage, which is the minimum voltage capable of causing a tunneling effect in the first select transistor, i.e., the tunneling voltage of the first select transistor. The eleventh voltage is less than the first voltage, and the voltage difference between the first voltage and the eleventh voltage is less than the fourth tunneling voltage. Therefore, after the channel voltage increases to the first voltage, the voltage difference between the gate and the channel of the first select transistor is less than the fourth tunneling voltage, thereby preventing the threshold voltage of the first select transistor from drifting.

[0177] In one possible embodiment, the memory string further includes at least one second selector tube, which is located away from the first end. For example, if the first end is coupled to the bit line contact, the second selector tube is also a lower selector tube. If the first end is coupled to the source contact, the second selector tube is also an upper selector tube.

[0178] In addition, a sixth voltage is configured for the select line coupled to the second select transistor in the memory string. The sixth voltage is less than the first voltage, and the voltage difference between the first voltage and the sixth voltage is less than a third tunneling voltage. The third tunneling voltage is the minimum voltage that can cause a tunneling effect in the second select transistor, i.e., the tunneling voltage of the second select transistor. As holes move in the channel, the voltage of the channel of the second select transistor gradually reaches the first voltage, thereby generating a voltage difference between the channel of the second select transistor and the gate of the second select transistor, i.e., the difference between the first voltage and the sixth voltage. Since this voltage difference is less than the third tunneling voltage, it is insufficient to cause a tunneling effect between the channel of the second select transistor and the gate of the second select transistor, thereby preventing the threshold voltage of the second select transistor from shifting.

[0179] It should be noted that if the first select tube is an upper select tube, the select line coupled to the first select tube is DSL; if the first select tube is a lower select tube, the select line coupled to the first select tube is SSL. If the second select tube is an upper select tube, the select line coupled to the second select tube is DSL; if the second select tube is a lower select tube, the select line coupled to the second select tube is SSL. Optionally, the sixth voltage and the eleventh voltage both have a value range of 10V to 25V, and the third tunneling voltage and the fourth tunneling voltage have a value range of 15V to 30V. The process of configuring the sixth voltage for the select line coupled to the second select tube in the memory string is similar to the process of configuring the third voltage for the word line coupled to the second memory cell. For example, the sixth voltage is applied to the select line coupled to the second select tube, or the select line coupled to the second select tube is floated, so that the voltage of the word line coupled to the second memory cell reaches the sixth voltage. The process of configuring the eleventh voltage for the select line coupled to the first select transistor in the memory string is similar to the process of configuring the third voltage for the word line coupled to the second memory cell. For example, the eleventh voltage is applied to the select line coupled to the first select transistor, or the select line coupled to the first select transistor is floated, so that the voltage of the word line coupled to the first memory cell reaches the eleventh voltage.

[0180] To further illustrate the voltage application of each device in the memory string during data erasure in case 1.1, see Figure 11 The voltage waveform diagram of the data erasing process under the situation 1.1 provided in the embodiment of the present application is shown. Figure 11As shown, the first memory cell, as the upper memory cell of the memory string, is close to the first end of the memory string, and the bit line contact coupled to the first end is an N-type heavily doped conductive structure. The second memory cell, as the lower memory cell of the memory string, is away from the first end and close to the source contact coupled to the memory string. The source line contact is connected to the source contact and the source line, respectively, wherein the source contact and the source line contact are both N-type heavily doped conductive structures (represented by "N+" in the figure).

[0181] During data erasing of the memory string, during the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and maintain the first voltage during the time period t3-t4.

[0182] In the time period t1-t2, TSG serves as the first selection tube of the storage string, and the selection line coupled to it maintains the fourth voltage. The voltage difference generated by the voltage of BL and the voltage of the selection line causes holes to be generated at the position corresponding to TSG. At this time, the voltage of the channel is lower than the first voltage, and the holes move toward the channel at a low voltage, causing the voltage of the channel to gradually increase. In the time period t2-t3, the selection line coupled to TSG is floated, and the selection line is in a floating state. When the voltage of the channel increases, the voltage jump principle at both ends of the capacitor causes the voltage of the selection line to increase. For example, the selection line coupled to TSG gradually increases from the fourth voltage until it increases to the eleventh voltage. This makes the voltage difference between the gate and the channel of the TSG less than the tunneling voltage of the TSG to avoid drifting of the threshold voltage of the TSG.

[0183] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the voltage of the channel increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0184] During the time period t1-t3, the word line coupled to the second memory cell is floated. When the voltage of the channel increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial voltage until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thereby preventing the data stored in the second memory cell from being erased.

[0185] During the time period t2-t3, similar to the floating select line coupled to the TSG, the BSG, serving as the second select transistor of the memory string, has its coupled select line floated, causing the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage becomes smaller than the tunneling voltage of the BSG, thereby preventing the threshold voltage of the BSG from drifting.

[0186] To further illustrate the voltage application of each device in the memory string during data erasure in case 1.2, see Figure 12 The voltage waveform diagram of the data erasing process in case 1.2 provided in the embodiment of the present application is shown. Figure 12 As shown, the first memory cell, as the upper memory cell of the memory string, is close to the first end of the memory string, and the bit line contact coupled to the first end is an N-type heavily doped conductive structure. The second memory cell, as the lower memory cell of the memory string, is away from the first end and close to the source contact coupled to the memory string. The source line contact is connected to the source contact and the source line respectively, wherein the source contact is a P-type heavily doped conductive structure (represented by "P+" in the figure), and the source line contact is an N-type heavily doped conductive structure.

[0187] During data erasing of the memory string, during the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and maintain the first voltage during the time period t3-t4.

[0188] In the time period t1-t2, TSG serves as the first selection tube of the storage string, and the selection line coupled to it maintains the fourth voltage. The voltage difference generated by the voltage of BL and the voltage of the selection line causes holes to be generated at the position corresponding to TSG. At this time, the voltage of the channel is lower than the first voltage, and the holes move toward the channel at a low voltage, causing the voltage of the channel to gradually increase. In the time period t2-t3, the selection line coupled to TSG is floated, and the selection line is in a floating state. When the voltage of the channel increases, the voltage jump principle at both ends of the capacitor causes the voltage of the selection line to increase. For example, the selection line coupled to TSG gradually increases from the fourth voltage until it increases to the eleventh voltage. This makes the voltage difference between the gate and the channel of the TSG less than the tunneling voltage of the TSG to avoid drifting of the threshold voltage of the TSG.

[0189] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the voltage of the channel increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0190] During the time period t1-t3, the word line coupled to the second memory cell is floated. When the voltage of the channel increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial voltage until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thereby preventing the data stored in the second memory cell from being erased.

[0191] During the time period t2-t3, similar to the floating select line coupled to the TSG, the BSG, serving as the second select transistor of the memory string, has its coupled select line floated, causing the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage becomes smaller than the tunneling voltage of the BSG, thereby preventing the threshold voltage of the BSG from drifting.

[0192] The process of controlling the movement of holes from the first end to the second end of the memory string varies depending on the situation of the memory string. Here, taking situation 2 as an example, the process of controlling the movement of holes from the first end to the second end of the memory string is described as follows:

[0193] For case 2, the first memory cell in the memory string is close to the first end, the second memory cell is far away from the first end, and the first end is coupled to the source contact portion corresponding to the memory string, controlling the movement of holes from the first end of the memory string to the second end of the memory string.

[0194] In different implementations, the source contact portion has different materials. For example, the source contact portion may be an N-type heavily doped conductive structure or a P-type heavily doped conductive structure. Based on the different source contact materials, Case 2 can be further expanded into the following Cases 2.1 and 2.2.

[0195] Case 2.1: The first memory cell in the memory string is close to the first end, the second memory cell is far from the first end, the first end is coupled to the source contact portion corresponding to the memory string, and the source contact portion is an N-type heavily doped conductive structure.

[0196] Case 2.2: The first memory cell in the memory string is close to the first end, the second memory cell is far from the first end, the first end is coupled to the source contact portion corresponding to the memory string, and the source contact portion is a P-type heavily doped conductive structure.

[0197] For the source contacts of different materials in Case 2.1 and Case 2.2, the methods for controlling the movement of holes from the first end to the second end of the memory string are different. The following describes the process of controlling the movement of holes from the first end coupled to the source contact to the second end of the memory string for Case 2.1 and Case 2.2, respectively:

[0198] For Case 2.1, the bitline contacts coupled to the memory string may also be made of different materials. For example, the bitline contacts may be N-type heavily doped conductive structures or N-type normally doped conductive structures. Based on the different bitline contact materials, Case 2.1 can be further expanded into the following Cases 2.1.1 and 2.1.2.

[0199] Case 2.1.1: The bit line contact coupled to the storage string is an N-type heavily doped conductive structure, the source contact coupled to the first end is an N-type heavily doped conductive structure, the first storage cell is close to the first end, and the second storage cell is away from the first end and close to the bit line contact.

[0200] Case 2.1.2: The bit line contact coupled to the storage string is an N-type normally doped conductive structure, the source contact coupled to the first end is an N-type heavily doped conductive structure, the first storage cell is close to the first end, and the second storage cell is far from the first end and close to the bit line contact.

[0201] For each of Cases 2.1.1 and 2.1.2, in one possible implementation, a first voltage is applied to the source contact to control the first selection tube of the storage string to generate electron-hole pairs, and the holes in the electron-hole pairs move toward the channel of the storage string and enter the channel of the storage string.

[0202] For example, a first voltage is applied to the bit line connected to the bit line contact, and a first voltage is applied to the source line, so that the voltages at both ends of the channel of the memory string are the same, thereby preventing the channel of the memory string from being turned on. A second voltage is applied to the word line coupled to the first selection transistor, so that a voltage difference between the first voltage and the second voltage is formed between the source and gate of the first selection transistor. This voltage difference causes band-to-band tunneling between the gate and source of the first selection transistor, generating GIDL. Holes in the GIDL move toward the channel of the memory string and enter the channel of the memory string.

[0203] Furthermore, before the channel voltage of the memory string increases to the tenth voltage, the select line coupled to the first select transistor is configured with the eleventh voltage to prevent the threshold voltage of the first select transistor from drifting as the channel voltage increases. The select line coupled to the second select transistor in the memory string is configured with the sixth voltage to prevent the threshold voltage of the second select transistor from drifting as the channel voltage increases.

[0204] To further illustrate the voltage application of each device in the memory string during data erasure in case 2.1.1, see Figure 13 The voltage waveform diagram of the data erasing process under the situation 2.1.1 provided in the embodiment of the present application is shown. Figure 13As shown, the second memory cell, as the upper memory cell of the memory string, is away from the first end of the memory string and close to the bit line contact coupled to the memory string, which is an N-type heavily doped conductive structure. The first memory cell, as the lower memory cell of the memory string, is close to the first end and coupled to the source contact. The source line contact is respectively connected to the source contact and the source line, wherein the source contact and the source line contact are both N-type heavily doped conductive structures.

[0205] During data erasing of the memory string, during the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and maintain the first voltage during the time period t3-t4.

[0206] In the t1-t2 time period, BSG serves as the first selection tube of the storage string, and the selection line coupled to it maintains the fourth voltage. The voltage difference generated by the voltage of the source line and the voltage of the selection line causes holes to be generated at the position corresponding to the BSG. At this time, the voltage of the channel is lower than the first voltage, and the holes move toward the channel at a low voltage, causing the voltage of the channel to gradually increase. In the t2-t3 time period, the selection line coupled to the BSG is floated, and the selection line is in a floating state. When the voltage of the channel increases, the voltage jump principle across the capacitor causes the selected voltage to increase. For example, the selection line coupled to the BSG gradually increases from the fourth voltage until it increases to the eleventh voltage. This makes the voltage difference between the gate and the channel of the BSG less than the tunneling voltage of the BSG to avoid drifting of the threshold voltage of the BSG.

[0207] During the time period t2-t4, the word line coupled to the first storage cell always maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first storage cell, the data stored in the first storage cell can be erased.

[0208] During the time period t1-t3, the word line coupled to the second memory cell is floated. When the voltage of the channel increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial voltage until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thereby preventing the data stored in the second memory cell from being erased.

[0209] During the time period t2-t3, similar to the floating select line coupled to the BSG, the TSG, serving as the second select transistor of the memory string, has its coupled select line floated, causing the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage becomes smaller than the tunneling voltage of the TSG, thereby preventing the threshold voltage of the TSG from drifting.

[0210] To further illustrate the voltage application of each device in the memory string during data erasure in case 2.1.2, see Figure 14 The voltage waveform diagram of the data erasing process under the situation 2.1.2 provided in the embodiment of the present application is shown. Figure 14 As shown, the second memory cell is an upper memory cell of the memory string, close to the bit line contact of the memory string, and the bit line contact is an N-type normal doped conductive structure (indicated by "N" in the figure). The first memory cell is a lower memory cell of the memory string, close to the first end of the memory string, and the source contact coupled to the first end is an N-type heavily doped conductive structure. The source line contact is respectively connected to the source contact and the source line, wherein the source line contact is an N-type heavily doped conductive structure.

[0211] During data erasing of the memory string, during the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and maintain the first voltage during the time period t3-t4.

[0212] In the t1-t2 time period, BSG serves as the first selection tube of the storage string, and the selection line coupled to it maintains the fourth voltage. The voltage difference generated by the voltage of the source line and the voltage of the selection line causes holes to be generated at the position corresponding to the BSG. At this time, the voltage of the channel is lower than the first voltage, and the holes move toward the channel at a low voltage, causing the voltage of the channel to gradually increase. In the t2-t3 time period, the selection line coupled to the BSG is floated, and the selection line is in a floating state. When the voltage of the channel increases, the voltage jump principle across the capacitor causes the selected voltage to increase. For example, the selection line coupled to the BSG gradually increases from the fourth voltage until it increases to the eleventh voltage. This makes the voltage difference between the gate and the channel of the BSG less than the tunneling voltage of the BSG to avoid drifting of the threshold voltage of the BSG.

[0213] During the time period t2-t4, the word line coupled to the first storage cell always maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first storage cell, the data stored in the first storage cell can be erased.

[0214] During the time period t1-t3, the word line coupled to the second memory cell is floated. When the voltage of the channel increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial voltage until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thereby preventing the data stored in the second memory cell from being erased.

[0215] During the time period t2-t3, similar to the floating select line coupled to the BSG, the TSG, serving as the second select transistor of the memory string, has its coupled select line floated, causing the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage and remains at the sixth voltage during the time period t3-t4. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage becomes less than the tunneling voltage of the TSG, thereby preventing the threshold voltage of the TSG from drifting.

[0216] The above is an introduction to the process of controlling the memory string to generate holes at the position corresponding to the first selection transistor, so that the holes move toward the channel of the memory string, in combination with Case 2.1. Here, in combination with Case 2.2, the process of controlling the holes to move from the first end to the second end of the memory string is described as follows:

[0217] Regarding scenario 2.2, in one possible implementation, when the first end is coupled to the source contact corresponding to the memory string, and the source contact is a heavily P-type conductive structure, the bit line contact coupled to the memory string may also be made of different materials, for example, an N-type normally doped conductive structure or an N-heavily doped conductive structure. Based on the different bit line contact materials, scenario 2.2 can be further expanded into the following scenarios 2.2.1 and 2.2.2.

[0218] Case 2.2.1: The source contact coupled to the first end is a P-type heavily doped conductive structure, the bit line contact coupled to the storage string is an N-type normally doped conductive structure, the first storage cell is close to the first end, and the second storage cell is far from the first end and close to the bit line contact.

[0219] Case 2.2.2: The substrate coupled to the first end is a P-type heavily doped conductive structure, the bit line contact coupled to the storage string is an N-type heavily doped conductive structure, the first storage unit is close to the first end, and the second storage unit is far from the first end and close to the bit line contact.

[0220] For each of Case 2.2.1 and Case 2.2.2, in one possible implementation, the source contact is controlled to generate holes, and the holes generated by the source contact move toward the channel of the memory string and enter the channel of the memory string.

[0221] For example, a first voltage is applied to the bit line connected to the bit line contact, and a first voltage is applied to the source line, so that the voltages at both ends of the channel of the memory string are the same, thereby preventing the channel of the memory string from being turned on. The first voltage of the source line acts on the source contact through the source line contact, continuously outputting a positive potential to the substrate. Because the source contact is a heavily P-type doped conductive structure, the continuous input of a positive potential causes holes to be generated in the source contact. The holes generated by the source contact move toward the channel of the memory string and enter the channel of the memory string.

[0222] In addition, a fifth voltage is applied to the selection line coupled to the first selection tube of the storage string, wherein the fifth voltage is lower than the first voltage, so that the holes generated by the source contact portion move toward the channel direction of the first selection tube and can move toward the channel direction of the second selection tube through the channel of the first selection tube.

[0223] Before the channel voltage of the memory string increases to the tenth voltage, the select line coupled to the first select transistor is configured with the eleventh voltage to prevent the threshold voltage of the first select transistor from drifting as the channel voltage increases. The select line coupled to the second select transistor in the memory string is configured with the sixth voltage to prevent the threshold voltage of the second select transistor from drifting as the channel voltage increases.

[0224] To further illustrate the voltage application of each device in the memory string during data erasure in case 2.2.1, see Figure 15 The voltage waveform diagram of the data erasing process under the situation 2.2.1 provided in the embodiment of the present application is shown. Figure 15 As shown, the second memory cell, as the upper memory cell of the memory string, is located away from the first end and close to the bit line contact coupled to the memory string. The bit line contact is an N-type normal doped conductive structure. The first memory cell, as the lower memory cell of the memory string, is located close to the first end and the source contact coupled to the first end is a P-type heavily doped conductive structure. The source line contacts are respectively connected to the source contact and the source line. Among them, the source line contact is an N-type heavily doped conductive structure.

[0225] During data erasure of the memory string, the voltages of BL and SL gradually increase from their respective initial voltages to a first voltage during the period t1-t3, and remain at the first voltage during the period t3-t4. The voltage of SL is applied to the source contact via the source line contact. As the voltage of the source contact increases, holes are generated in the source contact.

[0226] In the t1-t2 time period, BSG serves as the first selection tube of the storage string, and the selection line coupled to it maintains the fifth voltage. The fifth voltage is a low voltage. As the voltage of the source contact increases, the voltage difference between the source contact and the fifth voltage causes the holes generated by the source contact to move toward the channel of the BSG, and then enter the channel of the storage string. At this time, the voltage of the channel is lower than the first voltage, and the holes move toward the channel at a low voltage, causing the voltage of the channel to gradually increase. In the t2-t3 time period, the selection line coupled to the BSG is floated, and the selection line is in a floating state. When the voltage of the channel increases, the voltage jump principle across the capacitor causes the selected voltage to increase. For example, the selection line coupled to the BSG gradually increases from the fourth voltage until it increases to the eleventh voltage. This makes the voltage difference between the gate and the channel of the BSG less than the tunneling voltage of the BSG to avoid drifting the threshold voltage of the BSG.

[0227] During the time period t2-t4, the word line coupled to the first storage cell always maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first storage cell, the data stored in the first storage cell can be erased.

[0228] During the time period t1-t3, the word line coupled to the second memory cell is floated. When the voltage of the channel increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial voltage until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thereby preventing the data stored in the second memory cell from being erased.

[0229] During the time period t2-t3, similar to the floating select line coupled to the BSG, the TSG, serving as the second select transistor of the memory string, has its coupled select line floated, causing the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage becomes smaller than the tunneling voltage of the TSG, thereby preventing the threshold voltage of the TSG from drifting.

[0230] To further illustrate the voltage application of each device in the memory string during data erasure in case 2.2.2, see Figure 16 The voltage waveform diagram of the data erasing process under the situation 2.2.2 provided in the embodiment of the present application is shown. Figure 16As shown, the second memory cell, as the upper memory cell of the memory string, is located away from the first end and close to the bit line contact coupled to the memory string. The bit line contact is an N-type heavily doped conductive structure. The first memory cell, as the lower memory cell of the second memory string, is located close to the first end and the source contact coupled to the first end is a P-type heavily doped conductive structure. The source line contacts are connected to the source contact and the source line, respectively, wherein the source line contacts are N-type heavily doped conductive structures.

[0231] During data erasure of the memory string, the voltages of BL and SL gradually increase from their respective initial voltages to a first voltage during the period t1-t3, and remain at the first voltage during the period t3-t4. The voltage of SL is applied to the source contact via the source line contact. As the voltage of the source contact increases, holes are generated in the source contact.

[0232] In the t1-t2 time period, BSG serves as the first selection tube of the storage string, and the selection line coupled to it maintains the fifth voltage. The fifth voltage is a low voltage. As the voltage of the source contact increases, the voltage difference between the source contact and the fifth voltage causes the holes generated by the source contact to move toward the channel of the BSG, and then enter the channel of the storage string. At this time, the voltage of the channel is lower than the first voltage, and the holes move toward the channel at a low voltage, causing the voltage of the channel to gradually increase. In the t2-t3 time period, the selection line coupled to the BSG is floated, and the selection line is in a floating state. When the voltage of the channel increases, the voltage jump principle across the capacitor causes the selected voltage to increase. For example, the selection line coupled to the BSG gradually increases from the fourth voltage until it increases to the eleventh voltage. This makes the voltage difference between the gate and the channel of the BSG less than the tunneling voltage of the BSG to avoid drifting the threshold voltage of the BSG.

[0233] During the time period t2-t4, the word line coupled to the first storage cell always maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first storage cell, the data stored in the first storage cell can be erased.

[0234] During the time period t1-t3, the word line coupled to the second memory cell is floated. When the voltage of the channel increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial voltage until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thereby preventing the data stored in the second memory cell from being erased.

[0235] During the time period t2-t3, similar to the floating select line coupled to the BSG, the TSG, serving as the second select transistor of the memory string, has its coupled select line floated, causing the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage becomes smaller than the tunneling voltage of the TSG, thereby preventing the threshold voltage of the TSG from drifting.

[0236] The above is an introduction to the process of controlling the movement of holes into the channel of the memory string from the end close to the first memory cell in the memory string. In another possible implementation, the movement of holes into the channel of the memory string is controlled from the end far away from the first memory cell in the memory string. Figure 17 The flowchart of another method for operating a memory device provided by an embodiment of the present application is shown. The method is executed by a peripheral circuit in the memory device.

[0237] 1701. Apply a first voltage to a first end of a memory string.

[0238] By applying a first voltage to the first end of the storage string, holes are generated at the first end, for example, holes are generated by the source contact portion or at the corresponding position of the first selection transistor. This process has been described above and will not be repeated here.

[0239] In addition, a first voltage is applied to the second end of the memory string, so that voltages at both ends of the channel of the memory string are the same, so as to prevent the channel of the memory string from being turned on.

[0240] 1702. If the first memory cell is far away from the first end of the memory string and the second memory cell is close to the first end, before the channel voltage of the memory string reaches the seventh voltage, an eighth voltage is applied to the word line coupled to the second memory cell, the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and the voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage.

[0241] Among them, the seventh voltage is a voltage before the channel voltage of the storage string reaches the first voltage during the process of the hole moving toward the channel of the storage string, so the seventh voltage is less than the first voltage. In addition, the seventh voltage is greater than the eighth voltage, so that a voltage difference is formed between the channel of the second storage cell and the gate of the second storage cell, and the voltage difference is less than the tunneling voltage of the second storage cell to protect the data stored in the second storage cell from being erased. In addition, the eighth voltage is less than the first voltage at the first end, so that the holes move from the first end toward the channel of the second storage cell and enter the channel of the first storage cell. The value range of the eighth voltage is 0V to 5V, optionally, the value range of the eighth voltage is 0V to 3V. For example, the third gate voltage is 0V, 1V or 2V. Optionally, the third gate voltage is equal to the first gate voltage.

[0242] An eighth voltage is applied to the word line coupled to the second storage cell, and the eighth voltage is less than the voltage of the first end, so that the holes from the first end move toward the channel of the second storage cell at a low potential after entering the channel of the storage string, and enter the channel of the first storage cell through the channel of the second storage cell.

[0243] When holes enter the channel of the memory string and move within the channel, the voltage at each location in the channel gradually increases, eventually reaching the first voltage. Before the channel voltage reaches the seventh voltage, the eighth voltage is continuously applied to the word line coupled to the second memory cell. The seventh voltage is greater than the eighth voltage, so that the voltage difference between the channel and the gate of the second memory cell is less than the tunneling voltage of the second memory cell, thereby protecting the data stored in the second memory cell from being erased.

[0244] 1703. After the channel voltage of the storage string reaches the seventh voltage, a third voltage is configured for the word line coupled to the second storage cell, the third voltage is less than the first voltage, and the voltage difference between the first voltage and the third voltage is less than the second tunneling voltage.

[0245] As the channel voltage increases, when the channel voltage reaches a seventh voltage, a third voltage is configured for the word line coupled to the second memory cell, so that the voltage difference formed between the channel and the gate of the second memory cell is smaller than the tunneling unit of the second memory cell, so as to prevent the data stored in the second memory cell from being erased.

[0246] The process of configuring the second voltage for the word line coupled to the second memory cell can be referred to in the above step 903 and will not be described in detail here.

[0247] 1704. Apply a second voltage to the word line coupled to the first memory cell, where the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage.

[0248] This step 1704 is similar to the above-mentioned step 902. Here, this embodiment of the application will not repeat this step 1704.

[0249] Furthermore, before the channel voltage of the memory string increases to the tenth voltage, the select line coupled to the first select transistor is configured with the eleventh voltage to prevent the threshold voltage of the first select transistor from drifting as the channel voltage increases. The select line coupled to the second select transistor in the memory string is configured with the sixth voltage to prevent the threshold voltage of the second select transistor from drifting as the channel voltage increases.

[0250] It should be noted that there is no specific order in which steps 1701, 1702, and 1704 may be executed. For example, steps 1701, 1702, and 1704 may be executed simultaneously, or step 901 may be executed first, followed by steps 1702 and 1704. Alternatively, step 1704 may be executed first, followed by step 1702, and then step 1701. The present embodiment of the present application does not limit the order in which steps 1701, 1702, and 1704 may be executed.

[0251] To facilitate understanding of the process of steps 1701-1304, the following description is given using Case 3: the first memory cell is far from the first end of the memory string, the second memory cell is close to the first end, the source contact coupled to the first end is a P-type heavily doped conductive structure, and the bit line contact coupled to the memory string is an N-type normally doped conductive structure.

[0252] For case 3, the bit line contact coupled to the storage string is an N-type ordinary doped conductive structure, and the upper selection tube cannot be used. If GIDL is used for data erasing, the source contact can be controlled to generate holes. After the holes generated in the source contact enter the channel of the storage string, they first move to the channel of the second storage unit, and then move from the channel of the second storage unit to the channel of the first storage unit.

[0253] To further illustrate the voltage application of each device in the memory string during data erasure in case 3, see Figure 18 The voltage waveform diagram of the data erasing process under a case 3 provided by the embodiment of the present application is shown. Figure 18As shown, the first memory cell, as the upper memory cell of the memory string, is located away from the first end of the memory string and close to the bit line contact coupled to the memory string. The bit line contact is an N-type normal doped conductive structure. The second memory cell, as the lower memory cell of the memory string, is located close to the first end and the source contact coupled to the first end is a P-type heavily doped conductive structure. The source line contacts are respectively connected to the source contact and the source line, wherein the source line contacts are N-type heavily doped conductive structures.

[0254] During data erasure of the memory string, the voltages of BL and SL gradually increase from their respective initial voltages to a first voltage during the period t1-t3, and remain at the first voltage during the period t3-t4. The voltage of SL is applied to the source contact via the source line contact. As the voltage of the source contact increases, holes are generated in the source contact.

[0255] In the t1-t2 time period, BSG serves as the first selection tube of the storage string, and the selection line coupled to it maintains the fifth voltage. The fifth voltage is a low voltage. As the voltage of the source contact increases, the voltage difference between the source contact and the fifth voltage causes the holes generated by the source contact to move toward the channel of the BSG, and then enter the channel of the storage string. At this time, the voltage of the channel is lower than the first voltage, and the holes move toward the channel at a low voltage, causing the voltage of the channel to gradually increase. In the t2-t3 time period, the selection line coupled to the BSG is floated, and the selection line is in a floating state. When the voltage of the channel increases, the voltage jump principle across the capacitor causes the selected voltage to increase. For example, the selection line coupled to the BSG gradually increases from the fourth voltage until it increases to the eleventh voltage. This makes the voltage difference between the gate and the channel of the BSG less than the tunneling voltage of the BSG to avoid drifting the threshold voltage of the BSG.

[0256] During the time period t1-t2, the word line coupled to the second storage cell maintains an eighth voltage, which is lower than the first voltage. This allows holes generated by the source contact to move through the BSG channel toward the channel of the second storage cell, and then continue to move toward the channel of the first storage cell through the channel of the second storage cell. During the time period t2-t3, the word line coupled to the second storage cell is floated. When the voltage of the channel increases, the voltage jump principle across the capacitor causes the voltage of the word line to increase. For example, the voltage of the word line gradually increases from the initial voltage of the word line until it reaches the third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes lower than the tunneling voltage of the second storage cell, thereby preventing the data stored in the second storage cell from being erased.

[0257] During the time period t2-t4, the word line coupled to the first storage cell always maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first storage cell, the data stored in the first storage cell can be erased.

[0258] During the time period t2-t3, similar to the floating select line coupled to the BSG, the TSG, serving as the second select transistor of the memory string, has its coupled select line floated, causing the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage becomes smaller than the tunneling voltage of the TSG, thereby preventing the threshold voltage of the TSG from drifting.

[0259] The method provided by an embodiment of the present application applies a first voltage to a first end of a memory string and a second voltage, less than the first voltage, to a word line coupled to a first memory cell in the memory string. Because the voltage difference between the first and second voltages is greater than or equal to the tunneling voltage of the first memory cell, invalid data stored therein can be erased. Furthermore, a third voltage, less than the first voltage, is applied to a word line coupled to a second memory cell in the memory string. Because the voltage difference between the first and third voltages is less than the tunneling voltage of the second memory cell, valid data stored therein can be protected from being erased, eliminating the need to migrate valid data. This saves time in migrating valid data back and forth and improves the erase efficiency of the memory block. Furthermore, by controlling the movement of holes from the end of the memory string closest to the second memory cell toward the channel of the memory string to raise the channel voltage, an eighth voltage is applied to the word line coupled to the second memory cell before the channel voltage reaches a seventh voltage, allowing holes that have entered the channel to move to the channel of the first memory cell, thereby erasing the data stored in the first memory cell. When the channel voltage reaches the seventh voltage, a third voltage is configured for the word line coupled to the second memory cell to prevent data stored in the second memory cell from being erased.

[0260] It should be noted that, since the first and second memory cells in each memory string in the memory block are arranged identically, and the memory strings of the memory block share the same source line, applying a first voltage to the source line is equivalent to applying the same voltage to one end of each memory string in the memory block coupled to the source line. A first voltage is applied to the bit lines corresponding to each memory string in the memory block. When voltage is applied to the word lines coupled to each memory cell in the memory string and the select lines coupled to each select transistor, the data stored in the first memory cell in each memory string in the memory block can be erased, and the data stored in the second memory cell in each memory string can be protected from being erased.

[0261] In addition, in addition to the two distribution situations of storage string 1001 and storage string 1002 introduced above, there are other possible distribution situations of the storage string. When the distribution of the storage string is other possible distribution situations, data can also be erased from the storage string based on the above-mentioned operation method of the storage device.

[0262] Other possible distributions include Figure 10 Any of the memory strings 1003-1005 in the memory string 1003. The second memory cell in the memory string 1003 is located in an adjacent layer and in the middle of the memory string 1003. The first memory cell in the memory string 1003 is divided into two parts. One part of the first memory cell is located in an adjacent layer and is close to the bit line contact coupled to the memory string 1003, and the other part of the first memory cell is located in an adjacent layer and is close to the source contact coupled to the memory string 1003.

[0263] The first memory cells in the memory string 1004 are located in adjacent layers and in the middle of the memory string 1004. The second memory cells in the memory string 1004 are divided into two parts: one part of the second memory cells is located in adjacent layers and is close to the bit line contact coupled to the memory string 1004, and the other part of the second memory cells is located in adjacent layers and is close to the source contact coupled to the memory string 1004.

[0264] The first and second storage cells in storage string 1005 are located in adjacent layers. Of course, in addition to storage strings 1001-1005, storage strings may also have other distribution patterns, for example, one layer of first storage cells is distributed every two layers of second storage cells, or the first and second storage cells are alternately distributed in the storage string. The embodiments of the present application do not limit the distribution of the first and second storage cells in the storage string.

[0265] It should be understood that the “some embodiments” mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in some embodiments” or “in other embodiments” appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0266] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0267] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory device, characterized in that: The memory device includes a memory array and a peripheral circuit; The memory array includes a memory string and a plurality of word lines, the memory string includes at least one first memory cell and at least one second memory cell, the first memory cell is a memory cell in the memory string storing invalid data, and the second memory cell is a memory cell in the memory string storing valid data; The plurality of word lines are respectively coupled to the plurality of memory cells of the memory string; The peripheral circuit is coupled to the memory array and is configured to: Applying a first voltage to a first end of the memory string, where the first end is an end coupled to a bit line contact corresponding to the memory string or an end coupled to a source contact corresponding to the memory string; Applying a second voltage to a word line coupled to the first memory cell, wherein the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage; A third voltage is configured for a word line coupled to the second memory cell, where the third voltage is lower than the first voltage, and a voltage difference between the first voltage and the third voltage is lower than a second tunneling voltage.

2. The memory device according to claim 1, wherein: The peripheral circuit is further configured to: The third voltage is applied to the coupled word line of the second memory cell.

3. The memory device according to claim 1, wherein: The peripheral circuit is further configured to: The word line coupled to the second memory cell is floated.

4. The memory device according to any one of claims 1 to 3, wherein: The memory string further includes at least one first selection transistor, the first selection transistor being close to the first end; and the peripheral circuit is further configured as follows: A fourth voltage is applied to the selection line coupled to the first selection transistor, where the fourth voltage is lower than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfies a voltage difference condition for band-to-band tunneling.

5. The memory device according to claim 4, wherein: The first end is coupled to a bit line contact corresponding to the memory string, the bit line contact is an N-type doped conductive structure, and the doping concentration of the impurity is greater than or equal to a first concentration.

6. The memory device according to claim 4, wherein: The first end is coupled to a source contact portion corresponding to the memory string.

7. The memory device according to any one of claims 1 to 3, wherein: The memory string further includes at least one first selection transistor, the first selection transistor being close to the first end, the first end being coupled to a source contact portion corresponding to the memory string, the source contact portion being a P-type doped conductive structure; the peripheral circuit is further configured as follows: A fifth voltage is applied to the selection line coupled to the first selection transistor, where the fifth voltage is lower than the first voltage.

8. The memory device according to claim 4, wherein: The first storage unit is close to the first end, and the second storage unit is far from the first end.

9. The memory device according to claim 8, wherein: The memory string further includes at least one second selection transistor, and the at least one second selection transistor is far away from the first end; the peripheral circuit is further configured to: A sixth voltage is configured for the selection line coupled to the second selection transistor. The sixth voltage is lower than the first voltage, and a voltage difference between the first voltage and the sixth voltage is lower than a third tunneling voltage.

10. The memory device according to claim 4, wherein: The first storage unit is far away from the first end, and the second storage unit is close to the first end; the peripheral circuit is further configured as follows: Before the channel voltage of the memory string reaches a seventh voltage, applying an eighth voltage to the word line coupled to the second memory cell, wherein the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage; After the channel voltage of the memory string reaches the seventh voltage, the step of configuring a third voltage for the word line coupled to the second memory cell is performed.

11. The memory device according to claim 10, wherein: The memory string further includes at least one second selection transistor, and the at least one second selection transistor is far away from the first end; the peripheral circuit is further configured to: Before the channel voltage of the memory string reaches the seventh voltage, applying a ninth voltage to the selection line coupled to the second selection transistor, wherein the seventh voltage is greater than the ninth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the ninth voltage is less than a third tunneling voltage; After the channel voltage of the storage string reaches the seventh voltage, a sixth voltage is configured for the selection line coupled to the second selection transistor, the sixth voltage is less than the first voltage, and a voltage difference between the first voltage and the sixth voltage is less than a third tunneling voltage.

12. A system, characterized in that: The system includes a memory device configured to store data, the memory device including a memory array and peripheral circuits; The memory array includes a memory string and a plurality of word lines, the memory string includes at least one first memory cell and at least one second memory cell, the first memory cell is a memory cell in the memory string storing invalid data, and the second memory cell is a memory cell in the memory string storing valid data; The plurality of word lines are respectively coupled to the plurality of memory cells of the memory string; The peripheral circuit is coupled to the memory array and is configured to: Applying a first voltage to a first end of the memory string, where the first end is an end coupled to a bit line contact corresponding to the memory string or an end coupled to a source contact corresponding to the memory string; Applying a second voltage to a word line coupled to the first memory cell, wherein the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage; A third voltage is configured for a word line coupled to the second memory cell, where the third voltage is lower than the first voltage, and a voltage difference between the first voltage and the third voltage is lower than a second tunneling voltage.

13. The system according to claim 12, wherein: The peripheral circuit is further configured to: The third voltage is applied to the coupled word line of the second memory cell.

14. The system according to claim 12, wherein: The peripheral circuit is further configured to: The word line coupled to the second memory cell is floated.

15. The system according to any one of claims 12 to 14, characterized in that: The memory string further includes at least one first selection transistor, the first selection transistor being close to the first end; and the peripheral circuit is further configured as follows: A fourth voltage is applied to the selection line coupled to the first selection transistor, where the fourth voltage is lower than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfies a voltage difference condition for band-to-band tunneling.

16. The system according to claim 15, characterized in that The first end is coupled to a bit line contact corresponding to the memory string, the bit line contact is an N-type doped conductive structure, and the doping concentration of the impurity is greater than or equal to a first concentration.

17. The system according to claim 15, wherein: The first end is coupled to a source contact portion corresponding to the memory string.

18. The system according to any one of claims 12 to 14, characterized in that: The memory string further includes at least one first selection transistor, the first selection transistor being close to the first end, the first end being coupled to a source contact portion corresponding to the memory string, the source contact portion being a P-type doped conductive structure; the peripheral circuit is further configured as follows: A fifth voltage is applied to the selection line coupled to the first selection transistor, where the fifth voltage is lower than the first voltage.

19. The system according to claim 15, wherein: The first storage unit is close to the first end, and the second storage unit is far from the first end.

20. The system according to claim 19, wherein: The memory string further includes at least one second selection transistor, and the at least one second selection transistor is far away from the first end; the peripheral circuit is further configured to: A sixth voltage is configured for the selection line coupled to the second selection transistor. The sixth voltage is lower than the first voltage, and a voltage difference between the first voltage and the sixth voltage is lower than a third tunneling voltage.

21. The system according to claim 15, wherein: The first storage unit is far away from the first end, and the second storage unit is close to the first end; the peripheral circuit is further configured as follows: Before the channel voltage of the memory string reaches a seventh voltage, applying an eighth voltage to the word line coupled to the second memory cell, wherein the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage; After the channel voltage of the memory string reaches the seventh voltage, the step of configuring a third voltage for the word line coupled to the second memory cell is performed.

22. The system according to claim 21, wherein: The memory string further includes at least one second selection transistor, and the at least one second selection transistor is far away from the first end; the peripheral circuit is further configured to: Before the channel voltage of the memory string reaches the seventh voltage, applying a ninth voltage to the selection line coupled to the second selection transistor, wherein the seventh voltage is greater than the ninth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the ninth voltage is less than a third tunneling voltage; After the channel voltage of the storage string reaches the seventh voltage, a sixth voltage is configured for the selection line coupled to the second selection transistor, the sixth voltage is less than the first voltage, and a voltage difference between the first voltage and the sixth voltage is less than a third tunneling voltage.

23. The system according to any one of claims 12-14, 16, 17 or 19-22, characterized in that: The system also includes a host and a memory controller; The host is configured to send data to the storage device or receive data from the storage device; The memory controller is coupled to the host and the memory device and is configured to control the memory device.

24. A method for operating a memory device, characterized in that: The memory device includes a memory array, the memory array includes memory strings and a plurality of word lines, the memory strings include at least one first memory cell and at least one second memory cell, the first memory cell is a memory cell in the memory string storing invalid data, the second memory cell is a memory cell in the memory string storing valid data, the plurality of word lines are respectively coupled to the plurality of memory cells in the memory strings; the method includes: Applying a first voltage to a first end of the memory string, where the first end is an end coupled to a bit line contact corresponding to the memory string or an end coupled to a source contact corresponding to the memory string; Applying a second voltage to a word line coupled to the first memory cell, wherein the second voltage is lower than the first voltage, and a voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage; A third voltage is configured for a word line coupled to the second memory cell, where the third voltage is lower than the first voltage, and a voltage difference between the first voltage and the third voltage is lower than a second tunneling voltage.

25. The method according to claim 24, characterized in that Configuring a third voltage for the word line coupled to the second memory cell includes: The third voltage is applied to the coupled word line of the second memory cell.

26. The method according to claim 24, characterized in that Configuring a third voltage for the word line coupled to the second memory cell includes: The word line coupled to the second memory cell is floated.

27. The method according to any one of claims 24 to 26, characterized in that: The storage string further includes at least one first selection tube, the first selection tube being close to the first end; the method further includes: A fourth voltage is applied to the selection line coupled to the first selection transistor, where the fourth voltage is lower than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfies a voltage difference condition for band-to-band tunneling.

28. The method according to claim 27, characterized in that The first end is coupled to a bit line contact corresponding to the memory string, the bit line contact is an N-type doped conductive structure, and the doping concentration of the impurity is greater than or equal to a first concentration.

29. The method according to claim 27, characterized in that The first end is coupled to a source contact portion corresponding to the memory string.

30. The method according to any one of claims 24 to 26, characterized in that: The memory string further includes at least one first selection transistor, the first selection transistor being close to the first end, the first end being coupled to a source contact portion corresponding to the memory string, the source contact portion being a P-type doped conductive structure; The method further comprises: A fifth voltage is applied to the selection line coupled to the first selection transistor, where the fifth voltage is lower than the first voltage.

31. The method according to claim 27, wherein The first storage unit is close to the first end, and the second storage unit is far from the first end.

32. The method according to claim 31, characterized in that The storage string further includes at least one second selection tube, and the at least one second selection tube is away from the first end; the method further includes: A sixth voltage is configured for the selection line coupled to the second selection transistor. The sixth voltage is lower than the first voltage, and a voltage difference between the first voltage and the sixth voltage is lower than a third tunneling voltage.

33. The method according to claim 27, wherein The first storage unit is far away from the first end, and the second storage unit is close to the first end; the method further includes: Before the channel voltage of the memory string reaches a seventh voltage, applying an eighth voltage to the word line coupled to the second memory cell, wherein the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage; After the channel voltage of the memory string reaches the seventh voltage, the step of configuring a third voltage for the word line coupled to the second memory cell is performed.

34. The method according to claim 33, wherein The storage string further includes at least one second selection tube, and the at least one second selection tube is away from the first end; the method further includes: Before the channel voltage of the memory string reaches the seventh voltage, applying a ninth voltage to the selection line coupled to the second selection transistor, wherein the seventh voltage is greater than the ninth voltage and less than or equal to the first voltage, and a voltage difference between the seventh voltage and the ninth voltage is less than a third tunneling voltage; After the channel voltage of the storage string reaches the seventh voltage, a sixth voltage is configured for the selection line coupled to the second selection transistor, the sixth voltage is less than the first voltage, and a voltage difference between the first voltage and the sixth voltage is less than a third tunneling voltage.

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