Non-volatile memory with switchable erase method

Abstract

To improve the erase process, multiple erase methods are utilized. A first erase method is relied upon at the beginning of the life of a memory system. As the memory system is used and subjected to many program / erase cycles, a second method is relied upon increasingly. In one example, the first erase method includes separately applying an erase enable voltage to different subsets of word lines, with word lines that do not receive the erase enable voltage receiving an erase inhibit voltage. In one example, the second erase method includes simultaneously applying an erase enable voltage to all subsets of the word lines.

Description

TECHNICAL FIELD

[0001] This application relates to a non-volatile memory system with a switchable erase method and related methods. BACKGROUND

[0002] Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows storage and preservation of information even when the non-volatile memory is not connected to a power source, such as a battery. One example of non-volatile memory is flash memory (e.g., NAND and NOR flash memory).

[0003] A user of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read the data back. For example, a digital camera can take a picture and store the picture in non-volatile memory. Later, the user of the digital camera can view the picture by causing the digital camera to read the picture from the non-volatile memory.

[0004] All or part of non-volatile memory can also be erased. For example, if data becomes outdated or the data is no longer needed, the portion of non-volatile memory that stores the outdated or no longer needed data can be erased so that the portion of non-volatile memory can be used to store new data. Alternatively, erasing can be used to write data; for example, programming from a first state to a second state and erasing back to the first state (or between more than two states). The erase process used by a memory system should be accurate so that data is not lost and should be fast enough so that a user of the memory system does not experience unreasonable delays. In addition, the erase process should be implemented to mitigate side effects that can damage the memory system or cause data loss. SUMMARY

[0005] According to one embodiment, a non-volatile memory system is provided that includes a group of non-volatile memory cells; and control circuitry connected to the group of non-volatile memory cells, the control circuitry configured to perform an erase process for the group of non-volatile memory cells by performing an erase operation on each subset of a subset of the group of non-volatile memory cells separately in time and subsequently performing an erase operation on all of the non-volatile memory cells in the group of non-volatile memory cells simultaneously.

[0006] According to one embodiment, a method is provided that includes performing multiple iterations of an erase process to erase a group of non-volatile memory cells connected to a set of word lines, each iteration of the erase process including applying an erase voltage as one or more voltage pulses to the group of non-volatile memory cells, a first iteration of the erase process including performing a first erase method that includes applying an erase enable voltage to different subsets of the word lines separately in time without the word lines receiving the erase enable voltage receiving an erase inhibit voltage; and after a metric has exceeded a threshold, for one or more additional iterations of the erase process, switching from performing the first erase method to performing a second erase method that includes applying the erase enable voltage to all subsets of the word lines simultaneously.

[0007] According to another embodiment, a non-volatile memory system is provided that includes a group of non-volatile memory cells; and control circuitry connected to the group of non-volatile memory cells, the control circuitry configured to erase the group of non-volatile memory cells by performing iterations of an erase process, during each iteration the control circuitry configured to apply a first selected erase enable voltage to a first set of word lines while applying a first unselected erase voltage to a second set of word lines, and subsequently apply a second selected erase enable voltage to the second set of word lines while applying a second unselected erase voltage to the first set of word lines, and the control circuitry configured to change the first unselected erase voltage and the second unselected erase voltage over time while performing the iterations of the erase process such that the first unselected erase voltage approaches the first selected erase enable voltage and the second unselected erase voltage approaches the second selected erase enable voltage. BRIEF DESCRIPTION OF DRAWINGS

[0008] Numerically similar elements refer to common components in different figures.

[0009] Figure 1 is a block diagram depicting one embodiment of a memory system.

[0010] Figure 2 is a block diagram of one embodiment of a memory die.

[0011] Figure 3 is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure.

[0012] Figure 4A is a block diagram of a memory structure having two planes.

[0013] Figure 4B depicts a top view of a portion of a block of memory cells.

[0014] Figure 4C A cross-sectional view depicting a portion of a block of memory cells.

[0015] Figure 4D A view depicting select gate layers and word line layers.

[0016] Figure 4E A cross-sectional view of a vertical column of memory cells.

[0017] Figure 4F A schematic diagram showing a plurality of NAND strings of a plurality of sub-blocks.

[0018] Figure 5 Depicting a threshold voltage distribution.

[0019] Figure 6 A table describing one example of an assignment of data values to data states.

[0020] Figure 7 A flow diagram describing one embodiment of a process for programming non-volatile memory.

[0021] Figure 7A A block diagram showing details of one embodiment of circuitry for applying voltages to memory structure 126.

[0022] Figure 8 Depicting a NAND string undergoing GIDL erase.

[0023] Figure 9 Depicting a portion of a NAND string undergoing erase.

[0024] Figure 10A Depicting a portion of a NAND string undergoing erase.

[0025] Figure 10B Depicting a portion of a NAND string undergoing erase.

[0026] Figure 11 Depicting a portion of a NAND string undergoing erase.

[0027] Figure 12 Depicting a portion of a NAND string undergoing erase.

[0028] Figure 13 A flow diagram describing one embodiment of a process for erasing non-volatile memory.

[0029] Figure 14 A flow diagram describing one embodiment of a process for erasing non-volatile memory.

[0030] Figure 15 A block diagram of a portion of a non-volatile memory system.

[0031] Figure 16 is a graph depicting the final values of erase voltage versus program / erase cycles for multiple types of erase processes.

[0032] Figure 17 is a flowchart describing one embodiment of a process for erasing non-volatile memory.

[0033] Figure 18 is a flowchart describing one embodiment of a process for erasing non-volatile memory.

[0034] Figure 19 is a flowchart describing one embodiment of a process for erasing non-volatile memory. DETAILED DESCRIPTION

[0035] Some erase methods can be superior to others when the memory system is new, while other erase methods can be better when the memory system is older. Thus, to improve the erase process, multiple erase methods are utilized. A first erase method is relied on more at the beginning of the life of the memory system. As the memory system is used and the memory system is subjected to many program / erase cycles, a second erase method is relied on more and more. A program / erase cycle is where both programming and erasing are performed on the same population of memory cells. An example of the first erase method is to apply erase to a subset of the non-volatile memory cells being erased individually. An example of the second erase method is to apply erase to all of the non-volatile memory cells being erased simultaneously.

[0036] In one embodiment, control circuitry connected to a group of non-volatile memory cells is configured to erase the group of non-volatile memory cells by applying erase to a subset of the non-volatile memory cells individually and then applying erase to all of the non-volatile memory cells in the group of non-volatile memory cells simultaneously. The switch from applying erase to a subset of the non-volatile memory cells individually to applying erase to all of the non-volatile memory cells in the group simultaneously is based on a metric that indicates an amount of use of the memory cells. For example, the switch can be based on a number of iterations of the erase process (also referred to as a cycle count), a magnitude of the erase voltage, a number of program / erase cycles, or other metric.

[0037] Figure 1is a block diagram of one embodiment of a memory system 100 that implements the proposed technology including the proposed scrub process. In one embodiment, the memory system 100 is a solid state drive ("SSD"). The memory system 100 can also be a memory card, a USB drive, or other type of memory system. The proposed technology is not limited to any one type of memory system. The memory system 100 is connected to a host 102, which can be a computer, a server, an electronic device (such as a smartphone, tablet, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from but connected to the memory system 100. In other embodiments, the memory system 100 is embedded within the host 102.

[0038] Figure 1 The components of the memory system 100 depicted in FIG. 1 are circuits. The memory system 100 includes a controller 120 that is connected to one or more memory dies 130 and a local high-speed volatile memory 140 (such as DRAM). Each of the one or more memory dies 130 includes a plurality of non-volatile memory cells. More information about the structure of each memory die 130 is provided below. The local high-speed volatile memory 140 is used by the controller 120 to perform certain functions. For example, the local high-speed volatile memory 140 stores a logical to physical address translation table ("L2P table").

[0039] The controller 120 includes a host interface 152 that is connected to and in communication with the host 102. In one embodiment, the host interface 152 provides a PCIe interface. Other interfaces, such as SCSI, SATA, etc., can also be used. The host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. A NOC can span synchronous and asynchronous clock domains or use clockless asynchronous logic. NOC technology applies networking theory and methods to on-chip communication and brings significant improvements over conventional buses and crossbar interconnects. NOCs improve the scalability and power efficiency of a system-on-a-chip (SoC) over other designs. The wires and links of a NOC are shared by multiple signals. Because all links in a NOC can operate on different packets at the same time, a high level of parallelism is achieved. Thus, as the complexity of integrated subsystems continues to increase, a NOC provides enhanced performance (e.g., throughput) and scalability over previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. A processor 156, an ECC engine 158, a memory interface 160, and a DRAM controller 164 are connected to and in communication with the NOC 154. The DRAM controller 164 is used to operate and communicate with the local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 140 can be SRAM or another type of volatile memory.

[0040] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to an implemented ECC technique. In one embodiment, the ECC engine 158 is a circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0041] The processor 156 performs various controller memory operations, such as program, erase, read, and memory management processes. In one embodiment, the processor 156 is programmed by firmware. In other embodiments, the processor 156 is a custom and dedicated hardware circuit without any software. The processor 156 also implements the translation module, either in the form of software / firmware processes or in the form of dedicated hardware circuitry. In many systems, non-volatile memory is internally addressed to the memory system using physical addresses associated with one or more memory dies. However, a host system will address individual memory locations using logical addresses. This enables the host to allocate data to consecutive logical addresses, while the storage system is free to store the data anywhere among the locations of one or more memory dies. To implement this system, a controller (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation maintains a table that identifies the current translation between logical and physical addresses (i.e., the L2P table mentioned above). An entry in the L2P table can include a logical address and an identification of the corresponding physical address. Although the logical address to physical address table (or L2P table) includes the word "table," it is not necessarily a table in the literal sense. In fact, the logical address to physical address table (or L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all of the L2P table. In this case, the entire set of L2P tables is stored in the memory dies 130, and a subset of the L2P tables (L2P cache) is cached in the local high-speed volatile memory 140.

[0042] The memory interface 160 communicates with one or more memory dies 130. In one embodiment, the memory interface provides a toggle mode interface. Other interfaces can also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffers for transferring data to and from the one or more memory dies.

[0043] Figure 2 is a functional block diagram of one embodiment of a memory die 300. Figure 1 Each of the one or more memory dies 130 of Figure 2 the memory die 300 of Figure 2The depicted components are circuits. In one embodiment, each memory die 300 includes a memory structure 326, control circuitry 310, and read / write circuitry 328. The memory structure 326 is addressable via row decoders 324 by word lines and via column decoders 332 by bit lines. The read / write circuitry 328 includes a plurality of sense blocks 350 including SB1, SB2,..., SBp (sensing circuitry) and allows a page (or pages) of data in a plurality of memory cells to be read or programmed (written) in parallel. In one embodiment, each sense block includes a sense amplifier connected to a bit line and a set of latches. The latches store data to be written and / or data that has been read. The sense amplifier includes a bit line driver. Commands and data are transferred between the controller and the memory die 300 via lines 319. In one embodiment, the memory die 300 includes a set of input and / or output (I / O) pins connected to lines 118.

[0044] The control circuitry 310 cooperates with the read / write circuits 328 to perform memory operations (e.g., write, read, erase, etc.) on the memory structure 326. In one embodiment, the control circuitry 310 includes a state machine 312, an on-chip address decoder 314, a power control circuit 316, and memory die parameters 318. The state machine 312 provides die-level control of memory operations. In one embodiment, the state machine 312 can be programmed by software. In other embodiments, the state machine 312 does not use software and is implemented in hardware (e.g., circuitry) entirely. In some embodiments, the state machine 312 can be replaced by a programmable microcontroller or microprocessor. In one embodiment, the control circuitry 310 includes memory die parameters 318 stored in buffers such as registers, latches, ROM fuses, and other storage. The memory die parameters 318 are default values, e.g., basic voltages and other parameters used by the memory die 300 (e.g., by the state machine 312) to perform memory operations.

[0045] The on-chip address decoder 314 provides an address interface between addresses used by the controller 120 and hardware addresses used by the decoders 324 and 332. The power control module 316 controls the power and voltages supplied to the word lines and bit lines during memory operations. The power control module 316 can include charge pumps for generating voltages.

[0046] For the purposes of this document, the control circuitry 310, read / write circuits 328, and decoders 324 / 332 comprise one embodiment of control circuitry for the memory structure 326. In other embodiments, other circuits that support and operate on the memory structure 326 can be referred to as control circuitry. For example, in some embodiments, a controller can operate as or can be part of the control circuitry. In some embodiments, a controller in conjunction with the control circuitry 310, read / write circuits 328, and decoders 324 / 332 comprises one embodiment of control circuitry. In another embodiment, the state machine 312 comprises the control circuitry. In another embodiment, the host can provide the control circuitry.

[0047] In one embodiment, the memory structure 326 comprises a monolithic three- dimensional memory array of non-volatile memory cells, with multiple levels of memory formed above a single substrate (e.g., wafer). The memory structure can comprise any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having charge-trapping material, for example, as described in U.S. Patent 9,721,662, incorporated by reference herein in its entirety. The NAND strings contain memory cells connected by a channel.

[0048] In another embodiment, the memory structure 326 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells with floating gates, for example, as described in U.S. Patent 9,082,502, incorporated by reference herein in its entirety. Other types of memory cells (e.g., NOR type flash memory) can also be used.

[0049] The exact type of memory array architecture or memory cell contained in the memory structure 326 is not limited to the examples described above. Many different types of memory array architecture or memory cell technology can be used to form the memory structure 326. It is not required that a particular non-volatile memory technology be employed for the purposes of the new claimed embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 326 include ferroelectric memory (FeRAM or FeFET), ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of the memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0050] One example of a ReRAM or PCRAM cross-point memory includes reversible resistance switching elements arranged in a cross-point array accessed by X and Y lines, such as word and bit lines. In another embodiment, the memory cells can include conductive-bridging memory elements. Conductive-bridging memory elements can also be referred to as programmable metallization cells. Conductive-bridging memory elements can function as state-change elements based on physical migration of ions within a solid electrolyte. In some cases, conductive-bridging memory elements can include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases, causing the programming threshold of the conductive-bridging memory cell to decrease. Thus, conductive-bridging memory elements can have a wide range of programming thresholds that vary with temperature.

[0051] Magnetic RAM (MRAM) stores data by magnetic storage elements. The elements are formed by two ferromagnetic plates separated by a thin insulating layer, each of which can hold a magnetization. One of the two plates is a permanent magnet set to a particular polarity; the magnetization of the other plate can be changed to match that of an external field that stores the memory. Memory devices are constructed from a grid of such memory cells. In one embodiment with respect to programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current is passed through the pair of write lines, an induced magnetic field is generated.

[0052] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glasses. One embodiment uses a Ge2Sb2Te5alloy to effect phase changes by electrically heating the phase change material. Programming doses are electrical pulses of different amplitudes and / or lengths that cause different resistance values of the phase change material.

[0053] One of ordinary skill in the art will recognize that the techniques described herein are not limited to a single particular memory structure, but cover many related memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

[0054] Figure 3 is a perspective view of a portion of one example embodiment of a monolithic three-dimensional memory array that can include memory structures 326, which include a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 3A portion of a memory block is shown. The depicted structure comprises a set of bit lines BLs situated above a stack of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as word line layers) is labeled W. The number of alternating dielectric and conductive layers can vary based on the requirements of a particular implementation. One set of embodiments contains between 108 and 300 alternating dielectric and conductive layers. One example embodiment contains 96 data word line layers, 8 select layers, 6 virtual word line layers, and 110 dielectric layers. More or fewer layers than 108 to 300 can also be used. As will be explained below, the alternating dielectric and conductive layers are divided into four “finger” structures via local interconnects LI. Figure 3 Two fingers and two local interconnects LI are shown. The source line layer SL lies beneath alternating dielectric and word line layers. Memory vias are formed within a stack of alternating dielectric and conductive layers. For example, one of the memory vias is labeled MH. It should be noted that in... Figure 3 In the illustration, the dielectric layers are depicted in perspective so that the reader can see the memory holes situated within the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material containing a charge-trapping material to form a vertical column of memory cells. Each memory cell can store one or more data bits. Further details are provided below regarding... Figures 4A to 4F More details are provided for the three-dimensional monolithic memory array, including memory structure 326.

[0055] Figure 4A This is a block diagram illustrating an example organization of memory structure 326, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a memory cell block is the unit of erasure. That is, all memory cells in the block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize memory structure 326 to enable signaling and selection circuitry. In some embodiments, a block represents a connected group of memory cells because the memory cells in the block share a common set of word lines.

[0056] Figures 4B to 4F Describing corresponds to Figure 3 The structure can be used for implementation Figure 2 The memory structure 326 is an example of a three-dimensional (“3D”) NAND structure. Figure 4B It is a block diagram depicting a top view of a portion of a block of memory structure 326. Figure 4B The part of the block depicted in the middle corresponds to Figure 4A Part 306 in block 2. For example, it can be obtained from... Figure 4B see, Figure 4BThe depicted block extends in the direction 33 of the arrows. In one embodiment, the memory array has many tiers; however, Figure 4B Only the top tier is shown.

[0057] Figure 4B A plurality of circles are depicted representing vertical columns. Each of the vertical columns contains a plurality of select transistors (also known as select gates) and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B The vertical columns 422, 432, 442, and 452 are depicted. The vertical column 422 implements a NAND string 482. The vertical column 432 implements a NAND string 484. The vertical column 442 implements a NAND string 486. The vertical column 452 implements a NAND string 488. More details of the vertical columns are provided below. As Figure 4B The depicted block extends in the direction 33 of the arrows, thus the block contains more vertical columns than Figure 4B The depicted block contains more vertical columns than

[0058] Figure 4B A set of bit lines 415 is also depicted, including bit lines 411, 412, 413, 414,... 419. Figure 4B Twenty-four bit lines are shown because only a portion of the block is depicted. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each of the circles representing the vertical columns has an "x" indicating its connection to one bit line. For example, the bit line 414 is connected to the vertical columns 422, 432, 442, and 452.

[0059] Figure 4B The depicted block contains a set of local interconnects 402, 404, 406, 408, and 410 that connect the various tiers to the source lines below the vertical columns. The local interconnects 402, 404, 406, 408, and 410 are also used to divide each tier of the block into four zones; for example, Figure 4BThe top level depicted is divided into regions 420, 430, 440, and 450, which are referred to as fingers. In a level of a block in which memory cells are implemented, the four regions are referred to as word line fingers that are separated by local interconnects. In one embodiment, the word line fingers on a common level of a block are connected together to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In one example implementation, a bit line is connected to only one vertical column in each of regions 420, 430, 440, and 450. In that implementation, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to a common bit line (via different word line fingers connected together on the same level) are connected to the same word line; thus, the system uses a source side select line and a drain side select line to select one of the four (or another subset) for a memory operation (program, verify, read, and / or erase).

[0060] Although Figure 4B The block is shown with four regions and sixteen rows of vertical columns, each region having four rows of vertical columns, but those exact numbers are example implementations. Other embodiments can include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block.

[0061] Figure 4B The vertical columns are also shown to be staggered. In other embodiments, different staggering patterns can be used. In some embodiments, the vertical columns are not staggered.

[0062] Figure 4C A portion of one embodiment of the three-dimensional memory structure 326 is depicted, showing a cross-sectional view along line AA of Figure 4B The cross-sectional view is through vertical columns 432 and 434 and region 430 (see Figure 4B ). Figure 4CThe structure includes four drain side select layers SGD0, SGD1, SGD2, and SGD3; four source side select layers SGS0, SGS1, SGS2, and SGS3; six dummy word line layers DD0, DD1, DS0, DS1, WLDL, WLDU; and ninety-six data word line layers WLL0-WLL95 for connection to data memory cells. Other embodiments can implement more or less than four drain side select layers, more or less than four source side select layers, more or less than six dummy word line layers, and more or less than ninety-six word lines. Vertical columns 432 and 434 are depicted as protruding through the drain side select layers, source side select layers, dummy word line layers, and word line layers. In one embodiment, each vertical column includes a vertical NAND string. For example, vertical column 432 includes NAND string 484. Beneath the vertical column and the layers listed below are substrate 101, insulating film 454 on the substrate, and source line SL. The NAND string of vertical column 432 has a source end at the bottom of the stack and a drain end at the top of the stack. As consistent with Figure 4B Figure 4C Vertical column 432 is shown connected to bit line 414 via connection 417. Local interconnects 404 and 406 are also depicted.

[0063] For ease of reference, drain side select layers SGD0, SGD1, SGD2, and SGD3; source side select layers SGS0, SGS1, SGS2, and SGS3; dummy word line layers DD0, DD1, DS0, DS1, WLDL, and WLDU; and word line layers WLL0-WLL95 are collectively referred to as conductive layers. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal (e.g., tungsten), or metal silicide. In some embodiments, different conductive layers can be formed of different materials. Between the conductive layers are dielectric layers DL0-DL111. For example, dielectric layer DL104 is above word line layer WLL94 and below word line layer WLL95. In one embodiment, the dielectric layers are made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0064] ​Non-volatile memory cells are formed along vertical columns that extend through the alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0-WLL95 are connected to the memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL, and WLDU are connected to dummy memory cells. The dummy memory cells do not store and are not eligible to store host data (data provided from a host, such as data from a user of the host), while the data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells can have the same structure. Dummy word lines are connected to the dummy memory cells. Drain side select layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND strings to bit lines. Source side select layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND strings to source lines SL.

[0065] Figure 4C A junction region is also shown. In one embodiment, etching ninety-six word line layers interleaved with dielectric layers is costly and / or challenging. To mitigate this burden, one embodiment includes laying down a first stack of forty-eight word line layers interleaved with dielectric layers, laying down a junction region, and laying down a second stack of forty-eight word line layers interleaved with dielectric layers. The junction region is between the first stack and the second stack. The junction region is used to connect the first stack to the second stack. In Figure 4C , the first stack is labeled "lower word line set" and the second stack is labeled "upper word line set." In one embodiment, the junction region is made of the same material as the word line layers. In one set of example implementations, the plurality of word lines (control lines) includes a first stack of interleaved word line layers and dielectric layers, a second stack of interleaved word line layers and dielectric layers, and a junction region between the first stack and the second stack, as depicted in Figure 4C .

[0066] Figure 4D A logical representation of a conductive layer is depicted that includes word line layers WLL0 WLL1, WLL2, WLL3, WLL4, WLL5, WLL6, WLL7,... WLL88, WLL89, WLL90, WLL91, WLL92, WLL93, WLL94, and WLL95 of blocks partially depicted in Figure 4C , as described above with respect to Figure 4BAs mentioned, in one embodiment, local interconnects 402, 404, 406, 408, and 410 divide the conductive layer into four zones / fingers (or sub-blocks). For example, the word line layer WLL95 is divided into zones 460, 462, 464, and 466. Zone 460 is a word line finger on a word line layer. In one embodiment, four word line fingers on the same layer are connected together. In another embodiment, each word line finger operates as a separate word line.

[0067] Figure 4E Depicting Figure 4C A cross-sectional view of region 429, which includes a portion of vertical column 432 (memory vias). In one embodiment, the vertical column is circular; however, other shapes may be used in other embodiments. In one embodiment, vertical column 432 includes an inner core layer 470 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core layer 470 is a polysilicon channel 471. Materials other than polysilicon may also be used. Note that channel 471 connects to bit lines and source lines. Surrounding channel 471 is a tunneling dielectric 472. In one embodiment, tunneling dielectric 472 has an ONO structure. Surrounding tunneling dielectric 472 is a charge trapping layer 473, such as (for example) silicon nitride. Other memory materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

[0068] Figure 4E Dielectric layers DLL105, DLL104, DLL103, DLL102, and DLL101 are depicted, as well as word line layers WLL95, WLL94, WLL93, WLL92, and WLL91. Each of the word line layers includes a word line region 476 surrounded by an aluminum oxide layer 477, which is surrounded by a barrier oxide layer 478. In other embodiments, the barrier oxide layer may be a vertical layer parallel to and adjacent to the charge trapping layer 473. The physical interaction of the word line layers with the vertical columns forms a memory cell. Thus, in one embodiment, the memory cell includes a channel 471, a tunneling dielectric 472, a charge trapping layer 473, a barrier oxide layer 478, an aluminum oxide layer 477, and a word line region 476. For example, a portion of word line layer WLL95 and vertical column 432 includes memory cell MC1. A portion of word line layer WLL94 and vertical column 432 includes memory cell MC2. The word line layer WLL93 and vertical column 432 contain memory cells MC3. The word line layer WLL92 and vertical column 432 contain memory cells MC4. The word line layer WLL91 and vertical column 432 contain memory cells MC5. In other architectures, memory cells may have different structures; however, a memory cell will still be a storage unit.

[0069] When a memory cell is programmed, an electron is stored in a portion of the charge trapping layer 473 associated with the memory cell. In response to an appropriate voltage on the word line region 476, these electrons are drawn from the channel 471 into the charge trapping layer 473 through the tunneling dielectric 472. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is accomplished by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons that return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erasing is accomplished using hole injection into the charge trapping layer via a physical mechanism such as gate-induced drain leakage (GIDL).

[0070] Figure 4F is Figures 3 to 4E schematic diagram of a portion of the memory depicted in Figure 4F physical word lines WLL0-WLL95 are shown extending across the entire block. Figure 4F The structure of Figures 4A to 4E portion 306 in block 2 of includes bit lines 411, 412, 413, 414,... 419. Within the block, each bit line is connected to four NAND strings. Drain side select lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings are connected to the associated bit line. Source side select lines SGS0, SGS1, SGS2, and SGS3 are used to determine which of the four NAND strings are connected to a common source line. The block can also be considered to be divided into four sub-blocks SB0, SB1, SB2, and SB3. Sub-block SB0 corresponds to those vertical NAND strings controlled by SGD0 and SGS0, sub-block SB1 corresponds to those vertical NAND strings controlled by SGD1 and SGS1, sub-block SB2 corresponds to those vertical NAND strings controlled by SGD2 and SGS2, and sub-block SB3 corresponds to those vertical NAND strings controlled by SGD3 and SGS3.

[0071] Although Figures 3 to 4F example memory system of is a three-dimensional memory structure including vertical NAND strings having charge trapping material, other (2D and 3D) memory structures can also be used with the techniques described herein.

[0072] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process (verified), the threshold voltage of the memory cell should be within one or more threshold voltage distributions of the programmed memory cell or within the threshold voltage distribution of the erased memory cell, as desired. Figure 5is a plot of threshold voltage versus number of memory cells, and illustrates an example threshold voltage distribution of a memory array when each memory cell stores three bits of data. However, other embodiments can use other data capacities per memory cell (e.g., one, two, four, or five bits of data per memory cell). Figure 5 Eight threshold voltage distributions corresponding to eight data states are shown. For data state N, the data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. The first threshold voltage distribution (data state) S0 represents erased memory cells. The other seven threshold voltage distributions (data states) S1 through S7 represent programmed memory cells, and are thus also referred to as programmed states or programmed data states. In some embodiments, data states S1-S7 can overlap with the controller 122 relying on error correction to identify the correct data stored.

[0073] Figure 5 Seven read reference voltages Vrl, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 are shown for reading data from memory cells. By testing (e.g., performing a sense operation) whether a given memory cell's threshold voltage is higher or lower than the seven read reference voltages, the system can determine which data state (i.e., S0, S1, S2, S3,...) the memory cell is in.

[0074] Figure 5 Seven verify reference voltages Vvl, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 (also referred to as verify target voltages) are also shown. In programming memory cells to data state S1, the system will test whether those memory cells have a threshold voltage greater than or equal to Vvl. In programming memory cells to data state S2, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv2. In programming memory cells to data state S3, the system will determine whether memory cells have a threshold voltage greater than or equal to Vv3. In programming memory cells to data state S4, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv4. In programming memory cells to data state S5, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv5. In programming memory cells to data state S6, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv6. In programming memory cells to data state S7, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv7.

[0075] In one embodiment, referred to as full sequence programming, memory cells can be programmed directly from an erased data state SO to any one of programmed data states SI to S7. For example, a population of memory cells to be programmed can first be erased so that all memory cells in the population are in the erased data state SO. Subsequently, the memory cells are programmed directly to data states SI, S2, S3, S4, S5, S6, and / or S7 using a programming process. For example, while some memory cells are programmed from data state SO to data state SI, other memory cells are programmed from data state SO to data state S2 and / or from data state SO to data state S3, and so on. Figure 5 The arrows of FIG. 1 represent full sequence programming. The techniques described herein can also be used with other types of programming other than full sequence programming, including but not limited to multi-pass / multi-phase programming.

[0076] Figure 5 Each threshold voltage distribution (data state) of FIG. 1 corresponds to a predetermined value of a set of data bits stored in the memory cell. The particular relationship between data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme employed by the memory cell. In one embodiment, a Gray code assignment is used to assign data values to threshold voltage ranges such that if the threshold voltage of the memory shifts erroneously to its adjacent physical state, only one bit is affected.

[0077] Figure 6 is a table describing one example of an assignment of data values to data states. In Figure 6 In the table of FIG. 1, SO = 111 (erased state), SI = 110, S2 = 100, S3 = 000, S4 = 010, S5 = 011, S6 = 001, and S7 = 101. Other data encodings can also be used. The techniques disclosed herein do not require a particular data encoding. In one embodiment, when a block undergoes an erase operation, all memory cells move to data state SO, the erased state.

[0078] Generally, during verify operations and read operations, a selected word line is connected to a voltage (one example of a reference signal) that is specific to each read operation (see, e.g., FIG. 2). Figure 5 The read reference voltages Vrl, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 of FIG. 2) or verify operations (see, e.g., FIG. 3). Figure 5verify reference voltages Ev, Vvl, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7) to determine whether the threshold voltage of the memory cell has reached this level. After the word line voltage is applied, a conduction current of the memory cell is measured to determine whether the memory cell turns on (conducts current) in response to the voltage applied to the word line. If a conduction current greater than a certain value is measured, the memory cell is assumed to turn on, and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If a conduction current greater than the certain value is not measured, the memory cell is assumed not to turn on, and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verify process, unselected memory cells are provided with one or more read-through voltages (also referred to as bypass voltages) at their control gates, such that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0079] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate at which the conduction current discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) a NAND string containing the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see if the bit line has discharged. It should be noted that the techniques described herein can be used with different methods for sensing / reading known in the art. Other read and verify techniques known in the art can also be used.

[0080] Figure 7 is a flowchart that describes one embodiment of a program process performed by the memory die 300. In one example embodiment, the process of Figure 7 is performed on the memory die 300 using the control circuitry discussed above in the direction of the state machine 312. The process of Figure 7 is performed to implement the full sequence program of Figure 5 and other programming schemes that include multi-phase programming. When multi-level programming is implemented, the process of Figure 7 is used to implement any / each phase of the multi-phase programming process.

[0081] Generally, the program voltage applied to the control gate (through the selected word line) during a program operation is applied in the form of a series of program pulses (voltage pulses). Between the program pulses, there is a set of verify pulses for verification. In many implementations, the magnitude of the program pulses increases by a predetermined step size with each successive pulse. In Figure 7In step 570, the program voltage (Vpgm) is initialized to a starting value (e.g., about 12 to 16 V or another suitable level), and a program counter PC maintained by the state machine 312 is initialized to 1. In step 572, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, the entire group of memory cells being programmed simultaneously are all connected to the same word line (the selected word line). Unselected word lines receive one or more boost voltages (e.g., about 7 to 11 volts) to perform a boost scheme known in the art. In one embodiment, if a memory cell should be programmed, the corresponding bit line is grounded. On the other hand, if a memory cell should remain at its current threshold voltage, the corresponding bit line is connected to Vdd to inhibit programming. In step 572, the program pulse is applied simultaneously to all memory cells connected to the selected word line, such that all memory cells connected to the selected word line are programmed simultaneously. That is, the memory cells are programmed simultaneously or during overlapping time (both considered parallel). In this way, all memory cells connected to the selected word line will change their threshold voltage simultaneously, unless the memory cell has been locked from programming.

[0082] In step 574, one or more verify operations are performed using an appropriate set of verify reference voltages to verify appropriate memory cells. In one embodiment, the verify process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached an appropriate verify reference voltage.

[0083] In step 576, it is determined whether all memory cells have reached their target threshold voltage (pass). If so, the programming process is complete and successful, as all selected memory cells are programmed and verified to their target state. In step 578, a "pass" (or success) status is reported. If in 576 it is determined that not all memory cells have reached their target threshold voltage (fail), the programming process continues to step 580.

[0084] In step 580, the system counts the number of memory cells that have not reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have failed the verify process so far. This count can be performed by the state machine 312, the controller 120, or other logic. In one implementation, each of the sense blocks will store the status (pass / fail) of its respective memory cells. In one embodiment, there is one total count that reflects the total number of currently being programmed memory cells that failed the last verify step. In another embodiment, there is a separate count for each data state.

[0085] In step 582, it is determined whether the count from step 580 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during a read process of the memory cell page. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and report a "pass" status in step 578. In this case, enough memory cells are programmed correctly so that the fewer remaining memory cells that have not been fully programmed can be corrected using ECC during a read process. In some embodiments, step 580 counts the number of failed cells for each sector, each target data state, or other unit, and those counts are compared individually or collectively to one or more thresholds in step 582.

[0086] In one embodiment, the predetermined limit can be less than the total number of bits that can be corrected by ECC during a read process to allow for future errors. When less than all memory cells of a page, or counts for only one data state (or less than all states) are compared, then the predetermined limit can be a fraction (in proportion or not in proportion) of the number of bits that can be corrected by ECC during a read process of the memory cell page. In some embodiments, no predetermined limit is used. Instead, the limit varies based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0087] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 584 and the program counter PC is checked against a program limit (PL). Examples of program limits include 6, 20, and 30; however, other values can be used. If the program counter PC is not less than the program limit PL, the programming process is considered to have failed and a fail (FAIL) status is reported in step 588. If the program counter PC is less than the program limit PL, the process continues at step 586 during which the program counter PC is incremented by one and the program voltage Vpgm is stepped to the next value. For example, the next pulse will have a value that is a certain step size (e.g., 0.1 to 0.8 volts) greater than the previous pulse. After step 586, the process loops back to step 572 and another programming pulse is applied to the selected word line, performing another iteration of the programming process (steps 572-586). Figure 7

[0088] ​Because errors can occur when programming or reading, and errors can occur when storing data (e.g., due to electronic drift, data retention problems, or other phenomena), error correction is used when programming data. Memory systems often use error correction codes (ECC) to protect data from corruption. Numerous ECC decoding schemes are well known in the art. These conventional error correction codes are particularly useful in large scale memories including flash (and other non-volatile) memories because this decoding scheme can have a substantial impact on manufacturing yield and device reliability, enabling devices with a few unprogrammable or defective cells to be usable. Of course, there is a tradeoff between saving yield and the cost of providing extra memory cells to store code bits (i.e., the code "rate"). Thus, some ECC codes are more suitable for flash memory devices than others. In general, ECC codes used for flash memory devices tend to have a higher code rate (i.e., a lower ratio of code bits to data bits) than codes used in data communication applications, which can have a code rate as low as 1 / 2. Examples of well known ECC codes commonly used in conjunction with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, etc. Sometimes, the error correction codes used in conjunction with flash memory storage are "systematic" in that the data portion of the final code word is not changed from the actual data being encoded, and code or parity bits are appended to the data bits to form the complete code word.

[0089] The particular parameters of a given error correction code include the type of code, the size of the actual data block from which the code word is derived, and the overall length of the code word after encoding. For example, a typical BCH code applied to a sector of 512 bytes (4096 bits) of data can correct up to four error bits if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512 byte data sector using about 72 ECC bits. In the context of flash memory, error correction decoding significantly improves manufacturing yield as well as the reliability of flash memory over time.

[0090] In some embodiments, the controller 120 receives host data (also referred to as user data or data from an entity outside the memory system) to be stored in the non-volatile memory structure 326, also referred to as information bits. The information bits are represented by the matrix i = [1 0] (note that two bits are used for example purposes only, and many embodiments have codewords longer than two bits). An error correction decoding process (e.g., any of the processes mentioned above or below) is implemented by the ECC engine 158 of the controller 120, in which parity bits are added to the information bits to provide data represented by the matrix or codeword v = [1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used that map input data to output data in a more complex manner. For example, low density parity check (LDPC) codes, also known as Gallager codes, can be used. More details on LDPC codes can be found in R. G. Gallager, “Low-Density Parity-Check Codes,” IRE Transactions on Information Theory, vol. 8, pp. 21-28, January 1962, and D. MacKay, Information Theory, Inference, and Learning Algorithms, Cambridge University Press, 2003, Chapter 47. In practice, such LDPC codes are typically applied (e.g., by the ECC engine 158) to multiple pages of data encoded across multiple storage elements, but they need not be applied across multiple pages. The data bits can be mapped to a logical page and stored in the memory structure 326 by programming one or more memory cells to one or more programming states corresponding to v.

[0091] In one embodiment, programming is used to raise the threshold voltage of a memory cell to one of the programmed data states S1-S7. Erasing is used to lower the threshold voltage of a memory cell to the erased data state S0.

[0092] One technique to erase a memory cell in some memory devices is to bias the P-well (or other type of) substrate to a high voltage to charge the NAND channel. An erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell while the NAND channel is at a high voltage to erase the non-volatile storage element (memory cell). This is referred to herein as P-well erase.

[0093] Another method to erase a memory cell is to generate a gate-induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while the NAND string channel potential is held to erase the memory cell. This is referred to herein as GIDL erase. Both P-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of a memory cell.

[0094] In one embodiment, GIDL current is generated by inducing a drain-gate voltage at a select transistor (e.g., SGD and / or SGS). The transistor drain-gate voltage at which GIDL current is generated is referred to herein as a GIDL voltage. GIDL current can be generated when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. GIDL current is carrier generation, i.e., the result of electron-hole pair generation due to band-to-band tunneling and / or trap-assisted generation. In one embodiment, GIDL current can cause one type of carrier (e.g., holes) to predominantly move into the NAND channel, thereby increasing the potential of the channel. The other type of carrier (e.g., electrons) is extracted from the channel by an electric field in the direction of the bit line or in the direction of the source line. During erase, the holes can tunnel from the channel to the charge storage region of the memory cell and recombine with electrons there to lower the threshold voltage of the memory cell.

[0095] GIDL current can be generated at either end of a NAND string. A first GIDL voltage can be formed between two terminals of a select transistor (e.g., a drain-side select transistor) connected to a bit line to generate a first GIDL current. A second GIDL voltage can be formed between two terminals of a select transistor (e.g., a source-side select transistor) connected to a source line to generate a second GIDL current. Erase based on GIDL current at only one end of a NAND string is referred to as one-sided GIDL erase. Erase based on GIDL current at both ends of a NAND string is referred to as two-sided GIDL erase.

[0096] Figure 7A is a block diagram illustrating details of one embodiment of circuitry for applying voltages to the memory structure 326. Two blocks 700, 720 of memory cells are depicted. Figure 7A The circuitry of applies voltages to word lines and select lines. In one embodiment, the state machine 312 provides control signals to the circuitry. For example, the state machine 312 can issue control signals to one or more of the CONTROL 780, the HV GEN 772, the PB DRV 774, the CMD REG 776, and the I / O buffer 778. In one embodiment, the state machine 312 issues control signals to the CONTROL 780, which in turn controls other elements, such as the HV GEN 772 and the PB DRV 774.

[0097] In an embodiment, the HV GEN 772 is connected to the word line driver 750 to control the magnitude and timing of the voltage. In one embodiment, the HV GEN 772 provides an erase voltage to the word line driver 750. The erase voltage can be applied to the select line SGD in one of the blocks 700, 720 through the SGG DRV 752. The erase voltage can be applied to the select line SGS in one of the blocks 700, 720 through the SGS DRV 762.

[0098] In one embodiment, the HV GEN 772 is connected to the PB DRV 774, which is connected to the page buffer 740 to control the page buffer 740. The page buffer 740 can include a sense block, such as SB1 in Figure 2 In one embodiment, the HV GEN 772 provides an erase voltage to the page buffer 740. The erase voltage can be applied to the bit line 742. In one embodiment, the HV GEN 772 provides a temperature dependent erase voltage to the source line (see Figure 3 、 4C and 4F; Figure 7A In one embodiment, the HV GEN 772 provides an erase voltage to the page buffer 740. The erase voltage can be applied to the bit line 742. In one embodiment, the HV GEN 772 provides a temperature dependent erase voltage to the source line (see

[0099] In one embodiment, the combination of voltages applied to the bit line and the SGD line is referred to as a GIDL erase voltage. Thus, the HV GEN 772 can provide a GIDL erase voltage to the drain side of the NAND string.

[0100] In one embodiment, the combination of voltages applied to the source line and the SGS line is referred to as a GIDL erase voltage. Thus, the HV GEN 772 can provide an erase voltage to the source side of the NAND string.

[0101] Leakage current can exist along the path between the HV GEN 772 and the bit line 742, the SGD line, the SGS line, and / or the source line. GIDL erase can depend on having sufficient GIDL current in the NAND string. Leakage current can impact the ability to have sufficient current in the NAND string. In some embodiments, the HV GEN 772 is controlled in a manner that adjusts the erase voltage (to the bit line 742, SGS, SGS, and / or the source line) so as to reduce or compensate for the leakage current. Thus, sufficient GIDL current flows in the NAND string so that the GIDL erase operation is effective. Further, the leakage current can be temperature dependent. In some embodiments, the HV GEN 772 is controlled in a manner that reduces or compensates for the temperature dependent leakage current during GIDL erase of the NAND string.

[0102] In one possible embodiment, each block of non-volatile storage elements (memory cells) is associated with a set of transfer transistors. For example, block 700 (which in this example is a selected block) (e.g., the block in which a program, erase, or sense operation is to occur) includes a drain-side select gate (SGD) connected to transfer transistor 704, a drain-side dummy word line (WLDD) connected to transfer transistor 706, a word line (WL95) connected to transfer transistor 708, intermediate word lines WL94 to WL1 (not shown) connected to respective transfer transistors (not shown), a word line (WL0) connected to transfer transistor 710, a source-side dummy word line (WLDS) connected to transfer transistor 712, and a source-side select gate (SGS) connected to transfer transistor 714. Other embodiments can include more dummy word lines (e.g., as depicted in Figure 4C

[0103] The control gates of each transfer transistor of block 700 are connected to a block decoder (BD) 702 via a common path 703. BD 702 receives voltages from a transfer transistor driver (TT DRV) 764 and control signals from an address register (ADD REG) 770. The control signals include an address. If the address matches the address of BD 702, BD 702 acts as a conductive switch that passes the voltages to the control gates of the associated transfer transistors via path 703. If the address does not match the address of BD 702, BD 702 acts as a non-conductive switch that does not pass the voltages to the control gates of the associated transfer transistors.

[0104] Each transfer transistor can be an n-channel MOSFET, for example, with a drain node on the left side and a source node on the right side. The drain node for each transfer transistor is connected to a respective voltage driver in a set of high voltage voltage drivers 750. Each driver can include an on-chip charge pump.

[0105] For example, transfer transistor 704 is connected to a drain select gate driver (SGD DRV) 752, transfer transistor 706 is connected to a dummy word line driver (WLDD DRV) 754, transfer transistor 708 is connected to a word line driver (WL47 DRV) 756,..., transfer transistor 710 is connected to a word line driver (WL0 DRV) 758, transfer transistor 712 is connected to a source-side dummy word line driver (WLDS DRV) 760, and transfer transistor 714 is connected to a source select gate driver (SGS DRV). Each voltage driver can be independently controlled to provide a desired output voltage.

[0106] ​A similar arrangement is used for the instance unselected block 720, which includes a transfer transistor 724 connected to the SGD and SGD DRV 752, a transfer transistor 726 connected to the WLDD and WLDD DRV 754, a transfer transistor 728 connected to the WL95,..., a transfer transistor 730 connected to the WL0 and WL0 DRV 758, a transfer transistor 732 connected to the WLDS and WLDS DRV 760, and a transfer transistor 734 connected to the SGS and SGS DRV 762.

[0107] SGD lines for the plane can be referred to herein as local SGD lines and global SGD lines. For example, the SGD line in block 700 can be referred to as local SGD line 757a. The SGD line in block 720 can also be referred to as local SGD line 757b. The line 755 connected to the SGD DRV 752 can be referred to herein as a global SGD line (e.g., SGDg). Each local SGD line 757 can be connected to the global SGD line 755 through a transfer transistor (e.g., 704, 724).

[0108] SGS lines for the plane can be referred to herein as local SGS lines and global SGS lines. For example, the SGS line in block 700 can be referred to as local SGS line 761a. The SGD line in block 720 can also be referred to as local SGD line 761b. The line 759 connected to the SGS DRV 762 can be referred to herein as a global SGS line (e.g., SGSg). Each local SGS line 761 can be connected to the global SGS line 759 through a transfer transistor (e.g., 714, 734).

[0109] The control gates of the transfer transistors of the unselected block 720 are connected to a respective block decoder (BD) 725 via a common path 723. The BD 725 is also connected to a TT DRV 764 to receive a voltage and to an address register 770 to receive a control signal that instructs the BD 725 to pass or not pass the voltage to the control gates of the associated transfer transistors via the path 723. The address register (ADD REG) 770 also communicates with the voltage drivers in the set of high voltage voltage drivers 750.

[0110] In response to the column decoder 132, a plurality of bit lines (BL) 742 extend across the selected block 700 and the unselected block 720 (and in some embodiments, across additional unselected blocks, not shown in the figure) and into a page buffer 740. The page buffer 740 stores data written to or read from the selected word line of the selected block.

[0111] During operation of the memory device, address register 770 provides a data load command to input-output buffer 778 and command register 776. Input-output buffer 778 provides the command to page buffer 740. Command register 776 provides the command to control 780, which instructs high voltage generator 772 to control voltage driver 750 at the appropriate level.

[0112] Generally, during programming, the driver of the selected word line provides a program level voltage, e.g., 12 to 26 V, and the unselected word lines receive a pass voltage, VPASS, e.g., 4 to 6 V. During sensing, the driver of the selected word line provides a read or verify level voltage (VCGR or VVERIFY, respectively) and the unselected word lines receive a read pass voltage, VREAD-PASS. Control 780 also instructs page buffer driver (PB DRV) 774 to control page buffer 740. Address register 770 also communicates with column decoder 132.

[0113] Figure 8 Movement of holes and electrons in a NAND string during bilateral GIDL erase is depicted. Example NAND string 800 includes a channel 891 connected to a bit line (BL) and a source line (SL). Tunnel dielectric layer (TNL) 892, charge trapping layer (CTL) 893, and blocking oxide layer (BOX) 898 are layers that extend around the memory hole of the string (see, e.g., Figure 4E ). Different regions of the channel layer represent channel regions associated with respective memory elements or select gate transistors. These channel regions are at the same height and stack level as the control gates of the memory elements or select gate transistors in a stacked memory device.

[0114] NAND string 800 includes SGD transistor 801 having control gate 806 and channel region 807. Erase voltage V_GIDL1 is applied to control gate 806 of SGD transistor 801. NAND string 800 also includes memory elements 810, 815, 820, and 825, respectively; control gates 811, 816, 821, and 826; CTL regions 813, 818, 823, and 828; and channel regions 812, 817, 822, and 827, respectively.

[0115] NAND string 800 includes SGS transistor 802 having control gate 856 and channel region 857. Erase voltage V_GIDL2 is applied to control gate 856 of SGS transistor 802. NAND string 800 also includes memory elements 860, 865, 870, and 875, respectively; control gates 861, 866, 871, and 876; CTL regions 863, 868, 873, and 878; and channel regions 862, 867, 872, and 877, respectively.

[0116] An erase voltage, VERA, is applied to both the bit line (BL) and the source line (SL). The difference between VERA and V_GIDL1 can be referred to as AGIDL1. The difference between VERA and V_GIDL2 can be referred to as AGIDL2. Note that AGIDL1 and AGIDL2 are examples of GIDL erase voltages. Herein, the term "erase voltage" can apply to VERA, V_GIDL1, and / or V_GIDL2. Example magnitudes of VERA are 21 V or 24 V, and example magnitudes of V_GIDL1 and V_GIDL2 are 12 V. However, it is not required that V_GIDL1 have the same magnitude as V_GIDL2. In some embodiments, AGIDL1 and AGIDL2 are temperature dependent. The temperature dependence of AGIDL1 can be achieved by temperature dependence of VERA and / or V_GIDL1. The temperature dependence of AGIDL2 can be achieved by temperature dependence of VERA and / or V_GIDL2.

[0117] Representative holes are depicted in the channel layer as circles with "+" signs, and representative electrons are depicted in the channel layer as circles with "-" signs. Electron-hole pairs are generated by the GIDL process. Initially, during the erase operation, electron-hole pairs are generated at the SGD and SGS transistors. The holes move away from the drive end into the channel, thereby charging the channel to a positive potential. Due to the positive potential here, the electrons generated at the SGD transistor 801 move toward the bit line (BL). Due to the positive potential here, the electrons generated at the SGS transistor 802 move toward the source line (SL). Subsequently, during the erase period of each storage element, additional holes are generated by GIDL at a virtual junction formed in the channel at the edge of the control gate of the storage element. However, some of the holes also move away from the channel as they tunnel to the CTL region.

[0118] Electrons are also generated by the GIDL process. Initially, during the erase operation, electrons are generated at the SGD and SGS transistors and move toward the drive end. Subsequently, during the erase period of each storage element, additional electrons are generated by GIDL at a virtual junction formed in the channel at the edge of the control gate of the storage element.

[0119] At one end of the NAND string (e.g., the drain side), example electrons 840 and 841 move toward the bit line. Electron 840 is generated at the SGD transistor and electron 841 is generated at the junction of storage element 815 in channel region 817. Also, in the drain side, an example hole including hole 842 moves away from the bit line, as indicated by the arrow. Hole 842 is generated at the junction of storage element 815 in channel region 817 and can tunnel into CTL region 818, as indicated by arrow 843.

[0120] At the other end of the NAND string (e.g., the source side), example electrons 845 and 849 move toward the source line. Electron 845 is generated at the SGS transistor and electron 849 is generated at the junction of the storage element 865 in the channel region 867. Also, in the source side, an example hole containing hole 847 opens from the bit line source line, as indicated by the arrow. Hole 847 is generated at the junction of the storage element 865 in the channel region 867 and can tunnel into the CTL region 868, as indicated by arrow 848.

[0121] The techniques described above for erasing can be used with different erase methods. Two examples of erase methods include: (1) applying erase to all non-volatile memory cells of an erase unit at the same time (“full erase”), and (2) applying erase to a subset of groups of non-volatile memory cells of an erase unit individually (“individual erase groups”). Other erase methods can also be used. Each of full erase and individual erase groups will be discussed in more detail below.

[0122] Figure 9 Portions of a NAND string 900 undergoing erase (e.g., using P-well erase or GIDL erase) are depicted. Figure 9 A channel 902 (which can be an example of channel 471 or channel 891), a subset of word lines (WL44, WL45, WL46, WL47, WL48, WL49, WL50, WL51), and voltages applied to the word lines during full erase are shown. An erase voltage VERA is applied to the bit line and the source line. As Figure 9 As depicted in FIG. 5B, all of the word lines in the block of memory cells are receiving an erase enable voltage WLer_en. In one embodiment, WLer_en = 0v or a value between 0 and 0.5v. However, other low voltages can also be used. In some embodiments, WLer_en has a magnitude of voltage as low as possible (theoretically negative, requiring only additional circuitry to supply a negative voltage source). When the erase enable voltage WLer_en is applied to the word lines and the channel 902 is at a high voltage, the memory cells connected to the word lines receiving the erase enable voltage WLer_en will undergo erase. With full erase, all of the word lines of a block (or other erase unit or other grouping of word lines) will receive the erase enable voltage WLer_en, such that all of the memory cells of all of the NAND strings receiving the erase voltage VERA will undergo erase. In some embodiments, all of the word lines receive the same exact voltage, while in other embodiments, the erase enable voltage can vary by word line. It should be noted that while the above refers to a block of memory cells as the erase unit, other erase units (e.g., partial blocks, other groupings of word lines, or other groupings of memory cells) can also be used.

[0123] Figure 10A and 10B also depicts a portion of the NAND string 900 that has undergone erasure (e.g., using P-well erasure or GIDL erasure). However, in Figure 10A and 10B the erasure method is to erase groups individually. The memory cells are divided into groups of non-volatile memory cells. In one example embodiment, the memory cells are divided into two groups: (1) memory cells connected to even-numbered word lines and memory cells connected to odd-numbered word lines. Other groupings can also be used. Alternatively, the memory cells can be divided into more than two groups. For example, the memory cells are divided into four groups such that the memory cells connected to each four word lines are in the same group. Figure 10A and 10B depict an embodiment in which the memory cells are divided into memory cells connected to even-numbered word lines and memory cells connected to odd-numbered word lines. In Figure 10A and 10B 's embodiment, the memory cells connected to even-numbered word lines are erased together, the memory cells connected to even-numbered word lines are erased separately from the memory cells connected to odd-numbered word lines, the memory cells connected to odd-numbered word lines are erased together, and the memory cells connected to odd-numbered word lines are erased separately from the memory cells connected to even-numbered word lines. For example, the first memory cell connected to an even-numbered word line is erased while preventing the erasure of the memory cells connected to odd-numbered word lines. This is depicted in Figure 10A where the even-numbered word lines receive an erase enable voltage WLer_en and the odd-numbered word lines receive an erase inhibit voltage WLer_inh. In one embodiment, WLer_inh = 10v. However, other high voltages can also be used. In some embodiments, WLer_en << WLer_inh. When the erase inhibit voltage WLer_inh is applied to a word line and the channel 902 is at a high voltage, the memory cells connected to the word line receiving the erase inhibit voltage WLer_inh will not undergo erasure. In some embodiments, all word lines receiving WLer_inh will receive the same exact voltage, while in other embodiments, the erase inhibit voltage can vary by word line. After the memory cells connected to the even-numbered word lines have undergone erasure, the memory cells connected to the odd-numbered word lines will undergo erasure while preventing the erasure of the memory cells connected to the even-numbered word lines. This is depicted in Figure 10B where the odd-numbered word lines receive an erase enable voltage WLer_en and the even-numbered word lines receive an erase inhibit voltage WLer_inh. It should be noted that the order of erasure can be even-odd or odd-even. It should be noted that Figure 10A and 10B show the application of an erase voltage VERA to the bit line and the source line.

[0124] Figure 11is a block diagram describing the physics of the erase process of a NAND string 900 using the full erase method. In response to applying WLer_en on all word lines, holes are injected into the charge trapping layer 893. Some holes are further injected into the dielectric / oxide between the word lines and into the dielectric / oxide between the word lines. A possible consequence of having holes injected into the dielectric / oxide between the word lines is that the memory cells can experience data retention issues over a long period of time. That is, lateral hole movement can cause the threshold voltage of the memory cells to change, which can potentially cause errors. It has been found that holes are injected into the dielectric / oxide between the word lines due to the voltage difference between the channel and the adjacent word lines.

[0125] Figure 12 is a block diagram describing the physics of the erase process of a NAND string 900 using the separate erase group method. In Figure 12 on the left side, only the memory cells connected to the even numbered word lines are receiving WLer_en (e.g., n is even). On Figure 12 on the right side, only the memory cells connected to the odd numbered word lines are receiving WLer_en. It should be noted that for the purposes of this document, even word lines are even numbered word lines (e.g., WL0, WL2, WL4, etc.) and odd word lines are odd numbered word lines (e.g., WL1, WL3, etc.) because the adjacent word lines do not receive the erase enable voltage, hole injection into the space between the word lines is prevented. Thus, using the separate erase group method reduces the data retention issues described above. It has also been found that using the separate erase group method produces tighter and more accurate erase threshold voltage distributions (e.g., see S0 of Figure 5 ), which can improve programming accuracy. However, because the odd word lines are erased separately from the even word lines, more time is required to erase using the separate erase group method than using the full erase method.

[0126] It has also been found that the separate erase group method requires a higher erase voltage VERA than using the full erase method. Using a higher erase voltage VERA can degrade the tunnel oxide over time, which will reduce the endurance of the memory.

[0127] In view of the above findings, it is inferred that newer memory will benefit from using the separate erase group method. However, as the memory gets older and is used more (e.g., more program / erase cycles), the advantage diminishes and at some point it is better to use the full erase method. Thus, it is proposed to take advantage of the data retention benefits of the separate erase group method when the memory is new. However, once additional erase is required due to the memory having experienced multiple program / erase cycles (e.g., higher VERA), switch to full erase to avoid stress on the tunnel oxide and reduce the additional time required for erase. This strategy is depicted in Figure 13 .Figure 13 is a flowchart that describes one embodiment of a process for erasing non-volatile memory. In step 1302, the memory system performs a first erase method for a population of memory cells. Step 1302 is performed when the memory is new and has experienced few program / erase cycles (i.e., beginning of life or BOL). The population of memory cells can be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second erase method for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program / erase cycles (i.e., middle of life [MOL] or end of life [EOL]). The first erase method is different than the second erase method.

[0128] In one embodiment, the erase process includes applying VERA to the bit lines and source lines as a set of voltage pulses that increase in magnitude at each pulse. Each time a VERA pulse is applied for a full erase and each time a pair of equal magnitude VERA pulses are applied for a separate erase group, this is referred to as an iteration of the erase process. In one embodiment, the erase process includes performing steps 1302 and 1304, and the switch from step 1302 to 1304 is determined based on the number of iterations, the magnitude of VERA, or the number of program / erase cycles. In one embodiment, at BOL, the memory system performs the erase process by performing only step 1302, at EOL, the memory system performs the erase process by performing only step 1304, and between BOL and EOL (e.g., MOL), the memory system performs the erase process by performing steps 1302 and 1304, where the transition is based on the number of iterations required to complete the erase, the magnitude of VERA required to complete the erase, or the number of program / erase cycles.

[0129] Figure 14 is a flowchart that describes one embodiment of a process for erasing non-volatile memory. Figure 14 The process of Figure 13 is an example embodiment of the process of In step 1402 (an example implementation of step 1302), the memory system applies erase to a subset of the population of non-volatile memory cells (separate erase group) individually. For example, erase is performed for memory cells connected to even digit lines separate from memory cells connected to odd digit lines. In step 1404 (an example implementation of step 1304), the memory system then applies erase to all of the non-volatile memory cells in the population of non-volatile memory cells (full erase) simultaneously. For example, erase is performed for all memory cells of a block, or memory cells connected to all word lines of a block or other grouping.

[0130] In one embodiment, the erase process includes performing steps 1402 and 1404, and the switching from step 1402 to 1404 is determined based on the number of iterations, the magnitude of VERA, or the number of program / erase cycles. In one embodiment, at BOL, the memory system performs the erase process by performing only step 1402, at EOL, the memory system performs the erase process by performing only step 1404, and at MOL, the memory system performs the erase process by performing steps 1402 and 1404, where the transition is based on the number of iterations required to complete the erase, the magnitude of VERA required to complete the erase, or the number of program / erase cycles. In another embodiment, both steps 1402 and 1404 can be performed at BOL, MOL, and EOL, where the transition between steps 1402 and 1404 changes from BOL to EOL.

[0131] Figure 15 is a block diagram of a portion of a non-volatile memory system that can be used to perform the processes of Figure 13 and 14 . Figure 15 Control circuitry 1502 is shown connected to a memory structure 1504, which includes a plurality of non-volatile memory cells. For example, memory structure 1504 includes a block 1506 (Block X) that includes a plurality of word lines connected to a number of non-volatile memory cells, as described above. The memory cells can be grouped into clusters, such as non-volatile memory cells connected to even word lines and non-volatile memory cells connected to odd word lines. Other groupings can also be used. Control circuitry 1502 performs the processes of Figure 13 and / or 14 to erase the non-volatile memory cells in block 1506. Control circuitry 1502 can include control circuitry system 310, read / write circuits 328, and decoders 324 / 332 of Figure 2 . In other embodiments, other circuitry that supports and operates on memory structure 326 can be referred to as control circuitry. For example, in some embodiments, a controller can operate as or can be part of the control circuitry. In some embodiments, a controller in conjunction with control circuitry system 310, read / write circuits 328, and decoders 324 / 332 includes one embodiment of the control circuitry. In another embodiment, state machine 312 includes the control circuitry. In another embodiment, a host can provide the control circuitry. The control circuitry can also be a microprocessor, microcontroller, or other type of processor.

[0132] Figure 16is a bar graph depicting erase voltage versus final magnitude of program / erase cycles for multiple types of erase processes. Three bars 1602 represent performance at the beginning of the lifetime of the memory. Three bars 1604 represent performance at the middle of the lifetime of the memory. Three bars 1606 represent performance at the end of the lifetime of the memory. The y-axis is the magnitude of VERA at the end of a successful erase process. Bars 1602a, 1604a, and 1606a represent using only the full erase method. Bars 1602b, 1604b, and 1606b represent using only the separate erase group method. As can be seen, bar 1602b is higher than bar 1602a (e.g., about 0.6v higher), which indicates that the separate erase group method requires a higher VERA to successfully complete erasing memory cells. Bar 1604b is higher than bar 1602b and bar 1606b is higher than bar 1604b, which indicates that over time (and after using the memory), the separate erase group method requires a higher VERA to successfully complete erasing memory cells.

[0133] Bars 1602c, 1604c, and 1606c represent one example embodiment of the proposed technique for erasing non-volatile memory cells. At the beginning of the lifetime (e.g., BOL 1602), only the separate erase group method is used. At a similar middle (e.g., MOL 1604) and at the end of the lifetime (e.g., EOL 1606), both the separate erase group method and the full erase method are used. In an alternative embodiment: at the beginning of the lifetime (e.g., BOL 1602), only the separate erase group method is used; at the middle of the lifetime (e.g., MOL 1604), both the separate erase group method and the full erase method are used; and at the end of the lifetime (e.g., EOL 1606), only the full erase method is used. In another alternative, both the separate erase group method and the full erase method are used at BOL, MOL, and EOL.

[0134] Figure 17 is a flowchart depicting one embodiment of a process for erasing non-volatile memory. Figure 17 The process of Figure 13 and / or Figure 14 is an example implementation of the process of Figure 17The process is performed by any one of the above control circuits. In step 1702, the control circuit sets the initial magnitude value of VERA and sets the number of iteration cycles i = 1. As discussed above, VERA is the erase voltage applied to the bit lines and / or source lines. In one embodiment, the erase process includes applying VERA to the bit lines and / or source lines as a set of pulses that increase in magnitude with each pulse. Step 1702 sets the voltage magnitude of the first VERA voltage pulse. Whenever a VERA pulse is applied for full erase and whenever a pair of VERA pulses of equal magnitude are applied for individual erase groups, this is referred to as an iteration of the erase process. The first iteration is i = 0. In step 1704, the erase mode is set to the individual erase group method. The control circuit can have registers, flags, or other settings to indicate which type of erase method is currently being used. For example, parameter 318 (see Figure 2 ) can store an indication of which type of erase method is currently being used. In step 1706, since the erase mode is set to the individual erase group method, two VERA pulses of the same magnitude are applied to the bit lines and / or source lines (or P-well). During the first VERA pulse, the even-numbered bit lines receive WLer_en and the odd-numbered bit lines receive WLer_inh. During the second VERA pulse, the odd-numbered bit lines receive WLer_en and the even-numbered bit lines receive WLer_inh. In step 1708, erase verification is performed by testing whether all memory cells (e.g., blocks or other groupings) that have been erased have a threshold voltage within the threshold voltage distribution for the erased data state (e.g., Figure 5 's S0). For example, all word lines can receive a common voltage (or just the odd-numbered word lines or just the even-numbered word lines), and the control circuit will test the magnitude of the current passing through the channels of the NAND strings. One particular method for verifying erase is not required for the proposed technology, and any suitable verification operation is acceptable.

[0135] If the verification process indicates that all memory cells of all NAND strings have successfully passed the erase verification (step 17 **10**), then in step 17 **12**, a "pass" status is reported and the erase process ends successfully. If not all memory cells of all NAND strings have successfully passed the erase verification, then in step 17 **14**, it is determined whether the number of iterations of the erase process has reached the maximum number of iterations (i < iMax). If the number of iterations (i) of the erase process has reached the maximum number of iterations (iMax), then the erase has failed (17 **16**). In one embodiment, iMax = 6. In one embodiment, the value of iMax is stored in parameter 318 (see Figure 2). If the number of iterations of the erase process has not reached the maximum number of iterations, the erase process continues at step 1718, during which the erase voltage signal VERA is stepped to the next value. In one embodiment, for each iteration of the erase process, VERA is increased by a certain step size (e.g., 0.4v). Additionally, the number of iteration cycles i is increased by 1. In step 1720, it is determined whether the number of iteration cycles i is greater than a transition threshold (Trans_i). In one embodiment, Trans_i = 3, which means that after the third iteration (before the fourth iteration), the transition is made to performing the full erase method by executing the separate erase group method, Figure 17 the erase process begins. Thus, if i is not greater than the transition threshold Trans_i, the mode does not change and the process loops back to step 1706 such that another set of VERA pulses is applied. If i is greater than the transition threshold (Trans_i), the mode does change to full erase (step 1722) and the process loops back to step 1706 such that a VERA pulse is applied. When step 1706 is executed and the erase mode is set to full erase, one VERA pulse is applied (at a value that is the step size higher than the previous VERA pulse) and all word lines receive WLer_en. In one embodiment, the transition threshold (Trans_i) is stored in parameter 318 (see Figure 2 ).

[0136] It is noted that steps 1706-1718 represent iterations of the erase process. As can be seen, Figure 17 the erase process can include performing multiple iterations (e.g., multiple executions of steps 1706-1718).

[0137] Figure 17 represents an embodiment in which the transition from the first erase method to the second erase method is based on the number of iterations (i). In alternative embodiments, the transition from the first erase method to the second erase method is based on the value of VERA or the program / erase cycle count. In Figure 17 In another embodiment of the erase process, the erase process begins by performing full erase and transitions to the separate erase group method.

[0138] In another embodiment, if the value of VERA reaches a maximum value, the control circuit stops stepping (incrementing) VERA for future iterations of the erase process.

[0139] Figure 17 The process of FIG. 17 is an example of performing multiple iterations of an erase process to erase a group of non-volatile memory cells (e.g., a block), where each iteration of the erase process includes applying an erase voltage as one or more voltage pulses to the group of non-volatile memory cells. During a first iteration of one embodiment of the erase process, a first erase method (e.g., separate erase group) is performed. InFigure 17 At some point during the erasure process, after the metric has exceeded a threshold (e.g., i>Trans_i), for one or more additional iterations of the erasure process, the erasure process switches from executing the first erasure method (e.g., step 1722) to executing the second erasure method (e.g., full erasure).

[0140] Figure 18 This is a flowchart illustrating one embodiment of a process for erasing non-volatile memory. Figure 18 The process is Figure 13 and / or Figure 14 An example implementation of the process. In one embodiment, Figure 18 The process is executed by any of the control circuits described above. In step 1804, the control circuit sets the initial value of VERA and sets the number of iteration loops i = 1. In step 1806, the erase mode is set to the individual erase group method. In step 1808, the control circuit sets the unselected word line voltage WLunsel_era. As discussed above, during the individual erase group method, some word lines are selected for erase enable and some word lines are not selected. Selected word lines receive the erase enable voltage (e.g., WLer_en). Unselected word lines receive the unselected word line voltage WLunsel_era. For example, in an embodiment with even / odd erase, when even-numbered lines receive the erase enable voltage WLer_en, odd-numbered lines receive WLunsel_era, and when odd-numbered lines receive the erase enable voltage WLer_en, even-numbered lines receive WLunsel_era. In one embodiment, step 1808 includes setting the unselected word line voltage WLunsel_era = WLer_inh (e.g., 10V).

[0141] In step 1810, since the erase mode is set to the individual erase group method, two VERA pulses of the same magnitude are applied to the bit lines and / or source lines (or P-well). During the first VERA pulse, the even bit lines receive WLer_en and the odd bit lines receive WLunsel_era. During the second VERA pulse, the odd bit lines receive WLer_en and the even bit lines receive WLunsel_era. In step 1812, an erase verification is performed. If the verification process indicates that all memory cells of all NAND strings have successfully passed the erase verification (step 1814), then in step 1816, a "pass" status is reported and the erase process ends successfully. If not all memory cells of all NAND strings have successfully passed the erase verification, then in step 1818, it is determined whether the number of iterations of the erase process has reached the maximum number of iterations (i < iMax). If the number of iterations of the erase process has reached the maximum number of iterations, then the erase has failed (1820). If the number of iterations of the erase process has not reached the maximum number of iterations, then the erase process continues at step 1822, during which the erase voltage signal VERA steps to the next magnitude. Additionally, the number i of the iteration loop is incremented by 1. Figure 18 Steps 1812, 1814, 1816, 1818, 1820, and 1822 are similar to Figure 17 steps 1708, 1710, 1712, 1714, 1716, and 1718.

[0142] In step 1824, for the next iteration, the unselected word line voltage WLunsel_era is adjusted / changed by Δ. In one embodiment, Δ has a negative value, so WLunsel_era decreases at each iteration, such that WLunsel_era approaches WLer_en over time. After step 1824, Figure 18 the erase process of Figure 18 loops back to step 1810 to perform another iteration. It should be noted that steps 1810 to 1822 represent an iteration of the erase process. As can be seen, Figure 18 the erase process can include performing multiple iterations (e.g., performing steps 1810 to 1822 multiple times). In one embodiment, the value of Δ is stored in parameter 318 (see Figure 2 ).

[0143] In Figure 18 another embodiment of

[0144] In Figure 18In some embodiments, the control circuitry is configured to apply erasure individually to a subset of the non-volatile memory cell group and then... Figure 18 During the process, a certain dose of erase signal (e.g., VERA pulse or other waveform) is applied to simultaneously erase all non-volatile memory cells in a group of non-volatile memory cells, and the erase process is performed for the group of non-volatile memory cells. During the first dose of erase signal, a first group of word lines (e.g., even-numbered lines) is selected for erasure, and during the second dose of erase signal, a second group of word lines (e.g., odd-numbered lines) is selected for erasure. During the first dose of erase signal, in step 1810, a first erase enable voltage (e.g., WLer_en) is applied to the first group of word lines, and a first unselected word line voltage (e.g., WLunsel_era) is applied to the second group of word lines. The first unselected word line voltage applied to the second group of word lines for the first dose of erase voltage is changed such that during the first dose of erase voltage, the first unselected word line voltage approaches the first erase enable voltage over time (step 1824). During the erase signal of the second dose, a second erase enable voltage (e.g., WLer_en) is applied to the second word line, and a second unselected word line voltage (e.g., WLunsel_era) is applied to the first word line (step 1810). The second unselected word line voltage applied to the first word line for the erase voltage of the second dose is changed such that the second unselected word line voltage approaches the erase enable voltage over time during the erase voltage of the second dose (step 1824).

[0145] Figure 18 The process involves performing multiple iterations of an erase process to erase instances of a group of non-volatile memory cells (e.g., a block), wherein each iteration of the erase process includes applying an erase voltage as one or more voltage pulses to the group of non-volatile memory cells. During the first iteration of one embodiment of the erase process, a first erase method (e.g., erasing the group individually) is performed. Figure 18 At some point during some embodiments of the erase process, the unselected word line voltage (e.g., WLunsel_era) decreases to the point at which the erase process switches from performing a first erase method to performing a second erase method (e.g., full erase) for one or more additional iterations of the erase process.

[0146] Figure 19 This is a flowchart illustrating one embodiment of a process for erasing non-volatile memory. Figure 19 The process is Figure 13 and / or Figure 14 An example implementation of the process. In one embodiment, Figure 19The process of FIG. 19 is performed by any of the control circuits described above. In step 1902, the control circuit sets the initial magnitude of VERA and sets the number of iterations i = 1 of the iterative loop. In step 1904, the erase mode is set to the individual erase group method. In step 1906, the control circuit sets the unselected word line voltage WLunsel_era based on the number of program / erase cycles performed for the population of memory cells being erased. In one embodiment, the number of program / erase cycles is incremented each time the erase process is performed. The number of program / erase cycles can be maintained at any level of granularity, including at the block level, sub-block level, word line level, die level, plane level, page level, etc. Figure 19 Embodiments of FIG. 19 have an unselected word line voltage that approaches the erase enable voltage over time across multiple erase processes and over the lifetime of the memory. Figure 19 Steps 1908-1920 of FIG. 19 are the same as steps 1810-1822 of FIG. 18. After step 1920, Figure 18 Steps 1908-1920 of FIG. 19 are the same as steps 1810-1822 of FIG. 18. After step 1920, Figure 19 The process of FIG. 19 loops back to step 1908 to perform another iteration of the erase process. Note that Figure 19 Steps 1908-1920 of FIG. 19 represent an iteration of the erase process.

[0147] A system has been proposed to improve the erase process by utilizing multiple (e.g., two or more) erase methods. The first erase method is relied on more at the beginning of the lifetime of the memory system. The second erase method is relied on more as the memory system is used and the memory system is subjected to many program / erase cycles.

[0148] One embodiment includes a non-volatile memory system comprising a group of non-volatile memory cells and a control circuit connected to the group of non-volatile memory cells. The control circuit is configured to perform an erase process for the group of non-volatile memory cells by individually applying an erase to a subset of the group of non-volatile memory cells and then simultaneously applying an erase to all of the non-volatile memory cells in the group of non-volatile memory cells.

[0149] One embodiment includes a method comprising: performing multiple iterations of an erase process to erase a group of non-volatile memory cells, each iteration of the erase process including applying an erase voltage as one or more voltage pulses to the group of non-volatile memory cells, the first iteration of the erase process including performing a first erase method while applying the erase voltage to the group of non-volatile memory cells; and after a metric has exceeded a threshold value, for one or more additional iterations of the erase process, switching from performing the first erase method to performing a second erase method.

[0150] One embodiment includes a method of erasing non-volatile memory, comprising: erasing a group of non-volatile memory cells by performing a first erase method prior to the group of non-volatile memory cells experiencing a number of program / erase cycles; and erasing the group of non-volatile memory cells by performing a second erase method after the group of non-volatile memory cells experiences the number of program / erase cycles.

[0151] One embodiment includes a non-volatile memory system comprising a group of non-volatile memory cells and control circuitry connected to the group of non-volatile memory cells. The control circuitry is configured to erase the group of non-volatile memory cells by performing iterations of an erase process. The control circuitry is configured to, during each iteration, apply a first selected erase enable voltage to a first set of word lines while applying a first unselected erase voltage to a second set of word lines, and subsequently apply a second selected erase enable voltage to the second set of word lines while applying a second unselected erase voltage to the first set of word lines. The control circuitry is configured to change the first unselected erase voltage and the second unselected erase voltage over time while performing the iterations of the erase process such that the first unselected erase voltage approaches the first selected erase enable voltage and the second unselected erase voltage approaches the second selected erase enable voltage.

[0152] For the purposes of this document, a reference to an "embodiment," "one embodiment,” “some embodiments” or “another embodiment” can be a description of different embodiments or of the same embodiment.

[0153] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element can be directly connected to the other element or connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected such that they can exchange electronic signals.

[0154] For the purposes of this document, the term “based on” can be understood as “based at least in part on.”

[0155] For the purposes of this document, the use of the ordinal adjectives “first,” “second,” and “third,” etc., are to label different objects for identification only and are not to be construed as indicating a crucial distinction between objects.

[0156] For the purposes of this document, the term “set” of objects can mean a “collection” of one or more of the objects.

[0157] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best illustrate the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. A non-volatile memory system, comprising: Non-volatile memory cell group; as well as A control circuit connected to the group of non-volatile memory cells is configured to perform an erase process for the group of non-volatile memory cells by performing an erase operation individually in time on each subset of subsets of the group of non-volatile memory cells and simultaneously performing an erase operation on all non-volatile memory cells in the group of non-volatile memory cells after a metric has exceeded a threshold.

2. The non-volatile memory system according to claim 1, further comprising: A set of word lines connected to the group of non-volatile memory cells and the control circuitry, the control circuitry being configured to perform an erase operation individually in time on each subset of the group of non-volatile memory cells by: applying a first erase enable voltage to a first subset of the non-volatile memory cells connected to the first subset of the word lines, while simultaneously applying a first erase block voltage to a second subset of the non-volatile memory cells connected to a second subset of the word lines; then applying a second erase enable voltage to the second subset of the non-volatile memory cells connected to the second subset of the word lines, while simultaneously applying a second erase block voltage to the first subset of the non-volatile memory cells connected to the first subset of the word lines.

3. The non-volatile memory system according to claim 2, wherein: The control circuit is configured to perform an erase operation simultaneously on all non-volatile memory cells in the group of non-volatile memory cells by simultaneously applying an erase enable voltage to all the word lines in the group of word lines.

4. The non-volatile memory system according to claim 1, wherein: The erasure process includes a series of multiple iterations of applying an erasure signal to the group of non-volatile memory cells; and The control circuit is configured to switch between performing an erase operation individually in time on each subset of the non-volatile memory cell group based on the iteration count of the erase process, and subsequently performing an erase operation simultaneously on all non-volatile memory cells in the non-volatile memory cell group.

5. The non-volatile memory system according to claim 1, wherein: The erasure process includes a series of multiple iterations of applying an erasure signal to the group of non-volatile memory cells; The control circuit is configured to increase the erase signal for each of the multiple iterations; and The control circuit is configured to switch between performing an erase operation individually in time on each subset of the non-volatile memory cell group based on the magnitude of the erase signal, and subsequently performing an erase operation simultaneously on all non-volatile memory cells in the non-volatile memory cell group.

6. The non-volatile memory system according to claim 1, wherein: The control circuit is configured to program the group of non-volatile memory cells; and The control circuit is configured to switch between performing an erase operation individually on each subset of a subset of the nonvolatile memory cell group based on the number of programming / erase cycles performed on the nonvolatile memory cell group, and subsequently performing an erase operation simultaneously on all nonvolatile memory cells in the nonvolatile memory cell group.

7. The non-volatile memory system according to claim 1, wherein: The control circuit is configured to program the group of non-volatile memory cells; The control circuit is configured to perform an erase operation individually in time on each subset of the non-volatile memory cell group after performing multiple programming / erasing cycles on the non-volatile memory cell group, and then simultaneously perform an erase operation on all non-volatile memory cells in the non-volatile memory cell group. and The control circuit is configured to perform an erase operation individually in time on each subset of the non-volatile memory cell group before executing the plurality of programming / erasing cycles on the non-volatile memory cell group, and subsequently not to perform erase operations simultaneously on all non-volatile memory cells in the non-volatile memory cell group.

8. The non-volatile memory system according to claim 1, further comprising: A set of word lines connected to the non-volatile memory cell group and the control circuitry; The control circuit is configured to perform the erase process for the non-volatile memory cell group by performing an erase operation individually in time on each subset of the subset of the non-volatile memory cell group and then simultaneously performing an erase operation on all non-volatile memory cells in the non-volatile memory cell group: A certain dose of erase signal is applied, during the first dose of the erase signal, a first group of word lines is selected for erasure, and during the second dose of the erase signal, a second group of word lines is selected for erasure; During the erase signal of the first group dose, a first erase enable voltage is applied to the first group of word lines and a first unselected word line voltage is applied to the second group of word lines; The first unselected word line voltage applied to the second set of word lines is changed for the erase voltage of the first set of doses, such that the first unselected word line voltage approaches the first erase enable voltage over time during the erase voltage of the first set of doses. During the erase signal of the second group dose, a second erase enable voltage is applied to the second group word lines and a second unselected word line voltage is applied to the first group word lines; as well as The second unselected word line voltage applied to the first set of word lines is changed for the erase voltage of the second set of doses, such that the second unselected word line voltage approaches the erase enable voltage over time during the erase voltage of the second set of doses.

9. The non-volatile memory system according to claim 1, further comprising: A set of word lines connected to the non-volatile memory cell group and the control circuitry, the control circuitry being configured to perform the erase process for the non-volatile memory cell group by performing an erase operation individually in time on each subset of a subset of the non-volatile memory cell group via iterations of performing the erase process, and subsequently performing an erase operation simultaneously on all non-volatile memory cells in the non-volatile memory cell group. During each iteration, the control circuitry is configured to apply a first erase enable voltage to a first set of word lines while applying a first unselected word line voltage to a second set of word lines, and to apply a second erase enable voltage to the second set of word lines while applying a second unselected word line voltage to the first set of word lines. The control circuitry is configured to decrease the first unselected word line voltage and the second unselected word line voltage over time during the iterations of performing the erase process.

10. The non-volatile memory system according to claim 9, wherein: The control circuit is configured to decrease the first unselected erase voltage and the second unselected erase voltage over time based on the number of iterations performed for the erase process.

11. A method for erasing non-volatile memory, comprising: Multiple iterations of an erase process are performed to erase a group of non-volatile memory cells connected to a set of word lines. Each iteration of the erase process includes applying an erase voltage as one or more voltage pulses to the group of non-volatile memory cells. The first iteration of the erase process includes performing a first erase method, which includes applying an erase enable voltage to different subsets of the word lines in time, while word lines that do not receive the erase enable voltage receive an erase block voltage. as well as After the metric has exceeded the threshold, for one or more additional iterations of the erase process, the execution is switched from the first erase method to the second erase method, which includes simultaneously applying the erase enable voltage to all different subsets of the word lines.

12. The method according to claim 11, wherein: The first erasure method includes applying the erasure enable voltage to the even number line when the odd number line receives the erasure prevent voltage, and applying the erasure enable voltage to the odd number line when the even number line receives the erasure prevent voltage; and The second erasure method includes simultaneously applying the erasure enable voltage to both odd and even number lines.

13. The method according to claim 11, wherein: The metric is the number of iterations.

14. The method of claim 11, wherein: The metric is the number of programming / erase cycles of the group of non-volatile memory cells.

15. The method according to claim 11, wherein: The first erasure method includes applying the erasure enable voltage to the even number line when the odd number line receives the erasure blocking voltage, and applying the erasure enable voltage to the odd number line when the even number line receives the erasure blocking voltage; The second erasure method includes simultaneously applying the erasure enable voltage to both odd and even number lines; The metric is the number of iterations; The method further includes performing erasure verification during each iteration of the erasure process; and The non-volatile memory cell group is a non-volatile memory cell block.

16. A non-volatile memory system, comprising: Non-volatile memory cell group; as well as A control circuit connected to the non-volatile memory cell group is configured to erase the non-volatile memory cell group by performing an iterative erase process. During each iteration, the control circuit is configured to apply a first selected erase enable voltage to a first set of word lines and a first unselected erase voltage to a second set of word lines, and subsequently apply a second selected erase enable voltage to the second set of word lines and a second unselected erase voltage to the first set of word lines. The control circuit is also configured to change the first unselected erase voltage and the second unselected erase voltage over time during the iterations of the erase process, such that the first unselected erase voltage approaches the first selected erase enable voltage and the second unselected erase voltage approaches the second selected erase enable voltage.

17. The non-volatile memory system according to claim 16, wherein: The control circuit is configured to change the first unselected erase voltage and the second unselected erase voltage over time based on the number of iterations of the erase process.

18. The non-volatile memory system according to claim 16, wherein: The control circuit is configured to apply an erase voltage to the group of memory cells during each iteration of the erase process; The control circuit is configured to change the first unselected erase voltage and the second unselected erase voltage over time based on the magnitude of the erase voltage; The first selected erase enable voltage and the second selected erase enable voltage have the same value; and The first unselected erase voltage and the second unselected erase voltage have the same value.

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