Error correction method and device for memory, electronic equipment and medium

Abstract

The present disclosure provides an error correction method for a memory, comprising: inserting a first guide sequence into a preset position where first data needs to be stored, to obtain second data; encoding the second data to obtain third data containing check bit information; after the third data is read and written in the memory, the first guide sequence is affected by noise and changes into a second guide sequence, to obtain fourth data; replacing the second guide sequence with the first guide sequence to obtain fifth data; and performing error correction on the fifth data according to a parity check matrix and the check bit information. The present disclosure also provides an error correction device for a memory, an electronic device and a medium. The present disclosure improves the error correction capability of the memory by introducing a guide sequence and performing error correction using a parity check matrix and generated check bit information.

Description

TECHNICAL FIELD

[0001] The technical field related to the present disclosure is the field of communication and the field of memory error control, in particular, a memory error correction method and device, electronic equipment and medium. BACKGROUND

[0002] The increase of NAND Flash storage density and read-write times will lead to the increase of the raw bit error rate of the memory. The excessively high raw bit error rate limits the error correction performance of the decoder and the improvement of the NAND Flash storage density. A method of using auxiliary message coding to enhance the error correction performance of the decoder is proposed in the prior art, but this method cannot guarantee that the auxiliary information is always correct, so the effect of improving the error correction performance of the decoder fluctuates greatly. At the same time, the writing and reading process of the memory is complex, and the raw bit error rate of the memory cannot be estimated.

[0003] There are four states to choose from for reading NAND Flash, and the choice of state depends on the raw bit error rate of the NAND Flash. In the case where the raw bit error rate is unknown, it needs to be tried one by one, which reduces the reading speed. Therefore, a method is needed to estimate the raw bit error rate to provide a basis for state selection and reduce the time wasted by trying one by one.

[0004] Some current research introduces neural networks (ANN) into the error control system and proposes a decoding algorithm based on neural networks. By training in advance with noisy data, the neural network learns the probability characteristics of channel noise, and extrinsic information, usually the raw bit error rate or log-likelihood ratio, is introduced into the SPA decoder to improve the error correction performance of the decoder. However, this training can only be offline, and the trained neural network weights will not change. However, the noise characteristics of NAND Flash will gradually change with the increase of read-write times, which will affect the accuracy of neural network prediction to some extent. Therefore, it is necessary to regularly update the small-scale online training of the trained neural network.

[0005] Therefore, a method is needed to simply and quickly predict the raw bit error rate of the memory in real time, stably improve the error correction performance of the decoder, and support small-scale online training of the neural network. SUMMARY

[0006] (I) Technical problems to be solved

[0007] In view of the existing technical problems, the present disclosure provides a memory error correction method and device, electronic equipment and medium for at least partially solving the above technical problems.

[0008] (II) Technical solutions

[0009] The present disclosure provides an error correction method for a memory, comprising: obtaining first data to be stored, inserting a first guide sequence into a preset position of the first data to obtain second data; encoding the second data to obtain third data containing check bit information, wherein the check bit information is generated from the first data and the first guide sequence; writing the third data into the memory and reading the third data from the memory, after reading, the first guide sequence is changed into a second guide sequence to obtain fourth data containing the second guide sequence and the check bit information; replacing the second guide sequence with the first guide sequence to obtain fifth data; and correcting the fifth data according to a parity check matrix and the check bit information.

[0010] Optionally, the encoding of the second data is block encoding, and each block encoding comprises: multiplying the second data with a generator matrix to obtain the third data, wherein the generator matrix is orthogonal to the parity check matrix.

[0011] Optionally, after the first guide sequence is changed into the second guide sequence, the proportion of codes in the second guide sequence that are changed relative to the first guide sequence in all codes in the first guide sequence is counted to estimate an original error rate.

[0012] Optionally, after the estimation of the original error rate, the original error rate and a preset error rate are compared to determine which one is larger; if the original error rate is smaller than the preset error rate, hard decision decoding is selected to correct the fifth data; if the original error rate is larger than the preset error rate, soft decision decoding is selected to correct the fifth data.

[0013] Optionally, the correction of the fifth data according to the parity check matrix and the check bit information comprises: hard decision decoding, wherein a check equation of a code word in each position of the fifth data and a code word in the check bit information is 0 according to the parity check matrix, wherein when the code word in a certain position is wrong, the check equation containing the wrong code word is not equal to 0; it is determined whether more than half of the check equations are not equal to 0, if yes, the wrong code word is flipped, otherwise, it is not flipped; and soft decision decoding, wherein the fifth data is converted into a log-likelihood ratio (LLR), then the LLR value is iteratively updated according to the parity check matrix and the check bit information, and then the LLR value is determined into a bit value; it is determined whether there is a row in the parity check matrix that is not equal to 0, if yes, the error correction is successful, otherwise, the iteration is continued until a preset maximum iteration number is reached, wherein H is the parity check matrix, y is a matrix generated from the fifth data, and y T is the transpose matrix of y. T

[0014] ​Optionally, after the error correction of the fifth data according to the parity check matrix and the check bit information, the method further comprises: removing the first pilot sequence and the check bit information in the sixth data obtained after the error correction to obtain seventh data.

[0015] Optionally, the second data is grouped and encoded using a low-density parity check code (LDPC code) or an RS code and a BCH code.

[0016] Another aspect of the present disclosure provides an error correction device for a memory, comprising: an acquisition module configured to acquire first data to be stored, and insert a first pilot sequence into a preset position of the first data to obtain second data; an encoding module configured to encode the second data to obtain third data containing check bit information, wherein the check bit information is generated from the first data and the first pilot sequence; a read-write module configured to write the third data into the memory and read the third data from the memory, and after the reading, the first pilot sequence is changed into a second pilot sequence to obtain fourth data containing the second pilot sequence and the check bit information; a replacement module configured to replace the second pilot sequence with the first pilot sequence to obtain fifth data; and an error correction module configured to correct the fifth data according to a parity check matrix and the check bit information.

[0017] Another aspect of the present disclosure provides an electronic device, comprising: one or more processors; a memory configured to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the above-mentioned method.

[0018] Another aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, which when executed, implement the above-mentioned method.

[0019] (III) Beneficial Effects

[0020] The present disclosure provides an error correction method and device for a memory, an electronic device and a medium, which have the following beneficial effects:

[0021] 1. By inserting a pilot sequence into the stored data, generating check bit information through encoding, and backfilling the correct pilot sequence into the read data before decoding, the read data is corrected using a parity check matrix and check bit information, thereby increasing the error correction performance of the decoder.

[0022] 2. The read pilot sequences of each group are compared with the known pilot sequence inserted into the stored data, the errors in the read pilot sequences are counted, the bit error rate of each group is calculated, and the average value is taken to obtain the predicted original bit error rate of the memory, and thus the wear status of the memory storage unit is known, and the basis for the NAND Flash reading state selection is provided, thereby reducing the time wasted by trial and error.

[0023] 3. The application areas of this disclosure specifically relate to the estimation of the raw bit error rate of NAND Flash and the improvement of the error correction capability of error control systems. Furthermore, by introducing neural networks (ANNs) into error control systems, it is also possible to collect corresponding data that has not been corrected by the decoder at the read end through the customization of the guiding sequence, and use it as the training set and test set for online small-scale training and updating of the neural network, so as to periodically update the neural network in the memory online. Attached Figure Description

[0024] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 A flowchart illustrating an error correction method for a memory implemented according to this disclosure is shown schematically;

[0026] Figure 2 A flowchart illustrating a block coding implementation according to this disclosure is shown schematically;

[0027] Figure 3 The diagram illustrates the relationship between the mean squared error of the estimated bit error rate and the actual raw bit error rate for different bootstrap sequence lengths according to embodiments of the present disclosure.

[0028] Figure 4 This diagram illustrates the relationship between the estimated bit error rate and the actual raw bit error rate according to embodiments of the present disclosure.

[0029] Figure 5 The diagram illustrates the selection criteria for hard-decision decoding state and soft-decision decoding state according to an embodiment of the present disclosure.

[0030] Figure 6 The diagram illustrates a Tair graph in error correction using a soft-decision decoding algorithm according to an embodiment of this disclosure;

[0031] Figure 7 The illustration shows the effect of the proposed method using bit-flip decoding and sum-product decoding algorithms according to embodiments of the present disclosure.

[0032] Figure 8 This illustration schematically shows a comparison of the error correction effects with and without a guided sequence according to embodiments of the present disclosure;

[0033] Figure 9 A block diagram of an error-correcting electronic device according to an embodiment of the present disclosure is shown schematically;

[0034] Figure 10 A block diagram of an error correction apparatus according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0035] For the purposes of the present disclosure, technical solutions and advantages, the following will be further described in detail in combination with specific embodiments and with reference to the drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments can be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0036] The terms used herein are only intended to describe specific embodiments and are not intended to limit the present disclosure. The terms "include", "contain" and the like used herein indicate the existence of the described features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0037] All terms used herein, including technical and scientific terms, have meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted in a manner consistent with the context of the specification, and should not be interpreted in an idealized or overly formal manner.

[0038] In the case of using expressions similar to "at least one of A, B, or C, etc.", in general, it should be interpreted as having the meaning commonly understood by one of ordinary skill in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc.). One of ordinary skill in the art will also understand that substantially any disjunctive word and / or phrase presenting two or more alternative items, whether in the description, claim, or drawings, should be understood to present those items in the alternative (e.g., the phrase "A or B" should be understood as meaning either A or B, or both A and B). It should be understood that any numerical range recited herein includes all values from the lower value and the upper value. For example, if a concentration range is stated as 1% to 50%, it is intended that values ranging from 1% to 50%, such as 20%, are expressly enumerated in this specification. Any numerical range recited herein is intended to include all sub-ranges subsumed therein. For example, a range of "1% to 50%" is intended to include a range of 20% to 40% and a range of 10% to 30%.

[0039] Some of the blocks and / or combinations of the blocks in the flowcharts can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create means for implementing the functions / operations specified in the block diagrams and / or flowcharts.

[0040] Accordingly, the technology of the present disclosure can be realized in the form of hardware and / or software (including firmware, microcode, etc.). In addition, the technology of the present disclosure can take the form of a computer program product on a computer readable medium having instructions stored thereon, which can be used by or in conjunction with an instruction execution system. In the context of the present disclosure, a computer readable medium can be any medium capable of containing, storing, communicating, propagating, or transferring instructions. For example, the computer readable medium can include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, apparatus, or propagation medium. Specific examples of computer readable medium include: a magnetic storage device such as a magnetic tape or hard disk (HDD); an optical storage device such as a compact disc (CD-ROM); a memory such as a random access memory (RAM) or flash memory; and / or a wired / wireless communication link.

[0041] Figure 1 A flowchart of an error correction method for a memory implemented according to the present disclosure is schematically shown. Referring to Figure 1 , the method comprises:

[0042] S1, obtaining first data to be stored, inserting a first guide sequence into a preset position of the first data to obtain second data.

[0043] The guide sequence is a binary sequence of a certain length, which can be randomly generated or customized by a user according to needs. Before inserting the sequence into the stored data, the data needs to be evenly divided into a plurality of primary messages, and the number of the primary messages is the same as the number of the groups of the coders in the multi-coder cooperation architecture. The guide sequence is inserted into a specific position in the primary message to be stored according to a certain order, and the specific position can be randomly generated or customized by a user according to needs. The number of groups, the length of the guide sequence, and the insertion position can also be adjusted according to actual conditions.

[0044] In this embodiment, when data is written, the input message can be divided into 16 groups of primary messages, and a 300-bit guide sequence is inserted into each primary message. Under the premise of being fixed as 16 groups, the estimated error rate gradually approaches the true original error rate as the length of the guide sequence increases.

[0045] S2, encoding the second data to obtain third data containing check bit information, wherein the check bit information is generated from the first data and the first guide sequence.

[0046] Figure 2 A flowchart of group encoding implemented according to the present disclosure is schematically shown. As Figure 2After the message input encoder, the channel coding algorithm will be packet encoded, in the packet code, usually the input x is multiplied by the generator matrix to get the encoded code word y = [x c], c is the check bit information. Input x refers to the primary message after inserting the pilot sequence, that is, the pilot sequence also participates in the encoding and generates check bit information with the primary message. The generator matrix refers to a matrix G orthogonal to the parity check matrix H of the packet code. The parity check matrix is generated by a special method, usually using the method of Euclidean geometry or projection geometry in the finite field (Galois field), and a suitable parity check matrix can be constructed according to the actual application scenario. The parity check matrix is a sparse matrix containing only 0 / 1 elements. That is, H and G only contain 0 and 1 (binary), H.G T = 0. The generator matrix is used to generate the code word y in the encoding, so it is called the generator matrix, y = Gx = [x c]. G T is the transpose matrix of G. Based on the direct mathematical relationship y = [x c] between the pilot sequence, the original message and the check bit, the information entropy in the check bit is reduced due to the existence of the known pilot sequence, and the check bit obtains the external information carried by the pilot sequence. Since the pilot sequence is known at the receiving end / reading end and the insertion position will not change due to encoding, it can be completely correctly restored, thereby providing some external information for the decoder and enhancing the ability of the decoder to detect and correct errors.

[0047] S3, write the third data to the memory and read the third data from the memory, after reading, the first pilot sequence is changed to the second pilot sequence, to obtain the fourth data containing the second pilot sequence and the check bit information.

[0048] Compare the second pilot sequence with the first pilot sequence, and count the proportion of the codes in the second pilot sequence that change relative to the first pilot sequence in all codes in the first pilot sequence, to estimate the original error rate.

[0049] Figure 3 The relationship curve between the mean square deviation of the estimated error rate and the true original error rate corresponding to different pilot sequence lengths according to the embodiments of the present disclosure is schematically shown. As Figure 3 , for example, when the number of codec groups is 16 groups, the length of the pilot sequence inserted in each group of primary message is 3-5% of the total length of the primary message, and the insertion position is generated using uniform distribution, the mean square deviation of the estimated error rate and the true error rate can be only 3.4x10-6.

[0050] Figure 4 The relationship diagram between the estimated error rate and the true original error rate of the 16 groups of 300 / 8400 length pilot sequences according to the embodiments of the present disclosure is schematically shown. As Figure 4 , for example, the relationship between the estimated error rate and the true original error rate when using a 300-bit pilot sequence determines the coefficient R2 = 0.992. It can be seen that the estimated error rate can basically reflect the true error rate, and the error is very small. For example, the (10080, 8400) QC-LDPC code is used to encode the 16 parts respectively, and the code word is generated and stored in the memory. When reading data, the code word without error correction by the decoder is read first. The pilot sequence in each group of code words is compared with the known pilot sequence, the error rate of each group is calculated and averaged to obtain the estimated memory original error rate.

[0051] In a system containing a neural network, by comparing the error pilot sequence with the correct pilot sequence, the symbol error distribution of the memory can be counted, that is, the probability distribution of the error of each symbol, so as to establish a preliminary channel model and provide additional information for the neural network, support the neural network (ANN) to learn the noise model of the memory, and realize the neural network coupled decoding (ANN coupled decoding). The symbol refers to the smallest transmission unit with definite meaning, for example, in MLC NAND flash memory, there are 4 symbols 1110 0001, which represent 4 voltage values stored in the NAND flash memory cells. The voltage value stored in the memory cell can be converted into other symbols by counting the percentage of each symbol transition, and the voltage offset probability of the memory affected by noise (a state transition matrix) can be obtained, thereby supporting the neural network to learn the noise model of the memory. When the neural network is introduced into the error control system, the first pilot sequence can also be changed constantly, and the corresponding data without error correction by the decoder is collected at the reading end for online small-scale training, and the training set and test set of the neural network are updated.

[0052] The original error rate and the preset error rate are compared; if the original error rate is less than the preset error rate, hard decision decoding is selected to correct the fifth data; if the original error rate is greater than the preset error rate, soft decision decoding is selected to correct the fifth data.

[0053] In this embodiment, when reading data from the NAND Flash, the NAND flash error rate can be estimated in real time according to the known pilot sequence to select the read decoding state, reduce the time spent in selecting the state, and thus improve the reading speed. The data reading and decoding process has 4 states:

[0054] 1) default reading level with hard decision decoding (state 0)

[0055] 2) retry level with hard decision decoding (state 1)

[0056] 3) multiple reading level with soft decision decoding (state 2)

[0057] 4) Report decoding failure re-read (state 3)

[0058] Hard decision decoding is directly using the mathematical relationship between the bit value to correct error, which is much faster than soft decision decoding. The error correction capability of soft decision is stronger than that of hard decision, but it consumes more computing power. Which state to use depends on the error rate in NAND Flash. The error rate of NAND flash increases with the increase of P / E cycles. When the P / E cycles are small, the error rate is low, and 1) and 2) decoding are used; when the P / E cycles increase, the error rate is high, and 3) and 4) are used. When the error rate information cannot be known in advance, the reading and decoding process of NAND Flash is actually 1)-4) trying one by one, which will waste time on 1) and 2) when the channel condition is bad. The estimated error rate will be used to determine the read and write state, which helps NAND Flash to determine which reading and decoding state to use, reduces the time wasted by trying, and improves the reading and decoding speed. Figure 5 The error rate after correction is less than 10 -5 When the threshold value is selected, the judgment condition of hard decision decoding state and soft decision decoding state is 10 times of maximum iteration. For example, as shown in FIG. 2, when the threshold value is 0.002, the judgment condition of hard decision decoding state and soft decision decoding state is 10 times of maximum iteration. Figure 5 For example, the QC-LDPC code of (10080, 8400) is used as the encoding scheme, and the error rate less than 10 -5 When the raw BER is less than 0.002, the hard decision decoding state can be used; when the raw BER is greater than 0.002, the soft decision decoding state is used.

[0059] Since the original error rate can be considered to be constant within a certain P / E cycle, the long-term estimated error rate will be used for statistical analysis of the noise probability characteristics of the memory, and for supporting the selection of the read state.

[0060] The storage unit will gradually age in the repeated reading process, and the original error rate will also increase. The error rate value estimated by using the guide sequence can reflect the use state of the storage unit in real time. When the estimated error rate of a certain block increases to a certain threshold value, it can be considered that the block is being damaged, and a reminder can be given to the master control of the memory, so that the data is transferred to a block with good use state, or the decoding mode of multiple reading and soft decision is used. It is worth mentioning that the original error rate of the memory does not change much within a certain read-write cycle, such as the MLC NAND flash, which will not change much within 0-1000 P / E cycles. Therefore, only one measurement of the current original error rate is needed when the P / E cycle reaches a certain number, and it is not necessary to measure every time.

[0061] S4, replace the second pilot sequence with the first pilot sequence, backfill the known pilot sequence into each group of codewords to obtain the fifth data.

[0062] Specifically, after measuring the original bit error rate, the known pilot sequence is backfilled into the read codewords to ensure that the pilot sequence part input into the decoder is completely correct. Then the codewords will be divided into groups and input into the decoder for decoding, and the number of groups is the same as the number of groups of the decoder in the multi-decoding cooperation architecture, so as to detect and correct the error codes caused by noise during writing and reading.

[0063] S5, error correction of the fifth data according to the parity check matrix and the syndrome information. The decoding method can use large number logic decoding, bit flip decoding, sum-product decoding algorithm or min-sum decoding algorithm, etc.

[0064] Using hard decision decoding algorithm, this example is bit flip decoding algorithm, error correction:

[0065] The sum of the codewords in each position of the fifth data and the codewords in the syndrome information obtained from the parity check matrix is a check formula equal to 0, wherein when the codeword in a certain position is wrong, the check formula containing the wrong codeword is not equal to 0; it is judged whether more than half of the check formulas are not equal to 0, if yes, the wrong codeword is flipped, otherwise, it is not flipped.

[0066] Specifically, for example, let the fifth data y = [y1 y2 y3 y4 y5 y6], wherein y4 y5 y6 are syndrome information, according to the parity check matrix,

[0067]

[0068] y1 + y2 + y4 + y5 = 0, y1 + y3 + y5 + y6 = 0, y2 + y3 + y4 + y6 = 0, when y1 is wrong, the check formula containing y1 is y1 + y2 + y4 + y5 = 1, y1 + y3 + y5 + y6 = 1, if more than half of the check formulas are not equal to 0, y1 is flipped from 1 to 0, otherwise, it is not flipped;

[0069] ①, use the above method to traverse all codewords one by one;

[0070] ②, backfill the pilot sequence into the codewords that have been traversed;

[0071] ③, repeat steps ① and ② until the preset iteration number is reached;

[0072] Using soft decision decoding algorithm, this example is sum-product decoding algorithm, error correction:

[0073] Figure 6The Tanner Graph generated from the parity check matrix H described above is illustrated schematically and is used only for the convenience of explaining the steps of soft-decision decoding. Here, v is called the variable node and c is called the check node.

[0074] 1. Initialization: Convert each bit in the codeword that already contains errors into an LLR value, denoted as the initial L. vj At the same time, let L vj =L vj-ci L vj-ci The values ​​passed from each variable node to the check node are assigned, where 1 at the guide sequence position is assigned a very large negative value and 0 is assigned a very large positive value.

[0075] 2. Update the verification node: used for c i Connected v j L vj-ci Value update m ci-vj m ci-vj The values ​​passed from each verification node to the variable node.

[0076] 3. Update variable nodes: used with v j Connected c i m ci-vj Update L vj-ci value.

[0077] 4. Update the LLR value: Use L vj-ci Value update L vj The value of .

[0078] 5. Convert the LLR value back to a bit value: if LLR > 0, bit = 0; if LLR < 0, bit = 1, resulting in y. If Hy = 0, the decoding is successful, and it is considered... There are no errors in the current data; otherwise, repeat steps 2-5 until the maximum number of iterations is reached. The maximum number of iterations is preset, for example, 10, 20, or 50 iterations. The fifth data point is converted into a log-likelihood ratio (LLR), and then the LLR value is iteratively updated based on the parity check matrix and parity bit information. Finally, the LLR value is converted into a bit value to determine if Hy is present. T = 0, if so, the error correction is successful; otherwise, continue iterative updates until the preset maximum number of iterations is reached, where H is the parity check matrix, and y is the matrix generated based on the fifth data. T Let y be the transpose of y.

[0079] Taking the sum-product decoding algorithm (also known as the belief propagation algorithm) SPA as an example, the initial value of the decoder input is the posterior probability of each bit or the log-likelihood ratio (LLR) obtained by calculating the posterior probability.

[0080]

[0081] where y is the read codeword (disturbed by noise), vi is the transmitted codeword (not disturbed by noise), is the log-likelihood ratio of vi. Sum-product decoding is to update the LLR value of each codeword bit according to the check equation in parity check matrix H, and the value of vi is obtained after multiple iterations. If LLR > 0, vi = 0, otherwise vi = 1. The check equation specifies the relationship of the codeword in a specific position, such as c1 = v i + v k + v j +… The LLR value of the codeword vi will be updated by the LLR values of other codewords in the check equation of H containing vi. After the backfilling of the pilot sequence, the bit in the pilot sequence position is assigned a higher LLR value (recommended to be 10 times the LLR value of other bits). During the updating process of each bit LLR, the LLR value of the pilot sequence has a greater weight, which can play a guiding role (make the LLR value more positive / negative) to correct some errors that cannot be corrected before and reduce the number of iterations / speed up the decoder convergence, thereby enhancing the error correction performance of the decoder.

[0082] Low-density parity-check code (LDPC code) or other block codes have an upper limit of error correction. For example, without a pilot sequence, a certain LDPC code can correct a message with an original bit error rate RBER < 0.01. When the original bit error rate is 0.01, the LDPC code generally fails to correct errors (it cannot converge after 100 iterations, at which point the error is considered to be unable to converge, and the decoding fails. In practice, the decoder is generally not allowed to iterate 100 times, as it is too time-consuming and computationally intensive), and the decoding success rate is greatly improved after the pilot sequence is added (the average number of iterations is 20, which converges / decodes successfully, and all errors are corrected). This shows that some errors that the decoder could not correct before are corrected after the pilot sequence is added.

[0083] As for the decoding algorithm, the present disclosure does not propose a new decoding algorithm, but only improves the existing decoding method. For hard decision decoding algorithm, such as large number logic decoding algorithm, bit flip decoding algorithm, the input of such algorithm is each bit value of the codeword, by backfilling the correct pilot sequence before each iteration, the error correction capability of the corresponding algorithm is improved; for soft decision decoding algorithm, such as sum product algorithm SPA, the input of such algorithm is the log likelihood ratio (LLR) converted from each bit value of the codeword, before the first iteration, the correct pilot sequence is backfilled into the codeword, then when the bits in the codeword are converted into LLR values, the LLR at the position of the pilot sequence is given a larger value, so as to improve the error correction capability of the soft decision decoding algorithm, that is, there are fewer iteration times when correcting the same original error rate, there is faster convergence speed or the data with higher original error rate is corrected under the same iteration times. The soft decision decoding algorithm can also be applied in minimum sum algorithm (MSA), layered decoding algorithm (LBP) and dynamic information update strategy IDS (including RBP, NW-RBP, SVNF-RBP), further accelerating the convergence speed of the decoder.

[0084] Through experimental test, the method proposed in the present disclosure is effective for bit flip decoding and sum product decoding algorithm, and can improve the error correction performance of the decoder using these algorithms, Figure 7 The effect diagram of the method proposed in the embodiment of the present disclosure when using bit flip decoding and sum product decoding algorithm is schematically shown, and the maximum iteration number is 10. As shown in Figure 7 In this example, bit flip decoding and sum product decoding algorithm are used to decode each group of codewords respectively, and the maximum iteration number of the decoder is 10 times. Then, the pilot sequence is removed from the output message of the decoder, and the decoded message is recombined as the output of the read data. Figure 8 The comparison diagram of error correction effect with and without pilot sequence according to the embodiment of the present disclosure is schematically shown. As shown in Figure 8 It can be seen that when there is a pilot sequence, the error correction capability of the error control system of the memory is enhanced.

[0085] It should be pointed out that the pilot sequence plays a role in reducing the initial error number in the error correction process, and a role in guiding the LLR value to be faster biased to positive value or negative value in soft decision decoding. These two roles make the error correction capability of the decoder be enhanced. The parity check matrix H indicates the mathematical relationship of the check. The existence of the check bit information makes the error correction possible. All the codewords in y are equivalent in decoding, and the information bits, check bits and pilot sequence bits are not distinguished. Because y contains check bit information, it contains more redundancy than x, so x can be corrected.

[0086] After the fifth data is corrected to obtain the sixth data, the first preamble sequence and the check bit information in the sixth data need to be removed to obtain the seventh data, and the seventh data of each group is merged to output the final data read from the memory.

[0087] Specifically, for example, after the decoded output data x' is corrected, the preamble sequence and the check bit information inserted into the data are removed by a shifter. The preamble sequence and the check bit information can also be removed by other methods. In x', the inserted preamble sequence is in a fixed position, and the check bit information is placed at the back of x' by default, so the codes in the corresponding positions of each group of x' and the check bit information can be directly removed, and then an integrated output is synthesized, which is the data read from the memory.

[0088] In summary, the embodiments of the present disclosure propose an error correction method for a memory, aiming at the problems of complex noise environment of the memory, difficulty in measuring the error rate with the use time, and more errors in high-density storage. Through comparative analysis of the preamble sequence, the original error rate of the memory can be simply, quickly and real-timely predicted, the error correction performance of the decoder is stably improved, and the method can support small-scale online update training of NAND Flash neural networks.

[0089] Figure 9 A block diagram of an error correction electronic device according to an embodiment of the present disclosure is schematically shown.

[0090] As shown in Figure 9 The present disclosure provides an error correction electronic device for a memory, which includes a processor 910 and a memory 920. The error correction electronic device 900 can perform the method according to the embodiments of the present disclosure shown in Figure 1

[0091] Specifically, the processor 910 can include, for example, a general-purpose microprocessor, an instruction set processor, and / or a related chipset, and / or a special-purpose microprocessor (for example, an application-specific integrated circuit (ASIC)), and the like. The processor 910 can also include on-board memory for cache use. The processor 910 can be a single processing unit or a plurality of processing units for performing different actions of the method flow according to the embodiments of the present disclosure.

[0092] The memory 920, for example, can be any medium that can contain, store, communicate, propagate or transport instructions. For example, the readable storage medium can include, but is not limited to, an electric, magnetic, optical, electromagnetic, infrared or semiconductor system, device, component or propagation medium. Specific examples of the readable storage medium include a magnetic storage device such as a magnetic tape or a hard disk drive (HDD); an optical storage device such as a compact disc (CD-ROM); a memory such as a random access memory (RAM) or a flash memory; and / or a wired / wireless communication link.

[0093] ​The memory 920 can include a computer program 921, which can include code / computer-executable instructions that, when executed by the processor 910, cause the processor 910 to perform the method according to embodiments of the present disclosure or any variations thereof.

[0094] The computer program 921 can be configured to have, for example, computer program code including computer program modules. For example, in an example embodiment, the code in the computer program 921 can include at least one program module, for example, including modules 921A, 921B, … It should be noted that the division manner and number of the modules are not fixed, and a person skilled in the art can use a suitable program module or program module combination according to actual conditions, when the program module combination is executed by the processor 910, the processor 910 can perform the method according to embodiments of the present disclosure or any variations thereof.

[0095] Figure 10 A block diagram of an error correction apparatus for a memory according to embodiments of the present disclosure is schematically shown.

[0096] As Figure 10 shown, the embodiments of the present disclosure provide an error correction apparatus 1000 for a memory, comprising:

[0097] The acquisition module 1010 is configured to acquire first data to be stored, insert a first guide sequence into a preset position of the first data, and obtain second data.

[0098] Specifically, before inserting the sequence into the stored data, the data needs to be evenly divided into a plurality of groups of primary messages, and the number of groups of primary messages is the same as the number of groups of encoders in the multi-encoding cooperation architecture. The number of groups, the length of the guide sequence, and the insertion position can also be adjusted according to actual conditions. In this embodiment, when the data is written, for example, the input message is divided into 16 groups of primary messages, and a 300-bit guide sequence is inserted into each primary message. Under the premise of being fixed to 16 groups, the estimated error rate will gradually approach the true original error rate as the length of the guide sequence increases.

[0099] The encoding module 1020 is configured to encode the second data to obtain third data containing check bit information, wherein the check bit information is generated from the first data and the first guide sequence.

[0100] The read-write module 1030 is configured to write the third data into the memory and read the third data from the memory. After reading, the first guide sequence is changed into a second guide sequence to obtain fourth data containing the second guide sequence and the check bit information.

[0101] The replacement module 1040 is configured to replace the second guide sequence with the first guide sequence to obtain fifth data.

[0102] The error correction module 1050 is configured to perform error correction on the fifth data according to the parity check matrix and the check bit information.

[0103] The encoding module and the error correction module each include at least one group of block code encoders and decoders, and the encoders and the decoders can work in parallel or in series, and the block code includes, but is not limited to, a low-density parity check code (LDPC code), an RS code, and a BCH code.

[0104] Specifically, as Figure 2 After the message is input into the encoder, the message is subjected to block encoding by a channel coding algorithm. In the block code, the input x is usually multiplied by a generator matrix to obtain the encoded code word y = [x c], and c is the check bit information. The pilot sequence also participates in the encoding and generates the check bit information together with the primary message. Since the pilot sequence is known at the receiving end / reading end and the insertion position does not change due to the encoding, the pilot sequence can be completely correctly restored, thereby providing some external information for the decoder and enhancing the ability of the decoder to detect and correct errors. For example, as Figure 3 For example, when the number of the encoder-decoder groups is 16, the length of the pilot sequence inserted into each group of the primary message is 3-5% of the total length of the primary message, and the insertion positions are generated by uniform distribution, the mean square error between the estimated error rate and the real error rate is only 3.4×10-6. Figure 4 The relationship between the estimated error rate and the real original error rate when a 300-bit pilot sequence is used is shown, and the determination coefficient R 2 = 0.992. It can be seen that the estimated error rate can basically reflect the real error rate, and the error between the two is very small. For example, the 16 parts are encoded by using (10080, 8400) QC-LDPC codes respectively, and code words are generated and stored in the memory. When the data is read, the code words that are not corrected by the decoder are read first. The pilot sequence in each group of code words is compared with the known pilot sequence, the error rate of each group is calculated and averaged, and the estimated memory original error rate is obtained.

[0105] In this embodiment, when the NAND Flash data is read, the NAND flash error rate can be estimated in real time according to the known pilot sequence to select the read decoding state, the time spent in the selection state is reduced, and the reading speed is improved.

[0106] The stored codewords are inputted into the decoder for decoding after being read, so as to detect and correct the error codes caused by the noise during writing and reading. Specifically, for example, after the original error rate is estimated, the codewords are re-divided into 16 parts, and the known pilot sequence is backfilled into each group of codewords. The decoding method can use large number logic decoding, bit flip decoding, and product-sum decoding algorithm or min-sum decoding algorithm, etc. Through experimental tests, the method proposed in the present disclosure is effective for both bit flip decoding and product-sum decoding algorithm, and can improve the error correction performance of the decoder using these algorithms, such as Figure 7 In this example, bit flip decoding and product-sum decoding algorithm are used to decode each group of codewords respectively, and the maximum number of iterations of the decoder is 10 times. Thereafter, the pilot sequence is removed from the output message of the decoder, and the decoded message is recombined as the output of the read data. Figure 8 It can be seen that the error correction capability of the error control system of the memory is enhanced when the pilot sequence is present.

[0107] In addition, the pilot sequence removal module is also included, which comprises a plurality of shifters for removing the pilot sequence and the check bit information inserted into the data. Specifically, for example, the position of the inserted pilot sequence in x' is unchanged, and the check bit information is placed at the back of x' by default, so that the codes at the corresponding positions of each group of x' and the check bit information can be directly removed, and then an integral output is synthesized, which is the data read by the memory.

[0108] The present disclosure also provides a computer readable storage medium, which can be included in the device / apparatus / system described in the above embodiments, or can exist separately without being assembled into the device / apparatus / system. The above computer readable storage medium carries one or more programs, when the one or more programs are executed, the method according to the embodiments of the present disclosure is implemented.

[0109] According to an embodiment of the present disclosure, a computer readable medium can be a computer readable signal medium or a computer readable storage medium or any combination thereof. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any suitable combination thereof. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, the computer readable storage medium can be any tangible medium that contains or stores a program used by or in connection with an instruction execution system, apparatus or device. In the present disclosure, the computer readable signal medium can include a computer readable program code carried in a baseband or as a part of a carrier wave, in which the computer readable program code is used by or in connection with an instruction execution system, apparatus or device. Such a propagated computer readable signal medium can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination thereof. The computer readable signal medium can also be any computer readable medium that is not a computer readable storage medium and that can be used to carry or transmit a program for use by or in connection with an instruction execution system, apparatus or device. The program code contained in the computer readable medium can be transmitted by any suitable medium, including but not limited to wireless, wired, optical fiber cable, radio frequency (RF) signals, and the like, or any suitable combination thereof.

[0110] The flow diagrams and the block diagrams in the drawings are illustrations of possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may

[0111] As will be understood by those familiar with the art, the present disclosure can be embodied in many different forms and should not be limited to the specific embodiments described herein. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. Accordingly, many modifications can be made by one of average skill in the art to the particular embodiments without departing from the spirit and scope of the disclosure. Therefore, it is to be understood that the present disclosure is not to be limited to the specific examples described and as such may, of course, vary. It is therefore desired that what is claimed be supported by the prior art disclosure presented herein.

Claims

1. A method for error correction of a memory, characterized in that, The method comprises the following steps: obtaining first data to be stored, inserting a first guide sequence into a preset position of the first data to obtain second data; encoding the second data to obtain third data containing check bit information, wherein the check bit information is generated from the first data and the first guide sequence; writing the third data into a memory and reading the third data from the memory, after reading, the first guide sequence is changed into a second guide sequence to obtain fourth data containing the second guide sequence and the check bit information; replacing the second guide sequence with the first guide sequence to obtain fifth data; performing error correction on the fifth data according to a parity check matrix and the check bit information.

2. The method of claim 1, wherein, The encoding of the second data is group encoding, and each group encoding comprises the following steps: multiplying the second data by a generator matrix to obtain the third data, wherein the generator matrix is orthogonal to the parity check matrix.

3. The method of claim 1, wherein, The method further comprises the following steps: comparing the second guide sequence with the first guide sequence, counting the proportion of codes in the second guide sequence that are changed relative to the first guide sequence in all codes in the first guide sequence to estimate an original error rate.

4. The method of claim 3, wherein, The method further comprises the following steps: judging the size of the original error rate and a preset error rate; if the original error rate is smaller than the preset error rate, selecting hard decision decoding to perform error correction on the fifth data; if the original error rate is larger than the preset error rate, selecting soft decision decoding to perform error correction on the fifth data.

5. The method of claim 4, wherein, The error correction on the fifth data according to the parity check matrix and the check bit information comprises the following steps: using the hard decision decoding to perform error correction: obtaining a check equation that the sum of the code word at each position in the fifth data and the code word in the check bit information is 0 from the parity check matrix, wherein when the code word at a certain position is wrong, the check equation containing the wrong code word is not equal to 0; judging whether more than half of the check equations are not equal to 0, if yes, flipping the wrong code word, otherwise, not flipping; using the soft decision decoding to perform error correction: transforming the fifth data into log likelihood ratio (LLR) values, iteratively updating the LLR values according to the parity check matrix and the check bit information, and judging whether there is H T =0, if yes, the error correction is successful, otherwise, the iteratively updating is continued until a preset maximum iteration number is reached, wherein H is the parity check matrix, y is a matrix generated according to the fifth data, and y T is a transposed matrix of y.

6. The method of claim 1, wherein, After the error correction on the fifth data according to the parity check matrix and the check bit information, the method further comprises the following steps: removing the first guide sequence and the check bit information in the sixth data obtained after the error correction to obtain seventh data.

7. The method of claim 2, wherein, The second data is group encoded using low-density parity check code or RS code and BCH code.

8. An error correction device for a memory, characterized by The method comprises the following steps: an obtaining module, configured to obtain first data to be stored, and insert a first guide sequence into a preset position of the first data to obtain second data; an encoding module, configured to encode the second data to obtain third data containing check bit information, wherein the check bit information is generated from the first data and the first guide sequence; a read-write module, configured to write the third data into a memory and read the third data from the memory, after reading, the first guide sequence is changed into a second guide sequence to obtain fourth data containing the second guide sequence and the check bit information; a replacing module, configured to replace the second boot sequence with the first boot sequence to obtain fifth data; an error correction module, configured to perform error correction on the fifth data according to the parity check matrix and the check bit information. 9.An electronic device, comprising: one or more processors; memory storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1 to 7. 10.A computer-readable storage medium storing computer-executable instructions that, when executed, implement the method of any one of claims 1 to 7.

Images