Multilayer Ceramic Capacitors

Abstract

The present invention provides a laminated ceramic capacitor with high moisture resistance. The laminated ceramic capacitor (1) of the present invention comprises a laminate (2) and an external electrode (3), wherein the laminate (2) comprises: an inner layer portion (11) in which dielectric layers (14) and internal electrode layers (15) are alternately arranged; two outer layer portions (12) arranged on both sides of the inner layer portion (11) in a stacking direction (T); and two side spacers (20) arranged on two side surfaces of the inner layer portion (11) and the outer layer portion (12) in a width direction (W) intersecting the stacking direction (T), the external electrodes (3) are arranged on two end surfaces of the laminate (2) in a length direction (L) intersecting the stacking direction (T) and the width direction (W), and are connected to the internal electrode layer (15), and nickel and magnesium are segregated between the side spacers (20) and the outer layer portion (12).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, a laminated ceramic capacitor having external electrodes provided at both ends of a laminated body having side spacers provided on both side surfaces of a laminated body chip having internal electrode layers and dielectric layers laminated thereon has been manufactured (see Patent Document 1).

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-148117

[0006] Among such multilayer ceramic capacitors, those having high moisture resistance have been desired in recent years from the viewpoint of durability. Summary of the invention

[0007] Problems to be solved by the invention

[0008] An object of the present invention is to provide a multilayer ceramic capacitor having high moisture resistance.

[0009] Technical solutions to solve problems

[0010] In order to solve the above-mentioned problems, the present invention provides a laminated ceramic capacitor, comprising a laminate and an external electrode, wherein the laminate has: an inner layer portion in which dielectric layers and internal electrode layers are alternately arranged; two outer layer portions arranged on both sides of the inner layer portion in a stacking direction; and two lateral spacer portions, respectively arranged on two side surfaces of the inner layer portion and the outer layer portion in a width direction intersecting the stacking direction, the external electrodes are respectively arranged on two end surfaces of the laminate in a length direction intersecting the stacking direction and the width direction, and are connected to the internal electrode layers, and nickel and magnesium are segregated between the lateral spacer portions and the outer layer portions.

[0011] Effects of the Invention

[0012] According to the present invention, a multilayer ceramic capacitor having high moisture resistance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic perspective view of a multilayer ceramic capacitor 1 according to the embodiment.

[0014] Figure 2 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II.

[0015] Figure 3 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.

[0016] Figure 4 yes Figure 3 A partial enlarged view of .

[0017] Figure 5 yes Figure 2 An enlarged view of the circled portion Q2.

[0018] Figure 6 1 is a cross-sectional view taken along the line LW passing through the internal electrode layer 15 of the multilayer ceramic capacitor 1 .

[0019] Figure 7 1 is a flowchart for explaining a method for manufacturing the multilayer ceramic capacitor 1 .

[0020] Figure 8 It is a diagram for explaining the laminate preparation step S1 and the barrel polishing step S2.

[0021] Fig. 9 It is a diagram for explaining the base electrode layer forming step S3 and the plating layer forming step S4.

[0022] Description of Reference Numerals

[0023] A: Main side;

[0024] B: side view;

[0025] C: end face;

[0026] G: Glass;

[0027] L: length direction;

[0028] N: connection rate;

[0029] N1: connection rate;

[0030] N2: connection rate;

[0031] T: stacking direction;

[0032] W: width direction;

[0033] d: position offset;

[0034] d1: position offset;

[0035] d2: position offset;

[0036] 1: Multilayer ceramic capacitor;

[0037] 2: laminate;

[0038] 3: External electrode;

[0039] 10: Laminated chip;

[0040] 11: inner layer;

[0041] 12: outer layer;

[0042] 14: dielectric layer;

[0043] 15: internal electrode layer;

[0044] 15a: small hole;

[0045] 16: Sn layer;

[0046] 20: lateral septum;

[0047] 30: base electrode layer (base metal layer);

[0048] 30a: Zone 1;

[0049] 30b: Area 2;

[0050] 30c: Zone 3;

[0051] 31: plating layer;

[0052] 31a: Ni plating layer;

[0053] 31b: Sn plating layer;

[0054] 33: Protective layer. DETAILED DESCRIPTION

[0055] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Figure 1 It is a schematic perspective view of a multilayer ceramic capacitor 1 according to the embodiment. Figure 2 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.

[0056] The multilayer ceramic capacitor 1 is substantially in the shape of a rectangular parallelepiped and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 11 including a plurality of sets of dielectric layers 14 and internal electrode layers 15.

[0057] In the following description, as terms indicating the orientation of the multilayer ceramic capacitor 1, in the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided is referred to as the length direction L. The direction in which the dielectric layer 14 and the internal electrode layer 15 are stacked is referred to as the stacking direction T. The direction intersecting either the length direction L or the stacking direction T is referred to as the width direction W. In the embodiment, the width direction is orthogonal to either the length direction L or the stacking direction T.

[0058] In addition, the cross section extending in the length direction L and the stacking direction T is referred to as the LT cross section, the cross section extending in the length direction L and the width direction W is referred to as the LW cross section, and the cross section extending in the width direction W and the stacking direction T is referred to as the WT cross section. Figure 2 is a LT cross-sectional view of the center portion of the multilayer ceramic capacitor 1 in the width direction W. Figure 3 WT is a cross section taken along a line WT at the center of the multilayer ceramic capacitor 1 in the longitudinal direction L.

[0059] Furthermore, among the six outer surfaces of the stacked body 2, a pair of outer surfaces opposite to each other in the stacking direction T are called the first main surface A1 and the second main surface A2, a pair of outer surfaces opposite to each other in the width direction W are called the first side surface B1 and the second side surface B2, and a pair of outer surfaces opposite to each other in the length direction L are called the first end surface C1 and the second end surface C2.

[0060] In addition, when there is no need to distinguish between the first main surface A1 and the second main surface A2, they are uniformly described as main surface A; when there is no need to distinguish between the first side surface B1 and the second side surface B2, they are uniformly described as side surface B; and when there is no need to distinguish between the first end surface C1 and the second end surface C2, they are uniformly described as end surface C.

[0061] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited, but preferably, the length direction L dimension is 0.2 mm to 1.2 mm, the width direction W dimension is 0.1 mm to 0.7 mm, and the stacking direction T dimension is 0.1 mm to 0.7 mm.

[0062] (Laminate 2)

[0063] The laminate 2 includes a laminate chip 10 and side spacers 20 provided on both sides of the laminate chip 10 in the width direction W. In the laminate 2, ridges R1 of two of the main surface A, the side surface B, and the end surface C are chamfered and rounded.

[0064] (Laminated Chip 10)

[0065] The laminated chip 10 includes an inner layer portion 11, an upper outer layer portion 12a disposed on the first principal surface A1 side of the inner layer portion 11, and a lower outer layer portion 12b disposed on the second principal surface A2 side of the inner layer portion 11. In addition, when there is no need to particularly distinguish between the upper outer layer portion 12a and the lower outer layer portion 12b for description, they are collectively described as the outer layer portion 12.

[0066] (Inner layer portion 11)

[0067] The inner layer portion 11 includes a plurality of sets of dielectric layers 14 and internal electrode layers 15 alternately stacked in a stacking direction T.

[0068] (Dielectric layer 14)

[0069] The thickness of dielectric layer 14 is preferably 0.4 μm or more and 1.0 μm or less, and more preferably 0.4 μm or more and 0.6 μm or less.

[0070] The dielectric layer 14 is made of a ceramic material. For example, a dielectric ceramic having BaTiO3 as a main component is used as the ceramic material. The number of dielectric layers 14 constituting the laminated chip 10 is preferably 15 or more and 700 or less, including the upper outer layer 12a and the lower outer layer 12b.

[0071] In the embodiment, the dielectric layer 14 does not contain Ni (nickel), or contains less Ni than the outer layer portion 12. This can increase the size of the dielectric particles formed in the dielectric layer 14, and thus increase the electrostatic capacitance.

[0072] (Internal Electrode Layer 15)

[0073] The thickness of the internal electrode layer 15 is preferably 0.2 μm or more and 0.8 μm or less. The number of internal electrode layers 15 is preferably 15 or more and 700 or less.

[0074] The average thickness of each of the plurality of internal electrode layers 15 and the plurality of dielectric layers 14 is measured as follows. First, a cross section perpendicular to the length direction L of the laminate 2 exposed by grinding is observed using a scanning electron microscope. Next, the thickness on the following five lines is measured in total, which are the center line along the stacking direction T passing through the center of the cross section of the laminate 2, and two lines drawn from the center line at equal intervals to both sides. The average value of the five measured values ​​is taken. In order to obtain a more accurate average thickness, the above five measured values ​​are obtained for the upper part, the central part, and the lower part in the stacking direction T, respectively, and the average value of these measured values ​​is taken as the average thickness.

[0075] The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are alternately arranged. In addition, when there is no need to distinguish between the first internal electrode layers 15A and the second internal electrode layers 15B, they are collectively described as the internal electrode layers 15.

[0076] The first internal electrode layer 15A includes a first opposing portion 152a opposing the second internal electrode layer 15B and a first lead portion 151a led from the first opposing portion 152a to the first end surface C1. The end of the first lead portion 151a is exposed at the first end surface C1 and is electrically connected to a first external electrode 3A described later.

[0077] The second internal electrode layer 15B includes a second opposing portion 152b opposing the first internal electrode layer 15A and a second lead portion 151b led from the second opposing portion 152b to the second end surface C2. The end of the second lead portion 151b is electrically connected to a second external electrode 3B described later.

[0078] Then, electric charges are accumulated in the first opposing portion 152a of the first internal electrode layer 15A and the second opposing portion 152b of the second internal electrode layer 15B, thereby exhibiting capacitor characteristics.

[0079] Figure 4 yes Figure 3 The enlarged view of part Q1. Figure 4 In the cross section WT at the center in the longitudinal direction L shown, the positional deviation d1 between the ends in the width direction W of the adjacent internal electrode layers 15 is within 5 μm.

[0080] Furthermore, a positional deviation d2 between the outermost end portion in the width direction W, i.e., the side surface B side, and the innermost end portion in the width direction W of all the internal electrode layers 15 is within 10 μm.

[0081] That is, the ends of the stacked internal electrode layers 15 in the width direction W are located at substantially the same position in the width direction W, and the positions of the ends are aligned in the stacking direction T.

[0082] In the embodiment, the internal electrode layer 15 is mainly made of Ni (nickel) containing Sn (tin), but is not limited thereto and may be formed of a metal material represented by Cu, Ag, Pd, Ag-Pd alloy, Au, or the like.

[0083] Furthermore, Mg (magnesium) contained in the side spacers 20 is segregated on the side of the side spacers 20 on both side surfaces of the internal electrode layer 15 .

[0084] (Sn layer 16 extending from internal electrode layer 15)

[0085] Figure 5 yes Figure 2 An enlarged view of the circled portion Q2.

[0086] The Sn layer 16 formed by moving from the inside to the surface during sintering exists on the surface of the internal electrode layer 15. The Sn layer 16 extends from the surface of the internal electrode layer 15 to the boundary region Z1 between the dielectric layer 14 and the external electrode 3 adjacent to the internal electrode layer 15 in the stacking direction T. In addition, the Sn layer 16 also covers the boundary surface between the internal electrode layer 15 and the external electrode 3. In addition, the Sn layer 16 does not need to cover all of the internal electrode layer 15, and may cover a portion.

[0087] (Effect of Sn layer 16)

[0088] In the multilayer ceramic capacitor 1 of the embodiment, the Sn layer 16 extends to the boundary region Z1 between the dielectric layer 14 and the external electrode 3 . Therefore, for example, it is possible to suppress the inflow of water into the inner layer portion 11 along the boundary surface between the external electrode 3 and the laminate 2 , thereby achieving high moisture resistance.

[0089] In addition, in the embodiment, the Sn layer 16 extending from one internal electrode layer 15 is not connected to the Sn layer 16 extending from the internal electrode layer 15 adjacent to the internal electrode layer 15, and there is also a portion where the Sn layer 16 is not provided in the boundary area Z1 between the dielectric layer 14 and the external electrode 3, but even in this case, the improvement in the moisture resistance of the stacked ceramic capacitor 1 is sufficiently effective.

[0090] (Outer layer 12)

[0091] The thickness of the upper outer layer portion 12a and the lower outer layer portion 12b of the outer layer portion 12 is preferably 9.5 μm or more and 30 μm or less, and more preferably 9.5 μm to 20 μm.

[0092] (Ni of the outer layer 12)

[0093] In the outer layer portion 12, the upper outer layer portion 12a and the lower outer layer portion 12b are the same as the dielectric layer 14 of the inner layer portion 11, for example, made of a dielectric ceramic material with BaTiO3 as the main component, but different from the dielectric layer 14 of the inner layer portion 11, contain Ni, or the Ni content is higher than that of the dielectric layer 14.

[0094] As in Figure 4 As schematically shown, in the region Z3 of the outer layer portion 12 that is extremely close to the internal electrode layer 15, Ni is absorbed by the internal electrode layer 15 and does not exist. That is, Ni does not exist in the entire outer layer portion 12 but exists unevenly. Moreover, the density of Ni is highest in the center portion of the outer layer portion 12 in the stacking direction T.

[0095] (Effect)

[0096] Since the multilayer ceramic capacitor 1 of the embodiment contains Ni in the outer layer portion 12 , the particles of the dielectric ceramic are densified after sintering.

[0097] Furthermore, since the small pores formed in the dielectric ceramic in the outer layer portion 12 are filled with Ni, the moisture resistance of the multilayer ceramic capacitor 1 is high.

[0098] Furthermore, Ni in the outer layer portion 12 diffuses into the Cu layer of the external electrode 3 , thereby strengthening the bonding force with the external electrode 3 .

[0099] In addition, although Mg is not contained in the outer layer portion 12 in the embodiment, Mg may be added to the outer layer portion 12 .

[0100] (Side partition 20)

[0101] The side spacers 20 are provided on the first side surface B1 and the second side surface B2 of the laminated chip 10. When the first side spacers 20a and the second side spacers 20b are not particularly distinguished, they are collectively described as the side spacers 20.

[0102] (Components of the Side Spacer 20)

[0103] The side spacers 20 cover the ends of the laminated body chip 10 on the width direction W side of the internal electrode layer 15 exposed on both sides. Figure 3 as well as Figure 4 The interface shown in U.

[0104] The side spacers 20 are made of the same dielectric ceramic material as the dielectric layer 14, for example, BaTiO3 as the main component, but further contain Mg as a sintering aid. The content of Mg is 0.2 mol% or more and 2.8 mol% or less relative to 100 mol of Ti in the central portion of the length direction L of the side spacers 20. By setting Mg to 2.8 mol% or less, the growth of dielectric particles in the dielectric layer 14 near the outermost layer of the internal electrode layer 15 is not hindered, so that the capacitance is not easily reduced.

[0105] In addition, Mg of the side spacer 20 and Ni of the outer layer 12 are segregated to the boundary region Z2 between the side spacer 20 and the outer layer 12 during sintering. A portion of the segregated Ni and a portion of the segregated Mg form Ni-Mg oxide. That is, Ni-Mg oxide is segregated in the boundary region Z2. A portion of Ni segregated to the boundary region Z2 exists as Ni in the boundary region Z2. A portion of Mg segregated to the boundary region Z2 exists as Mg in the boundary region Z2. Ni-Mg oxide, Ni, and Mg are segregated in the boundary region Z2.

[0106] In addition, the dielectric layer 14 does not contain Ni. Therefore, the segregation amount of Ni and Ni—Mg oxide in the boundary region between the dielectric layer 14 and the side spacer 20 is smaller than the segregation amount of Ni and Ni—Mg oxide in the boundary region Z2.

[0107] Since dielectric layer 14 does not contain Ni, the growth of particles constituting dielectric layer 14 is not inhibited. Therefore, the particles constituting dielectric layer 14 become larger, and the capacitance of multilayer ceramic capacitor 1 can be increased.

[0108] The Ni-Mg alloy, which is an alloy of Mg contained in the side spacer 20 and Ni contained in the outer layer 12, segregates in the boundary region Z2 between the side spacer 20 and the outer layer 12, which is a path for moisture to enter. A part of the small holes existing in the boundary region Z2 is filled with Ni-Mg oxide. A part of the small holes existing in the boundary region Z2 is filled with Ni or Mg. Therefore, the laminated ceramic capacitor 1 of the embodiment has high moisture resistance.

[0109] (Boundary area Z2)

[0110] In addition, as described above, regarding the end portion of the internal electrode layer 15, Figure 4 The positional offset d1 of the adjacent internal electrode layers 15 on the WT cross section including the width direction W and the stacking direction T at the center of the length direction L shown in is within 5 μm. Moreover, the positional offset d2 of the outermost end of the internal electrode layer 15 in the width direction W and the innermost end of the internal electrode layer 15 in the width direction W in all the internal electrode layers 15 is within 10 μm.

[0111] The so-called boundary area Z2 between the side spacer 20 and the outer layer 12 is a band-shaped area of ​​approximately 3 μm in the width direction W, centered on an extension line e extending in the stacking direction T from the center of the width direction W of the outermost end of the internal electrode layer 15 in the width direction W and the innermost end of the internal electrode layer 15 in the width direction W.

[0112] In addition, the segregation of Ni—Mg oxide, the segregation of Ni, and the segregation of Mg can be observed by WDX (wavelength dispersive X-ray analysis).

[0113] (External electrode 3)

[0114] The external electrode 3 includes a first external electrode 3A provided on the first end surface C1 of the stacked body 2 and a second external electrode 3B provided on the second end surface C2 of the stacked body 2. In addition, when there is no need to distinguish between the first external electrode 3A and the second external electrode 3B, they are collectively described as the external electrode 3. The external electrode 3 covers not only the end surface C but also a part of the main surface A and the side surface B on the end surface C side.

[0115] As described above, the end of the first lead portion 151a of the first internal electrode layer 15A is exposed at the first end surface C1 and is electrically connected to the first external electrode 3A. In addition, the end of the second lead portion 151b of the second internal electrode layer 15B is exposed at the second end surface C2 and is electrically connected to the second external electrode 3B. Thus, a structure in which a plurality of capacitor elements are electrically connected in parallel is formed between the first external electrode 3A and the second external electrode 3B.

[0116] (External electrode 3)

[0117] (Connectivity between internal electrode layer 15 and external electrode 3)

[0118] Figure 6 1 is a cross-sectional view taken along the line LW passing through the internal electrode layer 15 of the multilayer ceramic capacitor 1 . Figure 6 The WT section at the position W1 passing through the center of the width direction W is Figure 3 . Figure 6 The position W2 is a position passing through the end portion in the width direction W of the internal electrode layer 15 .

[0119] The internal electrode layer 15 is thin, so a plurality of small holes 15a are actually provided penetrating in the stacking direction T. Figure 2 When viewed in the LT cross section, not all of the internal electrode layers 15 are connected to the external electrode 3, but Figure 2 As shown in the position P1 of FIG. 1 , there is a case where the internal electrode layer 15 is separated from the external electrode 3. However, although the internal electrode layer 15 and the external electrode 3 are not connected at the position P1, the internal electrode layer 15 and the external electrode 3 are connected at a position offset in the width direction W from the position P1.

[0120] Here, Figure 6 At a certain position in the width direction W Figure 2The number of all internal electrode layers 15 extending toward one external electrode 3 in the LT cross section shown is N0, and the number of internal electrode layers 15 connected to the external electrode 3 on that side is N, and N / N0 is taken as the connection ratio at that position.

[0121] For example, Figure 6 The position W1 passing through the center of the width direction W Figure 2 In the LT cross section shown, the number of all internal electrode layers 15 extending toward one external electrode 3 is N0, and the number of internal electrode layers 15 connected to the external electrode 3 on that side is N1. In this case, N1 / N0 is the connection ratio at position W1.

[0122] Moreover, in Figure 6 The position W2 of the end portion in the width direction W is Figure 2 In the LT cross section shown, similarly, the number of all internal electrode layers 15 extending to one external electrode 3 is N0, and the number of internal electrode layers 15 connected to the external electrode 3 on that side is N2. At this time, N2 / N0 is the connection ratio at position W2.

[0123] In a general multilayer ceramic capacitor different from the embodiment, for example, the connection ratio N1 / N0 in the LT cross section at the position W1 passing through the center of the width direction W and the connection ratio N2 / N0 in the LT cross section at the position W2 passing through the end of the width direction W are greater than 90% when expressed as percentages. Furthermore, for example, the difference between the connection ratio N1 / N0 at the position W1 passing through the center of the width direction W and the connection ratio N2 / N0 at the position W2 passing through the end of the width direction W is less than 10%.

[0124] If the connection rate is less than 90% and the difference in connection rate is large depending on the position, the connectivity between the internal electrode layer 15 and the external electrode 3 deteriorates, the flow of current is blocked or becomes unstable, and the equivalent series resistance (ESR) of the multilayer ceramic capacitor may increase.

[0125] However, in the multilayer ceramic capacitor 1 of the embodiment, the connection rate N1 / N0 at the position W1 passing through the center of the width direction W and the connection rate N2 / N0 at the position W2 passing through the end of the width direction W are expressed as percentages of 90% or more. Furthermore, the difference between the connection rate N1 / N0 at the position W1 passing through the center of the width direction W and the connection rate N2 / N0 at the position W2 passing through the end of the width direction W is 10% or less.

[0126] Therefore, the multilayer ceramic capacitor 1 of the embodiment can sufficiently ensure the contact area between the internal electrode layer 15 and the external electrode 3, and there is no deviation in the connection rate. It can ensure a good connection rate, a good flow of current, and can also suppress the equivalent series resistance (ESR) of the multilayer ceramic capacitor.

[0127] (Detection method)

[0128] The connection rate between the external electrode 3 and the internal electrode layer 15 is detected in the following manner.

[0129] (Connectivity at position W1)

[0130] Polishing is started from the LT side surface of the multilayer ceramic capacitor 1, and the internal electrode layer 15 begins to be exposed, so that the LT cross section polished by about 5 μm is exposed.

[0131] Then, the number of connections between one external electrode 3 and the internal electrode layer 15 extending toward the external electrode 3 in the LT cross section is counted and is defined as N1.

[0132] The total number of internal electrode layers 15 connected to the external electrode 3 on the same side is denoted as N0.

[0133] The connection ratio N1 / N0 at the position W1 is calculated based on N1 and N0.

[0134] (Connectivity at position W2)

[0135] The grinding is started from the LT side surface of the multilayer ceramic capacitor 1 , and the LT cross section is exposed by grinding to the center position in the width direction of the internal electrode layer 15 .

[0136] Then, the number of connections between one external electrode 3 and the internal electrode layer 15 extending toward the external electrode 3 in the LW cross section is counted and is defined as N2.

[0137] The total number of internal electrode layers 15 connected to the external electrode 3 on the same side is denoted as N0.

[0138] The connection ratio N2 / N0 at the position W2 is calculated based on N2 and N0.

[0139] When the number of internal electrode layers 15 is large, the number of connected electrodes may be counted as about 20 in the outermost region in the stacking direction T and as about 40 in the central region, and the average value may be obtained.

[0140] In the multilayer ceramic capacitor 1 according to the embodiment, as a result of actual measurement, the connection rate at the position W1 and the position W2 was 90% or more.

[0141] The reason why such a high connection rate can be obtained will be described in the production method to be described later.

[0142] (Structure of External Electrode 3)

[0143] The external electrode 3 includes a base electrode layer 30 and a plating layer 31 from the laminated body 2 side.

[0144] like Figure 2 as well as Figure 6 As shown, the base electrode layer 30 is divided into a first region 30a of 0.1 to 5 μm, a second region 30b, and a third region 30c of 0.1 to 5 μm from the laminate 2 side. The thickness of the second region 30b is not limited to 0.1 to 5 μm, but is the remaining thickness after removing the first region 30a and the third region 30c from the external electrode 3. The plating layer 31 includes a Ni plating layer 31a and a Sn plating layer 31b from the base electrode layer 30 side. The external electrode 3 including these layers covers not only the end face C, but also covers a portion of the main surface A and the side surface B on the end face C side.

[0145] In addition, the first region 30a, the second region 30b, and the third region 30c may be divided according to the ratio of the glass G. For example, in the LT cross section, if the area ratio of the glass of the entire base electrode layer 30 to Cu (the area of ​​the glass / the area of ​​the Cu) is set to P, then 0.1P or less may be set as the first region 30a, 1.2P or more may be set as the second region 30b, and the region below 1.0P may be set as the third region 30c. In addition, the second region is not necessarily included. As long as it is specified by thickness or P and any one of them is satisfied, it is set to belong to each region.

[0146] (Material of External Electrode 3)

[0147] The first region 30a, the second region 30b, and the third region 30c of the base electrode layer 30 are formed by sintering a Cu paste containing Ba (barium) mixed with glass G for densification, and are post-fired electrodes sintered separately after the laminate 2 is sintered.

[0148] (First area 30a)

[0149] The thickness of the first region 30 a in the longitudinal direction L is, for example, not less than 0.1 μm and not more than 5 μm.

[0150] As in Figure 5 As shown in the schematic diagram, the first region 30a contains more Ni, which is a metal contained in the internal electrode layer 15, than the second region 30b and the third region 30c. When measured by WDX, the intensity ratio of Ni to Cu is preferably 20% or more.

[0151] In particular, Ni is contained at a higher density on the inner layer 11 side of the first region 30a than in other regions, that is, on the second region 30b side of the first region 30a and in the second region 30b and the third region 30c, and a layer containing a large amount of Ni is formed on the inner layer 11 side of the first region 30a. Furthermore, the density of Ni near the internal electrode layer 15 on the inner layer 11 side of the first region 30a is higher than that near the dielectric layer 14. Moreover, Ni is alloyed by solid solution with Cu in the first region 30a.

[0152] As described above, the first region 30 a contains a larger amount of Ni component than the second region 30 b and the third region 30 c , and thus the connection rate between the internal electrode layer 15 and the base electrode layer 30 is improved.

[0153] (Cu particles on the laminate 2 side have a larger diameter)

[0154] In addition, the size of Cu particles in the first region 30a is larger than that in the second region 30b and the third region 30c. Furthermore, the thickness decreases as it approaches the second region 30b and the third region 30c. The size of Cu particles can be Figure 5 The area of ​​the LT section shown is determined.

[0155] (Second area 30b)

[0156] The second region 30b is a region other than the first region 30a and the third region 30c. The second region 30b is preferably thicker than the total thickness of the first region 30a and the third region 30c, and is, for example, 10 μm to 40 μm.

[0157] The second region 30b contains more glass G than the first region 30a and the third region 30c. In the LT cross section, if the area ratio of the entire glass of the base electrode layer 30 to Cu (the area of ​​glass / the area of ​​Cu) is P, the glass G is greater than or equal to 1.2P. The ratio of glass G can be obtained by measuring the area of ​​Si using WDX and calculating the ratio of the area of ​​Si to the entire area.

[0158] (3rd area 30c)

[0159] The third region 30c contains more Cu than the first region 30a and the second region 30b, and the content of glass is between Figure 5 The LT profile shown is below 1.0P, ie, less than 1.0P.

[0160] The third region 30 c has a higher Cu content than the second region 30 a and the third region 30 c , and therefore the connection rate is good when the multilayer ceramic capacitor 1 is mounted on a substrate.

[0161] Furthermore, the adhesion of the Ni plating layer 31 a can be determined by visually inspecting 100 locations on the surface of the plating layer 31 and counting the number of portions where no plating is applied.

[0162] Since the third region 30c contains the most Cu, the outer Ni plating layer 31a is easily attached, and the plating layer 31 as a whole is not easily peeled off. In the embodiment, there is no portion without plating.

[0163] In the multilayer ceramic capacitor 1 of the embodiment, the ratio of the glass G in the second region 30b is 1.2P or more, so the sealing and moisture resistance are high. Regarding moisture resistance, a voltage of 6.3V is applied to the multilayer ceramic capacitor 1 under an environment of temperature 85°C and humidity 85%, and when it is less than 100MΩ, it is judged that the moisture resistance is low. The threshold value of 100MΩ is when the electrostatic capacitance is 1μF.

[0164] Unlike the present embodiment, in the comparative multilayer ceramic capacitors 1 in which the ratio of the glass G in the second region 30 b was less than 1.2P, 11 out of 100 capacitors had values ​​lower than 100 MΩ.

[0165] Regarding the multilayer ceramic capacitors 1 according to the embodiment in which the ratio of glass G in the second region 30 b was 1.2P or more, none of the 100 multilayer ceramic capacitors 1 had a resistance lower than 100 MΩ.

[0166] As described above, in the multilayer ceramic capacitor 1 according to the embodiment, the ratio of the glass G in the second region 30 b is 1.2P or more, and therefore has excellent moisture resistance.

[0167] (Protective layer 33)

[0168] In the multilayer ceramic capacitor 1 of the embodiment, a protective layer 33 containing S (sulfur) and Ba (barium) is formed on the surface of the glass G facing the Ni plating layer 31a in the third region 30c. The protective layer 33 covers more than 50% of the surface of the third region 30c, that is, the surface of the base electrode layer 30 containing the glass G, and preferably covers more than 70%. The thickness of the protective layer 33 is not less than 10 nm and not more than 1 μm.

[0169] (Method for Confirming Protective Layer 33)

[0170] The protective layer 33 can be confirmed by photographing the area including the glass G, the third area 30c, and the Ni plating layer 31a in the area within the external electrode 3 in the LT cross section in the center of the width direction W using a TEM (Transmission Electron Microscope)-EDX (Energy Dispersive X-ray Spectroscopy).

[0171] (Thickness of protective layer 33)

[0172] The thickness of the protective layer 33 can be obtained by measuring the S and Ba thicknesses from the glass G toward the Ni plating layer 31a based on the observed S and Ba images. When the surface of the glass G is a curved surface, the thickness is taken as the thickness in the normal direction. When the thickness varies depending on the position, it may be the average value of the region divided into three equal parts in the stacking direction in the LT section.

[0173] (Coverage of protective layer 33)

[0174] The coverage of the protective layer 33 can be obtained from a value obtained by dividing the length of the protective layer 33 measured on the LT cross section by the length of the surface of the base electrode layer 30 including the surface of the glass G.

[0175] (Plating layer 31)

[0176] The plating layer 31 includes a Ni plating layer 31 a and a Sn plating layer 31 b from the base electrode layer 30 side.

[0177] (Method for Manufacturing Multilayer Ceramic Capacitor 1)

[0178] Figure 7 1 is a flowchart for explaining a method for manufacturing a laminated ceramic capacitor 1. The method for manufacturing a laminated ceramic capacitor 1 includes a laminate preparation step S1 for preparing a laminate 2, a barrel polishing step S2, a base electrode layer forming step S3, and a plating layer forming step S4.

[0179] (Laminate preparation step S1)

[0180] The laminate preparation step S1 includes a green sheet preparation step S11 , a green sheet stacking step S12 , a mother block forming step S13 , a mother block cutting step S14 , a side spacer forming step S15 , and a firing step S16 . Figure 8 It is a diagram for explaining the laminate preparation step S1 and the barrel polishing step S2.

[0181] (Raw Material Sheet Preparation Step S11)

[0182] A ceramic slurry containing a ceramic powder mainly composed of BaTiO 3 , a binder, and a solvent is prepared. In the embodiment, the ceramic slurry does not contain Ni, or the Ni content is less than that of the outer layer portion 12 .

[0183] The ceramic slurry is molded into a sheet shape on a carrier film using a die coater, a gravure coater, a micro gravure coater, or the like, thereby producing the inner layer ceramic green sheet 101 .

[0184] Furthermore, the upper outer layer portion ceramic green sheet 112 to be the upper outer layer portion 12 a and the lower outer layer portion ceramic green sheet 113 to be the lower outer layer portion 12 b are similarly produced.

[0185] The upper outer layer ceramic green sheet 112 and the lower outer layer ceramic green sheet 113 are manufactured using a ceramic slurry containing a ceramic powder with BaTiO3 as the main component, a binder and a solvent, similarly to the inner layer ceramic green sheet 101, but unlike the inner layer ceramic green sheet 101, they contain Ni, or the Ni content is higher than that of the inner layer ceramic green sheet 101.

[0186] Next, a conductor paste 102 containing Ni, glass (Si oxide), and Sn is printed on the inner layer ceramic green sheet 101 by screen printing, inkjet printing, gravure printing, or the like so as to have a stripe-shaped pattern.

[0187] Thus, the green sheet 103 is prepared in which the conductive paste 102 to be the internal electrode layer 15 is printed on the surface of the inner layer ceramic green sheet 101 to be the dielectric layer 14 .

[0188] (Raw Material Sheet Lamination Step S12)

[0189] Next, in the green sheet stacking step S12, a plurality of green sheets 103 are stacked. Specifically, the plurality of green sheets 103 are stacked so that the strip-shaped conductive paste 102 faces the same direction and the strip-shaped conductive paste 102 is staggered by half a pitch in the width direction between adjacent green sheets 103.

[0190] Furthermore, an upper outer layer ceramic green sheet 112 to become the upper outer layer 12a is stacked on one side of the stacked plurality of green sheets 103, and a lower outer layer ceramic green sheet 113 to become the lower outer layer 12b is stacked on the other side.

[0191] (Master Block Formation Step S13)

[0192] Next, in the mother block forming step S13 , the upper outer layer portion ceramic green sheet 112 , the stacked plurality of raw material sheets 103 , and the lower outer layer portion ceramic green sheet 113 are thermocompressed to form the mother block 110 .

[0193] (Master Block Cutting Step S14)

[0194] Next, in the mother block cutting step S14, the mother block 110 is cut along a cutting line X corresponding to the size of the laminated chip 10 and a cutting line Y intersecting the cutting line X. Thus, the laminated chip 10 is manufactured. In the embodiment, the cutting line Y is orthogonal to the cutting line X.

[0195] (Side Spacer Forming Step S15)

[0196] Next, a ceramic slurry is prepared by adding Mg as a sintering aid to the same dielectric powder as the inner layer ceramic green sheet 101. Then, the ceramic slurry is applied to the resin film and dried to prepare the ceramic green sheet for the side spacer. In addition, the ceramic green sheet for the side spacer may also be a plurality of layers.

[0197] Next, ceramic green sheets for side spacers are attached to the side portions of the laminated chip 10 where the internal electrode layers 15 are exposed, thereby forming layers to be the side spacers 20 .

[0198] Thus, the laminated body 2 in a state before sintering is formed, in which the side spacers 20 are adhered to the LT side surface of the laminated body chip 10 .

[0199] (Firing Step S16)

[0200] The laminated body 2 is obtained by forming a layer to be the side spacer 20 on the laminated body chip 10 , which is degreased in a nitrogen atmosphere under predetermined conditions, and then fired and sintered in a nitrogen-hydrogen-steam mixed atmosphere at a predetermined temperature to obtain the laminated body 2 .

[0201] In addition, since the side spacers 20 adhere to the laminated body chip 10 including the dielectric layer 14 , an interface exists between the side spacers 20 and the laminated body chip 10 even after sintering.

[0202] Here, Ni-Mg oxide, which is an alloy of Mg contained in the side spacers 20 and Ni contained in the outer layer 12, segregates in the boundary region Z2 between the side spacers 20 and the outer layer 12, which is a path for moisture to easily enter. Therefore, the small pores existing in this portion are filled, and moisture resistance is improved.

[0203] Here, if Figure 4 As shown, since Ni is contained in outer layer portion 12, the particles of the dielectric ceramic are densified after sintering. In addition, small pores formed in the dielectric ceramic in outer layer portion 12 are filled with Ni, so the moisture resistance of the multilayer ceramic capacitor 1 is improved.

[0204] like Figure 5As shown, a Sn layer 16 is formed on the surface of the internal electrode layer 15 so as to move from the inside to the surface.

[0205] (Barrel grinding step S2)

[0206] Next, barrel polishing is performed on the laminated body 2. Thus, the ridgeline portion R1 of the laminated body 2 is rounded.

[0207] In the firing step S16, the internal electrode layer 15 shrinks, so a part of the internal electrode layer 15 may not be exposed on the end surface C side. By providing the barrel polishing step S2, the end surface C of the stacked body 2 is also polished, and the internal electrode layer 15 not exposed on the end surface C side is reduced.

[0208] Furthermore, a positional deviation d2 between the outermost end portion in the width direction W, i.e., the side surface B side, and the innermost end portion in the width direction W of all the internal electrode layers 15 is within 10 μm.

[0209] That is, the ends of the stacked internal electrode layers 15 in the width direction W are located at substantially the same position in the width direction W, and the positions of the ends are aligned in the stacking direction T.

[0210] (Base Electrode Layer Formation Step S3)

[0211] The base electrode layer forming step S3 includes a first region forming step S31 , a second region forming step S32 , a third region forming step S33 , and a firing step S34 . Fig. 9 It is a diagram for explaining the base electrode layer forming step S3 and the plating layer forming step S4.

[0212] (First Region Forming Step S31)

[0213] In the first region forming step S31, the two end faces C of the stacked body 2 are respectively immersed in the Cu paste 116 to which glass is added to form the first region 30a. In order to form the first region 30a, a Cu paste 116 containing Cu particles with a small particle diameter is used. The particle diameter of the Cu particles is, for example, 0.05 μm or more and 3 μm or less. In addition, it is preferably 0.05 μm or more and 1 μm or less.

[0214] Here, the positional deviation d on the end surface C side of the internal electrode layer 15 is reduced in the barrel polishing step. However, there is a possibility that the positional deviation d may slightly remain on the end surface C side of the internal electrode layer 15 .

[0215] In the embodiment, since the Cu paste 116 with small particles is used, the Cu paste 116 can enter the portion of the positional deviation d remaining on the end surface C side of the internal electrode layer 15 and make good contact with the internal electrode layer 15 .

[0216] (Second Region Forming Step S32)

[0217] Next, in the second region forming step S32 , both end faces C of the laminate 2 are immersed in the Cu paste 117 having a larger glass content than the first region 30 a and the third region 30 c to form the second region 30 b .

[0218] The second region 30b contains more glass G than the first region 30a and the third region 30c. In the LT cross section, if the area ratio of the glass of the entire base electrode layer 30 to Cu (the area of ​​glass / the area of ​​Cu) is P, the glass G is greater than or equal to 1.2P. Since the ratio of the glass G in the second region 30b is greater than or equal to 1.2P, the sealing performance and moisture resistance are high.

[0219] However, in order to suppress deterioration of the electrical conductivity of the second region 30 b , the ratio of the glass G in the second region 30 b is set to 2.5P or less.

[0220] In addition, the particle diameter of the Cu particles included in the Cu paste 117 may be the same as the particle diameter of the Cu particles included in the Cu paste 116 , or may be larger than the particle diameter of the Cu particles included in the Cu paste 116 .

[0221] (Third Region Forming Step S33)

[0222] Next, in the third region forming step S33, the third region 30c is formed by immersing in a Cu paste 118 having a higher Cu content than the first region 30a and the second region 30b. The Cu paste 118 contains glass G. Glass G is, for example, BaO-B2O3-SiO2-based glass or BaO-B2O3-SiO2-LiO-NaO-based glass containing Ba. In addition, glass G contains sulfur (S).

[0223] (Firing Step S34)

[0224] Then, heating is performed in a nitrogen atmosphere at a set firing temperature for a predetermined time, thereby baking the base electrode layer 30 to the laminate 2 .

[0225] At this time, the Sn layer 16 formed on the surface of the internal electrode layer 15 extends from the surface of the internal electrode layer 15 to the boundary region Z1 between the dielectric layer 14 adjacent to the internal electrode layer 15 in the stacking direction T and the external electrode 3 .

[0226] In addition, as in Figure 5 As shown in the schematic diagram, the Cu bonding in the first region 30 a makes the Cu block larger than that in the second region 30 b and the third region 30 c , and the thickness in the stacking direction T becomes larger than the thickness of the internal electrode layer 15 .

[0227] (Plating Layer Forming Step S4)

[0228] The plating layer forming step S4 includes a Ni plating layer forming step S41 and a Sn plating layer forming step S42 .

[0229] (Ni Plating Layer Forming Step S41)

[0230] In the Ni plating layer forming step S41 , the third region 30 c of the base electrode layer 30 is immersed in a plating solution for forming the plating layer 31 , and the Ni plating layer 31 is formed on the outer periphery of the external electrode 3 .

[0231] At this time, the third region 30c contains more Cu than the first region 30a and the second region 30b. The amount of Cu can be measured by calculating the area of ​​Cu detected by WDX. The content of Cu in the third region 30c is greater than that in the first region 30a and the second region 30b, so the connection rate when the multilayer ceramic capacitor 1 is mounted on the substrate is good.

[0232] Here, when the plating solution and the treatment solution containing S (sulfur) are mixed and immersed in the third region 30 c of the base electrode layer 30 , the plating solution and the treatment solution containing S will continuously corrode the glass G exposed on the surface of the third region 30 c .

[0233] However, according to the embodiment, the glass G contains S and Ba, and therefore these S and Ba gradually form the protective layer 33 on the surface of the glass G where corrosion by the plating layer 31 is progressing.

[0234] As the protective layer 33 is continuously formed, the corrosion of the glass G by the plating solution is gradually suppressed. When the protective layer 33 is formed to a certain thickness, the glass G is hardly corroded.

[0235] On the other hand, unlike the embodiment, if the protective layer 33 is not formed, the plating solution continues to corrode the glass G and progresses toward the second region 30 b and the first region 30 a inside the foundation electrode layer 30 .

[0236] However, according to the present embodiment, in the initial stage when the third region 30c of the base electrode layer 30 is immersed in the plating solution, the protective layer 33 is formed by the Ba contained in the glass G and the processing solution containing S. Then, the protective layer 33 serves as a barrier for the glass G to the plating solution, and further erosion of the glass G by the plating solution can be suppressed.

[0237] Therefore, the base electrode layer 30 is less corroded by the plating solution, and the multilayer ceramic capacitor 1 having high heat resistance, water resistance, and humidity resistance can be obtained.

[0238] Since the third region 30 c contains the most Cu, the outer Ni plating layer 31 a is easily attached, and the plating layer 31 as a whole is not easily peeled off.

[0239] (Sn plating layer forming step S42)

[0240] Next, the Sn plating layer 31 b is formed on the outer side of the Ni plating layer 31 a .

[0241] The multilayer ceramic capacitor 1 of the embodiment is manufactured through the above-described steps. As mentioned above, the embodiment of the present invention has been described, but the present invention is not limited to the embodiment, and various modifications can be made within the scope of the gist of the invention.

[0242] For example, although the foundation electrode layer 30 is formed of three regions in the embodiment, the present invention is not limited thereto, and the foundation electrode layer 30 may not have the second region 30 b but may be formed of the first region 30 a and the third region 30 c . Alternatively, the foundation electrode layer 30 may be formed of only one region.

[0243] In the embodiment, the base electrode layer 30 including three regions is manufactured by three coating steps of the first region forming step S31, the second region forming step S32, and the third region forming step S33. However, the present invention is not limited thereto, and the base electrode layer 30 including a plurality of regions may be manufactured by adjusting the material or adjusting the temperature profile.

[0244] In the embodiment, glass G contains Ba, but glass G may not contain Ba. In this case, although protective layer 33 does not contain Ba, protective layer 33 contains S due to the processing liquid containing S.

[0245] Although in the embodiment, the connection rate is improved by using a Cu paste with a small particle size during the barrel grinding process and when forming the first region 30a of the base electrode layer 30, the present invention is not limited thereto. In order to improve the connection rate, for example, only one of the following may be performed, that is, barrel grinding or using a Cu paste with a small particle size.

[0246] The multilayer ceramic capacitor 1 of the embodiment has a structure in which the side spacers 20 are attached to both side surfaces of the multilayer chip 10 after the multilayer chip 10 is manufactured. However, the present invention is not limited thereto, and the side spacers 20 may be manufactured together with the multilayer chip 10.

[0247] Although two plating layers are provided in the embodiment, the present invention is not limited thereto, and the plating layer may be provided in one layer.

[0248] The dimensions of the multilayer ceramic capacitor 1 , the thicknesses of the internal electrode layer 15 , the dielectric layer 14 , the outer layer portion 12 , and the number of layers of the external electrode 3 specified in the embodiment are not limited to the values ​​described, and different thicknesses and numbers of layers may be used.

[0249] Furthermore, the components contained in each layer are not limited to the components described in the embodiment.

Claims

1. A laminated ceramic capacitor comprising a laminate and external electrodes, The laminated body has: The inner layer portion has dielectric layers and internal electrode layers alternately arranged; two outer layer parts arranged on both sides of the inner layer part in the stacking direction; and Two side spacers are respectively arranged on two side surfaces in the width direction intersecting the stacking direction of the inner layer portion and the outer layer portion, The external electrodes are respectively arranged on two end surfaces of the stacked body in a longitudinal direction intersecting the stacking direction and the width direction, and are connected to the internal electrode layer. Nickel and magnesium are segregated between the side spacer portion and the outer layer portion. The outer layer portion contains nickel.

2. The multilayer ceramic capacitor according to claim 1, wherein Nickel is segregated in the outer layer portion.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: Magnesium is segregated on both sides of the internal electrode layer in the width direction.

4. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The thickness of the outer layer portion is 9.5 μm or more and 30 μm or less.

5. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: A Sn layer exists on the surface of the internal electrode layer.

6. The multilayer ceramic capacitor according to claim 3, wherein: A Sn layer exists on the surface of the internal electrode layer.

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