A MOSFET and a method of manufacturing the same

Abstract

The application provides a MOSFET and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, a mask layer is formed on the surface of the substrate, the mask layer comprises a first dielectric layer and a second dielectric layer which are stacked from bottom to top, the first dielectric layer and the second dielectric layer are different material layers, a first opening is formed in the first dielectric layer, a second opening is formed in the second dielectric layer, the second opening exposes the first opening, and the size of the second opening is larger than that of the first opening, and a doped region is formed in the area of the substrate opposite to the first opening, wherein the first opening is formed based on a photoetching and etching process; taking the second dielectric layer as a mask, etching the first dielectric layer to form the second opening in the first dielectric layer and the second dielectric layer; taking the first dielectric layer and the second dielectric layer as masks, and forming a well region outside the doped region by second ion implantation, wherein the well region has a first conductive type.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a MOSFET and a manufacturing method thereof. BACKGROUND

[0002] As a representative of the third generation semiconductor material, silicon carbide (SiC) has excellent performances such as large band gap, high breakdown electric field, high saturation electron drift rate, high thermal conductivity, good chemical stability and strong anti-radiation ability, and can be widely applied in the fields of high temperature, high pressure, large current and high frequency.

[0003] The breakdown critical electric field of silicon carbide MOSFET is almost 10 times that of silicon, and silicon carbide MOSFET has higher bandwidth, lower loss and higher working temperature than high-voltage silicon IGBT devices in application. However, due to the relatively low impurity diffusion coefficient of silicon carbide material, the formation of doped regions can only be realized by multiple implantation and high-temperature annealing, and it is difficult to realize self-alignment process. The multiple photolithography and implantation process leads to complex production and manufacturing process of the device, high production cost of the device, and the cell size, current sharing and channel resistance of the device are limited by the alignment accuracy of photolithography.

[0004] In view of the above problems, it is necessary to propose a new MOSFET and a manufacturing method thereof. SUMMARY

[0005] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor to determine the protection scope of the claimed technical solution.

[0006] In view of the existing problems, the present application provides a manufacturing method of MOSFET, which comprises the following steps: providing a substrate, a mask layer is formed on the surface of the substrate, the mask layer comprises a first dielectric layer and a second dielectric layer stacked from bottom to top, the first dielectric layer and the second dielectric layer are different material layers, a first opening is formed in the first dielectric layer, a second opening is formed in the second dielectric layer, the second opening exposes the first opening, and the size of the second opening is greater than that of the first opening, a doped region is formed in the area of the substrate opposite to the first opening, wherein the first opening is formed based on photolithography and etching process;

[0007] Etching the first dielectric layer with the second dielectric layer as a mask to form the second opening in the first dielectric layer and the second dielectric layer;

[0008] forming a well region outside the doped region by a second ion implantation, wherein the well region has a first conductivity type.

[0009] In one example, the method of forming the mask layer comprises the following steps:

[0010] depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate in sequence as a mask layer, the first dielectric layer and the second dielectric layer are different material layers, and the third dielectric layer has a different material from the second dielectric layer;

[0011] forming a first opening in the mask layer by photolithography and etching, wherein the first opening exposes part of the surface of the substrate;

[0012] etching part of the width of the second dielectric layer outside the first opening from the sidewall of the second dielectric layer exposed by the first opening by a wet etching method to form a second opening in the second dielectric layer, wherein the etching rate of the wet etching on the second dielectric layer is greater than the etching rate on the first dielectric layer;

[0013] removing the third dielectric layer.

[0014] In one example, the method of forming the doped region comprises:

[0015] after forming the first opening, before the wet etching, or after the wet etching, performing a first ion implantation with the mask layer as a mask to form a doped region in part of the region of the substrate opposite to the first opening, wherein the doped region has a first conductivity type.

[0016] In one example, the center axis of the second opening and the center axis of the first opening are on the same straight line; and / or

[0017] The size of the second opening is greater than the size of the first opening by 1.2 μm to 2.4 μm.

[0018] In one example, the method of forming the mask layer comprises the following steps:

[0019] depositing a first dielectric layer and a second dielectric layer on the substrate in sequence as a mask layer, the first dielectric layer and the second dielectric layer are different material layers,

[0020] forming a patterned photoresist layer on the second dielectric layer by a photolithography process;

[0021] wet-etching the second dielectric layer as a mask of the patterned photoresist layer to form a second opening in the second dielectric layer, wherein a size of the second opening is larger than a size of the opening region of the patterned photoresist layer;

[0022] dry-etching the first dielectric layer as a mask of the patterned photoresist layer to form a first opening in the first dielectric layer, wherein a size of the first opening is the same as a size of the opening region of the patterned photoresist layer;

[0023] removing the patterned photoresist layer.

[0024] In one example, the method of forming the doped region includes:

[0025] after removing the photoresist layer, performing a first ion implantation as a mask of the first dielectric layer to form a doped region in a portion of the substrate opposite the first opening, wherein the doped region has a first conductivity type.

[0026] In one example, after forming the well region, the manufacturing method further includes the following steps:

[0027] removing the second dielectric layer;

[0028] forming a sidewall on a sidewall of the first dielectric layer;

[0029] performing a source doped region ion implantation to form a source doped region on the doped region and the well region.

[0030] In one example, forming a sidewall on a sidewall of the first dielectric layer includes:

[0031] oxidizing at least the sidewall of the first dielectric layer by an oxidation process to form the sidewall.

[0032] In one example, after forming the source doped region, the manufacturing method further includes:

[0033] removing the first dielectric layer and the sidewall;

[0034] performing an annealing process to activate the doped impurities;

[0035] forming a gate structure on the substrate, wherein the gate structure includes a gate dielectric layer and a gate layer stacked from bottom to top;

[0036] depositing an insulating dielectric isolation layer to cover the gate structure and an exposed surface of the substrate;

[0037] etching the insulating medium isolation layer and part of the substrate to form a contact opening, wherein the contact opening penetrates the source doped region and is partially located in the well region;

[0038] depositing a metal layer to fill the contact opening and cover the surface of the insulating medium isolation layer to form a contact electrically connected with the source doped region.

[0039] The application also provides a MOSFET prepared by the above manufacturing method.

[0040] The manufacturing method of the MOSFET of the embodiment of the application has the following advantages:

[0041] 1. The manufacturing method of the application can realize the implantation of various doping distributions of the MOSFET (for example, silicon carbide MOSFET) cell region only once, and the surface doping distribution of the MOSFET does not have the problem of photolithography offset, better production consistency can be realized, and the device has better current sharing property;

[0042] 2. The manufacturing method of the application can obtain a MOSFET device with smaller channel resistance, better current sharing property, smaller cell structure and better consistency in combination with reasonable structure design and process control. BRIEF DESCRIPTION OF DRAWINGS

[0043] The following drawings of the application are hereby incorporated as part of the application for the purpose of understanding the application. The drawings of the embodiments of the application and the description thereof are used to explain the principles of the application.

[0044] In the drawings:

[0045] Figures la to lj The manufacturing method of the conventional silicon carbide MOSFET is shown in the cross-sectional schematic diagram of the obtained device executed in sequence;

[0046] Figures 2a to 2i The manufacturing method of the silicon carbide MOSFET in one embodiment of the application is shown in the cross-sectional schematic diagram of the obtained device executed in sequence;

[0047] Figures 3a to 3h The manufacturing method of the silicon carbide MOSFET in another embodiment of the application is shown in the cross-sectional schematic diagram of the obtained device executed in sequence;

[0048] Figure 4 The flowchart of the manufacturing method of the silicon carbide MOSFET in one embodiment of the application is shown. DETAILED DESCRIPTION

[0049] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon

[0050] It should be understood that the present application can be practiced with the elements in different forms and should not be limited to the embodiments set forth. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals can represent like elements throughout.

[0051] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0052] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0055] The conventional manufacturing method for silicon carbide MOSFETs typically includes the following steps:

[0056] First, such as Figure la As shown, a substrate (e.g., a silicon carbide epitaxial wafer) is provided. The substrate includes a substrate 101 and an epitaxial layer 102 formed on the substrate 101. A suitable silicon carbide epitaxial wafer is selected according to the voltage withstand requirements. The epitaxial layer 102 serves as the drift region of the device and is a part that withstands high voltage. The substrate 101 is a low-resistance contact layer.

[0057] Next, as Figure lb As shown, a first dielectric layer 103 is grown on a silicon carbide epitaxial wafer as a hard mask for Pwell implantation.

[0058] Next, as Figure lc As shown, the Pwell region is opened on the first dielectric layer 103 by photolithography, that is, an opening is formed in the first dielectric layer 103 to expose part of the epitaxial layer 102. After removing the photoresist, Pwell implantation is performed to form a well region 104.

[0059] Next, as Figure Id As shown, a second dielectric layer 105 is deposited, which covers the epitaxial layer 102 and the first dielectric layer 103;

[0060] Next, as Figure le As shown, the second dielectric layer 105 is etched back by dry etching to form sidewalls (spacers) on both sides of the opening. The sidewalls and the first dielectric layer 103 are used as hard masks to block implantation, and the source doped region 106 is formed in the well region 104.

[0061] Next, the sidewalls and the first dielectric layer are removed, and a third dielectric layer 107 is grown as a hard mask for P+ injection, as shown below. Figure If ;

[0062] Next, the P+ region is opened in the third dielectric layer 107 by photolithography, that is, an opening is formed in the third dielectric layer 107 to correspond to the position where the P+ region is to be formed in the substrate. After removing the photoresist, P+ implantation is performed to form the P+ region 108, as shown below. Figure Ig ;

[0063] Next, the third dielectric layer is removed, and impurity activation annealing is performed, such as... Figure Ih ;

[0064] Next, a gate oxide layer 109 is grown on the surface of the epitaxial layer 102, and polysilicon is deposited. The gate structure 110 is defined by photolithography etching of the polysilicon, as shown below. Figure li ;

[0065] Next, an insulating dielectric layer 111 is deposited, the contact opening region is defined by photolithography etching, and the front metal 112 is deposited to fill the contact opening and cover the insulating dielectric layer 111, as shown. Figure lj .

[0066] The aforementioned silicon carbide MOSFET manufacturing process requires at least two more photolithography steps to achieve the required front-side doping. This process is relatively complex, and if there is a significant photolithography misalignment between the two steps, it will have a significant negative impact on the device performance.

[0067] Therefore, given the existence of the above problems, such as Figure 4As shown, the present application provides a manufacturing method of a silicon carbide MOSFET, comprising: in step S401, providing a substrate, a mask layer is formed on a surface of the substrate, the mask layer comprises a first dielectric layer and a second dielectric layer stacked from bottom to top, a first opening is formed in the first dielectric layer, a second opening is formed in the second dielectric layer, the second opening exposes the first opening, and the size of the second opening is greater than the size of the first opening, a doped region is formed in a region of the substrate opposite to the first opening, the first opening is formed based on a photoetching and etching process; in step S402, etching the first dielectric layer with the second dielectric layer as a mask to form the second opening in the first dielectric layer and the second dielectric layer; in step S403, forming a well region outside the doped region by a second ion implantation with the first dielectric layer and the second dielectric layer as a mask, wherein the well region has a first conductivity type.

[0068] The manufacturing method of the silicon carbide MOSFET of the embodiment of the present application has the following advantages:

[0069] 1. The manufacturing method of the present application only needs one photoetching to realize the implantation of various doped distributions of the silicon carbide MOSFET (for example, a silicon carbide MOSFET) cell region, and the surface doped distribution of the silicon carbide MOSFET does not have a photoetching offset problem, better production consistency can be realized, and the device has better current sharing property.

[0070] 2. The manufacturing method of the present application can obtain a silicon carbide MOSFET device with smaller channel resistance, better current sharing property, smaller cell structure and better consistency under the combination of reasonable structure design and process control.

[0071] In order to thoroughly understand the present application, detailed steps will be proposed in the following description in order to explain the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail as follows, however, in addition to these detailed descriptions, the present application can also have other implementation manners.

[0072] In the following, the manufacturing method of the silicon carbide MOSFET of the present application will be described in combination with the drawings, wherein, Figures 2a to 2i Fig. 1 shows the cross-sectional schematic diagram of the obtained device obtained by sequentially performing the manufacturing method of the silicon carbide MOSFET in one embodiment of the present application; Figures 3a to 3h Fig. 2 shows the cross-sectional schematic diagram of the obtained device obtained by sequentially performing the manufacturing method of the silicon carbide MOSFET in another embodiment of the present application.

[0073] In one embodiment, the manufacturing method of the silicon carbide MOSFET of the present application comprises the following steps:

[0074] Firstly, as shown in Fig. 1, Figure 2aAs shown, a substrate is provided;

[0075] Specifically, as shown in Figure 2a The substrate can include a substrate 201 and an epitaxial layer 202 formed on the substrate 201. The substrate can be a wafer, and in some examples, the substrate can include the substrate 201, while the epitaxial layer is optionally provided.

[0076] The substrate 201 is a semiconductor substrate, which can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaN, GaAs, InP, or other III / V compound semiconductor, also including a multi-layer structure composed of these semiconductors, etc., or a silicon-on-insulator (SOI), a silicon-on-silicon-on-insulator (SSOI), a silicon germanium-on-silicon-on-insulator (S-SiGeOI), a silicon germanium-on-insulator (SiGeOI), and a germanium-on-insulator (GeOI), etc. The substrate 201 is a low resistance contact layer, i.e., the resistance of the substrate 201 is lower than a threshold resistance.

[0077] A suitable silicon carbide epitaxial wafer is selected according to the voltage withstand requirement, and the parameters of the epitaxial layer 202 are related to the voltage withstand requirement of the device. Generally, the higher the voltage withstand requirement, the lower the doping concentration of the epitaxial layer 202, and the thicker the thickness of the epitaxial layer 202. The doping concentration of the epitaxial layer 202 is generally 1013cm-3~1017cm-3, and the thickness is generally greater than 6μm.

[0078] The material of the epitaxial layer 202 can be any suitable semiconductor material, such as Si, Ge, SiGe, SiC, SiGeC, InAs, GaN, GaAs, InP, or other III / V compound semiconductor, etc. In the present embodiment, the material of the epitaxial layer 202 can be SiC. The epitaxial layer 202 serves as a drift region of the device, and is a part that bears high voltage.

[0079] The conductivity type of the substrate 201 and the epitaxial layer 202 can be a first conductivity type, which can be N-type or P-type, and can be reasonably selected according to actual needs.

[0080] Next, as shown in Figure 2b A mask layer is formed on the surface of the substrate, wherein the mask layer includes a first dielectric layer 203, a second dielectric layer 204, and a third dielectric layer 205 stacked from bottom to top, the first dielectric layer and the second dielectric layer are different materials; the third dielectric layer has a different material from the second dielectric layer. By setting two adjacent dielectric layers as different materials, the etching selectivity of one of the materials in subsequent etching is achieved.

[0081] In one example, the first dielectric layer 203 is made of polysilicon; the second dielectric layer 204 is a dielectric layer different from polysilicon, for example, the material of the second dielectric layer includes silicon dioxide or silicon nitride, or other suitable dielectric layers; and the third dielectric layer 205 is a dielectric layer different from the second dielectric layer, for example, the material of the third dielectric layer includes one or more of the following materials: polysilicon, silicon nitride, silicon dioxide, and polyimide.

[0082] Optionally, the thicknesses of the first dielectric layer, the second dielectric layer, and the third dielectric layer can be reasonably set according to actual process requirements. For example, the thickness range of the first dielectric layer is 0.5μm-2μm; the thickness range of the second dielectric layer is 1.6μm-3μm; and the thickness range of the third dielectric layer is 0.4μm-2μm.

[0083] The first dielectric layer, the second dielectric layer, and the third dielectric layer together serve as a hard mask for subsequent ion implantation.

[0084] Next, as Figure 2c As shown, a first opening 2031 is formed in the mask layer by photolithography and etching, wherein the first opening 2031 exposes a portion of the surface of the substrate, such as a portion of the surface of the epitaxial layer 202, and the first opening is used to define the region of a predetermined doped region, such as a P+ region.

[0085] In one example, forming a first opening in the mask layer by photolithography and etching includes: forming a patterned photoresist layer on the mask layer using photolithography processes such as exposure and development; using the patterned photoresist layer as a mask, etching the mask layer to form the first opening, i.e., sequentially etching the third dielectric layer, the second dielectric layer, and the first dielectric layer until a portion of the surface of the epitaxial layer 202 is exposed; and then removing the patterned photoresist layer.

[0086] The mask layer can be etched using, for example, a dry etching process, which can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can also be used, or more than one etching method can be used.

[0087] Then, continue as follows Figure 2c As shown, using the mask layer (e.g., the third dielectric layer 205, the second dielectric layer 204, and the first dielectric layer 203) as a mask, a first ion implantation is performed to form a doped region 206 in a portion of the substrate (e.g., the epitaxial layer 202) opposite to the first opening 2031, wherein the doped region has a first conductivity type, for example, the doped region is a P+ doped region, that is, a P-type heavily doped region.

[0088] The dopant for the first ion implantation may include Al, or other suitable dopant capable of forming P-type doping.

[0089] The doping concentration range of the P+ doped region can be 1×10⁻⁶. 19 cm -3 -1×10 21 cm -3 Alternatively, other suitable doping concentrations can be used. The first ion implantation can also be performed after wet etching.

[0090] Next, as Figure 2d As shown, a second opening is formed in the second dielectric layer 204 by etching back a portion of the width of the second dielectric layer 204 exposed in the first opening 2031 towards the outside of the first opening 2031 using a wet etching method. The etching rate of the second dielectric layer 204 is greater than the etching rates of the first dielectric layer 203 and the third dielectric layer 205. For example, the wet etching hardly etches the first dielectric layer 203 and the third dielectric layer 205, while the etching rate of the second dielectric layer 204 is greater than a threshold rate. The third dielectric layer 205 can also serve as a mask, allowing the etching of the second dielectric layer to proceed along a predetermined width direction, without proceeding in the thickness direction of the second dielectric layer. For example, the size of the second opening is 1.2 μm to 2.4 μm larger than the size of the first opening, and the second opening exposes the first opening. Preferably, the central axis of the second opening and the central axis of the first opening are on the same straight line.

[0091] In this article, the width dimension of the second dielectric layer also refers to the radial dimension of the first opening.

[0092] In other examples, the wet etching can also have a certain degree of etching capability on the third dielectric layer 205.

[0093] For example, when the material of the second dielectric layer 204 includes silicon nitride, the chemical reagent for wet etching can be a phosphoric acid solution, while when the material of the second dielectric layer 204 includes silicon oxide, a chemical reagent including hydrofluoric acid can be used.

[0094] Optionally, the width of the second dielectric layer etched back can range from 0.6 μm to 1.2 μm, and can be reasonably set according to the actual size of the pre-formed well region.

[0095] Next, as Figure 2e As shown, the third dielectric layer is removed.

[0096] The third dielectric layer can be removed by any suitable method. Specifically, a suitable method can be selected according to the material of the third dielectric layer. For example, a wet etching method can be used, where the etching selectivity of the third dielectric layer relative to the second and first dielectric layers is greater than a threshold, such as greater than 10, so that the second and first dielectric layers are not corroded when the third dielectric layer is etched away.

[0097] For example, if the third dielectric layer is made of silicon oxide and the second dielectric layer is made of silicon nitride, then hydrofluoric acid can be used to remove the third dielectric layer.

[0098] Continue, as Figure 2e As shown, using the second dielectric layer 204 after back etching as a mask, the first dielectric layer 203 is etched to form a second opening 2032 in the first dielectric layer 203 and the second dielectric layer 204, wherein the size of the second opening is larger than the size of the first opening, and the surface of a portion of the doped region is exposed in the second opening.

[0099] Continue, as Figure 2e As shown, using the first dielectric layer 203 and the second dielectric layer 204 as masks, a well region 207 is formed outside the doped region 206 by second ion implantation, wherein the well region 207 has a first conductivity type.

[0100] The doping concentration of the formed well region 207 is 5 × 10⁻⁶. 16 cm -3 -1×10 19 cm -3 The well region 207 can be a P-type well region, or in some examples, it can also be an N-type well region. The specific choice can be made according to the actual needs of the device.

[0101] Well region 207 and doped region 206 have the same conductivity type. The doping concentration of doped region 206 is greater than that of well region 207. The dopant may include Al, or other suitable dopant capable of forming p-type doping.

[0102] In the above steps, photolithography was used only in the process of forming the first opening. When forming the second opening, wet etching was used to selectively etch different dielectric layers. Instead, the mask pattern was further patterned first, reducing one photolithography process, avoiding the problem of photolithography misalignment, and saving costs.

[0103] After forming the well region 207, the manufacturing method further includes the following steps:

[0104] First, such as Figure 2fAs shown, the second dielectric layer can be removed using any suitable method, such as wet etching.

[0105] Then, continue as follows Figure 2f As shown, sidewalls 208 are formed on the sidewalls of the first dielectric layer 203. The method for forming the sidewalls can be any suitable method well known to those skilled in the art. For example, at least the sidewalls of the first dielectric layer 203 (e.g., polycrystalline silicon) can be oxidized by an oxidation process to form the sidewalls 208. Oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing (RTO), and in-situ steam oxidation (ISSG), can be used. The oxidation process results in an oxide layer forming on both the exposed surface and the sidewalls of the first dielectric layer 203 (e.g., polycrystalline silicon), with the oxide layer on the sidewalls serving as the sidewalls 208.

[0106] The thickness of the oxide layer can be reasonably set according to actual needs, and no specific limit is imposed here.

[0107] Then, continue as follows Figure 2f As shown, source doping region ion implantation is performed to form source doping region 209 on the doped region and the well region, for example, source doping region 209 is formed on the entire doped region 206 and part of the well region 207.

[0108] The source doped region can have a second conductivity type, such as N-type, and has a different conductivity type than the aforementioned doped region 206 and well region 207.

[0109] Subsequently, after forming the source doped region, the manufacturing method further includes the following steps:

[0110] like Figure 2g As shown, when removing the first dielectric layer and the sidewall, and covering the surface of the first dielectric layer with an oxide layer, the oxide layer can be removed at the same time.

[0111] Continue as Figure 2g As shown, an annealing process is performed to activate the doped impurities. This annealing process can be rapid thermal annealing or furnace tube thermal annealing, etc., using a high temperature of 900 to 1050°C to activate the dopants in the source doping region and at the same time repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process.

[0112] Next, as Figure 2h As shown, a gate structure is formed on the substrate, wherein the gate structure includes a gate dielectric layer 210 and a gate layer 211 stacked from bottom to top.

[0113] Specifically, the gate dielectric layer can be silicon oxide (SiO2) or silicon oxynitride (SiON). The gate dielectric layer made of silicon oxide can be grown using oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), and in-situ steam oxidation (ISSG). This gate dielectric layer is also known as the gate oxide layer.

[0114] A gate material layer, such as polysilicon, is deposited on the gate dielectric layer 210. The size and shape of the gate structure are defined by photolithography and etching processes. For example, a photoresist layer is first formed on the gate material layer, the shape of the gate structure is defined by photolithography, and then the gate material layer is etched to stop in the gate dielectric layer 210 using a patterned photoresist layer as a mask, thereby forming the gate layer 211.

[0115] The thickness of the gate dielectric layer 210 is 0.3 μm-0.8 μm, or other suitable thickness. The thickness of the gate layer, for example, polysilicon, is 0.5 μm-2 μm, or other suitable thickness.

[0116] Subsequently, as Figure 2i As shown, an insulating dielectric isolation layer 212 is deposited to cover the exposed surfaces of the gate structure (e.g., gate layer 211 and gate dielectric layer 210) and the substrate (e.g., epitaxial layer 202).

[0117] The insulating dielectric layer 212 may be a silicon oxide layer, including a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (CVD) or high-density plasma (HDP) processes, such as undoped silicon glass (USG), phosphosilicate glass (PSG), or borosilicate glass (BPSG). Alternatively, the insulating dielectric layer 212 may also be a boron-doped or phosphorus-doped spin-on-glass (SOG), a phosphorus-doped tetraethoxysilane (PTEOS), or a boron-doped tetraethoxysilane (BTEOS).

[0118] The thickness of the insulating dielectric layer 212 ranges from 0.4 μm to 2 μm, or other suitable thicknesses.

[0119] Then, continue as follows Figure 2i As shown, the insulating dielectric isolation layer 212 and a portion of the substrate are etched to form a contact opening, wherein the contact opening penetrates the source doped region 209 and is partially located within the doped region 206.

[0120] This contact opening is used to form a contact that is electrically connected to the source doped region, so as to bring out the source doped region.

[0121] This etching can be performed using photolithography and etching processes, with dry etching being the preferred method.

[0122] Finally, a metal layer 213 is deposited to fill the contact openings and cover the surface of the insulating dielectric spacer 212 to form contacts electrically connected to the source doped regions.

[0123] The material of the metal layer 213 is not particularly limited as long as the material is electrically conductive. Metals and metal compounds having one or more selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al can be used as the metal layer 213, which can be deposited by a method such as physical deposition.

[0124] The thickness of the metal layer 213 is 1 μm to 10 μm, or other suitable thickness.

[0125] Since part of the contact is located in the doped region 206, it can also be electrically connected to the doped region 206, and an alloying process can also be performed to form a good ohmic contact between the metal layer and the source doped region 209 and the doped region 206 which it contacts.

[0126] The above describes the main steps of the manufacturing process of the MOSFET device of the present application, and the completed device can also include other steps, such as forming a drain on the back of the substrate 201, etc.

[0127] In summary, the present application discloses a self-aligned manufacturing method of a silicon carbide MOSFET, which can achieve the injection of various doping distributions of the silicon carbide MOSFET cell region through one three-layer overlapping dielectric layer and various operations on each layer step by step through one photolithography, thereby saving cost. The manufacturing method disclosed in the present application can achieve the surface doping distribution of the silicon carbide MOSFET without the problem of photolithography offset, can achieve better production consistency, and the device has better current sharing.

[0128] In another embodiment, as Figures 3a to 3h The present application also provides a manufacturing method of a silicon carbide MOSFET, comprising the following steps:

[0129] First, as Figure 3a shown, a substrate is provided;

[0130] Specifically, as Figure 3a shown, the substrate can include a substrate 301 and an epitaxial layer 302 formed on the substrate 301. The substrate can be a wafer, and in some examples, the substrate can include the substrate 301, while the epitaxial layer is optionally provided.

[0131] Substrate 301 is a semiconductor substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaN, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Substrate 301 is a low-resistance contact layer, meaning that the resistance of substrate 301 is lower than the threshold resistance.

[0132] The appropriate silicon carbide epitaxial wafer is selected based on the voltage withstand requirements. The parameters of the epitaxial layer 302 are related to the voltage withstand requirements of the device. Generally, the higher the voltage withstand requirement, the lower the doping concentration of the epitaxial layer 302 and the thicker the epitaxial layer 302. The doping concentration of the epitaxial layer 302 is usually between 10¹³ cm⁻³ and 10¹⁷ cm⁻³, and the thickness is generally greater than 6 μm.

[0133] The epitaxial layer 302 can be made of any suitable semiconductor material, such as Si, Ge, SiGe, SiC, SiGeC, InAs, GaN, GaAs, InP, or other III / V compound semiconductors. In this embodiment, the epitaxial layer 302 can be made of SiC. The epitaxial layer 302 serves as the drift region of the device, absorbing high voltages.

[0134] The conductivity type of the substrate 301 and the epitaxial layer 302 can be the first conductivity type, which can be either N-type or P-type, and can be reasonably selected according to actual needs.

[0135] Next, as Figure 3b As shown, a mask layer is formed on the surface of the substrate, wherein the mask layer includes a first dielectric layer 303 and a second dielectric layer 304 stacked from bottom to top. The first dielectric layer and the second dielectric layer are different material layers. By setting two adjacent dielectric layers to different materials, etching selectivity of one of the materials can be achieved in subsequent etching.

[0136] In one example, the first dielectric layer 303 is made of polysilicon; while the second dielectric layer 304 is a dielectric layer different from polysilicon, for example, the material of the second dielectric layer includes silicon dioxide or silicon nitride, or other suitable dielectric layers.

[0137] Optionally, the thicknesses of the first dielectric layer and the second dielectric layer can be reasonably set according to actual process requirements. For example, the thickness range of the first dielectric layer is 1.5μm-3μm, and the thickness range of the second dielectric layer is 0.5μm-3μm.

[0138] The first and second dielectric layers together serve as a hard mask for subsequent ion implantation.

[0139] Next, as Figure 3c As shown, a patterned photoresist layer is formed on the second dielectric layer 304 through photolithography processes, such as exposure and development. The patterned photoresist layer has an opening region with the same size as the predetermined first opening. Using the patterned photoresist layer as a mask, the second dielectric layer 304 is etched to form a second opening 3032 within it. The size of the second opening 3032 is larger than the size of the opening region in the photoresist layer; for example, the size of the second opening is 1.2 μm to 2.4 μm larger than the size of the opening region. The second dielectric layer can be etched using a wet etching process, which has a higher etch selectivity for the second dielectric layer compared to the first dielectric layer. Alternatively, dry etching can be used first, followed by wet etching. The second opening exposes the first opening, and preferably, the central axis of the second opening and the central axis of the first opening are on the same straight line.

[0140] Alternatively, the second dielectric layer can be etched first using a dry etching method, and then the opening can be enlarged into a second opening using a wet etching method.

[0141] Continue as Figure 3c As shown, using a patterned photoresist layer as a mask, a first dielectric layer 303 is etched (e.g., dry etched) to form a first opening 3031 in the first dielectric layer 303. The size of a second opening 3032 is larger than the size of the first opening 3031, for example, the size of the second opening is 1.2 μm to 2.4 μm larger than the size of the first opening 3031. In one example, the first opening can also be simultaneously formed during the dry etching process of the second dielectric layer.

[0142] A first opening 3031 is formed in the mask layer by photolithography and etching, wherein the first opening 3031 exposes a portion of the surface of the substrate, such as a portion of the surface of the epitaxial layer 302, and the first opening is used to define a region of a predetermined doped region, such as a P+ region.

[0143] In this paper, the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method or more than one etching method can also be used.

[0144] Then, continue as follows Figure 3cAs shown, the patterned photoresist layer is removed, and the first dielectric layer 303 is used as a mask to perform the first ion implantation to form a doped region 305 in a portion of the substrate (e.g., epitaxial layer 302) opposite to the first opening 3031, wherein the doped region has a first conductivity type, for example, the doped region is a P+ doped region, that is, a P-type heavily doped region.

[0145] The dopant for the first ion implantation may include Al, or other suitable dopant capable of forming P-type doping.

[0146] The doping concentration range of the P+ doped region can be 1×10⁻⁶. 19 cm -3 -1×10 21 cm -3 Alternatively, other suitable doping concentrations can be used.

[0147] Next, as Figure 3d As shown, the first dielectric layer 303 is etched using the second dielectric layer 304 as a mask to form a second opening 3032 in the first dielectric layer 303 and the second dielectric layer 304. The size of the second opening is larger than the size of the first opening, and the surface of a portion of the doped region is exposed in the second opening.

[0148] Continue, as Figure 3d As shown, using the first dielectric layer 303 and the second dielectric layer 304 as masks (i.e., hard masks), a well region 306 is formed outside the doped region 305 by second ion implantation, wherein the well region 306 has a first conductivity type.

[0149] The doping concentration of the formed well region 306 is 5 × 10¹⁶ cm⁻¹. -3 -1×10¹⁹cm -3 The well region 306 can be a P-type well region, or in some examples, it can also be an N-type well region. The specific choice can be made according to the actual needs of the device.

[0150] Well region 306 and doped region 305 have the same conductivity type. The doping concentration of doped region 305 is greater than that of well region 306. The dopant may include Al, or other suitable dopant capable of forming p-type doping.

[0151] After forming the well region 306, the manufacturing method further includes the following steps:

[0152] First, such as Figure 3e As shown, the second dielectric layer can be removed using any suitable method, such as wet etching.

[0153] Then, continue as followsFigure 3e As shown, sidewalls 307 are formed on the sidewalls of the first dielectric layer 303. The method for forming the sidewalls can be any suitable method well known to those skilled in the art. For example, at least the sidewalls of the first dielectric layer 303 (e.g., polycrystalline silicon) can be oxidized by an oxidation process to form the sidewalls 307. Oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing (RTO), and in-situ steam oxidation (ISSG), can be used. The oxidation process results in oxide layers being formed on both the exposed surface and the sidewalls of the first dielectric layer 303 (e.g., polycrystalline silicon), with the oxide layers on the sidewalls serving as the sidewalls 307.

[0154] The thickness of the oxide layer can be reasonably set according to actual needs, and no specific limit is imposed here.

[0155] Then, continue as follows Figure 3e As shown, source doping region ion implantation is performed to form source doping region 308 on the doped region and the well region, for example, source doping region 308 is formed on the entire doped region 305 and a portion of the well region 306.

[0156] The source doped region may have a second conductivity type, such as N-type, and has a different conductivity type from the aforementioned doped region 305 and well region 306.

[0157] Subsequently, after forming the source doped region, the manufacturing method further includes the following steps:

[0158] like Figure 3f As shown, when removing the first dielectric layer and the sidewall, and covering the surface of the first dielectric layer with an oxide layer, the oxide layer can be removed at the same time.

[0159] Continue as Figure 3f As shown, an annealing process is performed to activate the doped impurities. This annealing process can be rapid thermal annealing or furnace tube thermal annealing, etc., using a high temperature of 900 to 1050°C to activate the dopants in the source doping region and at the same time repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process.

[0160] Next, as Figure 3g As shown, a gate structure is formed on the substrate, wherein the gate structure includes a gate dielectric layer 309 and a gate layer 310 stacked from bottom to top.

[0161] Specifically, the gate dielectric layer can be silicon oxide (SiO2) or silicon oxynitride (SiON). The gate dielectric layer made of silicon oxide can be grown using oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), and in-situ steam oxidation (ISSG). This gate dielectric layer is also known as the gate oxide layer.

[0162] A gate material layer, such as polysilicon, is deposited on the gate dielectric layer 309. The size and shape of the gate structure is defined by a photolithography process and an etching process. For example, a photoresist layer is first formed on the gate material layer. The shape of the gate structure is defined by a photolithography process. The patterned photoresist layer is used as a mask to etch the gate material layer to stop on the gate dielectric layer 309, thereby forming the gate layer 310.

[0163] The thickness of the gate dielectric layer 309 is 0.3 μm to 0.8 μm, or other suitable thickness. The thickness of the gate layer, such as polysilicon, is 0.5 μm to 2 μm, or other suitable thickness.

[0164] Subsequently, as shown in FIG. 3C, an insulating dielectric isolation layer 311 is deposited to cover the gate structure (e.g., the gate layer 310 and the gate dielectric layer 309) and the exposed surface of the substrate (e.g., the epitaxial layer 302). Figure 3h

[0165] The insulating dielectric isolation layer 311 can be a silicon oxide layer, including a doped or undoped silicon oxide material layer formed by a thermal CVD process or a high-density plasma (HDP) process, such as undoped silicon glass (USG), phosphorus silicon glass (PSG), or boron phosphorus silicon glass (BPSG). In addition, the insulating dielectric isolation layer 311 can also be a boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS).

[0166] The thickness of the insulating dielectric isolation layer 311 is in the range of 0.4 μm to 2 μm, or other suitable thickness.

[0167] Next, as shown in FIG. 3D, the insulating dielectric isolation layer 311 and part of the substrate are etched to form a contact opening, wherein the contact opening penetrates the source doped region 308 and is partially located in the doped region 305. Figure 3h The contact opening is used to form a contact that is electrically connected to the source doped region for leading out the source doped region.

[0168] The etching can be performed by a photolithography process and an etching process. Preferably, a dry etching process is used for the etching process.

[0169] Finally, a metal layer 312 is deposited to fill the contact opening and cover the surface of the insulating dielectric isolation layer 311, thereby forming a contact that is electrically connected to the source doped region.

[0170]

[0171] ​​The material of the metal layer 312 is not particularly limited as long as the material is electrically conductive. A metal and a metal compound having one or more selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al can be used as the metal layer 312, and the metal layer 312 can be deposited by a method such as physical deposition.

[0172] The thickness of the metal layer 312 is 1 μm to 10 μm, or other suitable thickness.

[0173] Since the partial contact is located in the doped region 305, it can also be electrically connected to the doped region 305, and an alloying process can also be performed to form a good ohmic contact between the metal layer and the source doped region 308 and the doped region 305 which it contacts.

[0174] The above describes the main steps of the manufacturing process of the MOSFET device of the present application, and the completed device can also include other steps, such as forming a drain on the back of the substrate 301, etc.

[0175] In summary, the embodiment of the present application reduces one layer of dielectric layer based on the first embodiment, and realizes the injection of various doping distribution of the silicon carbide MOSFET cell region by performing various operations on the two layers of dielectric layer and only once photolithography. The silicon carbide MOSFET surface doping distribution realized by the self-alignment manufacturing method of the silicon carbide MOSFET disclosed in the present application does not have the problem of photolithography offset, and can realize better production consistency, and the device has better current sharing.

[0176] The embodiment of the present application also provides a MOSFET device, such as a silicon carbide MOSFET, which can be prepared by the above method, and thus has the same advantages as the above method. Specifically, the structure of the MOSFET is described in the above method, and is not described here.

[0177] The present application has been described by the above embodiments, but it should be understood that the above embodiments are only for example and illustration, and are not intended to limit the present application to the scope of the described embodiments. In addition, those skilled in the art can understand that the present application is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present application, which all fall within the scope of the present application. The scope of protection of the present application is defined by the attached claims and their equivalent scope.

Claims

1. A method of manufacturing a MOSFET, characterized by, The manufacturing method comprises: providing a substrate, a mask layer is formed on a surface of the substrate, the mask layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer stacked from bottom to top, the first dielectric layer and the second dielectric layer are different material layers, the third dielectric layer is different from the second dielectric layer in material, a first opening is formed in the first dielectric layer and the third dielectric layer, a second opening is formed in the second dielectric layer, the second opening exposes the first opening, and the size of the second opening is greater than the size of the first opening, wherein the second opening is formed based on wet etching, the etching rate of the second dielectric layer is greater than the etching rate of the first dielectric layer and the third dielectric layer, and a doped region is formed in the region of the substrate opposite to the first opening, wherein the first opening is formed based on photolithography and etching process; removing the third dielectric layer; using the second dielectric layer as a mask, etching the first dielectric layer to form the second opening in the first dielectric layer and the second dielectric layer; using the first dielectric layer and the second dielectric layer as a mask, forming a well region outside the doped region by second ion implantation, wherein the well region has a first conductivity type.

2. The production method according to claim 1, wherein After forming the well region, the manufacturing method further comprises the following steps: removing the second dielectric layer; forming a side wall on the side wall of the first dielectric layer; performing source doped region ion implantation to form a source doped region on the doped region and the well region.

3. The production method according to claim 1, wherein The method for forming the mask layer comprises the following steps: depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate in sequence as a mask layer, the first dielectric layer and the second dielectric layer are different material layers, and the third dielectric layer has a different material from the second dielectric layer; forming a first opening in the mask layer by photolithography and etching, wherein the first opening exposes part of the surface of the substrate; forming a second opening in the second dielectric layer by etching part of the width of the second dielectric layer from the side wall of the second dielectric layer exposed in the first opening to the outside of the first opening by wet etching, wherein the etching rate of the second dielectric layer is greater than the etching rate of the first dielectric layer; removing the third dielectric layer.

4. The production method according to claim 3, wherein The method for forming the doped region comprises: after forming the first opening, before the wet etching, or after the wet etching, performing first ion implantation using the mask layer as a mask to form a doped region in the partial region of the substrate opposite to the first opening, wherein the doped region has a first conductivity type.

5. The production method according to claim 1, wherein the center axis of the second opening and the center axis of the first opening are on the same straight line; and / or the size of the second opening is 1.2 μm-2.4 μm larger than the size of the first opening.

6. The production method according to claim 2, wherein forming a side wall on the side wall of the first dielectric layer comprises: oxidizing at least the side wall of the first dielectric layer by an oxidation process to form the side wall.

7. The production method according to claim 2, wherein After forming the source doped region, the manufacturing method further comprises: removing the first dielectric layer and the sidewall; performing an annealing process to activate the doped impurities; forming a gate structure on the substrate, wherein the gate structure comprises a gate dielectric layer and a gate layer stacked from bottom to top; depositing an insulating dielectric isolation layer to cover the gate structure and the exposed surface of the substrate; etching the insulating dielectric isolation layer and part of the substrate to form a contact opening, wherein the contact opening penetrates the source doped region and partially locates in the well region; depositing a metal layer to fill the contact opening and cover the surface of the insulating dielectric isolation layer to form a contact electrically connected with the source doped region.

8. A MOSFET prepared by the manufacturing method of any one of claims 1 to 7.

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