Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a mark region and a device region; forming a first mask structure on the substrate, the first mask structure having a first mask opening exposing part of the mark region and a second mask opening exposing part of the device region; etching the substrate at the bottom of the first mask opening to form a first opening in the mark region; forming an alignment structure in the first opening; etching the substrate at the bottom of the second mask opening to form a second opening in the device region; and forming an isolation structure in the second opening. The method for forming the semiconductor structure simplifies the forming process of the deep trench structure and the alignment mark, thereby improving the reliability of the semiconductor manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor structure. Background Technology

[0002] Deep trench structures are widely used in the manufacture of semiconductor devices, such as CMOS devices and image sensors. In the process of CMOS devices, deep trench structures are usually formed first on a flat silicon wafer surface, and then the subsequent active area (AA) process is performed.

[0003] The active region process requires alignment marks for alignment. However, existing alignment marks are uneven, unclear, and have low alignment accuracy, leading to uneven photoresist coating and poor chemical mechanical polishing in subsequent processes. This reduces the reliability of the fabrication process and affects the performance of semiconductor devices. Furthermore, there is still room for simplification in the formation process of existing deep trench structures and alignment marks. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the alignment accuracy and flatness of the alignment marks. In addition, it simplifies the formation process of the deep trench structure and the alignment marks, thereby improving the reliability of the semiconductor fabrication process and improving the performance of the semiconductor device.

[0005] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a marking region and a device region; forming a first mask structure on the substrate, the first mask structure having a first mask opening exposing a portion of the marking region and a second mask opening exposing a portion of the device region; etching the substrate at the bottom of the first mask opening to form a first opening in the marking region; forming an alignment structure in the first opening; etching the substrate at the bottom of the second mask opening to form a second opening in the device region; and forming an isolation structure in the second opening.

[0006] Optionally, the substrate includes a base and a first epitaxial structure located on the base.

[0007] Optionally, the first epitaxial structure includes: a first epitaxial layer on a substrate, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer.

[0008] Optionally, the thickness of the first epitaxial structure ranges from 2 micrometers to 4 micrometers.

[0009] Optionally, the material of the third epitaxial layer includes N-type doped silicon.

[0010] Optionally, the method for forming the first mask structure includes: forming an initial first mask structure on the substrate; forming a first patterning layer on the initial first mask structure, the first patterning layer exposing the initial first mask structure surface on a portion of the marker area and the initial first mask structure surface on a portion of the device area; using the patterning layer as a mask, etching the initial first mask structure to form the first mask structure, the first mask structure having a first mask opening exposing a portion of the marker area and a second mask opening exposing a portion of the device area.

[0011] Optionally, the initial first mask structure includes: an initial oxygen pad layer located on the substrate, an initial first mask layer located on the initial oxygen pad layer, and an initial second mask layer located on the initial first mask layer.

[0012] Optionally, the thickness of the first mask structure ranges from 2000 angstroms to 4000 angstroms.

[0013] Optionally, the material of the initial first mask layer includes silicon nitride; the material of the initial second mask layer includes silicon oxide.

[0014] Optionally, after forming the first opening and the alignment structure located within the first opening, the second opening and the isolation structure located within the second opening are formed.

[0015] Optionally, the method for forming the first opening includes: forming a second patterned layer on the first mask structure, the second patterned layer exposing the first mask structure on the marked area; using the first mask structure as a mask, etching a first epitaxial structure at the bottom of the first mask opening to form the first opening.

[0016] Optionally, the depth of the first opening ranges from 0.5 micrometers to 1 micrometer.

[0017] Optionally, the method for forming the alignment structure includes: forming a first initial dielectric layer within the first epitaxial structure and within the first mask structure, wherein the first initial dielectric layer fills the first opening, the first mask opening, and the second mask opening; planarizing the first initial dielectric layer until the surface of the first mask structure is exposed, thereby forming an alignment structure from the first initial dielectric layer located on the marking region.

[0018] Optionally, the material of the first initial dielectric layer includes silicon oxide.

[0019] Optionally, the method for forming the semiconductor structure further includes: after forming the alignment structure and before forming the second opening, using the first mask structure as a mask, etching a first initial dielectric layer located within the second mask opening until the surface of the first epitaxial structure is exposed.

[0020] Optionally, the method for forming the second opening includes: after forming the alignment structure, using the first mask structure as a mask, etching the first epitaxial structure at the bottom of the second mask opening to form the second opening, wherein the second opening exposes the substrate surface.

[0021] Optionally, the material of the isolation structure includes p-type doped silicon; the material of the substrate includes silicon.

[0022] Optionally, the method for forming the isolation structure includes: forming an initial isolation material layer on the substrate that fills the second opening and the second mask opening; planarizing the initial isolation material layer until the surface of the first mask structure is exposed to form the isolation structure.

[0023] Optionally, the initial isolation material layer is formed by an epitaxial growth process.

[0024] Optionally, the method for forming the semiconductor structure further includes: after forming the alignment structure and the isolation structure, removing the first mask structure; after removing the first mask structure, planarizing the alignment structure and the isolation structure to form alignment marks and deep trench device layers, wherein the alignment marks and deep trench device layers are flush with the top surface of the substrate.

[0025] Optionally, the method for planarizing the alignment structure and the isolation structure includes: etching the alignment structure until a portion of the alignment structure above the top surface of the substrate is removed; and after etching the alignment structure, performing chemical mechanical polishing on the alignment structure and the isolation structure to form alignment marks and a deep trench device layer.

[0026] Optionally, the method for etching the alignment structure includes wet etching.

[0027] Optionally, the method for forming the semiconductor structure further includes: after forming the alignment mark and the deep trench device layer, forming a second epitaxial structure on the substrate, wherein the second epitaxial structure exposes the alignment mark.

[0028] Optionally, after forming the second opening and the isolation structure located within the second opening, the first opening and the alignment structure located within the first opening are formed.

[0029] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0030] In the semiconductor structure formation method provided by the technical solution of the present invention, since the same hard mask structure is used, namely, the first mask structure forms the alignment structure located in the marking region and the isolation structure located in the device region, the number of times the mask structure is formed on the surface of the marking region and the device region is reduced, the formation process of the isolation structure and the alignment structure is simplified, thereby improving the reliability of the semiconductor fabrication process and improving the performance of the semiconductor device. In addition, since the alignment structure in the first opening has a relatively regular morphology, it has high alignment accuracy, providing a clearer positioning mark for subsequent active region processes; secondly, the presence of the alignment structure reduces the risk of mechanical polishing process and optimizes the flatness of the substrate surface.

[0031] Furthermore, after the second epitaxial structure is formed on the substrate surface, the presence of the alignment mark enables the openings within the second epitaxial structure above it to maintain a better morphology, thereby giving the alignment mark higher alignment accuracy and providing a clearer positioning identifier for subsequent active region processes. In addition, the presence of the alignment mark makes the second epitaxial structure grown on the substrate surface more uniform, thus optimizing the surface flatness of the second epitaxial structure. Attached Figure Description

[0032] Figures 1 to 8 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0033] As described in the background section, the alignment marks in the existing technology are uneven, unclear, and have low alignment accuracy, which leads to problems such as uneven photoresist coating and poor chemical mechanical polishing effect in subsequent processes, reducing the reliability of the fabrication process and affecting the performance of semiconductor devices. In addition, there is still room for further simplification in the existing deep trench structure and alignment mark formation process.

[0034] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a first mask structure on a substrate; using the first mask structure as a mask to form a first opening located in a marking region and a second opening located in a device region; and forming an alignment structure and an isolation structure within the first and second openings, respectively. By utilizing the first mask structure to form the alignment structure located in the marking region and the isolation structure located in the device region within the substrate, the number of times the mask structure is formed on the surfaces of the marking region and the device region is reduced, simplifying the formation process of the isolation structure and the alignment structure. Furthermore, since the alignment structure within the first opening has a relatively regular morphology, it possesses high alignment accuracy, and the presence of the alignment structure reduces the risk of mechanical polishing processes, optimizing the flatness of the substrate surface.

[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 1 to 8 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0037] Please refer to Figure 1 A substrate is provided, the substrate including a marking region A and a device region B.

[0038] In this embodiment, the marking region A of the substrate provides a platform for the subsequent formation of the alignment structure, and the device region B of the substrate provides a platform for the subsequent formation of the isolation structure.

[0039] In this embodiment, the substrate includes a substrate 100 and a first epitaxial structure 101 located on the substrate 100. The first epitaxial structure 101 includes: a first epitaxial layer 102 located on the substrate 100, a second epitaxial layer 103 located on the first epitaxial layer 102, and a third epitaxial layer 104 located on the second epitaxial layer 103.

[0040] The substrate 100 is made of materials including silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. In this embodiment, the substrate 100 is made of silicon.

[0041] In this embodiment, the first epitaxial layer 102 is made of P-type doped silicon; the second epitaxial layer 103 is made of P-type doped silicon, and the doping concentration of the ions in the second epitaxial layer 103 is higher than that in the first epitaxial layer 102. The third epitaxial layer 104 is made of N-type doped silicon.

[0042] In this embodiment, the thickness of the first epitaxial structure 101 ranges from 2 micrometers to 4 micrometers.

[0043] Please refer to Figure 2 A first mask structure 108 is formed on the substrate. The first mask structure 108 has a first mask opening 109 that exposes a portion of the marking region A and a second mask opening 110 that exposes a portion of the device region B.

[0044] In subsequent processes, the first mask structure 108 serves as a mask to form a first opening within the marking region A and a second opening within the device region B. Specifically, the first mask opening 109 is used to etch the first opening within the marking region A, thereby forming an alignment structure within the first opening in subsequent processes; the second mask opening 110 is used to etch the second opening within the device region B, thereby forming an isolation structure within the second opening in subsequent processes.

[0045] In this embodiment, the method for forming the first mask structure 108 includes: forming an initial first mask structure (not shown) on the substrate; forming a first patterning layer (not shown) on the initial first mask structure; the first patterning layer exposing a portion of the initial first mask structure surface on the marker region A and a portion of the initial first mask structure surface on the device region B; using the patterning layer as a mask, etching the initial first mask structure to form the first mask structure 108; the first mask structure 108 has a first mask opening 109 exposing a portion of the marker region A and a second mask opening 110 exposing a portion of the device region B.

[0046] In this embodiment, the initial first mask structure includes: an initial oxygen pad layer located on the substrate, an initial first mask layer located on the initial oxygen pad layer, and an initial second mask layer located on the initial first mask layer. Since the initial second mask layer has a better surface morphology, it is located on the initial first mask layer, thus optimizing the surface morphology of the initial first mask structure and the subsequently formed first mask structure 108.

[0047] Specifically, the material of the initial first mask layer includes silicon nitride; the material of the initial second mask layer includes silicon oxide.

[0048] In this embodiment, the method for forming the initial oxygen pad layer includes chemical vapor deposition; the method for forming the initial first mask layer includes chemical vapor deposition; and the method for forming the initial second mask layer includes chemical vapor deposition or decomposition deposition, wherein the precursor used in the decomposition deposition method includes TEOS.

[0049] In this embodiment, the initial first mask structure is etched to form the first mask structure 108. Specifically, after etching the initial first mask structure, the initial first mask structure includes an initial oxide pad layer forming an oxide pad layer 105, an initial first mask layer forming a first mask layer 106, and an initial second mask layer forming a second mask layer 107. The first mask opening 109 and the second mask opening 110 penetrate the oxide pad layer 105, the first mask layer 106, and the second mask layer 107. The oxide pad layer 105, the first mask layer 106, and the second mask layer 107 constitute the first mask structure 108.

[0050] In this embodiment, the thickness of the first mask structure 108 ranges from 2000 angstroms to 4000 angstroms.

[0051] In this embodiment, after the first mask structure 108 is formed, the first mask structure 108 is cleaned to remove residual impurities from the etching process.

[0052] Please refer to Figure 3 Using the first mask structure 108 as a mask, the substrate at the bottom of the first mask opening 109 is etched to form a first opening 111 in the marking area A.

[0053] In this embodiment, the first opening 111 provides space for the subsequent formation of the alignment structure.

[0054] The method for forming the first opening 111 includes: forming a second patterning layer 130 on the first mask structure 108, the second patterning layer 130 exposing the first mask structure 108 on the marking area A; using the first mask structure 108 as a mask, etching the first epitaxial structure 101 at the bottom of the first mask opening 109 to form the first opening 111.

[0055] Since the second patterning layer 130 covers the first mask structure 108 on the device region B, the structure of the device region B is protected from being affected when the first opening 111 is etched.

[0056] In this embodiment, the method for etching the first epitaxial structure 101 includes dry etching.

[0057] In this embodiment, the depth of the first opening 111 ranges from 0.5 micrometers to 1 micrometer. Specifically, if the depth of the first opening 111 is too large, it will result in uneven deposition of the subsequent alignment structure within the first opening 111; if the depth of the first opening 111 is too small, the regularity of the subsequently formed alignment structure will be poor, resulting in unclear alignment.

[0058] In this embodiment, during the etching of the first epitaxial structure 101, the thickness of the first mask structure 108 is reduced to a certain extent, but since the degree of thinning is small, it does not affect the function of the first mask structure 108 as a mask layer.

[0059] In this embodiment, the method for forming the semiconductor structure further includes: removing the second patterned layer 130 after forming the first opening 111. Specifically, the process for removing the second patterned layer 130 is an ashing process.

[0060] In this embodiment, after removing the second patterned layer 130, a cleaning process is performed to remove residual impurities from the etching process of the substrate.

[0061] Please refer to Figure 4 An alignment structure 112 is formed within the first opening 111.

[0062] In this embodiment, the alignment structure 112 provides raw materials for the subsequent formation of alignment marks.

[0063] Specifically, the method for forming the alignment structure 112 includes: forming a first initial dielectric layer (not shown) within the first epitaxial structure 101 and the first mask structure 108, wherein the first initial dielectric layer fills the first opening 111, the first mask opening 109, and the second mask opening 110; planarizing the first initial dielectric layer until the surface of the first mask structure 108 is exposed, and the first initial dielectric layer located on the marking region A forms the alignment structure 112.

[0064] In this embodiment, the alignment structure 112 is located within the first opening 111 and the first mask opening 109, such that the top surface of the alignment structure 112 is higher than the surface of the first epitaxial structure 101. Therefore, during the subsequent etching of the substrate of device region B to form the second opening, the alignment structure 112 located within the first mask opening 109 acts as an etching buffer layer, protecting the alignment structure 112 within the first opening 111 from the influence of the etching process.

[0065] In this embodiment, the formation process of the first initial dielectric layer includes: chemical vapor deposition, HARP, HDP or decomposition deposition, wherein the precursor used in the decomposition deposition process includes TEOS.

[0066] In this embodiment, the material of the first initial dielectric layer includes silicon oxide.

[0067] Since the material of the initial first dielectric layer is the same as the material of the second mask layer 107 on top of the first mask structure 108, the second mask layer 107 is removed simultaneously during the planarization of the first initial dielectric layer, thereby exposing the surface of the first mask layer 106.

[0068] The method for forming the semiconductor structure further includes: after forming the alignment structure 112, using the first mask structure 108 as a mask, etching the first initial dielectric layer located within the second mask opening 110 until the surface of the first epitaxial structure 101 is exposed. By removing the first initial dielectric layer within the second mask opening 110, subsequent etching of the first epitaxial structure 101 at the bottom of the second mask opening 110 can be better connected.

[0069] During the etching of the first initial dielectric layer within the second mask opening 110, the alignment structure 112 on the marking region A is simultaneously etched, thereby reducing the height of the alignment structure 112. In this process, the alignment structure 112 within the first mask opening 109 acts as an etching buffer layer, protecting the alignment structure 112 within the first opening 111 from the effects of the etching process.

[0070] In this embodiment, after the first opening 111 and the alignment structure 112 located within the first opening 111 are formed, the second opening and the isolation structure located within the second opening are formed.

[0071] Please refer to Figure 5 The substrate at the bottom of the second mask opening 110 is etched to form a second opening 114 in the device region B.

[0072] In this embodiment, the first opening 111 provides space for the formation of the subsequent isolation structure.

[0073] The method for forming the second opening 114 includes: after forming the alignment structure 112, using the first mask structure 108 as a mask, etching the first epitaxial structure 101 at the bottom of the second mask opening 110 to form the second opening 114, the second opening 114 exposing the surface of the substrate 100.

[0074] During the etching of the first epitaxial structure 101 at the bottom of the second mask opening 110, the alignment structure 112 within the first mask opening 109 is simultaneously etched, thereby further reducing the height of the alignment structure 112. Since the alignment structure 112 is made of a different material than the first epitaxial structure 101, the etching process has a high etching selectivity for both the alignment structure 112 and the first epitaxial structure 101. Therefore, the etching process has a limited impact on the alignment structure 112. Furthermore, the alignment structure 112 within the first mask opening 109 acts as an etching buffer layer, protecting the alignment structure 112 within the first opening 111 from the effects of the etching process and ensuring the structural integrity of the subsequently formed alignment marks. Therefore, in the process of forming the second opening 114, it is not necessary to form an additional mask layer to protect the alignment structure 112 on the marking region A. The second opening 114 located in the device region B can be formed by using only the first mask structure 108 as a mask without affecting the alignment structure 112 in the first opening 111. This eliminates the need for the preparation of the mask layer on the marking region A and simplifies the semiconductor structure formation process.

[0075] In this embodiment, during the etching of the first epitaxial structure 101, the thickness of the first mask structure 108 is reduced to a certain extent. However, since the etching process has a large selectivity between the first mask structure 108 and the first epitaxial structure 101, the reduction in the thickness of the first mask structure 108 does not affect the function of the first mask structure 108 as a mask layer.

[0076] In this embodiment, the depth of the second opening 114 ranges from 2 micrometers to 4 micrometers. The second opening 114 exposes the surface of the substrate 100, thereby facilitating the subsequent epitaxial growth of an isolation structure located within the second opening on the silicon substrate 100.

[0077] In this embodiment, the method for etching the first epitaxial structure 101 includes dry etching.

[0078] In this embodiment, after the second opening 114 is formed in the device region B, a cleaning process is performed to remove residual impurities from the etching process.

[0079] Please refer to Figure 6 An isolation structure 115 is formed within the second opening 114.

[0080] The method of forming the isolation structure 115 includes: forming an initial isolation material layer on the substrate 100 that fills the second opening 114 and the second mask opening 110; planarizing the initial isolation material layer until the surface of the first mask structure 108 is exposed to form the isolation structure 115. The isolation structure 115 is located within the second opening 114 and the second mask opening 110.

[0081] In this embodiment, the initial isolation material layer is higher than the top surface of the first mask structure 108, thereby achieving reverse wrapping of the top surface of the first mask structure 108 on the device region B. This ensures that the second opening 114 is completely filled by the initial isolation material layer, making the formed isolation structure 115 more uniform.

[0082] In this embodiment, the material of the isolation structure 115 includes p-type doped silicon. The initial isolation material layer is formed by an epitaxial growth process.

[0083] Since the isolation structure 115 on device region B is formed on the silicon substrate 100 through an epitaxial growth process, and the material of the alignment structure 112 on marker region A is silicon oxide, the formation process of the isolation structure 115 has no effect on the alignment structure 112. Therefore, it is not necessary to form an additional protective layer on marker region A, and the isolation structure 115 located in device region B can be formed without affecting the alignment structure 112.

[0084] Therefore, in this embodiment, by utilizing the same hard mask structure, namely, the first mask structure 108 forms the alignment structure 112 located in the marking region A and the isolation structure 115 located in the device region B respectively in the substrate, the number of times the mask structure is formed on the surface of the marking region A and the device region B is reduced, the formation process of the isolation structure 115 and the alignment structure 112 is simplified, thereby improving the reliability of the semiconductor fabrication process and improving the performance of the semiconductor device.

[0085] In this embodiment, the isolation structure 115 is formed after the alignment structure 112 is formed. In another embodiment, the first opening and the alignment structure located within the second opening are formed after the second opening and the isolation structure located within the second opening are formed.

[0086] Please refer to Figure 7 After forming the alignment structure 112 and the isolation structure 115, the first mask structure 108 is removed.

[0087] Since the alignment structure 112 and the isolation structure 115 are made of different materials than the first mask structure 108, after the first mask structure 108 is removed, the alignment structure 112 in the first mask opening 109 and the isolation structure 115 in the second mask opening 110 are retained, so that the top surface of the alignment structure 112 and the top surface of the isolation structure 115 are higher than the top surface of the substrate.

[0088] In this embodiment, the method for removing the first mask structure 108 includes wet etching or dry etching.

[0089] Please continue to refer to this. Figure 7 After removing the first mask structure 108, the alignment structure 112 and the isolation structure 115 are planarized to form alignment marks 120 and deep trench device layer 121, which are flush with the top surface of the substrate.

[0090] The alignment mark 120 is used to provide positioning identification for subsequent active area processes. Compared with traditional unfilled shallow trench alignment marks, the alignment mark 120 filled in the first opening 111 in this embodiment has a more regular morphology, thus providing higher alignment accuracy; secondly, the material of the alignment mark 120 is silicon oxide, which provides higher contrast during the alignment process, thus providing clearer positioning identification for subsequent active area processes; thirdly, the presence of the alignment mark 120 reduces the risk of mechanical polishing and optimizes the flatness of the substrate surface.

[0091] The method for planarizing the alignment structure 112 and the isolation structure 115 includes: after removing the first mask structure 108, etching the alignment structure 112 until a portion of the alignment structure 112 above the top surface of the substrate is removed; after etching the alignment structure 112, performing chemical mechanical polishing on the alignment structure 112 and the isolation structure 115 to form alignment marks 120 and a deep trench device layer 121.

[0092] In this embodiment, since the alignment structure 112 is made of a material with high hardness, the portion of the alignment structure 112 above the top surface of the substrate is removed before chemical mechanical polishing, thereby improving the effect of the chemical mechanical polishing and optimizing the surface flatness of the substrate, alignment mark 120 and deep trench device layer 121.

[0093] In this embodiment, the method of etching the alignment structure 112 includes wet etching.

[0094] In this embodiment, since the material of the alignment structure 112 has a high hardness, the surface of the alignment mark 120 formed after the alignment structure 112 is chemically mechanically polished is slightly raised.

[0095] Please refer to Figure 8 After forming the alignment mark 120 and the deep trench device layer 121, a second epitaxial structure 122 is formed on the substrate, the second epitaxial structure 122 exposing the alignment mark 120.

[0096] The second epitaxial structure 122 is used to connect to subsequent CMOS processes. The second epitaxial structure 122 has a third opening 123 that exposes the alignment mark 120. The presence of the third opening 123 creates a height difference between the top surface of the alignment mark 120 and the top surface of the second epitaxial structure 122. Therefore, the third opening 123 and the alignment mark 120 work together to provide a clear alignment mark for subsequent active region processes.

[0097] In this embodiment, the material of the second epitaxial structure 122 includes silicon or p-type doped silicon. The second epitaxial structure 122 is formed by an epitaxial growth process. Specifically, the second epitaxial structure 122 is formed on the third epitaxial layer 104 of the first epitaxial structure 101. Since the material of the third epitaxial layer 104 is n-type doped silicon, the second epitaxial structure 122 is formed by epitaxial growth on the surface of the third epitaxial layer 104.

[0098] Since the second epitaxial structure 122 is formed by an epitaxial growth process, and the alignment mark 120 is made of silicon oxide, the area above the alignment mark 120 is unaffected by the epitaxial growth process during the formation of the second epitaxial structure 122. This results in the second epitaxial structure 122 having a third opening 123 located on the alignment mark 120. The presence of the alignment mark 120 helps the third opening 123 maintain a more regular morphology, thereby giving the alignment mark 120 higher alignment accuracy and providing a clearer positioning marker for subsequent active region processes. Furthermore, since the substrate, alignment mark 120, and deep trench device layer 121 have good surface flatness, the second epitaxial structure 122 grown on the substrate surface is more uniform, resulting in better surface flatness of the second epitaxial structure 122.

[0099] In this embodiment, the thickness of the second epitaxial structure 122 is 3000 angstroms to 5000 angstroms.

[0100] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application relates to a method for manufacturing a semiconductor device. The method comprises the following steps: providing a substrate, which comprises a mark area and a device area; forming a first mask structure on the substrate, the first mask structure having a first mask opening exposing part of the mark area and a second mask opening exposing part of the device area; etching the substrate at the bottom of the first mask opening to form a first opening in the mark area; forming an alignment structure in the first opening; etching the substrate at the bottom of the second mask opening to form a second opening in the device area; forming an isolation structure in the second opening; wherein the alignment structure is also located in the first mask opening; 2. The method of forming a semiconductor structure of claim 1, wherein, during the forming of the second opening, the alignment structure in the first mask opening acts as an etching buffer layer to protect the alignment structure in the first opening from the etching process.

3. The method of forming a semiconductor structure of claim 2, wherein, The substrate comprises a base and a first epitaxial structure on the base.

4. The method of forming a semiconductor structure of claim 2, wherein, The first epitaxial structure comprises a first epitaxial layer on the base, a second epitaxial layer on the first epitaxial layer and a third epitaxial layer on the second epitaxial layer.

5. The method of forming a semiconductor structure of claim 3, wherein, The thickness of the first epitaxial structure ranges from 2 microns to 4 microns.

6. The method of forming a semiconductor structure of claim 1, wherein, The material of the third epitaxial layer comprises N-doped silicon.

7. The method of forming a semiconductor structure of claim 6, wherein, The forming method of the first mask structure comprises the following steps: forming an initial first mask structure on the substrate, forming a first patterning layer on the initial first mask structure, the first patterning layer exposing part of the initial first mask structure surface on the mark area and part of the initial first mask structure surface on the device area; and etching the initial first mask structure with the patterning layer as a mask to form the first mask structure, the first mask structure having the first mask opening exposing part of the mark area and the second mask opening exposing part of the device area.

8. The method of forming a semiconductor structure of claim 1, wherein, The initial first mask structure comprises an initial pad oxygen layer on the substrate, an initial first mask layer on the initial pad oxygen layer and an initial second mask layer on the initial first mask layer.

9. The method of forming a semiconductor structure of claim 7, wherein, The thickness of the first mask structure ranges from 2000 angstroms to 4000 angstroms.

10. The method of forming a semiconductor structure of claim 2, wherein, The material of the initial first mask layer comprises silicon nitride and the material of the initial second mask layer comprises silicon oxide.

11. The method of forming a semiconductor structure of claim 10, wherein, After the forming of the first opening and the alignment structure in the first opening, the second opening and the isolation structure in the second opening are formed.

12. The method of forming a semiconductor structure of claim 11, wherein, The forming method of the first opening comprises the following steps: forming a second patterning layer on the first mask structure, the second patterning layer exposing the first mask structure on the mark area; and etching the first epitaxial structure at the bottom of the first mask opening with the first mask structure as a mask to form the first opening. The depth of the first opening ranges from 0.5 microns to 1 micron.

13. The method of forming a semiconductor structure of claim 10, wherein, The method for forming the alignment structure comprises: forming a first initial dielectric layer in the first epitaxial structure and in the first mask structure, the first initial dielectric layer filling the first opening, the first mask opening and the second mask opening; planarizing the first initial dielectric layer until the surface of the first mask structure is exposed, the first initial dielectric layer on the mark area forming an alignment structure.

14. The method of forming a semiconductor structure of claim 13, wherein, The material of the first initial dielectric layer comprises silicon oxide.

15. The method of forming a semiconductor structure of claim 13, wherein, After the alignment structure is formed, before the second opening is formed, the method further comprises: etching the first initial dielectric layer in the second mask opening until the surface of the first epitaxial structure is exposed, with the first mask structure as a mask.

16. The method of forming a semiconductor structure of claim 10, wherein, The method for forming the second opening comprises: etching the first epitaxial structure at the bottom of the second mask opening to form a second opening exposing the surface of the substrate, with the first mask structure as a mask after the alignment structure is formed.

17. The method of forming a semiconductor structure of claim 10, wherein, The material of the isolation structure comprises P-type doped silicon, and the material of the substrate comprises silicon.

18. The method of forming a semiconductor structure of claim 17, wherein, The method for forming the isolation structure comprises: forming an initial isolation material layer filling the second opening and the second mask opening on the substrate; planarizing the initial isolation material layer until the surface of the first mask structure is exposed to form the isolation structure.

19. The method of forming a semiconductor structure of claim 18, wherein, The forming process of the initial isolation material layer is epitaxial growth process.

20. The method of forming a semiconductor structure of claim 1, wherein, The method further comprises: After the alignment structure and the isolation structure are formed, the first mask structure is removed; After the first mask structure is removed, the alignment structure and the isolation structure are planarized to form an alignment mark and a deep trench device layer, the alignment mark and the deep trench device layer being flush with the top surface of the substrate.

21. The method of forming a semiconductor structure of claim 20, wherein, The method for planarizing the alignment structure and the isolation structure comprises: etching the alignment structure until the part of the alignment structure higher than the top surface of the substrate is removed; after the alignment structure is etched, the alignment structure and the isolation structure are subjected to chemical mechanical polishing to form an alignment mark and a deep trench device layer.

22. The method of forming a semiconductor structure of claim 21, wherein, The method for etching the alignment structure comprises wet etching.

23. The method of forming a semiconductor structure of claim 20, wherein, After the alignment mark and the deep trench device layer are formed, the method further comprises: forming a second epitaxial structure on the substrate, the second epitaxial structure exposing the alignment mark.

24. The method of forming a semiconductor structure of claim 1, wherein, After the second opening and the isolation structure in the second opening are formed, the first opening and the alignment structure in the first opening are formed.

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