Fan-out wafer-level packaging structure and packaging method for infrared thermopile chips

Abstract

The present invention provides a fan-out wafer-level packaging structure and packaging method for an infrared thermopile chip. The structure includes: an infrared thermopile chip having a solder pad; a first infrared-transparent substrate, the infrared thermopile chip being bonded to a groove in the first substrate; a second infrared-transparent substrate bonded to the first substrate; a metal connection column extending through the second substrate and connected to the solder pad; a rewiring layer formed on the second substrate, electrically connected to the metal connection column, the rewiring layer having an opening area facing the photosensitive area of ​​the infrared thermopile chip; and metal bumps formed on the rewiring layer. By simultaneously bonding multiple infrared thermopile chips to the same substrate and then packaging them into a fan-out wafer-level package, the package size is greatly reduced, saving packaging costs. Furthermore, both the first and second substrates are made of infrared-transparent materials, enabling double-sided light transmission of the package, thereby increasing the package's application range and flexibility.

Description

Technical Field

[0001] The present invention belongs to the technical field of packaging of infrared thermopile chips, and in particular relates to a fan-out wafer-level packaging structure and a packaging method for infrared thermopile chips. Background Art

[0002] Infrared thermopile chips are semiconductor structures composed of thermocouples that convert temperature differences into electrical energy. When a temperature difference occurs across the thermopile, it generates a current that can be used to measure temperature. Currently, they are widely used as temperature sensing devices in fields such as ear thermometers, radiation thermometers, electric ovens, and food temperature monitoring.

[0003] Infrared thermopile chips currently utilize a TO package (through-hole package). This package structure features a metal cover with a hole at the front end, which is then filled with an appropriate infrared-transmitting material. However, this metal transistor package is complex to manufacture, bulky, and expensive, limiting its application. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a fan-out wafer-level packaging structure and packaging method for an infrared thermopile chip, so as to solve the problems in the prior art that the packaging structure formed by the infrared thermopile chip using the TO packaging form is large in size and expensive.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a fan-out wafer-level packaging method for an infrared thermopile chip, the packaging method comprising:

[0006] Providing an infrared thermopile chip having a bonding pad and a first substrate that transmits infrared light, and etching a groove in the first substrate;

[0007] placing the infrared thermopile chip in the groove and bonding it to the first substrate, wherein the thickness of the infrared thermopile chip is no greater than the depth of the groove;

[0008] Providing a second substrate that is transparent to infrared light and bonding it to the first substrate carrying the infrared thermopile chip;

[0009] Etching the second substrate to form a through hole exposing the pad, and forming a metal connecting column in the through hole;

[0010] forming a redistribution layer on the second substrate, wherein the metal connection column is electrically connected to the redistribution layer, and the redistribution layer has an opening area, and the opening area is directly opposite to the photosensitive area of ​​the infrared thermopile chip;

[0011] Metal bumps are formed on the redistribution layer.

[0012] Optionally, the first substrate is made of silicon or germanium, and the second substrate is made of silicon or germanium.

[0013] Optionally, the thickness of the first substrate is between 400 μm and 700 μm, and the thickness of the second substrate is between 400 μm and 700 μm.

[0014] Optionally, the infrared thermopile chip is bonded into the groove of the first substrate using a surface mounting process.

[0015] Optionally, the step of forming the rewiring layer includes:

[0016] forming a dielectric layer on the surface of the second substrate by a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form a patterned dielectric layer, wherein the patterned dielectric layer has an opening area, and the opening area is directly opposite to the photosensitive area of ​​the infrared thermopile chip;

[0017] A metal wiring layer is formed on the surface of the patterned dielectric layer by a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or an electroless plating process, and the metal wiring layer is etched to form a patterned metal wiring layer, and the metal connecting column is electrically connected to the patterned metal wiring layer.

[0018] The present invention also provides a fan-out wafer-level packaging structure of an infrared thermopile chip, the packaging structure comprising:

[0019] an infrared thermopile chip having a bonding pad;

[0020] a first substrate transparent to infrared light, wherein the first substrate has a groove, the infrared thermopile chip is placed in the groove and bonded to the first substrate, and the thickness of the infrared thermopile chip is no greater than the depth of the groove;

[0021] A second substrate that is transparent to infrared light and is bonded to the first substrate carrying the infrared thermopile chip;

[0022] a metal connecting column, passing through the second substrate and connected to the bonding pad;

[0023] a redistribution layer formed on the second substrate and electrically connected to the metal connection column to achieve electrical extraction of the pad, wherein the redistribution layer has an opening area, and the opening area faces the photosensitive area of ​​the infrared thermopile chip;

[0024] Metal bumps are formed on the rewiring layer.

[0025] Optionally, the first substrate is made of silicon or germanium, and the second substrate is made of silicon or germanium.

[0026] Optionally, the thickness of the first substrate is between 400 μm and 700 μm, and the thickness of the second substrate is between 400 μm and 700 μm.

[0027] Optionally, the rewiring layer includes a dielectric layer and a metal wiring layer, the material of the dielectric layer includes one or more combinations of the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or more combinations of the group consisting of copper, aluminum, nickel, gold, silver and titanium.

[0028] Optionally, the metal bump includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball; or the metal bump includes a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.

[0029] As described above, the fan-out wafer-level packaging structure and packaging method of the infrared thermopile chip of the present invention can realize the packaging of multiple infrared thermopile chips at the same time by simultaneously bonding multiple infrared thermopile chips to the same substrate and then packaging them into a fan-out wafer-level package, thereby greatly reducing the package size and saving packaging costs. In addition, the first substrate and the second substrate are both made of materials that are transparent to infrared light, which can achieve double-sided light transmission of the package body. When in use, the light-transmitting surface of the package body can be flexibly selected according to the specific usage situation, thereby improving the application range and application flexibility of the package body. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 7 It is a schematic cross-sectional structure diagram showing each step of the fan-out wafer-level packaging method of the infrared thermopile chip according to the second embodiment of the present invention, wherein: Figure 7 Also shown is a cross-sectional schematic diagram of the fan-out wafer-level packaging structure of the infrared thermopile chip according to the first embodiment of the present invention.

[0031] Component number description

[0032] 100 infrared thermopile chips

[0033] 101 solder pad

[0034] 102 First Base

[0035] 103 grooves

[0036] 104 Second Base

[0037] 105 adhesive layer

[0038] 106 through holes

[0039] 107 Metal connecting column

[0040] 108 Rewiring Layer

[0041] 109 dielectric layer

[0042] 110 Metal Wiring Layer

[0043] 111 Opening Area

[0044] 112 metal bumps

[0045] A Photosensitive area DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] See also Figures 1 to 7 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0048] Example 1

[0049] like Figure 7 As shown, this embodiment provides a fan-out wafer-level packaging structure of an infrared thermopile chip, the packaging structure comprising:

[0050] An infrared thermopile chip 100 having a bonding pad 101;

[0051] a first substrate 102 that is transparent to infrared light, wherein the first substrate 102 has a groove 103 therein, the infrared thermopile chip 100 is placed in the groove 103 and bonded to the first substrate 102, and the thickness of the infrared thermopile chip 100 is no greater than the depth of the groove 103;

[0052] A second substrate 104 that is transparent to infrared light and is bonded to the first substrate 102 carrying the infrared thermopile chip 100;

[0053] a metal connecting column 107 , passing through the second substrate 104 and connected to the bonding pad 101 ;

[0054] A redistribution layer 108 is formed on the second substrate 104 and electrically connected to the metal connection pillars 107 to enable electrical extraction of the pads 101. The redistribution layer 108 has an opening 111 that faces the photosensitive area A of the infrared thermopile chip 100 and is configured to receive incident infrared light.

[0055] The metal bumps 11 are formed on the rewiring layer 108 .

[0056] The infrared thermopile chip packaging method of this embodiment realizes fan-out wafer-level packaging by simultaneously bonding multiple infrared thermopile chips to the same substrate and then packaging them. This can simultaneously realize the packaging of multiple infrared thermopile chips, greatly reducing the package size and saving packaging costs. In addition, the first substrate and the second substrate are both made of infrared light-transmissive materials, which can achieve double-sided light transmission of the package body. During use, the light-transmissive surface of the package body can be flexibly selected according to the specific usage situation, thereby improving the application range and application flexibility of the package body.

[0057] The first substrate 102 and the second substrate 104 can be made of any suitable material, as long as the material can provide support and filter infrared light. As an example, the material of the first substrate 102 can be silicon or germanium, and the material of the first substrate 104 can be silicon or germanium. In this embodiment, the material of the first substrate 102 is preferably silicon, and the material of the second substrate 104 is preferably silicon.

[0058] As an example, the thickness of the first substrate 102 may be selected to be between 400 μm and 700 μm, and the thickness of the second substrate 104 may be selected to be between 400 μm and 700 μm.

[0059] like Figure 7 As shown, as an example, the rewiring layer 108 includes a dielectric layer 109 and a metal wiring layer 110, and the material of the dielectric layer 109 includes one or more combinations of the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer 110 includes one or more combinations of the group consisting of copper, aluminum, nickel, gold, silver and titanium.

[0060] like Figure 7 As shown, as an example, the material of the solder pad 101 of the infrared thermopile chip 100 includes metal aluminum, which is an aluminum solder pad. In order to improve the electrical performance of the solder pad 101 and the bonding performance with the infrared thermopile chip 100, an adhesive layer can be formed under the solder pad 101 and an anti-reflection layer can be formed on the solder pad 101.

[0061] like Figure 7As shown, as an example, the metal bump 112 includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball, or the metal bump includes a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer. In this embodiment, the metal bump 112 is preferably a gold-tin solder ball.

[0062] Example 2

[0063] This embodiment provides a fan-out wafer-level packaging method for an infrared thermopile chip. This packaging method can be used to prepare the fan-out wafer-level packaging structure of the infrared thermopile chip described in the first embodiment. However, the preparation of the packaging structure of the first embodiment is not limited to the method of this embodiment. This embodiment only illustrates a relatively typical packaging method for preparing the fan-out wafer-level packaging structure of the infrared thermopile chip described in the first embodiment. The packaging method includes:

[0064] like Figure 1 and Figure 2 As shown, step 1) is first performed to provide an infrared thermopile chip 100 having a bonding pad 101 and a first substrate 102 that transmits infrared light, and to etch a groove 103 in the first substrate 102 .

[0065] The first substrate 102 can be made of any suitable material as long as it can provide support and filter infrared light. For example, the material of the first substrate 102 can be silicon or germanium. In this embodiment, silicon is preferably used as the material of the first substrate 102.

[0066] As an example, the thickness of the first substrate 102 may be selected to be between 400 μm and 700 μm, and the thickness of the second substrate 104 may be selected to be between 400 μm and 700 μm.

[0067] As an example, the material of the bonding pad 101 in the infrared thermopile chip 100 includes aluminum, thus forming an aluminum bonding pad. When preparing the bonding pad 101, to improve the electrical performance of the bonding pad 101 and the bonding performance with the infrared thermopile chip 100, an adhesive layer may be formed under the bonding pad 101, and an anti-reflection layer may be formed on the bonding pad 101.

[0068] The groove 103 can be formed using an existing conventional etching process, such as dry etching or wet etching. Since the infrared thermopile chip 100 will be placed in the groove 103 later, the size of the groove 103 is set with reference to the infrared thermopile chip 100. The size of the groove 103 can be adapted to the size of the infrared thermopile chip 100 or slightly larger than the size of the infrared thermopile chip 100.

[0069] like Figure 2As shown, step S2 is then performed to place the infrared thermopile chip 100 in the groove 103 and bond it to the first substrate 102 . The thickness of the infrared thermopile chip 100 is not greater than the depth of the groove 103 .

[0070] As an example, the infrared thermopile chip 100 may be bonded to the groove 103 of the first substrate 102 using a surface mount process. When bonding the infrared thermopile chip 100 to the groove 103, the side of the infrared thermopile chip 100 with the solder pad 101 is bonded upward.

[0071] like Figure 3 As shown, step S3 is then performed to provide a second substrate 104 that is transparent to infrared light and bond it to the first substrate 102 carrying the infrared thermopile chip 100 .

[0072] The second substrate 104 can be made of any suitable material as long as it can provide support and filter infrared light. For example, the second substrate 104 can be made of silicon or germanium. In this embodiment, silicon is preferably used as the material for the second substrate 104.

[0073] The bonding of the first substrate 102 and the second substrate 104 can be achieved by using existing conventional bonding methods. In this embodiment, an adhesive layer 105 is formed on the surface of the first substrate 102 and the sidewalls of the groove 103; the adhesive layer 105 is then patterned to expose the bonding pad 101 and the photosensitive area A of the infrared thermopile chip 100; finally, the second substrate 104 is placed on the adhesive layer 105 and hot-pressed to bond with the first substrate 102.

[0074] like Figure 4 and Figure 5 As shown, the next step is to perform step S4), etching the second substrate 104 to form a through hole 106 (as shown in FIG. Figure 4 ), and forming a metal connecting column 107 in the through hole 106 (as shown Figure 5 shown).

[0075] The metal connecting studs 107 may be made of at least one of gold, silver, aluminum, and copper. It is foreseeable that the metal connecting studs 107 are not limited thereto and may be any other low-resistance material. Methods for forming the metal connecting studs 107 include, but are not limited to, electroplating, chemical plating, physical vapor deposition, and chemical vapor deposition.

[0076] like Figure 6As shown, step S5 is then performed to form a redistribution layer 108 on the second substrate 104. The metal connection column 107 is electrically connected to the redistribution layer 108, and the redistribution layer 108 has an opening area 111. The opening area 111 is opposite to the photosensitive area A of the infrared thermopile chip 100.

[0077] As an example, the rewiring layer 108 includes a dielectric layer 109 and a metal wiring layer 110, and the material of the dielectric layer 109 includes one or more combinations of the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer 110 includes one or more combinations of the group consisting of copper, aluminum, nickel, gold, silver and titanium.

[0078] As an example, forming the rewiring layer 108 includes the following steps: first, forming a dielectric layer 109 on the second substrate 104 using a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer 109 to form a patterned dielectric layer 109, wherein the patterned dielectric layer 109 has an opening area 111, and the opening area 111 is directly opposite the photosensitive area A of the infrared thermopile chip 100; then, forming a metal wiring layer 110 on the surface of the patterned dielectric layer 109 using a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or an electroless plating process, and etching the metal wiring layer 110 to form a patterned metal wiring layer 110, and the metal connection column 107 is electrically connected to the patterned metal wiring layer 110. It should be noted that the material, number of layers, and distribution morphology of the dielectric layer 109 and the metal wiring layer 110 can be set according to the specific situation of the infrared thermopile chip 100 and are not limited here.

[0079] like Figure 7 As shown, step S6 is finally performed to form metal bumps 112 on the redistribution layer 108 .

[0080] As an example, the metal bumps 112 include one of gold-tin solder balls, silver-tin solder balls, and copper-tin solder balls, or the metal bumps 112 include metal pillars and solder balls formed on the metal pillars. Preferably, the metal pillars are copper pillars or nickel pillars. In this embodiment, the metal bumps 112 are gold-tin solder balls, and the steps of manufacturing the gold-tin solder balls include: first forming a gold-tin layer on the surface of the redistribution layer 108, then reflowing the gold-tin layer into balls using a high-temperature reflow process, and then cooling the gold-tin solder balls; or forming the gold-tin solder balls using a ball planting process.

[0081] In summary, the present invention provides a fan-out wafer-level packaging structure and packaging method for infrared thermopile chips. By simultaneously bonding multiple infrared thermopile chips to the same substrate and then packaging them into a fan-out wafer-level package, multiple infrared thermopile chips can be packaged simultaneously, significantly reducing the package size and saving packaging costs. In addition, both the first substrate and the second substrate are made of infrared light-transmissive materials, which enables double-sided light transmission of the package. During use, the light-transmissive surface of the package can be flexibly selected according to the specific usage situation, thereby increasing the application range and application flexibility of the package. Therefore, the present invention effectively overcomes the various shortcomings of the existing technology and has high industrial application value.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A fan-out wafer-level packaging method for an infrared thermopile chip, characterized in that: The packaging method comprises: Providing an infrared thermopile chip having a bonding pad and a first substrate that transmits infrared light, and etching a groove in the first substrate; placing the infrared thermopile chip in the groove and bonding it to the first substrate, wherein the thickness of the infrared thermopile chip is no greater than the depth of the groove; Providing a second substrate that is transparent to infrared light and bonding it to the first substrate carrying the infrared thermopile chip; Etching the second substrate to form a through hole exposing the pad, and forming a metal connecting column in the through hole; forming a redistribution layer on the second substrate, wherein the metal connection column is electrically connected to the redistribution layer, and the redistribution layer has an opening area, and the opening area is directly opposite to the photosensitive area of ​​the infrared thermopile chip; Metal bumps are formed on the redistribution layer.

2. The fan-out wafer-level packaging method for infrared thermopile chips according to claim 1, characterized in that: The material of the first substrate is silicon or germanium, and the material of the second substrate is silicon or germanium.

3. The fan-out wafer-level packaging method for infrared thermopile chips according to claim 2, wherein: The thickness of the first substrate is between 400 μm and 700 μm, and the thickness of the second substrate is between 400 μm and 700 μm.

4. The fan-out wafer-level packaging method for infrared thermopile chips according to claim 1, wherein: The infrared thermopile chip is bonded to the groove of the first substrate using a surface mounting process.

5. The fan-out wafer-level packaging method for infrared thermopile chips according to claim 1, wherein: The step of forming the rewiring layer includes: forming a dielectric layer on the surface of the second substrate by a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form a patterned dielectric layer, wherein the patterned dielectric layer has an opening area, and the opening area is directly opposite to the photosensitive area of ​​the infrared thermopile chip; A metal wiring layer is formed on the surface of the patterned dielectric layer by a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or an electroless plating process, and the metal wiring layer is etched to form a patterned metal wiring layer, and the metal connecting column is electrically connected to the patterned metal wiring layer.

6. A fan-out wafer-level packaging structure for an infrared thermopile chip, characterized in that: The packaging structure includes: an infrared thermopile chip having a bonding pad; a first substrate transparent to infrared light, wherein the first substrate has a groove, the infrared thermopile chip is placed in the groove and bonded to the first substrate, and the thickness of the infrared thermopile chip is no greater than the depth of the groove; A second substrate that is transparent to infrared light and is bonded to the first substrate carrying the infrared thermopile chip; a metal connecting column, passing through the second substrate and connected to the bonding pad; a redistribution layer formed on the second substrate and electrically connected to the metal connection column to achieve electrical extraction of the pad, wherein the redistribution layer has an opening area, and the opening area faces the photosensitive area of ​​the infrared thermopile chip; Metal bumps are formed on the rewiring layer.

7. The fan-out wafer-level packaging structure of the infrared thermopile chip according to claim 6, characterized in that: The material of the first substrate is silicon or germanium, and the material of the second substrate is silicon or germanium.

8. The fan-out wafer-level packaging structure of the infrared thermopile chip according to claim 7, characterized in that: The thickness of the first substrate is between 400 μm and 700 μm, and the thickness of the second substrate is between 400 μm and 700 μm.

9. The fan-out wafer-level packaging structure of the infrared thermopile chip according to claim 6, characterized in that: The rewiring layer includes a dielectric layer and a metal wiring layer, and the material of the dielectric layer includes one or more combinations of the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or more combinations of the group consisting of copper, aluminum, nickel, gold, silver and titanium.

10. The fan-out wafer-level packaging structure of the infrared thermopile chip according to claim 6, characterized in that: The metal bump includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball; or the metal bump includes a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.

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