Semiconductor package with chip carrier featuring pad offset characteristics

Abstract

This invention relates to a semiconductor package having a chip carrier with pad offset features. A semiconductor package includes: a carrier having an electrically insulating body and a first contact structure at a first side of the electrically insulating body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at a source or emitter potential. The first pad is spaced inwardly from the edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inwardly from the edge of the semiconductor die by a second distance greater than the first distance, such that an electric field emitted from the edge termination region in the direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. A method of manufacturing is also provided.

Description

Technical Field

[0001] The present invention relates generally to semiconductor packaging, and particularly to semiconductor packaging having a chip carrier with pad offset features. Background Technology

[0002] Cooling semiconductor packages is a challenge for power applications. This challenge is amplified for high-temperature compound semiconductors such as GaN and SiC. Without adequate cooling, the full performance and potential of compound semiconductors cannot be realized. Cooling performance is limited by the amount of metal (e.g., Cu) in the semiconductor package and the interconnect area / technology at the die-on-chip interface.

[0003] Chip-to-package ratio is another parameter that is often not optimized, especially for high-voltage applications where creepage distance requirements tend to lead to larger packages. This problem is even more pronounced for compound semiconductors such as GaN and SiC, where chip size can be reduced at higher efficiencies. However, creepage distances must be maintained. This results in a chip-to-package ratio that is less than optimal.

[0004] Therefore, there is a need for a power semiconductor packaging technology that provides better cooling and chip-to-package ratio. Summary of the Invention

[0005] According to an embodiment of a semiconductor package, the semiconductor package includes: a carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite to the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having dimensions independent of the dimensions of the carrier, but based on the expected thermal load presented by the semiconductor die; and a sealant defined by the carrier and the metal plate and laterally surrounding the edge of the semiconductor die.

[0006] According to an embodiment of the method, the method includes: providing a carrier sheet having a plurality of carriers interconnected with each other, each carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; attaching a semiconductor die to each of the carriers, each semiconductor die having a first side and a second side opposite to the first side, the first side of each semiconductor die having a plurality of pads attached to the plurality of contact structures corresponding to the first side of the carrier; after attaching the semiconductor die, slicing the carrier sheet into separate partial packages, each of the partial packages including one carrier and a pad attached to the first side of the carrier. The semiconductor die of the carrier; attaching a metal sheet to a second side of the partially packaged semiconductor die, the partially packaged portions being interconnected by the metal sheet; dispensing a sealant onto the metal sheet and around the edge of each semiconductor die in the semiconductor die; curing the sealant; and cutting the metal sheet between adjacent semiconductor dies to form an entire semiconductor package, each of the entire semiconductor packages having a metal plate cut from the metal sheet, and the size of the metal plate being independent of the size of the carrier included in the entire semiconductor package and based on the expected thermal load presented by the semiconductor dies included in the entire semiconductor package.

[0007] According to another embodiment of a semiconductor package, the semiconductor package includes: a carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; a vertical power semiconductor die having a first side and a second side opposite to the first side, the first side of the vertical power semiconductor die having a source pad and a gate pad, the source pad being attached to one or more first contact structures in the contact structures at the first side of the carrier, the gate pad being attached to a second contact structure in the contact structures at the first side of the carrier, the second side of the vertical power semiconductor die having a drain pad; a substrate having a first patterned metal body at the first side of an electrically insulating substrate and a second patterned metal body at the second side of the electrically insulating substrate opposite to the first side, the first patterned metal body being attached to the drain pad at the second side of the vertical power semiconductor die, the substrate having dimensions independent of the dimensions of the carrier, but based on the expected thermal load presented by the vertical power semiconductor die; and a sealant defined by the carrier and the substrate and laterally surrounding the edge of the vertical power semiconductor die.

[0008] According to another embodiment of a semiconductor package, the semiconductor package includes: a carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite to the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die; and a sealant defined by the carrier and the metal plate and laterally surrounding the edge of the semiconductor die, wherein the dimension of the metal plate in a first direction parallel to a two-dimensional plane of the metal plate and the carrier is greater than the dimension of the carrier in the first direction, and wherein the dimension of the metal plate in a second direction perpendicular to the first direction in the two-dimensional plane is greater than or less than the dimension of the carrier in the second direction.

[0009] According to another embodiment of a semiconductor package, the semiconductor package includes: a carrier having an electrically insulating body and a first contact structure on a first side of the electrically insulating body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at a source or emitter potential, wherein the first pad is spaced inwardly from the edge of the semiconductor die by a first distance, wherein the semiconductor die has an edge termination region between the edge and the first pad, and wherein the first contact structure of the carrier is spaced inwardly from the edge of the semiconductor die by a second distance greater than the first distance, such that an electric field emitted from the edge termination region in the direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

[0010] According to an embodiment of a method for manufacturing a semiconductor package, the method includes: providing a carrier having an electrically insulating body and a first contact structure at a first side of the electrically insulating body; and attaching a first pad of a semiconductor die to the first contact structure of the carrier, the first pad being at a source or emitter potential, wherein the first pad is spaced inwardly from an edge of the semiconductor die by a first distance, wherein the semiconductor die has an edge termination region between the edge and the first pad, and wherein the first contact structure of the carrier is spaced inwardly from the edge of the semiconductor die by a second distance greater than the first distance, such that an electric field emitted from the edge termination region in the direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0012] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are shown in the accompanying drawings and described in detail in the following description.

[0013] Figure 1 A cross-sectional view of a semiconductor package is shown.

[0014] Figures 2A to 2C A different view of another embodiment of a semiconductor package is shown.

[0015] Figure 3A A plan view of an embodiment of a lateral power semiconductor die is shown.

[0016] Figure 3B It shows the use of housing Figure 3A A perspective view of the corresponding contact structure layout of the chip carrier of a lateral power semiconductor die.

[0017] Figures 4A to 4C A perspective view of the chip carrier at different assembly levels is shown.

[0018] Figures 5 to 8 A corresponding cross-sectional view of a semiconductor package according to an additional embodiment is shown.

[0019] Figure 9A and 9B A method for manufacturing semiconductor packages is shown.

[0020] Figure 10 It shows in Figure 9A and 9B A plan view of an embodiment of the metal sheet used in the method.

[0021] Figure 11 It shows in Figure 9A and 9B A plan view of another embodiment of the metal sheet used in the method.

[0022] Figure 12 A cross-sectional view of a semiconductor package with a chip carrier featuring pad offset characteristics is shown.

[0023] Figure 13 A cross-sectional view of another semiconductor package with a chip carrier featuring pad offset characteristics is shown.

[0024] Figure 14 A cross-sectional view of another semiconductor package with a chip carrier featuring pad offset characteristics is shown.

[0025] Figure 15 A cross-sectional view of another semiconductor package with a chip carrier featuring pad offset characteristics is shown. Detailed Implementation

[0026] The embodiments described herein provide a semiconductor package including a die carrier and a metal plate, the size of which is independent of the die carrier size, but instead based on the expected thermal load presented by each semiconductor die attached to the die carrier. The terms "die" and "chip" are used interchangeably herein to refer to an electronic device or circuit formed on a piece of semiconductor material. The metal plate may have a larger footprint and / or different dimensions than the die carrier. The die carrier is often more expensive than the metal plate, therefore the size of the die carrier may be limited to reduce the overall cost of the package without adversely affecting the design and size of the metal plate. Therefore, the dimensions of the die carrier and the metal plate are independent, and the metal plate can be designed to optimize the thermal performance of the semiconductor package.

[0027] Next, exemplary embodiments of the power semiconductor module will be described with reference to the accompanying drawings.

[0028] Figure 1 A cross-sectional view of a semiconductor package 100 is shown. The semiconductor package 100 includes a chip carrier 102 having a first side 104 and a second side 106 opposite to the first side 104. The first side 104 of the chip carrier 102 has a contact structure 108. The chip carrier 102 can be a circuit board, such as a single-layer or multi-layer PCB (printed circuit board), lead frame, DCB (direct copper bonding) substrate, AMB (active metal solder) substrate, IMS (metal insulated substrate), etc. For example, in the case of a DCB substrate, the carrier 102 may include copper sheets 110, 112 bonded to one or both sides 104, 106 of a ceramic substrate 114. Each copper sheet 110, 112 may be patterned or unpatterned. For example, the top copper sheet 110 may be patterned as the contact structure 108 at the first side 104 of the chip carrier 102. The contact structure 108 may include bonding pads or similar structures. The contact structure 108 may also include metal traces for providing signal redistribution at a first side 104 of the chip carrier 102. A solder mask 109 may be provided at one or both sides 104, 106 of the chip carrier 102. In the case of a low-complexity chip (die) pad layout (e.g., source and gate pads on one side of the die and drain pads on the opposite side of the die), the chip carrier 102 may be a leadframe, and the contact structure 108 may be formed by leads of the leadframe. In this case, one or more first leads of the leadframe may be attached to the source pads of the die, and at least one additional lead of the leadframe may be attached to the gate pads of the die.

[0029] The chip carrier 102 can provide signal wiring between a first side 104 and a second side 106. For example, in the case of a PCB, the chip carrier 102 may have a patterned metal layer 110 at the first side 104 of the circuit board, and this patterned metal layer 110 forms a plurality of contact structures 108. The circuit board may also have a patterned metal layer 112 at the second side 106 of the circuit board, which is patterned differently from the patterned metal layer 110 at the first side 104 of the circuit board. The patterned metal layer 112 at the second side 106 of the circuit board may be configured to accommodate a land pattern of the circuit board to which the semiconductor package 100 will be attached. The land pattern includes pads of the circuit board to which the semiconductor package 100 will be soldered.

[0030] The semiconductor package 100 also includes at least one semiconductor die 116 attached to a chip carrier 102. The semiconductor die 116 has a first side 118 and a second side 120 opposite to the first side 118. The first side 118 of the semiconductor die 116 has (contact) pads 122 attached to a contact structure 108 at a first side 104 of the chip carrier 102. The die pads 122 can be attached to the carrier contact structure 108 by a die attachment material 124 (e.g., solder paste, sintering paste, adhesive, etc.).

[0031] In the case of lateral devices, all power and signal connections to the semiconductor die 116 are made via the die pad 122 on the first side 118 of the die 116. For example, in the case of a lateral GaN power HEMT (High Electron Mobility Transistor), source, drain, and gate connections are made via the die pad 122 on the first side 118 of the die 116. In the case of vertical devices, some power connections and possibly even signal connections to the semiconductor die 116 are made on the second side 120 of the die 116. For example, in the case of a vertical power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a vertical IGBT (Insulated Gate Bipolar Transistor), such as in Si, SiC, or other semiconductor devices, source / emitter and gate connections are made via the die pad 122 on the first side 118 of the die 116, and drain / collector connections are made on the second side 120 of the die 116.

[0032] More than one semiconductor die 116 may be attached to the chip carrier 102, and the package 100 may include more than one chip carrier 102. For example, power transistors and / or power diodes may be electrically connected within the package 100 in a half-bridge or full-bridge configuration. In this example, the semiconductor package 100 is configured as a power rectifier. However, this is merely an example. Each semiconductor die 116 included in the package 100 may be electrically connected within and / or outside the package 100 to form any type of circuit or circuit section.

[0033] The semiconductor package 100 also includes a metal plate 126 attached to a second side 120 of the semiconductor die 116. The metal plate 126 may be attached to the second side 120 of the semiconductor die 116 by a bonding material 128 such as solder paste, sintering paste, thermally conductive (and possibly electrically conductive) adhesive. A sealant 130 is defined by the chip carrier 102 and the metal plate 126 and laterally surrounds the edge 132 of the semiconductor die 116.

[0034] The dimensions of the metal plate 126 are independent of the dimensions of the chip carrier 102, but are instead based on the expected thermal load presented by each semiconductor die 116 attached to the chip carrier 102. In one embodiment, the metal plate 126 is positioned in a first direction parallel to a two-dimensional plane of the metal plate 126 and the chip carrier 102. Figure 1 The dimension of the metal plate 126 in the second direction (x or z direction) is larger than the dimension of the chip carrier 102 in the first direction. The metal plate 126 in the second direction (perpendicular to the first direction) in the two-dimensional plane... Figure 1 The dimension in the x or z direction (or the other direction) is greater than or less than the dimension of the chip carrier 102 in the second direction. Figure 1 The two-dimensional plane in the image is defined by the x and z directions.

[0035] In one embodiment, the metal plate 126 is a stamped piece of copper. However, other metals or metal alloys, such as Al, AlSiCu, etc., may also be used.

[0036] The metal plate 126 may be larger than both the semiconductor die 116 and the chip carrier 102, either alone or additionally.

[0037] Sealant 130 may, individually or additionally, comprise silicone resins, bismaleimide triazine (BT) epoxy resins or other types of epoxy resins, any polymeric material having an operating temperature of at least 175°C (e.g., 200°C or higher), etc. Molding compounds, on the other hand, typically have an operating temperature of 150°C or lower. An example of a silicone-based material with a high melting point suitable as sealant 130 is a glob top material. Sealant 130 may have a relatively low modulus (soft) compared to molding compounds. For CTE (coefficient of thermal expansion) mismatch or thermomechanical stress, sealant 130 absorbs most of the stress. That is, sealant 130 may have a relatively high CTE and a relatively low modulus.

[0038] The semiconductor material of the semiconductor die 116 may be formed from a single type of semiconductor (e.g., Si) or may be a compound semiconductor (e.g., GaN, SiC, GaAs, etc.).

[0039] Figures 2A to 2C A different view of another embodiment of a semiconductor package 200 is shown, which includes a chip carrier 102 and a metal plate 126 having dimensions independent of the chip carrier size, but instead based on the expected thermal load presented by each semiconductor die 116 attached to the chip carrier 102. Figure 2A A cross-sectional view of package 200 is shown. Figure 2B The top plan view of package 200 is shown, while Figure 2C A bottom plan view of package 200 is shown.

[0040] according to Figures 2A to 2C In the illustrated embodiment, the dimension (m1) of the metal plate 126 in the first direction (z-direction) of the two-dimensional plane is larger than the dimension (c1) of the chip carrier 102 in the first direction. The dimension (m2) of the metal plate 126 in the second direction (x-direction) of the two-dimensional plane is smaller than the dimension (c2) of the chip carrier 102 in the second direction. The second direction (x-direction) is perpendicular to the first direction (z-direction), and the two-dimensional plane is parallel to the metal plate 126 and the chip carrier 102.

[0041] In addition, according to Figures 2A to 2C In the embodiment shown, in a plan view where the metal plate 126 is located above the chip carrier 102, one or more contact structures 202 disposed around the periphery of the chip carrier 102 are at least partially visible, such as... Figure 2B As shown. This contact structure configuration allows for visual inspection of the bonding between the peripheral contact structure 202 and the board or other substrate (not shown) to which the semiconductor package 200 is ultimately mounted.

[0042] Figure 3A It shows Figure 1 and Figure 2A-2C The semiconductor die 116 shown is a plan view of an embodiment of the lateral power semiconductor die 300. Figure 3B A perspective view is shown of the corresponding contact structure layout at the first side 104 of the chip carrier 102, wherein the chip carrier 102 is used to accommodate Figure 3A The lateral power semiconductor die 300 is shown.

[0043] According to this embodiment, the lateral power semiconductor die 300 has a single source pad "S", a single drain pad "D", and a single gate pad "G" on a first side 302 of the lateral power semiconductor die 300. The lateral power semiconductor die 300 is attached to the chip carrier 102 in a flip-chip configuration, wherein the pads "S", "D", and "G" face the contact structure 108 of the chip carrier 102.

[0044] A single source pad "S" of the lateral power semiconductor die 300 is attached to a first contact structure 304 in a contact structure 108 on a first side 104 of the chip carrier 102. A single drain pad "D" of the lateral power semiconductor die 300 is attached to a second contact structure 306 in a contact structure 108 on a first side 104 of the chip carrier 102. A single gate pad "G" of the lateral power semiconductor die 300 is attached to a third contact structure 308 in a contact structure 108 on a first side 104 of the chip carrier 102.

[0045] according to Figure 3A and 3B In the illustrated embodiment, the chip carrier 102 is implemented as a lead frame. As used herein, the term "lead frame" refers to a metal structure within a semiconductor package that transmits signals from the semiconductor die 116 / 300 to the outside. The lead frame can be fabricated as part of a panel, with individual lead frames fixed as units to a peripheral area via interconnecting structures. The interconnecting structures are then cut, for example, after molding, to produce individual packages. The semiconductor package 300 may include more than one lead frame, depending on the type of one or more devices included in the package 300.

[0046] exist Figure 3B In the chip carrier 102, the first contact structure 304 in the contact structure 108 is the first lead of the lead frame. The second contact structure 306 in the contact structure 108 is the second lead of the lead frame. The third contact structure 308 in the contact structure 108 is the third lead of the lead frame.

[0047] Figure 3A and 3B The illustrated chip carrier configuration can be used to accommodate a lateral power semiconductor die because all power (e.g., source and drain) pads and signal (e.g., gate) pads of the die are located on the same side of the die. In this case, the first lead 304 of the leadframe can be attached to the source pad of the die, the second lead 306 of the leadframe can be attached to the drain pad of the die, and the third lead 308 of the leadframe can be attached to the gate pad of the die, with all pads on the same side of the die. In the case of a vertical power semiconductor die where the main current path is located between opposite sides of the die, the power terminals are located on opposite sides of the die. In this case, the first lead 304 and the second lead 306 of the leadframe can be attached to the source pad of the die, and the third lead 308 of the leadframe can be attached to the gate pad of the die. In this vertical device example, the drain connection to the die is provided via a metal plate 126.

[0048] As previously mentioned, other types of chip carriers can be used. The type of chip carrier can depend on the type of device included in the package and the type of application the package design is intended for.

[0049] Figures 4A to 4C A perspective view of the chip carrier 102 at different assembly levels according to an embodiment is shown. Figure 4A A fully assembled chip carrier 102 is shown. According to this embodiment, the chip carrier 102 is implemented as a circuit board, such as a single-layer or multi-layer PCB. A solder mask 400 can be applied to the front side 104 of the chip carrier 102. Die attachment materials (not shown), such as solder paste, sintering paste, adhesive, etc., can be applied to the contact structure 108 at the first side 104 of the chip carrier 102. The die attachment materials can be applied by printing processes such as stencil or screen printing, or by dispensing or jetting processes.

[0050] Figures 4A to 4C The chip carrier embodiment shown is compared to Figure 3B The chip carrier embodiment shown is more complex. However, Figures 4A to 4C The types of semiconductor dies that can be accommodated in the illustrated chip carrier embodiment are... Figure 3B The chip carrier embodiments shown can accommodate the same type of semiconductor die, but Figures 4A to 4C The chip carrier embodiment shown has a more complex contact pad configuration.

[0051] For example, a first contact structure 402 in the contact structure 108 on the first side 104 of the chip carrier 102 can be configured to attach to the gate pad of a lateral power transistor die. A set of second contact structures 404 in the contact structure 108 on the first side 104 of the chip carrier 102 can be configured to attach to corresponding source pads of a lateral power transistor die. A set of third contact structures 406 in the contact structure 108 on the first side 104 of the chip carrier 102 can be configured to attach to corresponding drain pads of a lateral power transistor die.

[0052] Figure 4B A chip carrier 102 is shown, in which the solder mask 400 has been removed, exposing the underlying electrically insulating substrate 408. The metallization layer 410 is patterned into three separate portions 412, 414, and 416. The first portion 412 is connected to a gate contact structure 402 at a first side 104 of the chip carrier 102. The second portion 414 is connected to a source contact structure 404 at the first side 104 of the chip carrier 102. The third portion 416 is connected to a drain contact structure 406 at the first side 104 of the chip carrier 102.

[0053] Figure 4CA metal via 418 is shown that connects different contact structures 402, 404, 406 at the first side 104 of the chip carrier 102 to corresponding patterned metal portions at the second side 106 of the chip carrier 102 (outside the view).

[0054] Designed to be attached to Figures 4A to 4C The lateral power semiconductor die of the chip carrier 102 shown has multiple source pads, multiple drain pads, and a gate pad on the side of the power semiconductor die to be mounted to the chip carrier 102. For example, the lateral power semiconductor die can be a lateral GaN power semiconductor die, a lateral Si power semiconductor die, a lateral SiC power semiconductor die, etc. During packaging assembly, the source pads of the lateral power semiconductor die are attached to a first set of contact structures 404 on a first side 104 of the chip carrier 102. The drain pads of the lateral power semiconductor die are attached to a second set of contact structures 406 on the first side 104 of the chip carrier 102. The gate pads of the lateral power semiconductor die are attached to an additional contact structure 402 on the first side 104 of the chip carrier 102.

[0055] Figure 5 A cross-sectional view of semiconductor package 500 is shown. Figure 5 The illustrated embodiments and Figure 1 The illustrated embodiment is similar. However, the difference is that the metal plate 126 is bent in the direction (y-direction) toward the chip carrier 102, outside the periphery of both the semiconductor die 116 and the carrier 102. This metal plate configuration allows the ends 502 of the metal plate 126 to contact or be mounted to another substrate, such as the circuit board to which the package 500 will be mounted. In the case of a vertical semiconductor die, the gate pad 504 and source pad 506 at the first side 118 of the semiconductor die 116 can be attached to the contact structure 108 at the first side 104 of the chip carrier 102. The drain pad 508 at the second side 120 of the semiconductor die 116 can be attached to the metal plate 126. The drain connection of the semiconductor die 116 can be made to an application board (not shown) through one or both downwardly bent ends 502 of the metal plate 126.

[0056] Figure 6 A cross-sectional view of semiconductor package 600 is shown. Figure 6 The illustrated embodiments and Figure 5 The embodiment shown is similar. However, the difference is that the end 502 of the metal plate 126 is not aligned with... Figure 5 It bends in the same way as in the middle.

[0057] Figure 7 A cross-sectional view of semiconductor package 700 is shown. Figure 7 The illustrated embodiments and Figure 5 and6 The illustrated embodiment is similar. However, the difference is that a metal connector 702, such as a metal ball, metal block, metal strip, or metal pillar, is attached to the metal plate 126 at a side 704 of the metal plate 126 that is attached to the semiconductor die 116. The metal connector 702 is laterally spaced from both the semiconductor die 116 and the chip carrier 102. The metal connector 702 has a height “H_ball” equal to or greater than the combined height of the semiconductor die 116 and the chip carrier 102. The metal connector 702 can be attached to the metal plate 126 via a bonding material 706 such as solder paste or sintering paste.

[0058] Figure 8 A cross-sectional view of a semiconductor package 800 is shown. The semiconductor package 800 includes a chip carrier 102 having a first side 104 and a second side 106 opposite to the first side 104. The first side 104 of the chip carrier 102 has contact structures 108. A vertical power semiconductor die 116 having a first side 118 and a second side 120 opposite to the first side 118 is attached to the chip carrier 102. The first side 118 of the vertical power semiconductor die 116 has a source pad 506 and a gate pad 504. The source pad 506 is attached to one or more first contact structures in the contact structures 108 at the first side 104 of the chip carrier 102, while the gate pad 504 is attached to a second contact structure in the contact structures 108 at the first side 104 of the carrier 102. The second side 120 of the vertical power semiconductor die 116 has a drain pad 508.

[0059] The semiconductor package 800 also includes a substrate 802, such as a DCB substrate, having a first patterned metal body 804 at a first side 806 of an electrically insulating substrate 808 and a second patterned metal body 810 at a second side 812 of the electrically insulating substrate 808 opposite to the first side 806. The first patterned metal body 804 is attached, for example, to a drain pad 508 at a second side 120 of a vertical power semiconductor die 116 via a bonding material 128 such as solder paste, sintering paste, conductive adhesive, etc. The dimensions of the substrate 802 are independent of the dimensions of the chip carrier 102, but are instead based on the expected thermal load presented by the vertical power semiconductor die 116. A sealant 130 defined by the chip carrier 102 and the substrate 802 laterally surrounds the edge 132 of the vertical power semiconductor die 116. One or more metal connectors 814 may be attached to the first patterned metal body 804 of the substrate 802. Each metal connector 814 is laterally spaced from both the vertical power semiconductor die 116 and the chip carrier 102. Each metal connector 814 has a height “H_ball” equal to or greater than the combined height of the vertical power semiconductor die 116 and the chip carrier 102. Each metal connector 814 can be attached to a first patterned metal body 804 of the substrate 802 via a bonding material 816 such as solder paste, sintering paste, etc.

[0060] Figure 9A and 9B A method for manufacturing the semiconductor package described herein is illustrated. In step 1, a carrier sheet 900 having a plurality of interconnected chip carriers 102 is provided. Each chip carrier 102 has a first side 104 and a second side 106 opposite to the first side 104, the first side 104 having a contact structure 108 as previously described herein.

[0061] In step 2, die attachment material 124, such as solder paste, sintering paste, or adhesive, is placed on the contact structure 108 of each chip carrier 102. The die attachment material 124 can be applied by printing processes such as stencil or screen printing, or by dispensing or spraying processes.

[0062] In step 3, at least one semiconductor die 116 is attached to each of the chip carriers 102. Each semiconductor die 116 has a first side 118 and a second side 120 opposite to the first side 118, and the first side 118 of each semiconductor die 116 has a plurality of pads 122 attached to a contact structure 108 at a first side 104 of the corresponding carrier 102, as previously described herein.

[0063] In step 4, the carrier sheet 900 is cut into separate partial packages 902 by a cutting process 903 such as sawing, laser cutting, or stamping. Each partial package 902 includes a chip carrier in the chip carrier 102 and each semiconductor die 116 attached to the carrier 102.

[0064] In step 5, the dicing process is completed, which produces physically separated partial semiconductor packages 904.

[0065] In step 6a, a metal sheet 906 is provided. In one embodiment, the metal sheet 906 is a Cu sheet. However, other materials can also be used for the metal sheet 906, such as Al, AlSiCu, etc.

[0066] In step 6b, bonding material 128, such as solder paste, sintering paste, thermally conductive (and possibly electrically conductive) adhesive, is applied to metal sheet 906.

[0067] In step 7, the metal sheet 906 is attached to the second side 120 of the semiconductor die 116 of the partial package 902 via a corresponding bonding material 128. When solder paste is used as the bonding material 128, the die attachment process may include solder reflow. Regardless of the type of bonding material 128 used, the partial package 902 is interconnected via the metal sheet 906.

[0068] In step 8, sealant 130 is dispensed onto the metal sheet 906 and around the edge 132 of each semiconductor die 116. Sealant 130 may include silicone resin, BT epoxy resin or other types of epoxy resin, any polymeric material having an operating temperature of at least 175°C (e.g., 200°C or higher), etc.

[0069] In step 9, the encapsulant 130 is cured. The curing process depends on the type of sealant used. For example, the curing process may include heat curing, UV curing, etc.

[0070] In step 10, a metal sheet 906 is cut between adjacent semiconductor dies in the semiconductor dies 116 of the different portion packages 904 to form an entire semiconductor package 908. Each of the entire semiconductor packages 908 has a metal plate 126 cut from the metal sheet 906, and the size of the metal plate 126 is independent of the size of the chip carrier 102 included in the entire semiconductor package 908, but is instead based on the expected thermal load presented by each semiconductor die 116 included in the entire semiconductor package 908. The package cutting process 910 for cutting the metal sheet 906 between adjacent semiconductor dies in the semiconductor dies 116 of the different portion packages 904 may include sawing, laser cutting, stamping, etc.

[0071] Figure 10 It shows Figure 9A and 9B The diagram shows a plan view of one embodiment of the metal sheet 906. According to this embodiment, each metal plate 126 is positioned in a first direction parallel to the two-dimensional plane of the metal plate 126 and the chip carrier 102. Figure 10 The dimension of the metal plate 126 in the second direction (x-direction) is larger than the dimension of the chip carrier 102 in the first direction. Each metal plate 126 has a second direction (x-direction) perpendicular to the first direction in the two-dimensional plane. Figure 10 The dimension in the z-direction is the same as the dimension of the chip carrier 102 in the second direction. Figure 10 The two-dimensional plane in the image is defined by the x and z directions.

[0072] Figure 11 It shows Figure 9A and 9B A plan view of another embodiment of the metal sheet 906 shown. According to this embodiment, each metal plate 126 is positioned in a first direction parallel to the two-dimensional plane of the metal plate 126 and the chip carrier 102. Figure 11 The dimension of the metal plate 126 in the second direction (x-direction) is larger than the dimension of the chip carrier 102 in the first direction. Each metal plate 126 has a second direction (x-direction) perpendicular to the first direction in the two-dimensional plane. Figure 11 The dimension in the z-direction is smaller than the dimension of the chip carrier 102 in the second direction, so that the bonding between the peripheral contact structure 202 of each chip carrier 102 and the board or other substrate (not shown) to which each chip carrier 102 is finally mounted can be visually inspected. Figure 11 The two-dimensional plane in the image is defined by the x and z directions.

[0073] The embodiments described herein provide a packaging concept capable of dual-sided cooling, wherein the package can have an excessively large top metal structure to achieve optimal cooling surface area and minimum creepage distance where applicable. Both the interconnect area with the chip on the carrier and the interconnect area at the chip interconnect interface can be maximized. A sealant with low stress and high-temperature properties can be used to seal the die.

[0074] The following describes an embodiment of a semiconductor package having a chip carrier with pad offset features. The features previously described herein can be used in combination with any of the semiconductor package embodiments described below.

[0075] Figure 12A cross-sectional view of a semiconductor package 1200 with pad offset features is shown, which meet gap requirements and do not require special tools, additional components, or process steps. According to this embodiment, the semiconductor package 1200 includes a chip carrier 1202 having an electrically insulating body 1204 and a first contact structure 1206 at a first side 1208 of the electrically insulating body 1204. At least one semiconductor die 1210 is attached to the chip carrier 1202. The semiconductor die 1210 may be a Si power MOSFET, IGBT, SiC MOSFET, GaN HEMT, etc., and has a high breakdown voltage, for example, in the range of hundreds to thousands of volts.

[0076] Semiconductor die 1210 has a first pad 1212 attached to a first contact structure 1206 of carrier 1202. The first pad 1212 is at the source (S) or emitter (E) potential of a transistor device included in semiconductor die 1210. The first pad 1212 is spaced inwardly from the edge 1214 of semiconductor die 1210 by a first distance d1. Semiconductor die 1210 has an edge termination region 1216 between the die edge 1214 and the first pad 1212.

[0077] During normal (non-faulty) operation of the semiconductor die 1210, the edge termination region 1216 is located away from the die edge 1214 and guides an electric field (“E field”) along the direction of the carrier 1202. The electric field emitted outward from the edge termination region 1216 during normal operation of the semiconductor die 1210 can be in the range of, for example, 100 to 500 μm∝V. Figure 12 The enlarged view provided shows the electric field emanating outward from the edge termination region 1216 along the direction toward the carrier 1202.

[0078] To ensure an appropriate gap between the edge termination region 1216 of the die 1210 and the first contact structure 1206 of the carrier 1202, the first contact structure 1206 of the carrier 1202 is spaced inwardly from the edge 1214 of the semiconductor die 1210 by a second distance d2 greater than a first distance d1. Therefore, during normal operation of the semiconductor die 1210, the electric field emanating from the edge termination region 1216 in the direction of the carrier 1202 will not reach the first contact structure 1206 of the carrier 1202, thus ensuring an appropriate gap, which is particularly challenging for high-voltage applications in the range of hundreds to thousands of volts.

[0079] The degree to which d2 > d1 depends on the required gap between the edge termination region 1216 of the die 1210 and the first contact structure 1206 of the carrier 1202, which in turn depends on the voltage rating of the package 1200 and the material type of the electrically insulating body 1204 for the die carrier 1202. In one embodiment, the area of ​​the surface of the first contact structure 1206 of the carrier 1202 facing the first pad 1212 of the semiconductor die 1210 is smaller than the area of ​​the surface of the first pad 1212 of the first contact structure 1206 of the semiconductor die 1210 facing the carrier 1202. That is, the first contact structure 1206 of the carrier 1202 may have a smaller occupied area (area) than the first pad 1212 of the semiconductor die 1210.

[0080] The carrier 1202 also has a conductive structure 1218 at a second side 1220 of the electrically insulating body 1204 opposite to the first side 1208. The conductive structure 1218 is electrically connected to the first contact structure 1206 and covers at least a portion of the edge termination region 1216 of the semiconductor die 1210.

[0081] The carrier 1202 has a thickness tC between a first side 1208 and a second side 1220 of the electrically insulating body 1204. This thickness tC satisfies the gap requirement between the edge termination region 1216 of the die 1210 and the conductive structure 1218 at the second side 1220 of the electrically insulating body 1204 of the carrier 1202. Therefore, during normal operation of the semiconductor die 1210, the electric field emanating from the edge termination region 1216 in the direction of the carrier 1202 will not reach the conductive structure 1218 at the second side 1220 of the electrically insulating body 1204.

[0082] like Figure 12 As shown in the enlarged view, during normal operation of the semiconductor die 1210, the electric field emanating outward from the edge termination region 1216 toward the carrier 1202 is not disturbed by the metal structures 1206, 1218 of the chip carrier 1202. In one embodiment, the thickness tC of the carrier 1202 between the first side 1208 and the second side 1220 of the electrically insulating body 1204 is in the range of 100 μm to 800 μm to ensure appropriate clearance.

[0083] Utilizing the pad offset feature implemented at the chip carrier 1202 described above, when attaching the semiconductor die 1210 to the carrier 1202 using die attachment material 1222, a source / emitter-side-down mounting configuration can be used. The die attachment material 1222 is, for example, solder, adhesive, etc., and has a thickness tDA. No additional components (e.g., interposers), process steps, or special tools are required to meet the gap requirements. Any type of chip carrier with electrical wiring capability at the first side 1208 and / or the second side 1220 of the electrically insulating body 1204 can be used as... Figure 12 The chip carrier 1202 in the middle.

[0084] In one embodiment, the carrier 1202 is a direct copper bonding (DCB) substrate, an active metal brazing (AMB) substrate, or an insulating metal substrate (IMS) having a first patterned metal body 1224 with a thickness of tPM1 on a first side 1208 of the electrically insulating body 1204. The first patterned metal body 1224 includes a first contact structure 1206 of the carrier 1202. The first patterned metal body 1224 may also include a second contact structure 1226 at the first side 1208 of the electrically insulating body 1204. The second contact structure 1226 is electrically isolated from the first contact structure 1206. The semiconductor die 1210 may have a second pad 1228 attached to the second contact structure 1226 of the carrier 1202. When a transistor device is included in the semiconductor die 1210, the second pad 1228 is a control terminal pad, such as a gate pad.

[0085] The chip carrier 1202 may further include a second patterned metal body 1230 at a second side 1220 of the electrically insulating body 1204. The second patterned metal body 1230 includes a conductive structure 1218 of the carrier 1202. The conductive structure 1218 at the second side 1220 of the electrically insulating body 1204 may be electrically connected via a conductive via 1232 to a first contact structure 1206 at a first side 1208 of the electrically insulating body 1204, the conductive via 1232 extending through the electrically insulating body 1204. In the case of a DCB substrate, an AMB substrate, or an IMS, the electrically insulating body 1204 may include, for example, ceramic.

[0086] The conductive structure 1218 at the second side 1220 of the electrically insulating body 1204 covers at least a portion of the edge termination region 1216 of the semiconductor die 1210. The electrically insulating body 1204 has a thickness tC between the first side 1208 and the second side 1220, which satisfies the gap requirement between the edge termination region 1216 of the semiconductor die 1210 and the conductive structure 1218 formed in the second patterned metal body 1230 of the carrier 1202. For example, the thickness tDA of the die attachment material 1222 can be about 20 μm, the thickness tPM1 of the first patterned metal body 1224 can be about 70 μm, and the thickness tC of the electrically insulating body 1204 of the carrier 1202 can be in the range of 100 μm to 800 μm, depending on the gap requirement.

[0087] The second patterned metal body 1230 may also include an additional conductive structure 1234 at a second side 1220 of the electrically insulating body 1204. The additional conductive structure 1234 may be electrically connected to a second contact structure 1226 at a first side 1208 of the electrically insulating body 1204 via one or more conductive vias 1236 extending through the electrically insulating body 1204.

[0088] In another embodiment, the carrier 1202 is a printed circuit board (PCB) having a first patterned metal body 1224 at a first side 1208 of the electrically insulating body 1204 and a second patterned metal body 1230 at a second side 1220 of the electrically insulating body 1204. According to this embodiment, the electrically insulating body 1204 includes one or more prepreg layers. In the case of the PCB-based carrier 1202, the solder mask 1237 can separate the contact structures 1206, 1226 formed in the first patterned metal body 1224 and the conductive structures 1218, 1234 formed in the second patterned metal body 1230.

[0089] The metal plate 1238 can be attached to the pad 1240 on the side 1242 of the semiconductor die 1210 opposite to the chip carrier 1202 using a die attachment material 1244 such as solder or adhesive. The pad 1240 on the side 1242 of the semiconductor die 1210 opposite to the chip carrier 1202 can be a drain (D) pad or a collector (C) pad for a transistor device included in the semiconductor die 1210.

[0090] Outside the periphery of both the semiconductor die 1210 and the carrier 1202, the metal plate 1238 may be positioned only at one end 1246 in the direction facing the carrier 1202. Figure 12The plate is bent in the z-direction to provide terminals 1248 for pads 1240 on the side 1242 of the semiconductor die 1210 opposite to the carrier 1202. Terminals 1248 may be covered by a plating layer 1250, such as Sn, for example, to be soldered onto a board. The plating layer 1250 may cover the first conductive structure 1218 and the second conductive structure 1234 on the second side 1220 of the electrically insulating body 1204. Exposed portions 1248 of the metal plate 1238 may also be covered by the plating layer 1250.

[0091] As previously described herein, the dimensions of the metal plate 1238 are independent of the dimensions of the carrier 1202 and are based on the expected thermal load presented by the semiconductor die 1210 during normal operation. The sealant 1252 may laterally surround the edge 1214 of the semiconductor die 1210. The sealant 1252 fills the gap 1254 between the edge termination region 1216 of the semiconductor die 1210 and the electrically insulating body 1204 of the chip carrier 1202.

[0092] Figure 13 A cross-sectional view of another embodiment of a semiconductor package 1300 with pad offset features is shown, which meets gap requirements and does not require special tools or additional components or process steps. Figure 13 The illustrated embodiments and Figure 12 The illustrated embodiment is similar. However, the difference is that the carrier 1202 is a pre-molded carrier having a copper block 1302 embedded in an electrically insulating material 1304 such as a molding compound, and a MIS (molded interconnect substrate) with high ionic purity (e.g., Na & Cl ion content <1 / <10 / <50ppm) and beneficial for high-voltage applications. The first side 1306 of the copper block 1302 is not covered by the electrically insulating material 1304 and a first contact structure 1206 is formed at the first side 1208 of the electrically insulating body 1204 of the carrier 1202. The second side 1308 of the copper block 1302 (opposite to the first side 1306 of the copper block 1302) is not covered by the electrically insulating material 1304 and a first conductive structure 1218 is formed at the second side 1220 of the electrically insulating body 1204 of the carrier 1202.

[0093] As previously described herein, a first conductive structure 1218 at the second side 1220 of the electrically insulating body 1204 of the carrier 1202 covers at least a portion of the edge termination region 1216 of the semiconductor die 1210. The electrically insulating material 1304 has a thickness tMC between the edge termination region 1216 of the semiconductor die 1210 and the first conductive structure 1218 at the second side 1220 of the electrically insulating body 1204, satisfying the gap requirement between the edge termination region 1216 and the conductive structure 1218.

[0094] The chip carrier 1202 may include a second copper block 1310 embedded in the same electrically insulating material 1304 as the first copper block 1302. The first copper block 1302 and the second copper block 1310 are electrically isolated from each other by the electrically insulating material 1304. A first side 1312 of the second copper block 1310 is not covered by the electrically insulating material 1304 and a second contact structure 1226 is formed on the first side 1208 of the electrically insulating body 1204 of the carrier 1202. A second (opposite) side 1314 of the second copper block 1310 is not covered by the electrically insulating material 1304 and a second conductive structure 1234 is formed on the second side 1220 of the electrically insulating body 1204 of the carrier 1202.

[0095] Figure 14 A cross-sectional view of another embodiment of a semiconductor package 1400 with pad offset features is shown, which meets gap requirements and does not require special tools, additional parts, or process steps. Figure 14 The illustrated embodiments and Figure 12 The illustrated embodiment is similar. However, the difference is that the carrier 1202 is part of a chip-embedded laminate structure. For example, the electrically insulating body 1204 of the carrier 1202 can be a composite material 1402 made of pre-impregnated (“pre-impregnated”) fibers and a partially cured polymer matrix. The semiconductor die 1210 can be arranged in an opening formed in the insulating core material 1404, wherein the insulating core material 1404 is stacked on the composite material 1402.

[0096] according to Figure 14 In one embodiment, a first contact structure 1206 of the carrier 1202 is formed by a conductive via 1406, which is attached to a first (S / E) pad 1212 of the semiconductor die 1210 and extends through the composite material 1402 to a second side 1220 of the electrically insulating body 1204. The conductive via 1406 is connected to a patterned metal body 1408 at the second side 1220 of the electrically insulating body 1204. The patterned metal body 1408 includes a conductive structure 1218 covering at least a portion of the edge termination region 1216 of the semiconductor die 1210, as previously described herein.

[0097] Composite material 1402 has a thickness tMC between its first side 1208 and second side 1220, which satisfies the gap requirement between the edge termination region 1216 of semiconductor die 1210 and the conductive structure 1218 formed in the patterned metal body 1408 at the second side 1220 of composite material 1402. When the prepreg serves as the electrically insulating body 1204 of the carrier 1202, the thickness of a single prepreg layer is typically in the range of 20 to 100 μm. If a larger thickness tMC is required to satisfy the gap requirement between the edge termination region 1216 of semiconductor die 1210 and the conductive structure 1218 at the second side 1220 of the electrically insulating body 1204 of carrier 1202, multiple prepreg layers can be stacked perpendicularly to each other to form the electrically insulating body 1204.

[0098] A second composite material 1410, made of pre-impregnated fibers and a partially cured polymer matrix, can be stacked on an insulating core material 1404. A contact structure 1412 for a pad 1240 on the side of the semiconductor die 1210 opposite to the carrier 1202 can be formed by a conductive via 1414 extending through the second composite material 1410. The conductive via 1414 is connected to a patterned metal body 1416 on the side of the second composite material 1410 opposite to the semiconductor die 1210. The composite materials 1402, 1410, and the insulating core material 1404 undergo a lamination process to form a chip-embedded laminate structure.

[0099] Figures 12 to 14 The carrier 1202 shown may include glass cloth material as a structure / layer within the carrier 1202. Adjusting the dielectric properties of the glass cloth structure / layer can modify the thickness tMC of the carrier 1202. Figure 13 ) / tMC( Figure 14 )Require.

[0100] Figure 15 A cross-sectional view of another embodiment of a semiconductor package 1500 with pad offset features is shown, which meets gap requirements and does not require special tools or additional components or process steps. Figure 15 The illustrated embodiments and Figure 12 The illustrated embodiment is similar. However, the difference is that the carrier 1202 includes a glass cloth structure or layer 1502 embedded within the carrier 1202. The glass cloth structure or layer 1502 may be embedded within, for example, a bismaleimide triazine (BT) resin material. The glass cloth structure or layer 1502 adjusts the dielectric properties of the carrier 1202, which in turn allows for modification of the carrier thickness requirements. For example, the dielectric constant of the carrier 1202 can be increased by embedding the glass cloth structure or layer 1502 within the carrier 1202, thereby enabling, for example, a thinner encapsulation.

[0101] Although this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0102] Example 1: A semiconductor package comprising: a carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite to the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having dimensions independent of the dimensions of the carrier but based on the expected thermal load presented by the semiconductor die; and a sealant defined by the carrier and the metal plate and laterally surrounding the edge of the semiconductor die.

[0103] Example 2: The semiconductor package according to Example 1, wherein the dimension of the metal plate in a first direction of the two-dimensional plane is greater than the dimension of the carrier in the first direction, wherein the dimension of the metal plate in a second direction of the two-dimensional plane is smaller than the dimension of the carrier in the second direction, wherein the second direction is perpendicular to the first direction, and wherein the two-dimensional plane is parallel to the metal plate and the carrier.

[0104] Example 3: A semiconductor package according to Example 1 or 2, wherein, in a plan view of the metal plate above the carrier, one or more of the contact structures disposed around the periphery of the carrier are at least partially visible.

[0105] Example 4: A semiconductor package according to any one of Examples 1 to 3, wherein the metal plate is a stamped piece of copper metal.

[0106] Example 5: A semiconductor package according to any one of Examples 1 to 4, wherein the metal plate is larger than both the semiconductor die and the carrier.

[0107] Example 6: A semiconductor package according to any one of Examples 1 to 5, wherein the sealant comprises a silicone resin.

[0108] Example 7: A semiconductor package according to any one of Examples 1 to 6, wherein the sealant has an operating temperature greater than 175°C.

[0109] Example 8: A semiconductor package according to any one of Examples 1 to 7, wherein the sealant has an operating temperature of 200°C or higher.

[0110] Example 9. A semiconductor package according to any one of Examples 1 to 8, wherein the semiconductor die is a lateral power semiconductor die having a single source pad, a single drain pad, and a single gate pad at a first side of the lateral power semiconductor die, wherein the single source pad is attached to a first contact structure in a contact structure at the first side of the carrier, wherein the single drain pad is attached to a second contact structure in a contact structure at the first side of the carrier, and wherein the single gate pad is attached to a third contact structure in a contact structure at the first side of the carrier.

[0111] Example 10: A semiconductor package according to Example 9, wherein the carrier is a lead frame, wherein the first contact structure in the contact structure is a first lead of the lead frame, wherein the second contact structure in the contact structure is a second lead of the lead frame, and wherein the third contact structure in the contact structure is a third lead of the lead frame.

[0112] Example 11. A semiconductor package according to any one of Examples 1 to 8, wherein the semiconductor die is a lateral power semiconductor die having a plurality of source pads, a plurality of drain pads, and a gate pad at a first side of the power semiconductor die, wherein the plurality of source pads are attached to a first set of contact structures at the first side of the carrier, wherein the plurality of drain pads are attached to a second set of contact structures at the first side of the carrier, and wherein the gate pad is attached to an additional contact structure in the contact structure at the first side of the carrier.

[0113] Example 12: A semiconductor package according to Example 11, wherein the carrier is a circuit board having a patterned metal layer at a first side of the circuit board, and the patterned metal layer forming the first set of contact structures, the second set of contact structures, and the additional contact structure in the contact structures.

[0114] Example 13: A semiconductor package according to Example 11 or 12, wherein the lateral power semiconductor die is a lateral GaN power semiconductor die.

[0115] Example 14: A semiconductor package according to any one of Examples 1 to 13, wherein the carrier provides signal wiring between a first side and a second side of the carrier.

[0116] Example 15: A semiconductor package according to Example 14, wherein the carrier is a circuit board having a patterned metal layer on a first side of the circuit board and the patterned metal layer forming a plurality of contact structures.

[0117] Example 16. A semiconductor package according to Example 15, wherein the circuit board has a patterned metal layer on a second side of the circuit board, the patterned metal layer being patterned differently from the patterned metal layer on a first side of the circuit board, and wherein the patterned metal layer on the second side of the circuit board accommodates a connection pad pattern of the circuit board to which the semiconductor package will be attached.

[0118] Example 17: A semiconductor package according to any one of Examples 1 to 16, wherein the metal plate is bent in a direction toward the carrier, outside the periphery of both the semiconductor die and the carrier.

[0119] Example 18. The semiconductor package according to any one of Examples 1 to 17 further includes a metal connector attached to the metal plate at a side of the metal plate attached to the semiconductor die, wherein the metal connector is laterally spaced from both the semiconductor die and the carrier, and wherein the metal connector has a height equal to or greater than the combined height of the semiconductor die and the carrier.

[0120] Example 19. A method comprising: providing a carrier sheet having a plurality of carriers interconnected with each other, each carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; attaching a semiconductor die to each of the carriers, each semiconductor die having a first side and a second side opposite to the first side, the first side of each semiconductor die having a plurality of pads attached to the plurality of contact structures corresponding to the first side of the carrier; and, after attaching the semiconductor die, dicing the carrier sheet into separate partial packages, each of the partial packages including one carrier and a pad attached to the carrier. The semiconductor die is assembled into a package; a metal sheet is attached to a second side of the partially packaged semiconductor die, the partially packaged packages being interconnected by the metal sheet; a sealant is applied to the metal sheet and around the edge of each semiconductor die in the package; the sealant is cured; and the metal sheet is cut between adjacent semiconductor dies to form an entire semiconductor package, each of the entire semiconductor packages having a metal plate cut from the metal sheet, the size of which is independent of the size of the carrier included in the entire semiconductor package, but is based on the expected thermal load presented by the semiconductor dies included in the entire semiconductor package.

[0121] Example 20. A semiconductor package comprising: a carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; a vertical power semiconductor die having a first side and a second side opposite to the first side, the first side of the vertical power semiconductor die having a source pad and a gate pad, the source pad being attached to one or more first contact structures of the contact structures on the first side of the carrier, the gate pad being attached to a second contact structure of the contact structures on the first side of the carrier, the second side of the vertical power semiconductor die having a drain pad; a substrate having a first patterned metal body on a first side of an electrically insulating substrate and a second patterned metal body on a second side of the electrically insulating substrate opposite to the first side, the first patterned metal body being attached to the drain pad on the second side of the vertical power semiconductor die, the substrate having dimensions independent of the dimensions of the carrier but based on an expected thermal load presented by the vertical power semiconductor die; and a sealant defined by the carrier and the substrate and laterally surrounding the edge of the vertical power semiconductor die.

[0122] Example 21: The semiconductor package according to Example 20 further includes a metal connector attached to a first patterned metal body of a substrate, wherein the metal connector is laterally spaced from both the vertical power semiconductor die and the carrier, and wherein the metal connector has a height equal to or greater than the combined height of the vertical power semiconductor die and the carrier.

[0123] Example 22. A semiconductor package includes: a carrier having a first side and a second side opposite to the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite to the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die; and a sealant defined by the carrier and the metal plate and laterally surrounding the edge of the semiconductor die, wherein the dimension of the metal plate in a first direction parallel to a two-dimensional plane of the metal plate and the carrier is greater than the dimension of the carrier in the first direction, and wherein the dimension of the metal plate in a second direction perpendicular to the first direction in the two-dimensional plane is greater than or less than the dimension of the carrier in the second direction.

[0124] Example 23. A semiconductor package includes: a carrier having an electrically insulating body and a first contact structure on a first side of the electrically insulating body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at a source or emitter potential, wherein the first pad is spaced inwardly from an edge of the semiconductor die by a first distance, wherein the semiconductor die has an edge termination region between the edge and the first pad, wherein the first contact structure of the carrier is spaced inwardly from the edge of the semiconductor die by a second distance greater than the first distance, such that an electric field emitted from the edge termination region in the direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

[0125] Example 24, a semiconductor package according to Example 23, wherein: the carrier has a conductive structure on a second side of the electrically insulating body opposite to the first side; the conductive structure is electrically connected to the first contact structure and covers at least a portion of the edge termination region of the semiconductor die; and the carrier has a thickness between the first and second sides of the electrically insulating body, the thickness satisfying a gap requirement between the edge termination region of the semiconductor die and the conductive structure of the carrier.

[0126] Example 25: A semiconductor package according to Example 24, wherein the thickness of the carrier between a first side and a second side of the electrically insulating body is in the range of 100 μm to 800 μm.

[0127] Example 26: A semiconductor package according to any one of Examples 23 to 25, wherein the area of ​​the surface of the first contact structure of the carrier facing the first pad of the semiconductor die is smaller than the area of ​​the surface of the first pad of the first contact structure of the semiconductor die facing the carrier.

[0128] Example 27. A semiconductor package according to any one of Examples 23 to 26, wherein the carrier is a direct copper bonding substrate, an active metal soldering substrate, or an insulating metal substrate having a patterned metal body on a first side of an electrically insulating body, and wherein the first patterned metal body includes a first contact structure of the carrier.

[0129] Example 28. A semiconductor package according to any one of Examples 23 to 27, wherein: the carrier is a pre-molded carrier having a copper block embedded in an electrically insulating material; a first side of the copper block is not covered by the electrically insulating material and forms the first contact structure of the carrier; a second side of the copper block opposite to the first side of the copper block is not covered by the electrically insulating material and forms a conductive structure on the second side of the electrically insulating body opposite to the first side, and the conductive structure covers at least a portion of the edge termination region of the semiconductor die; and the electrically insulating material has a thickness between the edge termination region of the semiconductor die and the conductive structure on the second side of the electrically insulating body, the thickness satisfying the gap requirement between the edge termination region and the conductive structure.

[0130] Example 29. A semiconductor package according to any one of Examples 23 to 28, wherein: the carrier is a printed circuit board (PCB) having a first patterned metal body at a first side of the electrically insulating body and a second patterned metal body at a second side of the electrically insulating body opposite to the first side; the first patterned metal body includes the first contact structure of the carrier; the second patterned metal body includes a conductive structure covering at least a portion of the edge termination region of the semiconductor die; the conductive structure is electrically connected to the first contact structure via a plurality of conductive vias extending through the electrically insulating body; and the PCB has a thickness between the first and second sides of the electrically insulating body, the thickness satisfying a gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the second patterned metal body.

[0131] Example 30: A semiconductor package according to any one of Examples 23 to 29, wherein: the first contact structure of the carrier includes a plurality of conductive vias attached to the first pad of the semiconductor die and extending through the electrically insulating body to a second side of the electrically insulating body; the plurality of conductive vias are connected to a patterned metal body at the second side of the electrically insulating body; the patterned metal body includes a conductive structure covering at least a portion of the edge termination region of the semiconductor die; and the carrier has a thickness between the first and second sides of the electrically insulating body, the thickness satisfying a gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the patterned metal body at the second side of the electrically insulating body of the carrier.

[0132] Example 31: A semiconductor package according to any one of Examples 23 to 30, wherein the carrier has a second contact structure at a first side of an electrically insulating body, wherein the second contact structure is electrically isolated from the first contact structure, wherein the semiconductor die has a second pad attached to the second contact structure of the carrier, and wherein the second pad is a control terminal pad.

[0133] Example 32, the semiconductor package according to any one of Examples 23 to 31, further includes: a metal plate attached to a pad on the side of the semiconductor die opposite to the carrier.

[0134] Example 33, a semiconductor package according to Example 32, wherein, outside the periphery of both the semiconductor die and the carrier, the metal plate is bent only at one end in a direction toward the carrier to provide terminals for pads on the side of the semiconductor die opposite to the carrier.

[0135] Example 34: A semiconductor package according to Example 32 or 33, wherein the size of the metal plate is independent of the size of the carrier but is based on the expected thermal load presented by the semiconductor die.

[0136] Example 35, the semiconductor package according to any one of Examples 32 to 34, further includes: a sealant that laterally surrounds the edge of the semiconductor die.

[0137] Example 36: A semiconductor package according to Example 35, wherein the sealant fills the gap between the edge termination region of the semiconductor die and the electrically insulating body of the carrier.

[0138] Example 37. A method of manufacturing a semiconductor package, the method comprising: providing a carrier having an electrically insulating body and a first contact structure at a first side of the electrically insulating body; and attaching a first pad of a semiconductor die to the first contact structure of the carrier, the first pad being at a source or emitter potential, wherein the first pad is spaced inwardly from an edge of the semiconductor die by a first distance, wherein the semiconductor die has an edge termination region between the edge and the first pad, wherein the first contact structure of the carrier is spaced inwardly from the edge of the semiconductor die by a second distance greater than the first distance, such that an electric field emitted from the edge termination region in the direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

[0139] Example 38, according to the method of Example 37, wherein: the carrier has a conductive structure at a second side of the electrically insulating body opposite to the first side; the conductive structure is electrically connected to the first contact structure and covers at least a portion of the edge termination region of the semiconductor die; and the carrier has a thickness between the first and second sides of the electrically insulating body, the thickness satisfying the gap requirement between the edge termination region of the semiconductor die and the conductive structure of the carrier.

[0140] Example 39. The method according to Example 38 or 39, wherein: providing a carrier includes embedding a copper block in an electrically insulating material to form a pre-molded carrier; a first side of the copper block is not covered by the electrically insulating material and forms the first contact structure of the carrier; a second side of the copper block opposite to the first side is not covered by the electrically insulating material and forms a conductive structure on the second side of the electrically insulating body opposite to the first side, and the conductive structure covers at least a portion of the edge termination region of the semiconductor die; and the electrically insulating material has a thickness between the edge termination region of the semiconductor die and the conductive structure on the second side of the electrically insulating body, the thickness satisfying a gap requirement between the edge termination region and the conductive structure.

[0141] Example 40, the method according to Example 38 or 39, wherein: providing a carrier includes forming a printed circuit board (PCB) having a first patterned metal body at a first side of an electrically insulating body and a second patterned metal body at a second side of the electrically insulating body opposite to the first side; the first patterned metal body includes the first contact structure of the carrier; the second patterned metal body includes a conductive structure covering at least a portion of the edge termination region of the semiconductor die; the conductive structure is electrically connected to the first contact structure via a plurality of conductive vias extending through the electrically insulating body; and the PCB has a thickness between the first and second sides of the electrically insulating body, the thickness satisfying a gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the second patterned metal body.

[0142] Example 41, the method according to Example 38 or 39, wherein: providing a carrier includes forming a plurality of conductive vias attached to a first pad of a semiconductor die and extending through an electrically insulating body to a second side of the electrically insulating body; the plurality of conductive vias forming a first contact structure of the carrier; the plurality of conductive vias connected to a patterned metal body at the second side of the electrically insulating body; the patterned metal body including a conductive structure covering at least a portion of the edge termination region of the semiconductor die; and the carrier having a thickness between the first and second sides of the electrically insulating body, the thickness satisfying a gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the patterned metal body at the second side of the electrically insulating body of the carrier.

[0143] Example 42, the method according to any one of Examples 38 to 41, further includes: attaching a metal plate to a pad on the side of the semiconductor die opposite to the carrier, wherein, outside the periphery of both the semiconductor die and the carrier, the metal plate is bent only at one end in a direction toward the carrier to provide a terminal for the pad on the side of the semiconductor die opposite to the carrier.

[0144] Terms such as "first" and "second" are used to describe various components, areas, parts, etc., and are not intended to be limiting. Throughout the specification, the same term refers to the same component.

[0145] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude other elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0146] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0147] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: A carrier having an electrically insulating body and a first contact structure at a first side of the electrically insulating body; A semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at a source or emitter potential; as well as A metal plate is attached to pads on the side of the semiconductor die opposite to the carrier. The dimensions of the metal plate are independent of the dimensions of the carrier, but are based on the expected thermal load presented by the semiconductor die. The first pad is spaced inwards from the edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. Wherein, the first contact structure of the carrier is spaced inwardly from the edge of the semiconductor die by a second distance greater than the first distance, such that during normal operation of the semiconductor die, the electric field emitted from the edge termination region in the direction of the carrier will not reach the first contact structure of the carrier, and Wherein, outside the periphery of both the semiconductor die and the carrier, the metal plate is bent at only one end in a direction toward the carrier to provide terminals for the pads on the side of the semiconductor die opposite to the carrier. Wherein, the dimension of the metal plate in the first direction of the two-dimensional plane is larger than the dimension of the carrier in the first direction. Wherein, the dimension of the metal plate in the second direction of the two-dimensional plane is smaller than the dimension of the carrier in the second direction. Wherein, the second direction is perpendicular to the first direction, and The two-dimensional plane is parallel to the metal plate and the carrier.

2. The semiconductor package according to claim 1, wherein: The carrier has a conductive structure on a second side of the electrically insulating body opposite to the first side; The conductive structure is electrically connected to the first contact structure and covers at least a portion of the edge termination region of the semiconductor die; and The carrier has a thickness between the first side and the second side of the electrically insulating body, the thickness satisfying the gap requirement between the edge termination region of the semiconductor die and the conductive structure of the carrier.

3. The semiconductor package according to claim 2, wherein, The thickness of the carrier between the first and second sides of the electrically insulating body is in the range of 100 μm to 800 μm.

4. The semiconductor package according to claim 1, wherein, The surface area of ​​the first contact structure of the carrier facing the first pad of the semiconductor die is smaller than the surface area of ​​the first pad of the first contact structure of the semiconductor die facing the carrier.

5. The semiconductor package according to claim 1, wherein, The carrier is a direct copper bonding substrate, an active metal brazing substrate, or an insulating metal substrate having a first patterned metal body on the first side of the electrically insulating body, wherein the first patterned metal body includes the first contact structure of the carrier.

6. The semiconductor package according to claim 1, wherein: The carrier is a pre-molded carrier having copper blocks embedded in an electrically insulating material; The first side of the copper block is not covered by the electrical insulating material and forms the first contact structure of the carrier; The second side of the copper block, opposite to the first side of the copper block, is not covered by the electrical insulating material, and a conductive structure is formed on the second side of the electrical insulating body opposite to the first side of the electrical insulating body, and the conductive structure covers at least a portion of the edge termination region of the semiconductor die; and The electrical insulating material has a thickness between the edge termination region of the semiconductor die and the conductive structure at the second side of the electrical insulating body, the thickness of the electrical insulating material satisfying the gap requirement between the edge termination region and the conductive structure.

7. The semiconductor package according to claim 1, wherein: The carrier is a printed circuit board (PCB) having a first patterned metal body on the first side of the electrical insulating body and a second patterned metal body on the second side of the electrical insulating body opposite to the first side of the electrical insulating body. The first patterned metal body includes the first contact structure of the carrier; The second patterned metal body includes a conductive structure covering at least a portion of the edge termination region of the semiconductor die; The conductive structure is electrically connected to the first contact structure via a plurality of conductive vias extending through the electrically insulating body; and The printed circuit board has a thickness between the first side and the second side of the electrically insulating body, and the thickness of the printed circuit board satisfies the gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the second patterned metal body.

8. The semiconductor package according to claim 1, wherein: The first contact structure of the carrier includes a plurality of conductive vias, which are attached to the first pad of the semiconductor die and extend through the electrical insulating body to a second side of the electrical insulating body. The plurality of conductive vias are connected to a patterned metal body on the second side of the electrically insulating body; The patterned metal body includes a conductive structure covering at least a portion of the edge termination region of the semiconductor die; and The carrier has a thickness between the first side and the second side of the electrically insulating body, the thickness of the carrier satisfying the gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the patterned metal body at the second side of the electrically insulating body of the carrier.

9. The semiconductor package according to claim 1, wherein, The carrier has a second contact structure at the first side of the electrically insulating body, wherein the second contact structure is electrically isolated from the first contact structure, wherein the semiconductor die has a second pad attached to the second contact structure of the carrier, and wherein the second pad is a control terminal pad.

10. The semiconductor package according to claim 1, further comprising: A sealant that laterally surrounds the edge of the semiconductor die.

11. The semiconductor package of claim 10, wherein, The sealant fills the gap between the edge termination region of the semiconductor die and the electrically insulating body of the carrier.

12. A method for manufacturing a semiconductor package, the method comprising: A carrier is provided, the carrier having an electrically insulating body and a first contact structure at a first side of the electrically insulating body; The first pad of the semiconductor die is attached to the first contact structure of the carrier, and the first pad is at the source or emitter potential. as well as A metal plate is attached to a pad on the side of the semiconductor die opposite to the carrier. The dimensions of the metal plate are independent of the dimensions of the carrier, but are based on the expected thermal load presented by the semiconductor die. The first pad is spaced inwards from the edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inwardly from the edge of the semiconductor die by a second distance greater than the first distance, such that during normal operation of the semiconductor die, the electric field emitted from the edge termination region in the direction of the carrier will not reach the first contact structure of the carrier. Wherein, outside the periphery of both the semiconductor die and the carrier, the metal plate is bent at only one end in a direction toward the carrier to provide terminals for the pads on the side of the semiconductor die opposite to the carrier. Wherein, the dimension of the metal plate in the first direction of the two-dimensional plane is larger than the dimension of the carrier in the first direction. Wherein, the dimension of the metal plate in the second direction of the two-dimensional plane is smaller than the dimension of the carrier in the second direction. Wherein, the second direction is perpendicular to the first direction, and The two-dimensional plane is parallel to the metal plate and the carrier.

13. The method of claim 12, wherein: The carrier has a conductive structure on a second side of the electrically insulating body opposite to the first side; The conductive structure is electrically connected to the first contact structure and covers at least a portion of the edge termination region of the semiconductor die; and The carrier has a thickness between the first side and the second side of the electrically insulating body, the thickness satisfying the gap requirement between the edge termination region of the semiconductor die and the conductive structure of the carrier.

14. The method according to claim 12, wherein: Providing the carrier includes embedding a copper block into an electrically insulating material to form a pre-molded carrier; The first side of the copper block is not covered by the electrical insulating material and forms the first contact structure of the carrier; The second side of the copper block, opposite to the first side of the copper block, is not covered by the electrical insulating material, and a conductive structure is formed on the second side of the electrical insulating body opposite to the first side of the electrical insulating body, and the conductive structure covers at least a portion of the edge termination region of the semiconductor die; and The electrical insulating material has a thickness between the edge termination region of the semiconductor die and the conductive structure on the second side of the electrical insulating body, the thickness satisfying the gap requirement between the edge termination region and the conductive structure.

15. The method according to claim 12, wherein: Providing the carrier includes forming a printed circuit board (PCB) having a first patterned metal body at a first side of the electrical insulating body and a second patterned metal body at a second side of the electrical insulating body opposite to the first side; The first patterned metal body includes the first contact structure of the carrier; The second patterned metal body includes a conductive structure covering at least a portion of the edge termination region of the semiconductor die; The conductive structure is electrically connected to the first contact structure via a plurality of conductive vias extending through the electrically insulating body; and The printed circuit board has a thickness between the first side and the second side of the electrically insulating body, the thickness satisfying the gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the second patterned metal body.

16. The method of claim 12, wherein: Providing the carrier includes forming a plurality of conductive vias, the plurality of conductive vias being attached to the first pad of the semiconductor die and extending through the electrically insulating body to a second side of the electrically insulating body; The plurality of conductive vias form the first contact structure of the carrier; The plurality of conductive vias are connected to a patterned metal body on the second side of the electrically insulating body; The patterned metal body includes a conductive structure covering at least a portion of the edge termination region of the semiconductor die; and The carrier has a thickness between the first and second sides of the electrically insulating body, the thickness satisfying the gap requirement between the edge termination region of the semiconductor die and the conductive structure formed in the patterned metal body at the second side of the electrically insulating body of the carrier.

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