Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a chip, a first edge pad, a first central pad, a second edge pad, and a second central pad. The substrate has a first surface and a conductive trace extending on the substrate. The chip is on the first surface of the substrate. The chip has a sidewall, a central region, and an edge region between the central region and the sidewall. The first edge pad is on the edge region of the chip. The first central pad is on the central region of the chip and electrically connected to the first edge pad. The second edge pad is on the edge region of the chip. A distance between the first edge pad and the sidewall of the chip is substantially less than a distance between the second edge pad and the sidewall of the chip. The second central pad is on the central region of the chip and electrically connected to the second edge pad. Thus, the semiconductor structure of the present disclosure can reduce the capacitance, thereby improving the output signal of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure. BACKGROUND

[0002] Semiconductor elements are indispensable for many modern electronic applications. As electronic technology advances, semiconductor elements are becoming smaller in size while having more functions and more integrated circuits. Due to the miniaturization of semiconductor elements, various types and sizes of semiconductor elements performing different functions are integrated and packaged into a single module. In addition, in order to integrate various types of semiconductor elements, a large number of manufacturing operations are implemented.

[0003] However, the manufacturing and integration of semiconductor elements involve many complex steps and operations. The integration of semiconductor elements in thin and high-density configurations becomes more complex. The increase in the complexity of the manufacturing and integration of semiconductor elements can result in defects such as poor electrical interconnections and interference. SUMMARY

[0004] The present disclosure relates to a semiconductor structure.

[0005] According to some embodiments of the present disclosure, a semiconductor structure includes a substrate, a chip, a first edge pad, a first central pad, a second edge pad, and a second central pad. The substrate has a first surface and a conductive trace extending on the substrate. The chip is on the first surface of the substrate. The chip has a sidewall, a central region, and an edge region between the central region and the sidewall. The first edge pad is on the edge region of the chip. The first central pad is on the central region of the chip and electrically connected to the first edge pad. The second edge pad is on the edge region of the chip. A distance between the first edge pad and the sidewall of the chip is substantially smaller than a distance between the second edge pad and the sidewall of the chip. The second central pad is on the central region of the chip and electrically connected to the second edge pad.

[0006] In some embodiments, the first edge pad and the first central pad are aligned in a first direction, and the second edge pad and the second central pad are substantially aligned in the first direction.

[0007] In some embodiments, the first central pad and the second central pad are aligned in a second direction substantially perpendicular to the first direction.

[0008] In some embodiments, the first edge pad and the first central pad are connected by a power line, and the second edge pad and the second central pad are connected by a signal line.

[0009] In some embodiments, a length of the power line is substantially greater than a length of the signal line.

[0010] In some embodiments, a width of the power line is substantially greater than a width of the signal line.

[0011] In some implementations, the semiconductor structure includes a first bond wire and a second bond wire. The first bond wire electrically connects between the substrate and the first edge pad. The second bond wire electrically connects between the substrate and the second edge pad.

[0012] In some implementations, a vertical projection length of the first bond wire on the chip is substantially less than a vertical projection length of the second bond wire on the chip.

[0013] In some implementations, the first bond wire is separated from the first central pad, and the second bond wire is separated from the second central pad.

[0014] In some implementations, a ratio of a length of the second bond wire to a length of the signal line is in a range of 0.5 to 2.

[0015] In some implementations, the semiconductor structure further includes an encapsulation, the encapsulation being on the first surface of the substrate and covering the chip.

[0016] In some implementations, the semiconductor structure further includes a conductive bump, the conductive bump being on a second surface of the substrate opposite the first surface of the substrate.

[0017] Another technical aspect of the present disclosure is a semiconductor structure.

[0018] According to some implementations of the present disclosure, a semiconductor structure includes a substrate, a chip, an edge pad, a central pad, a signal line, and a bond wire. The substrate has a first surface and a conductive trace extending on the substrate. The chip is on the first surface of the substrate. The edge pad is on the chip. The central pad is on a central region of the chip. The signal line is on the chip, the signal line interconnecting the edge pad and the central pad. The bond wire electrically connects between the substrate and the edge pad. A ratio of a length of the bond wire to a length of the signal line is in a range of 0.5 to 2.

[0019] In some implementations, the length of the bond wire is substantially equal to the length of the signal line.

[0020] In some implementations, the bond wire extends from the conductive trace to the edge pad.

[0021] In some implementations, the semiconductor structure further includes a power line. The power line is on the chip, the power line being substantially coplanar with the signal line.

[0022] In some implementations, the length of the power line is substantially greater than the length of the signal line.

[0023] In some implementations, the semiconductor structure further includes an encapsulation, the encapsulation being on the first surface of the substrate and covering the chip.

[0024] In some implementations, the encapsulation gel contacts the edge pad, the center pad, and the signal line.

[0025] In some implementations, the semiconductor structure further includes a conductive bump on a second surface of the substrate opposite the first surface of the substrate.

[0026] According to the above implementations of the present disclosure, since the distance between the first edge pad and the sidewall of the chip is substantially smaller than the distance between the second edge pad and the sidewall of the chip, the capacitance can be reduced. In this way, the output signal of the semiconductor structure can be improved.

[0027] It should be apparent that the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] Aspects of the present disclosure can be understood from the following detailed description in conjunction with the drawings.

[0029] Figure 1 is a top view of a layout of a semiconductor structure according to some implementations of the present disclosure.

[0030] Figure 2A is a cross-sectional view taken along line 2A-2A of Figure 1

[0031] Figure 2B is a cross-sectional view taken along line 2B-2B of Figure 1

[0032] Figure 3 is a cross-sectional view taken along line 3-3 of Figure 1

[0033] Figure 4 is a cross-sectional view taken along line 4-4 of Figure 1

[0034] Figure 5 is a schematic diagram illustrating an input signal and an output signal. DETAILED DESCRIPTION

[0035] Several embodiments of the present disclosure will be described with reference to the drawings. For the purpose of explanation, numerous specific details will be set forth in the description of the embodiments. It should be noted, however, that these specific details are not to be taken into inflexible planning of the present disclosure, as the embodiments are presented as examples of the present disclosure only. That is, the present disclosure is well suited to the application but, optionally, can also be directed to other applications. Moreover, in the following detailed description, numerous specific details are given regarding the application. However, it will be apparent that the application can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the present disclosure. In addition, some of the details have been simplified and are shown in simplified or partial form. Similarly, block diagram blocks that are represented by broken lines represent optional blocks that can or can not be part of the present disclosure.

[0036] ​​​​As used in the present disclosure, "around," "about," "approximately," or "substantially" generally means within 20% or within 10%, or within 5% of a given value or range. Values given in the present disclosure are approximate, meaning that the term "around," "about," "approximately," or "substantially" can be inferred if not explicitly stated.

[0037] Figure 1 is a top view of a layout of a semiconductor structure 100 according to some embodiments of the present disclosure, Figure 2A is a cross-sectional view taken along Figure 1 line 2A-2A of semiconductor structure 100, and Figure 2B is a cross-sectional view taken along Figure 1 line 2B-2B of semiconductor structure 100. For clarity, the substrate 110 and the bond wires (e.g., the first bond wire 190, the second bond wire 200, the bond wire 310, and the bond wire 350) are illustrated in the cross-sectional views and are omitted in the top view. In some embodiments, the semiconductor structure 100 is a semiconductor package or a portion of a semiconductor package. See Figure 1 , Figure 2A and Figure 2B , the semiconductor structure 100 includes a substrate 110, a chip 120, a first edge pad 130, a first central pad 140, a second edge pad 150, and a second central pad 160.

[0038] The substrate 110 includes a core layer 115 and has a first surface 111 and a second surface 113 opposite to the first surface 111. In some embodiments, the core layer 115 has a quadrilateral shape, a rectangular shape, a square shape, a polygonal shape, or any other suitable shape. In some embodiments, the core layer 115 is a semiconductor substrate. The core layer 115 can include an elemental semiconductor, a compound semiconductor, an alloy semiconductor, or a combination thereof. The elemental semiconductor can be, for example, germanium (Ge) or silicon (Si). The compound semiconductor can include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor can include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, the core layer 115 includes a material such as ceramic, glass, or the like.

[0039] In some embodiments, the core layer 115 has a predetermined functional circuit fabricated thereon. The substrate 110 can further include a conductive trace 112 extending on the first surface 111 of the substrate 110. The conductive trace 112 can be made of copper, tungsten, aluminum, palladium, an alloy of the above, or other suitable materials.

[0040] Chip 120 can be disposed on first surface 111 of substrate 110. In some embodiments, chip 120 contains various circuits suitable for a particular application. Chip 120 can contain semiconductor elements such as memory, microprocessors, application-specific integrated circuits (ASICs), etc. In some embodiments, chip 120 is a dynamic random access memory (DRAM) chip.

[0041] In some embodiments, chip 120 has a front side 121, a back side 123 opposite front side 121, first side walls 122a and 122b opposite each other, and second side walls 122c and 122d opposite each other. First side walls 122a and 122b, second side walls 122c and 122d connect front side 121 and back side 123 such that first side walls 122a and 122b, second side walls 122c and 122d, front side 121, and back side 123 form an outer boundary of chip 120. Chip 120 also has a central region 124 and edge regions 126a and 126b. Edge region 126a is between central region 124 and first side wall 122a, and edge region 126b is between central region 124 and first side wall 122b. Back side 123 of chip 120 is electrically connected to conductive traces 112 of substrate 110. In some embodiments, chip 120 is bonded over substrate 110 by an adhesive material such as a gel. For example, the adhesive material contacts back side 123 of chip 120 and conductive traces 112 of substrate 110.

[0042] A redistribution layer (RDL) is disposed on front side 121 of chip 120 to connect input / output pads of chip 120 to bond wires. As shown in FIG. 1, RDL 130 is disposed on front side 121 of chip 120. RDL 130 is electrically connected to input / output pads of chip 120. In some embodiments, RDL 130 is electrically connected to conductive traces 112 of substrate 110. For example, RDL 130 is electrically connected to conductive traces 112 of substrate 110 by bond wires 140. Figure 1As shown, the redistribution layer includes a plurality of central pads (e.g., first central pad 140 and second central pad 160), a plurality of edge pads (e.g., first edge pad 130 and second edge pad 150), and a plurality of conductors (e.g., power line 170, signal line 180, power line 230, signal line 300, and signal line 340). The central pads are disposed on the central region 124 of the chip 120, while the edge pads are disposed on the edge regions 126a or 126b of the chip 120. In some embodiments, the chip 120 has vertical connection elements (e.g., vertical vias) electrically connected to the central pads, while the edge pads are separated from the vertical connection elements of the chip 120. Conductors interconnect the central pads and edge pads such that the edge pads can be electrically connected to the vertical connection elements via corresponding conductors to the central pads, forming a fan-out configuration. The connected central pads and edge pads (e.g., central pad 140 and edge pad 130) are substantially arranged in a first direction D1.

[0043] The central pad is positioned on a second direction D2, which is different from the first direction D1. For example, the second direction D2 is substantially perpendicular to the first direction D1. Figure 1 There are two central pads. However, the number of central pads can be one or more than three. In addition, edge pads are arranged in the second direction D2.

[0044] The conductors include signal lines (e.g., signal line 180, signal line 300, signal line 340) and power lines (power line 170, power line 230). Each conductor extends substantially in a first direction D1. Power lines may be coupled to a Vdd source or a ground source. Signal lines may be coupled to a wave source (e.g., address, data, and / or annotation signals).

[0045] like Figure 1 and Figure 2A As shown, a first edge pad 130 is disposed on the edge region 126a of the chip 120. A first central pad 140 is disposed on the central region 124 of the chip 120 and is electrically connected to the first edge pad 130. In some embodiments, such as Figure 1 As shown, the first edge pad 130 and the first central pad 140 are aligned in the first direction D1.

[0046] like Figure 1 and Figure 2B As shown, a second edge pad 150 may be disposed on the edge region 126a of the chip 120. A second central pad 160 is disposed on the central region 124 of the chip 120 and is electrically connected to the second edge pad 150. In some embodiments, the distance d1 between the first edge pad 130 and the sidewall 122a of the chip 120 is substantially smaller than the distance d2 between the second edge pad 150 and the sidewall 122a of the chip 120. In other words, Figure 2AWith Figure 2B The reference line RL is adjacent to the sidewall 122a of the chip 120. The reference line RL passes through the first edge pad 130 in the Figure 2A but not through the second edge pad 150 in the Figure 2B The second edge pad 150 is separated from the reference line RL by a distance. Since the distance dl is substantially less than the distance d2, the capacitance (e.g., between the signal line and the conductive line of the chip 120) can be reduced. In this way, the output signal of the semiconductor structure 100 can be improved.

[0047] As shown in Figure 1 The second edge pad 150 and the second central pad 160 can be substantially aligned in the first direction Dl. In some embodiments, the first central pad 140 and the second central pad 160 are aligned in a second direction D2 that is substantially perpendicular to the first direction Dl.

[0048] In some embodiments, the first edge pad 130 and the first central pad 140 are connected by a power line 170, and the second edge pad 150 and the second central pad 160 are connected by a signal line 180. In other words, the power line 170 interconnects the first edge pad 130 and the first central pad 140, and the signal line 180 interconnects the second edge pad 150 and the second central pad 160.

[0049] In some embodiments, the length of the power line 170 is substantially greater than the length of the signal line 180. The length of the power line 170 can be in the range of about 3500 micrometers to about 4500 micrometers, and the length of the signal line 180 can be in the range of about 1500 micrometers to about 2500 micrometers. For example, the length of the power line 170 is about 4000 micrometers, and the length of the signal line 180 is about 2000 micrometers. In some embodiments, the length of the signal line 180 is substantially in the range of one-third to two-thirds of the length of the power line 170. In some embodiments, the length of the signal line 180 is substantially half of the length of the power line 170. With this configuration, the capacitance can be reduced, thereby improving the output signal.

[0050] In some embodiments, as shown in Figure 1 The width wl of the power line 170 is substantially greater than the width w2 of the signal line 180. In some embodiments, the first edge pad 130 that is electrically connected to the power line 170 is substantially closer to the sidewall 122a of the chip 120 than the second edge pad 150 that is electrically connected to the signal line 180.

[0051] In some embodiments, the semiconductor structure 100 further comprises a plurality of bonding wires (e.g., the first bonding wire 190 and the second bonding wire 200) connecting corresponding edge pads (e.g., the first edge pad 130 and the second edge pad 150). The first bonding wire 190 electrically connects between the substrate 110 and the first edge pad 130. The second bonding wire 200 electrically connects between the substrate 110 and the second edge pad 150. In other words, the first bonding wire 190 extends from the conductive trace 112 of the substrate 110 to the first edge pad 130, and the second bonding wire 200 extends from the conductive trace 112 of the substrate 110 to the second edge pad 150. In some embodiments, one end of the first bonding wire 190 is located at the position of the reference line RL (see Figure 2A ) and the second bonding wire 200 extends through the reference line RL (see Figure 2B ).

[0052] In some embodiments, the vertical projection length PL1 of the first bonding wire 190 on the chip 120 is substantially less than the vertical projection length PL2 of the second bonding wire 200 on the chip 120, where the vertical projection length PL1 is substantially equal to the distance between the sidewall 122a of the chip 120 and the reference line RL.

[0053] In some embodiments, as shown in Figure 2A , the first bonding wire 190 contacts the first edge pad 130 and the first bonding wire 190 is separated from the first central pad 140. In some embodiments, as shown in Figure 2B , the second bonding wire 200 contacts the second edge pad 150 and the second bonding wire 200 is separated from the second central pad 160.

[0054] In some embodiments, the ratio of the length of the second bonding wire 200 to the length of the signal line 180 is in the range of 0.5 to 2, so that the capacitance (e.g., the capacitance between the signal line 180 and the conductive pin in the chip 120) can be reduced. In this way, the output signal of the semiconductor structure 100 can be improved. In addition, the packaging of the semiconductor structure 100 can be simplified, thereby reducing the manufacturing cost. If the ratio of the length of the second bonding wire 200 to the length of the signal line 180 is less than about 0.5, the capacitance between the signal line 180 and the conductive pin in the chip 120 (e.g., the conductive pin) is high, resulting in poor electrical interconnection. For example, when the capacitance is high, the output signal is attenuated from the input end to the output end. As Figure 5As shown, when the ratio of the length of the second bond wire 200 to the length of the signal line 180 is less than about 0.5, the input signal IS is attenuated and an output signal OSi is generated. In contrast, when the ratio of the length of the second bond wire 200 to the length of the signal line 180 is in the range of about 0.5 to 2, the input signal IS is not attenuated (e.g., signal attenuation can be negligible or avoided) and an improved output signal OS2 is generated.

[0055] In some embodiments, the length of the second bond wire 200 is substantially equal to the length of the signal line 180. For example, the length of the second bond wire 200 is about 2000 microns, and the length of the signal line 180 is also about 2000 microns. In some other embodiments, the length of the second bond wire 200 is substantially greater than the length of the signal line 180.

[0056] In some embodiments, the first bond wire 190 and the second bond wire 200 comprise copper, gold, or any other suitable material. In some embodiments, the first bond wire 190 and the second bond wire 200 comprise a metal, such as gold or other suitable material.

[0057] In some embodiments, as Figure 1 In some embodiments, as Figure 2B As shown, the semiconductor structure 100 also includes another central pad 210 and another edge pad 220, where the central pad 210 and the edge pad 220 are connected by another power line 230. In other words, the power line 230 is disposed on the chip 120 and interconnects the central pad 210 and the edge pad 220. The power line 230 is substantially coplanar with the signal line 180. In some embodiments, the length of the power line 230 is substantially greater than the length of the signal line 180. The length of the power line 230 can be in the range of about 3500 microns to about 4500 microns. For example, the length of the power line 230 is about 4000 microns, and the length of the signal line 180 is about 2000 microns. In some embodiments, the length of the signal line 180 is substantially in the range of one-third to two-thirds of the length of the power line 230. In some embodiments, the length of the signal line 180 is substantially half of the length of the power line 230. With this configuration, the capacitance can be reduced, thereby improving the output signal.

[0058] In some embodiments, the semiconductor structure 100 further includes another bond wire 240 electrically connecting between the substrate 110 and the edge pad 220. In other words, the bond wire 240 extends from the conductive trace 112 of the substrate 110 to the edge pad 220. In some embodiments, the length of the bond wire 240 is substantially smaller than the length of the second bond wire 200. The vertically projected length of the bond wire 240 on the sidewall 122b of the chip 120 (on the opposite side relative to the sidewall 122a of the chip 120) is substantially smaller than the vertically projected length PL2 of the second bond wire 200 on the sidewall 122a of the chip 120. In some embodiments, the bond wire 240 contacts the edge pad 220, and the bond wire 240 is separated from the central pad 210.

[0059] Figure 2B The other relevant structures and fabrication details of the central pad 210, the edge pad 220, the power line 230, and the bond wire 240 are substantially the same as or similar to those of the first edge pad 130, the first central pad 140, the power line 170, and the first bond wire 190 of Figure 2A , and thus are not repeated here.

[0060] In some embodiments, as shown in Figure 2A and Figure 2B , the semiconductor structure 100 includes a molding compound 250 located above the substrate 110 and covering the redistribution layer. In detail, the molding compound 250 is disposed on the first surface 111 of the substrate 110 and covers (or encapsulates) the chip 120. In some embodiments, the molding compound 250 is disposed on the conductive trace 112 of the substrate 110 and exposes the sidewall of the conductive trace 112. In Figure 2A , the molding compound 250 surrounds the chip 120, the power line 170, and the first bond wire 190. As such, the molding compound 250 contacts the first edge pad 130, the first central pad 140, the power line 170, and the first bond wire 190. In Figure 2B , the molding compound 250 surrounds the chip 120, the signal line 180, the power line 230, the second bond wire 200, and the bond wire 240. As such, the molding compound 250 contacts the chip 120, the second edge pad 150, the edge pad 220, the second central pad 160, the central pad 210, the signal line 180, the power line 230, the second bond wire 200, and the bond wire 240.

[0061] In some embodiments, the molding compound 250 can be a single layer of film or a composite stack. The molding compound 250 can include various materials, such as a molding compound, a molding compound underfill, an epoxy, a resin, etc. In some embodiments, the molding compound 250 has high thermal conductivity, low moisture absorption, and / or high flexural strength.

[0062] In some embodiments, the substrate 110 further comprises electrically conductive traces 116 extending on the second surface 113 of the substrate 110 and a plurality of electrically conductive vias 114 extending through the substrate 110. The electrically conductive vias 114 can interconnect the electrically conductive traces 112 and the electrically conductive traces 116. The electrically conductive vias 114 can be made of gold, silver, copper, nickel, tungsten, aluminum, palladium, alloys of the above, or other suitable materials.

[0063] In some embodiments, the semiconductor structure 100 further comprises electrically conductive bumps 260 on the second surface 113 of the substrate 110. The electrically conductive bumps 260 can comprise electrically conductive materials such as solder, copper, nickel, or gold. In some embodiments, the electrically conductive bumps 260 are solder balls, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, micro bumps, pillars, or the like. In some embodiments, the electrically conductive bumps 260 have a spherical, semi-spherical, or cylindrical shape. The signal of the first central pad 140 is electrically connected to one of the electrically conductive bumps 260 through the power line 170, the first edge pad 130, the first bond wire 190, the electrically conductive traces 112, and the electrically conductive vias 114. Similarly, the signal of the second central pad 160 is electrically connected to another of the electrically conductive bumps 260 through the signal line 180, the second edge pad 150, the second bond wire 200, the electrically conductive traces 112, and the electrically conductive vias 114.

[0064] Returning to Figure 1 , the layout of the semiconductor structure 100 shows a fan-out lines structure. Figure 3 is a cross-sectional view taken along line 3-3 of Figure 1 , and Figure 4 is a cross-sectional view taken along line 4-4 of Figure 1 .

[0065] Referring to Figure 1 and Figure 3The semiconductor structure 100 further includes an edge pad 270, a central pad 280, a central pad 290, a signal line 300, and a bonding line 310. The edge pad 270, central pad 280, central pad 290, and signal line 300 are disposed above the chip 120. The signal line 300 interconnects the edge pad 270 and the central pad 280. The bonding line 310 electrically connects the substrate 110 and the edge pad 270. In other words, the bonding line 310 extends from a conductive trace 112 on the substrate 110 to the edge pad 270. In some embodiments, the bonding line 310 contacts the edge pad 270 and is separated from the central pads 280 and 290. In some embodiments, the central pad 290 is electrically connected to another signal line adjacent to the signal line 300.

[0066] In some embodiments, the ratio of the length of the bonding line 310 to the length of the signal line 300 is in the range of 0.5 to 2, thus reducing capacitance (e.g., the capacitance between the signal line 300 and the wires of the chip 120). This improves the output signal of the semiconductor structure 100. Furthermore, the packaging of the semiconductor structure 100 can be simplified, thereby reducing manufacturing costs. Figure 3 The edge pad 270, center pad 280, center pad 290, signal line 300, and other related structural and manufacturing details of the bonding line 310 are substantially the same as or similar to those of the other components. Figure 2B The second edge pad 150, the second central pad 160, the central pad 210, the signal line 180, and the second bonding line 200 are not described in detail here.

[0067] See Figure 1 and Figure 4 The semiconductor structure 100 further includes an edge pad 320, a central pad 330, a signal line 340, and a bonding line 350. The edge pad 320, central pad 330, and signal line 340 are disposed above the chip 120. The signal line 340 interconnects the edge pad 320 and the central pad 330. The bonding line 350 electrically connects the substrate 110 and the edge pad 320. In other words, the bonding line 350 extends from a conductive trace 112 on the substrate 110 to the edge pad 320. In some embodiments, the bonding line 350 contacts the edge pad 320, and the bonding line 350 is separated from the central pad 330.

[0068] In some embodiments, the ratio of the length of the bonding line 350 to the length of the signal line 340 is in the range of 0.5 to 2, thus reducing capacitance (e.g., the capacitance between the signal line 300 and the wires of the chip 120). This improves the output signal of the semiconductor structure 100. Furthermore, the packaging of the semiconductor structure 100 can be simplified, thereby reducing manufacturing costs. Figure 4The other relevant structures and manufacturing details of the edge pads 320, the central pads 330, the signal lines 340, and the bonding wires 350 are substantially the same or similar to those of the second edge pads 150, the second central pads 160, the signal lines 180, and the second bonding wires 200 of the semiconductor structure 100 of FIG. 1, and thus are not repeated here. Figure 2B The other relevant structures and manufacturing details of the edge pads 320, the central pads 330, the signal lines 340, and the bonding wires 350 are substantially the same or similar to those of the second edge pads 150, the second central pads 160, the signal lines 180, and the second bonding wires 200 of the semiconductor structure 100 of FIG. 1, and thus are not repeated here.

[0069] While the present disclosure has been disclosed in its preferred form with reference to specific embodiments, it is not to be limited to the particulars so disclosed but extends to numerous alternatives, modifications, and equivalents as will be readily apparent to those ordinarily skilled in the art. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0070] Various modifications and alterations of this disclosure will become apparent to those skilled in the art from the foregoing description without departing from the scope and spirit of this disclosure. It should be understood that this disclosure is not intended to be unduly limited by the illustrative embodiments and examples that have been set forth herein and that such examples and embodiments have been chosen and first presented by way of example and exposition only. Any combination of the above-described elements in all possible variations thereof is encompassed by the application unless otherwise indicated herein or otherwise clearly contradicted by context.

[0071] [SYMBOL DESCRIPTION]

[0072] 100: semiconductor structure

[0073] 110: substrate

[0074] 111: first surface

[0075] 112: conductive trace

[0076] 113: second surface

[0077] 114: conductive via

[0078] 115: core layer

[0079] 116: conductive trace

[0080] 120: chip

[0081] 121: front side

[0082] 122a: sidewall

[0083] 122b: sidewall

[0084] 122c: sidewall

[0085] 122d: sidewall

[0086] 123: back side

[0087] 124: central region

[0088] 126a: edge region

[0089] 126b: edge region

[0090] 130: edge pad

[0091] 140: central pad

[0092] 150: edge pad

[0093] 160: center pad

[0094] 170: power line

[0095] 180: signal line

[0096] 190: first bonding wire

[0097] 200: second bonding wire

[0098] 210: center pad

[0099] 220: edge pad

[0100] 230: power line

[0101] 240: bonding wire

[0102] 250: encapsulation

[0103] 260: conductive bump

[0104] 270: edge pad

[0105] 280: center pad

[0106] 290: center pad

[0107] 300: signal line

[0108] 310: bonding wire

[0109] 320: edge pad

[0110] 330: center pad

[0111] 340: signal line

[0112] 350: bonding wire

[0113] D1: first direction

[0114] D2: second direction

[0115] d1: distance

[0116] d2: distance

[0117] IS: input signal

[0118] OS1: output signal

[0119] OS2: output signal

[0120] PL1: perpendicular projection length

[0121] PL2: perpendicular projection length

[0122] RL: reference line

[0123] w1: width

[0124] w2: width

[0125] 2A-2A: line

[0126] 2B-2B: line

[0127] 3-3: line

[0128] 4-4: line

Claims

1. A semiconductor structure, characterized by, A semiconductor structure, comprising: a substrate having a first surface and a conductive trace extending on the substrate; a chip located on the first surface of the substrate, wherein the chip has a sidewall, a central region, and a peripheral region between the central region and the sidewall; a first peripheral pad located on the peripheral region of the chip; a first central pad located on the central region of the chip and electrically connected to the first peripheral pad; a second peripheral pad located on the peripheral region of the chip, wherein a distance between the first peripheral pad and the sidewall of the chip is substantially smaller than a distance between the second peripheral pad and the sidewall of the chip; a second central pad located on the central region of the chip and electrically connected to the second peripheral pad; a first bonding wire electrically connecting between the substrate and the first peripheral pad, and the first bonding wire physically contacts the first peripheral pad; and a second bonding wire electrically connecting between the substrate and the second peripheral pad, and the second bonding wire physically contacts the second peripheral pad.

2. The semiconductor structure of claim 1, wherein the first peripheral pad and the first central pad are aligned in a first direction, and wherein the second peripheral pad and the second central pad are substantially aligned in the first direction.

3. The semiconductor structure of claim 2, wherein the first central pad and the second central pad are aligned in a second direction substantially perpendicular to the first direction.

4. The semiconductor structure of claim 1, wherein the first peripheral pad and the first central pad are connected by a power line, and wherein the second peripheral pad and the second central pad are connected by a signal line.

5. The semiconductor structure of claim 4, wherein a length of the power line is substantially greater than a length of the signal line.

6. The semiconductor structure of claim 4, wherein a width of the power line is substantially greater than a width of the signal line.

7. The semiconductor structure of claim 1, wherein a length of a vertical projection of the first bonding wire on the chip is substantially smaller than a length of a vertical projection of the second bonding wire on the chip.

8. The semiconductor structure of claim 1, wherein the first bonding wire is separated from the first central pad, and the second bonding wire is separated from the second central pad.

9. The semiconductor structure of claim 1, wherein the second peripheral pad and the second central pad are connected by a signal line, and a ratio of a length of the second bonding wire to a length of the signal line is in a range of 0.5 to 2.

10. The semiconductor structure of claim 1, further comprising: an encapsulation located on the first surface of the substrate and covering the chip.

11. The semiconductor structure of claim 1, further comprising: a conductive bump located on a second surface of the substrate opposite to the first surface of the substrate. A semiconductor structure, comprising:

12. A semiconductor structure, characterized by a substrate having a first surface and a conductive trace extending on the substrate; a chip located on the first surface of the substrate; a first peripheral pad and a second peripheral pad located on the chip; a central pad located on a central region of the chip; a signal line located on the chip, the signal line interconnecting the second peripheral pad and the central pad; ​ a first bond wire electrically connecting between the substrate and the first edge pad, wherein the first bond wire physically contacts the first edge pad, wherein a ratio of a length of the first bond wire to a length of the signal line is in a range of 0.5 to 2; and a second bond wire electrically connecting between the substrate and the second edge pad, and the second bond wire physically contacts the second edge pad.

13. The semiconductor structure of claim 12, wherein the length of the second bond wire is substantially equal to the length of the signal line.

14. The semiconductor structure of claim 12, wherein the first bond wire extends from the conductive trace to the first edge pad, and the second bond wire extends from the conductive trace to the second edge pad.

15. The semiconductor structure of claim 12, further comprising: a power supply line on the chip, the power supply line being substantially coplanar with the signal line.

16. The semiconductor structure of claim 15, wherein a length of the power supply line is substantially greater than the length of the signal line.

17. The semiconductor structure of claim 12, further comprising: an encapsulation die on the first surface of the substrate and covering the chip.

18. The semiconductor structure of claim 17, wherein the encapsulation die contacts the first edge pad, the center pad, and the signal line.

19. The semiconductor structure of claim 12, further comprising: a conductive bump on a second surface of the substrate opposite the first surface of the substrate.

Images