Multi-chip package and manufacturing method thereof

Abstract

The present invention discloses a multi-chip package and a method for manufacturing the same, and belongs to the field of semiconductor packaging. The package of the present invention includes a substrate, a first chip, a second chip, a Hall device, a first plastic package and a second plastic package. The upper surface and the lower surface of the substrate are provided with a first redistribution layer and a second redistribution layer, respectively; the first chip and the second chip are provided on the first redistribution layer and the second redistribution layer, respectively; the Hall device is provided in the substrate, and the first redistribution layer and the second redistribution layer are connected to the Hall device, respectively; the first plastic package is used to wrap the first redistribution layer and the first chip; the second plastic package is used to wrap the second redistribution layer and the second chip. The present invention overcomes the problems of low reliability and high production cost of the packages of Hall devices and other chips in the prior art. The present invention realizes a simple packaging of the Hall device and other chips, and the resulting package is small in size and highly integrated, and greatly improves the reliability of the multi-chip package.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and more particularly, relates to a multi-chip package and a manufacturing method thereof. Background Art

[0002] As integrated circuits become increasingly powerful, perform higher, and integrate higher, and new types of integrated circuits emerge, packaging technology plays an increasingly important role in integrated circuit products. Existing technology packages multiple functional chips together to allow them to function together. In daily life, Hall effect devices are used as important functional chips in various electrical devices; they are often used in conjunction with other functional chips.

[0003] In response to the packaging problem of multifunctional chips, the existing technology has also proposed some solutions. For example, the invention is named: Multi-layer chip substrate and packaging method, multifunctional chip packaging method and wafer (application date: September 27, 2018; application number: CN201811128123.8). The scheme discloses a multi-layer chip substrate and packaging method, a multifunctional chip packaging method and wafer. The multi-layer chip substrate packaging method includes making circuit layers on the bottom and top of a detachable carrier board with copper foil; making metal pillars and a first through hole; flip-chip welding the micro-bump chip and the large solder ball chip on the circuit layer and placing them in the first through hole, and the large solder ball chip covers the surface of the micro-bump chip, and the height of the metal pillar is greater than the height of the large solder ball chip; making a first organic resin layer; cutting off the first organic resin layer to expose the metal pillar; making a metal layer and at least one first inner circuit layer; making a first solder resist layer; separating the multi-layer chip wafer from the carrier board and exposing the copper foil; removing the copper foil to expose the circuit layer. By implementing this solution, micro-bump chips and large solder ball chips are packaged in a fan-out format to form a multi-layer chip substrate, thereby improving process efficiency and integration, reducing the size of the structural module, and lowering packaging costs.

[0004] In addition, there is an invention entitled: Connecting a functional chip to a package to form a stacked package (application date: June 14, 2012; application number: CN201210199485.2), which discloses a stacked package (PoP) comprising: a substrate having a plurality of substrate traces; a first functional chip connected to the substrate on top of the substrate via a plurality of on-trace bonding connectors; and a second functional chip directly connected to the substrate on top of the first functional chip. Another stacked package (PoP) comprises: a substrate having a plurality of substrate traces; a first functional chip connected to the substrate on top of the substrate via a plurality of solder mask defined (SMD) connectors formed on SMD bonding pads connected to solder bumps; and a second functional chip directly connected to the substrate on top of the first functional chip via a plurality of on-trace bonding connectors. However, the above-mentioned solutions have the disadvantages of a complex packaging process and a large package size, resulting in high production costs and low reliability.

[0005] In summary, how to achieve simple packaging of Hall devices and other functional chips and ensure the reliability of the package is a problem that urgently needs to be solved in the existing technology. Summary of the Invention

[0006] 1. Problem to be solved

[0007] The present invention overcomes the problems of low reliability and high production cost of the packaging of Hall devices and other functional chips in the prior art, provides a multi-chip package and a manufacturing method thereof, realizes the simple packaging of Hall devices and other chips, and the generated package has small specifications and a high degree of integration, and greatly improves the reliability of the multi-chip package.

[0008] 2. Technical solution

[0009] In order to solve the above problems, the technical solutions adopted by the present invention are as follows:

[0010] A multi-chip package of the present invention includes a substrate, wherein a first redistribution layer is provided on the upper surface of the substrate, and a second redistribution layer is provided on the lower surface of the substrate; a first chip, wherein the first chip is provided on the first redistribution layer; a second chip, wherein the second chip is provided on the second redistribution layer; a Hall device, wherein the Hall device is provided in the substrate, and the first redistribution layer and the second redistribution layer are respectively connected to the Hall device; a first plastic package, wherein the first plastic package is used to encapsulate the first redistribution layer, the first chip and the Hall device; and a second plastic package, wherein the second plastic package is used to encapsulate the second redistribution layer, the second chip and the Hall device.

[0011] Furthermore, the invention further comprises a pin electrically connected to the first redistribution layer.

[0012] Furthermore, a mounting hole is provided on the substrate, and the Hall device is arranged in the mounting hole.

[0013] Furthermore, metal circuits are provided in the first plastic package and the second plastic package, and the first redistribution layer and the second redistribution layer are respectively connected to the Hall device through the metal circuits.

[0014] Furthermore, the pins are electrically connected to the first redistribution layer through metal lines.

[0015] A method for manufacturing a multi-chip package of the present invention is characterized by comprising the following steps:

[0016] (1) providing a first redistribution layer on the upper surface of the substrate, and mounting a first chip on the first redistribution layer;

[0017] (2) plastic-sealing the first chip and the first redistribution layer and drilling and sputtering to obtain metal circuits;

[0018] (3) plastic-sealing the metal circuit to obtain a first plastic-sealed body, and then performing sputtering on the surface of the first plastic-sealed body to obtain a pin;

[0019] (4) installing a Hall device in the substrate and the first plastic package, so that the Hall device is connected to the first redistribution layer through a metal line;

[0020] (5) providing a second redistribution layer on the lower surface of the substrate, and mounting a second chip on the second redistribution layer;

[0021] (6) Connecting the Hall device to the second redistribution layer, and plastic-sealing the second redistribution layer and the second chip to obtain a package.

[0022] Furthermore, before step (1), the method further includes: treating the surface of the substrate to remove oxides on the surface of the substrate.

[0023] Furthermore, the specific process of installing the Hall device in step (4) is: drilling holes on the lower surface of the substrate and the first plastic package to obtain installation holes, and then installing the Hall device in the installation holes.

[0024] Furthermore, the Hall device is electrically connected to the second redistribution layer through a sputtered metal circuit.

[0025] Furthermore, the first chip and the second chip are mounted on the substrate in a flip-chip manner.

[0026] 3. Beneficial effects

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) A multi-chip package of the present invention can expand the circuit layout by arranging metal circuits inside the plastic package, realize the electrical connection between the first chip, the second chip and the Hall device, thereby realizing the combined packaging of the Hall device and other chips; in addition, by arranging the first plastic package and the second plastic package, the practicality and reliability of the chip package are effectively improved.

[0029] (2) The present invention provides a method for manufacturing a multi-chip package. By arranging metal circuits inside a plastic package and expanding the overall circuit layout, the substrate, the first chip, the second chip and the Hall device can be electrically connected to achieve overall packaging. The method of the present invention is suitable for multi-chip combination packaging. The Hall device can be flexibly assembled and the metal circuits inside the plastic package can be designed in a coordinated manner. The package thus produced has small specifications and a high degree of integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of a package of the present invention;

[0031] Figure 2 Schematic diagram of the plastic package A of the package of the present invention;

[0032] Figure 3 Schematic diagram of the plastic package B of the package of the present invention.

[0033] Reference numerals: 100, substrate; 110, first chip; 120, second chip; 130, first redistribution layer; 140, second redistribution layer; 150, Hall effect device; 160, metal line; 170, pin;

[0034] 210, first plastic-encapsulated body; 211, plastic-encapsulated body A; 212, plastic-encapsulated body B; 220, second plastic-encapsulated body. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; moreover, the various embodiments are not relatively independent and can be combined with each other as needed to achieve better results. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0036] In order to further understand the content of the present invention, the present invention is described in detail with reference to the accompanying drawings and embodiments.

[0037] Example 1

[0038] like Figure 1 As shown, a multi-chip package of the present invention includes a substrate 100, a first chip 110, a second chip 120, a first redistribution layer 130, a second redistribution layer 140, a Hall device 150, a first plastic package 210, and a second plastic package 220. The first redistribution layer 130 and the second redistribution layer 140 are provided on the substrate 100. Specifically, the first redistribution layer 130 is provided on the upper surface of the substrate 100, and the second redistribution layer 140 is provided on the lower surface of the substrate 100. The substrate 100 has an electrical path connecting the upper and lower surfaces. Furthermore, the first chip 110 and the second chip 120 of the present invention are flip-chip mounted on the substrate 100. Specifically, the first chip 110 is flip-chip mounted on the first redistribution layer 130, and the second chip 120 is flip-chip mounted on the second redistribution layer 140. It should be noted that the first redistribution layer 130 and the second redistribution layer 140 are arranged correspondingly, that is, the first chip 110 and the second chip 120 are also arranged correspondingly, and the substrate 100 is provided with an electrical channel so that the first chip 110 and the second chip 120 are connected.

[0039] Furthermore, the Hall device 150 of the present invention is arranged in the substrate 100. Specifically, a mounting hole is provided on the substrate 100, and the Hall device 150 is arranged in the mounting hole. In this example, the Hall device 150 is vertically arranged in the mounting hole. In addition, the first redistribution layer 130 and the second redistribution layer 140 are electrically connected to the Hall device 150, respectively, so that the first chip 110 and the second chip 120 are electrically connected to the Hall device 150 through the first redistribution layer 130 and the second redistribution layer 140, respectively, that is, the coordinated use of multiple functional chips is realized. It should be noted here that the Hall device 150 is connected to the first redistribution layer 130 and the second redistribution layer 140 respectively through the metal line 160. It should be noted that the metal line 160 is obtained by depositing metal by sputtering.

[0040] The first plastic package 210 of the present invention is used to encapsulate the first chip 110, the first redistribution layer 130, the Hall device 150 and the metal line 160. It should be noted that, if Figure 2 and Figure 3As shown, the first plastic package 210 includes a plastic package A211 and a plastic package B212. The plastic package A211 wraps the first chip 110 and the first redistribution layer 130, thereby playing a protective role. The metal circuit 160 of the present invention is arranged on the surface of the plastic package A211 and extends inside thereof to connect with the first redistribution layer 130. The plastic package B212 wraps the metal circuit 160, that is, it plays a role in protecting the metal circuit 160. It should also be noted that a pin 170 is provided on the surface of the first plastic package 210, and the pin 170 is electrically connected to the first redistribution layer 130 through the metal circuit 160, that is, the I / O circuit of the first redistribution layer 130 is led out of the first plastic package 210 through the metal circuit 160.

[0041] In addition, the package of the present invention further includes a second plastic package 220, which encapsulates the second chip 120, the second redistribution layer 140, and the Hall effect device 150. This means that the second chip 120 and the second redistribution layer 140 are protected by the second plastic package 220, effectively improving the practicality and reliability of the package of the present invention. It should be noted that a portion of the Hall effect device 150 is encapsulated by the first plastic package 210, while another portion of the Hall effect device 150 is encapsulated by the second plastic package 220. This means that the Hall effect device 150 is protected by the first and second plastic packages 210 and 220.

[0042] A multi-chip package of the present invention can expand the circuit layout by providing a metal circuit 160 inside the plastic package, realize the electrical connection between the first chip 110, the second chip 120 and the Hall device 150, thereby realizing the combined packaging of the Hall device 150 and other chips; in addition, by providing the first plastic package 210 and the second plastic package 220, the practicality and reliability of the chip package are effectively improved.

[0043] A method for manufacturing a multi-chip package of the present invention is used to manufacture the multi-chip package described above. The method of the present invention comprises the following steps: first, treating the surface of a substrate 100 to remove oxides on the surface of the substrate 100; and then obtaining a package according to the following steps:

[0044] (1) The substrate 100 has an upper surface, a lower surface, and an electrical path connecting the upper and lower surfaces. The upper surface has a first redistribution layer 130. In this example, a redistribution method is used to arrange the first redistribution layer 130. A first chip 110 is mounted on the first redistribution layer 130. In this example, the first chip 110 is mounted on the first redistribution layer 130 by flip-chip mounting.

[0045] (2) The first chip 110 and the first redistribution layer 130 are plastic-encapsulated and sputtered to obtain metal circuits 160. It is worth noting that the first chip 110 and the first redistribution layer 130 are plastic-encapsulated to obtain a plastic encapsulation body A211, and then holes are drilled, metal is sputtered and deposited, and a portion of the metal is etched on the plastic encapsulation body A211 to obtain metal circuits 160. That is, the I / O circuits of the first redistribution layer 130 are led out through the metal circuits 160. It should be noted that the metal circuits 160 in this step are disposed above the substrate 100 and connected to the first redistribution layer 130.

[0046] (3) The metal circuit 160 in step (2) is plastic-encapsulated to obtain a first plastic-encapsulated body, that is, the metal circuit 160 is plastic-encapsulated to obtain a plastic-encapsulated body B212. The plastic-encapsulated body A211 and the plastic-encapsulated body B212 together constitute the first plastic-encapsulated body 210, and the first chip 110 and the first redistribution layer 130 are protected by the first plastic-encapsulated body 210. Thereafter, the first plastic-encapsulated body 210 is internally drilled, metal is deposited, and the upper surface is sputtered and partially etched to obtain the pin 170. It is worth noting that the I / O circuit of the first redistribution layer 130 is led out of the first plastic-encapsulated body 210 to the pin 170 through the metal circuit 160.

[0047] (4) Installing a Hall device 150 at one end of the substrate 100 so that the Hall device 150 is connected to the first redistribution layer 130 through the metal line 160 in step (2); specifically, the specific process of installing the Hall device 150 is as follows: punching a hole at one end of the substrate 100 to obtain a mounting hole, the mounting hole extending into the first plastic package, and then installing the Hall device 150 in the mounting hole; and then electrically connecting the Hall device 150 to the metal line 160 exposed in the mounting hole.

[0048] (5) The lower surface of the substrate 100 has a second redistribution layer 140 , and the second chip 120 is mounted on the second redistribution layer 140 ; ​​in this example, the second chip 120 is mounted on the second redistribution layer 120 in a flip-chip manner.

[0049] (6) Connecting the Hall device 150 to the second redistribution layer 140 . Specifically, the Hall device 150 is electrically connected to the second redistribution layer 140 by sputtering, that is, forming a metal line 160 under the substrate 100 by sputtering. Then, the second redistribution layer 140, the second chip 120, and the Hall device 150 are plastic-encapsulated to obtain a package, that is, the second plastic encapsulation body 220 is obtained by plastic-encapsulating the second redistribution layer 140, the second chip 120, and the Hall device 150, so as to protect the second redistribution layer 140, the second chip 120, and the Hall device 150; specifically, the method of step (2) can also be used to electrically connect the Hall device 150 with the second redistribution layer 140, that is, first partially plastic-encapsulate the second redistribution layer 140, the second chip 120, and the Hall device 150, and then grind, drill, and sputter-deposit metal on the plastic encapsulation body to obtain a metal line 160, and electrically connect the Hall device 150 with the second redistribution layer 140 through the metal line 160, and then plastic-encapsulate the second redistribution layer 140, the second chip 120, the Hall device 150, and the metal line 160 again.

[0050] The present invention provides a method for manufacturing a multi-chip package. By arranging a metal circuit 160 inside a plastic package, the overall circuit layout is expanded, and a first chip 110, a second chip 120, and a Hall device 150 are electrically connected. The method of the present invention is applicable to multi-chip combination packaging. The Hall device is set in a mounting hole. The package produced has small specifications and a high degree of integration.

[0051] The present invention has been described in detail above with reference to specific exemplary embodiments. However, it should be understood that various modifications and variations may be made without departing from the scope of the present invention as defined by the appended claims. The detailed description and accompanying drawings should be considered merely illustrative and not restrictive, and any such modifications and variations, if any, are intended to fall within the scope of the present invention as described herein. In addition, the background art is intended to illustrate the current status and significance of the present technology and is not intended to limit the present invention or the application and fields of application of the present invention.

Claims

1. A multi-chip package, characterized in that: include a substrate, wherein a first redistribution layer is provided on an upper surface of the substrate and a second redistribution layer is provided on a lower surface of the substrate; A first chip, wherein the first chip is disposed on a first redistribution layer; a second chip disposed on the second redistribution layer; A Hall device, wherein a mounting hole is provided on the substrate, the Hall device is disposed in the mounting hole, metal circuits are provided in the first plastic package and the second plastic package, and the first redistribution layer and the second redistribution layer are respectively connected to the Hall device via the metal circuits; A first plastic package, which is used to encapsulate the first redistribution layer, the first chip and the Hall device; the first plastic package includes a plastic package A and a plastic package B, wherein the plastic package A encapsulates the first chip and the first redistribution layer, and the plastic package B encapsulates the metal circuit; The second plastic package is used to encapsulate the second redistribution layer, the second chip and the Hall device.

2. The multi-chip package according to claim 1, wherein: It also includes pins electrically connected to the first redistribution layer.

3. The multi-chip package according to claim 2, wherein: The pins are electrically connected to the first redistribution layer through metal lines.

4. A method for manufacturing a multi-chip package according to any one of claims 1 to 3, characterized in that: The following steps are involved: (1) A first redistribution layer is provided on the upper surface of the substrate, and a first chip is mounted on the first redistribution layer; (2) Plastic-sealing the first chip and the first redistribution layer and drilling and sputtering to obtain metal circuits; (3) Plastic-sealing the metal circuit to obtain a first plastic-sealed body, and then performing sputtering on the surface of the first plastic-sealed body to obtain a pin; (4) drilling holes on the lower surface of the substrate and the first plastic package to obtain mounting holes, and then installing the Hall device in the mounting holes so that the Hall device is connected to the first redistribution layer through the metal circuit; (5) A second redistribution layer is provided on the lower surface of the substrate, and a second chip is mounted on the second redistribution layer; (6) The Hall device is electrically connected to the second redistribution layer through a sputtered metal circuit, and the second redistribution layer, the second chip, and the Hall device are plastic-encapsulated to obtain a second plastic-encapsulated body.

5. The method for manufacturing a multi-chip package according to claim 4, wherein: Before step (1), the method further includes: treating the surface of the substrate to remove oxides on the surface of the substrate.

6. The method for manufacturing a multi-chip package according to claim 4 or 5, characterized in that: The first chip and the second chip are mounted on the substrate in a flip-chip manner.

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