Semiconductor device having an interface and method for managing the interface of the semiconductor device

Abstract

The present invention provides a semiconductor device with an interface and an interface management method for the semiconductor device. The semiconductor device with the interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked one by one on the master device in a three-dimensional stack. Each of the slave devices includes a slave interface and a management circuit. The master interface and the slave interface form an interface for transmitting communication signals between the master device and the slave devices. The management circuit of the current slave device among the slave devices drives the next slave device among the slave devices. An operation command received at the current slave device among the slave devices is transmitted only through the interface to the next slave device among the slave devices. A response from the current slave device among the slave devices is transmitted back to the master device through the interface.

Description

Technical Field

[0001] The present invention relates to the fabrication of semiconductor devices, and more particularly to a semiconductor device in a three-dimensional (3D) stack having a communication interface and a method of managing the semiconductor device. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits, such as mobile phones, digital cameras, personal digital assistants (PDAs), etc., are designed to have more powerful functions to adapt to various applications in the modern digital world. However, digital electronic devices as a trend in semiconductor fabrication aim to be smaller and lighter, with improved functions and higher performance. Semiconductor devices can be packaged into three-dimensional semiconductor devices, in which several circuit chips can be stacked and integrated into a larger integrated circuit, where bonding parts and through-silicon vias (TSVs) are used for connections between chips.

[0003] System-on-integrated-chip (SoIC) packaging, wafer-on-wafer (WoW) packaging, and chip-on-wafer-on-substrate (CoWoS) packaging technologies have been proposed to package multiple chips stacked in height.

[0004] However, communication between a master chip and multiple slave chips in a 3D stack is still under development to have better performance and a compact structure. In addition, the bonding part patterns between two chips need to be arranged to be easily connected to adapt to the 3D stack of multiple chips. Moreover, since multiple slave chips are stacked on top of the master device, it is necessary to develop in a more efficient way how to address the slave chips in the initialization stage and how to manage the slave devices to identify the addresses requested by the master chip. Summary of the Invention

[0005] The present invention provides a semiconductor device in a three-dimensional stack having a communication interface and a method of managing the semiconductor device. The addresses of the slave chips can be easily set, and the target addresses requested by the master chip can be identified one slave chip after another. The total number of slave chips to be driven may also increase.

[0006] In an embodiment, the present invention provides a semiconductor device with an interface. The semiconductor device includes a main device and a plurality of slave devices. The main device includes a main interface. The slave devices are stacked one by one on the main device to form a three-dimensional stack. Each of the slave devices includes a slave interface and a management circuit. The main interface and the slave interface form the interface for transmitting communication signals between the main device and the slave devices. The management circuit of the current slave device among the slave devices drives the next slave device among the slave devices. An operation command received at the current slave device among the slave devices is transmitted to the next slave device among the slave devices only through the interface. A response from the current slave device among the slave devices is transmitted back to the main device through the interface.

[0007] In an embodiment, the present invention provides a method for managing a semiconductor device with an interface. The semiconductor device includes a main device and a plurality of slave devices stacked one by one on the main device to form a three-dimensional stack. The management method includes: configuring the main device to have a main interface; and configuring each of the slave devices to have a slave interface and a management circuit. The main interface and the slave interface form the interface for transmitting communication signals between the main device and the slave devices. The management circuit of the current slave device among the slave devices drives the next slave device among the slave devices. An operation command received at the current slave device among the slave devices is transmitted to the next slave device among the slave devices only through the interface. A response from the current slave device among the slave devices is transmitted back to the main device through the interface. Description of the Drawings

[0008] The drawings are included to provide a further understanding of the present disclosure, and the drawings are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0009] Figure 1 is a drawing schematically showing a cross-sectional stack structure of a 3D semiconductor device according to an embodiment of the present invention;

[0010] Figure 2 is a drawing schematically showing a cross-sectional stack structure of a 3D semiconductor device with an interface according to an embodiment of the present invention;

[0011] Figure 3 is a drawing schematically showing a perspective stack structure of a 3D semiconductor device with a communication mechanism having an interface according to an embodiment of the present invention;

[0012] Figure 4An accompanying drawing schematically showing the communication mechanism of the interface between the main chip and the slave chip according to an embodiment of the present invention;

[0013] Figure 5 An accompanying drawing schematically showing the 3D communication mechanism of the interface between the main chip and the slave chip according to an embodiment of the present invention;

[0014] Figure 6 An accompanying drawing schematically showing the circuit structure of the interface between the main chip and the slave chip according to an embodiment of the present invention;

[0015] Figure 7 An accompanying drawing schematically showing the circuit system structure of the interface between the main chip and the slave chip according to an embodiment of the present invention;

[0016] Figure 8 An accompanying drawing schematically showing the communication mechanism of the interface with a bonding pattern according to an embodiment of the present invention;

[0017] Figure 9A An accompanying drawing schematically showing the management mechanism for addressing the slave chip through the interface during the initialization phase according to an embodiment of the present invention;

[0018] Figure 9B An accompanying drawing schematically showing the management mechanism for responding to the main device through the interface during the initialization phase according to an embodiment of the present invention;

[0019] Figure 10A An accompanying drawing schematically showing the management mechanism for addressing the slave chip through the interface during the operation phase according to an embodiment of the present invention;

[0020] Figure 10B An accompanying drawing schematically showing the management mechanism for responding to the main device through the interface during the operation phase according to an embodiment of the present invention.

[0021] [Description of symbols]

[0022] 10: 3D semiconductor device

[0023] 20, 30: Substrate

[0024] 22, 32: Circuit layer

[0025] 24, 34: Circuit chip

[0026] 26, 36, 402: TSV structure

[0027] 38, 400: Bonding member

[0028] 40: Interface area

[0029] 100, M: Main chip

[0030] 102, S0, S1: from the chip

[0031] 104, 104M, 104S: bonding structure

[0032] 110: central processing unit block

[0033] 112: cache block

[0034] 120: SRAM block

[0035] 130: logic circuit

[0036] 132: fifth flip-flop block

[0037] 150, 150S, 150M, 170: bonding sheet

[0038] 152: bonding part

[0039] 154M, 154S, 156M, 156S: voltage bonding part

[0040] 158M, 158S: functional bonding part

[0041] 160: arrow

[0042] 200, Glink-3D: interface

[0043] 200M: main interface

[0044] 200S: slave interface

[0045] 202, 210: flip-flop (FF) block

[0046] 204: flip-flop unit

[0047] 204A: first-in first-out (FIFO) block

[0048] 206: multiplexer

[0049] 208: bonding part pattern

[0050] 220: bonding part pattern

[0051] 222: flip-flop block

[0052] 224: flip-flop block

[0053] 224a: enabled flip-flop block

[0054] 226: slave multiplexer

[0055] 228a, 228b: output control block

[0056] 230: Circuit block

[0057] 300: Command

[0058] 404, 404’: Operation command

[0059] 406, 406’, 407, 407’: From set address

[0060] 408, 408’: Enable signal

[0061] 410, 410’, 416, 416’: Response data

[0062] 412’, 414’: Response

[0063] 414: Response

[0064] 500: Management circuit

[0065] 500a: Comparison circuit

[0066] 500b: Multiplexing circuit

[0067] B: Back side

[0068] clk: Clock

[0069] clk in: Clock

[0070] command: Command

[0071] CS / RD / WR: Command / Read data / Write data

[0072] rd data: Data

[0073] rx data: Data

[0074] tx data: Data

[0075] tx en: Enable signal Detailed implementation manner

[0076] The present invention relates to an interface of a 3D semiconductor device, wherein the interface is also fabricated based on 3D packaging technology. The interface can link a single master chip (such as a processor) with multiple slave chips (such as static random access memory (SRAM)).

[0077] In addition, the chip may include management circuitry to address the slave chips one by one in an initialization phase. Further, responses may be passed back to the master device. It may not be necessary to send the address signal to all slave chips simultaneously. Instead, the address signal from the master chip may be passed one by one to the slave chips. The number of slave chips may be larger without restricting the driving ability of the master chip to a limited number of stacked slave chips.

[0078] To communicate between the master chip and the multiple slave chips in a 3D stack, an interface is first proposed. The management mechanism for the slave chips may be based on the provided interface. In an embodiment, the interface of the present invention for transmitting communication signals is first described.

[0079] In the present invention, the interface allows communication between the master chip and the multiple slave chips. The communication signals may include commands from the master chip and response information from one of the selected slave chips. The interface provides reliable communication. Additionally, the signal latency between the master chip and each of the slave chips may be stabilized to be approximately constant and predictable. Due to the control of the latency, the trigger edge of the valid clock may be appropriately set corresponding to the data packet (which may also be referred to as the data eye).

[0080] Multiple embodiments are provided below to illustrate the present invention, but the present invention is not limited to the described embodiments.

[0081] Figure 1 is a drawing schematically showing the structure of a 3D semiconductor device in a cross-sectional view according to an embodiment of the present invention. Referring to Figure 1 , the 3D semiconductor device 10 includes multiple circuit chips 24, 34, which are vertically stacked in addition to the horizontal distribution of the chips. Thus, a 3D semiconductor device including the chips is formed.

[0082] In an example, the circuit chip 24 may be regarded as the master chip, which generally includes a substrate 20 and a circuit layer 22. Several other circuit chips 34 (e.g., used as slave chips) will be stacked on top of the circuit chip 24, and a via structure (e.g., a TSV structure 26 with bonding parts) may be formed between the circuit chip 24 and the circuit chip 34 based on the packaging process. The circuit chip 34 includes a substrate 30 and a circuit layer 32 and may also include a TSV structure 36 at a corresponding position to electrically connect to the circuit chip 24. Additionally, bonding parts 38 may be formed at the outermost surface corresponding to the TSV structure 36.

[0083] 3D packaging technologies have been proposed in various stacking structures such as system-integrated chip (SoIC) packaging, wafer-to-wafer (WoW) packaging, and chip-on-wafer-on-substrate (CoWoS). The present invention is based on 3D packaging but is not limited to the type of 3D packaging.

[0084] Figure 2 FIG. is a cross-sectional stacking structure of a 3D semiconductor device having an interface, schematically showing an embodiment according to the present invention. Referring to Figure 2 , based on the 3D packaging structure, in an embodiment, the 3D semiconductor device 10 may further include an interface region 40, where the interfaces in each of the circuit chips 24, 34 are formed at the interface region 40. The interface may link the circuit chip 24 serving as the main chip to the owner in the circuit chip 34 serving as the slave chip. Communication between the circuit chip 24 and the circuit chip 34 may be through the interface at the interface region 40.

[0085] The circuit of the interface implemented within the interface region 40 will be elaborated in detail later. It should also be noted that in an embodiment, multiple interface regions 40 may be formed in the circuit chip according to actual needs, and are not limited to a single interface region.

[0086] Figure 3 FIG. is a perspective stacking structure of a 3D semiconductor device having a communication mechanism with an interface, schematically showing an embodiment according to the present invention.

[0087] Referring to Figure 3 , from the 3D stacking structure in the operation of the interface, a main chip 100, such as a processor chip, is included as a base chip in the semiconductor device. A plurality of slave chips 102, such as SRAM chips, are stacked on the main chip 100. The main chip 100 includes a main interface and each slave chip includes a slave interface. The main interface and the slave interface form an interface 200, which may also be referred to as Glink-3D. The main chip 100 and the slave chips 102 are linked through the interface 200 to communicate using information / data / signals.

[0088] In an example operation, the main chip 100 of the processor has a command to access data stored in the slave chip 102 of the SRAM chip. Due to the implemented interface, in the example, the read latency can be controlled to be approximately constant and small, such as 2 ns or 5 ns. A single clock is used in the interface to distribute to all slave chips, and the path length from the main chip 100 to each slave chip 102 is approximately the same and reliable. The latency can be adjusted to a predictable constant value.

[0089] Figure 4 FIG. is a diagram schematically showing the communication mechanism of the interface between the main chip and the slave chip, showing an embodiment according to the present invention. Referring to Figure 4, describes the communication mechanism between the main chip 100 with the main interface 200M and the slave chip 102 with the slave interface 200S connected by the bonding structure 104 in 3D packaging. As Figure 3 As described in, the main interface 200M and the slave interface 200S form the interface 200. Inside the main chip 100, in an example, the central processing unit (CPU) block 110 having the cache block 112 forms a processor. The processor is connected to the main interface 200M to transmit or receive signals at the main interface 200M, intending to communicate with the slave chip 102.

[0090] Inside the slave chip 102, it also includes the SRAM block 120 and the slave interface 200S. The SRAM block 120 is connected to the slave interface 200S for communicating with the main chip 100. In the communication, the main interface 200M and the slave interface 200S are connected by the bonding structure 104. Depending on the packaging process, the bonding structure 104 may include TSVs with a hybrid bonding pattern. The connection is bidirectional. Generally, the bonding pattern may correspond to the data bus. All signals are transmitted or received in parallel. In an example, the clock rate may be 2.5 GHz. The signal latency of the interface between the main chip 100 and the slave chip 102 through the main interface 200M and the slave interface 200S is reliable and may be approximately 2 ns in one way as an example.

[0091] Figure 5 is a drawing schematically showing the 3D communication mechanism of the interface between the main chip and the slave chip according to an embodiment of the present invention. Refer to Figure 5 , based on the operation mechanism described above, more details are shown of the main chip 100 and the slave chip 102 in the 3D structure as an example. The main chip 100 (such as a processor) includes the main interface 200M, and the main interface 200M includes the bonding structure 104M. The bonding structure 104M in the example includes a bonding pattern, and the bonding pattern is composed of a plurality of bonders in the example. Therefore, depending on the data size of the bus, the bonders are formed as an array, where one bonding chip 150 corresponds to a set of binary data (such as 16-bit data having voltage bonders, clock bonders, and other specified bonders). A plurality of bonding chips 150 form the entire bonding pattern of the main interface 200M. As described above, the data from the processor communicates bidirectionally with the main interface 200M.

[0092] Similarly, the chip 102 may include SRAM and a slave interface 200S. The SRAM communicates with the slave interface 200S, and the slave interface 200S communicates with the master interface 200M through the connection of the bonding structure 104S. The bonding structure 104S is also composed of a plurality of bonding elements arranged in an array to form a bonding element pattern, and each of the plurality of bonding elements is represented by a square unit. Similarly, the bonding element pattern is also divided into a plurality of bonding chips 150. In 3D packaging technology, the master interface 200M and the slave interface 200S are connected through the bonding structures 104M and 104S with matching bonding element patterns. Therefore, based on 3D packaging technology, the master interface 200M and the slave interface 200S are connected as a complete interface to enable communication between the master chip 100 and the slave chip 102. As described above, a plurality of slave chips 102 are stacked on top of the master chip 100, where the master interface 200M and the slave interface 200S are connected together in the vertical direction.

[0093] The circuits of the master interface 200M and the slave interface 200S are described as follows. Figure 6 FIG. is a schematic diagram showing the circuit structure of the interface between the master chip and the slave chip according to an embodiment of the present invention.

[0094] Refer to Figure 6 , and the master interface 200M of the master chip 100 and the slave interface 200S of the slave chip 102 are described using the implemented circuits. For the master interface 200M, it includes a flip-flop (FF) block 202 to receive commands intended by the core circuit of the master chip 100. Examples of commands input may include data clusters tx data and / or command, without specific limitations. The number of flip-flop blocks 202 may be one unit (FF) or more units (FFs) according to actual needs, and there is no limitation here. Examples of commands from the master chip 100 may include command and data clusters to be transmitted. The command may also include a selected slave identifier, and the command is used to select the slave chip 102 to execute the command from the master chip 100.

[0095] The multiplexer 206 receives the output of the flip-flop block 202. According to the input data at the flip-flop block 202, the multiplexer 206 in the example is of double data rate (DDR) type. The output of the multiplexer 206 is transmitted to the corresponding bonding element of the bonding element pattern 208 in the master interface 200M.

[0096] As described above, a single clock clk is provided to the slave chip 102 through the master interface 200M and the slave interface 200S. The flip-flop block 202 and the multiplexer 206 are controlled by the clock clk in in terms of timing. In the master interface 200M, the flip-flop block 202 and the master multiplexer 206 form a transmission path to transmit commands to the slave chip 102.

[0097] The host interface 200M also includes a receive path to receive responses from the slave chip 102 through the slave interface 200S and the host interface 200M having corresponding bonding part with the bonding pattern 208. The first-in-first-out (FIFO) block 204A receives the responses from the slave interface 200S. The FIFO block 204A in the example includes a plurality of flip-flop units 204. The output of the FIFO block 204A is provided to another flip-flop block 210, and then the output is transferred inward to the core of the host chip 100. The flip-flop block 210 is controlled by the clock clk in in terms of timing. The FIFO block 204A is controlled by a feedback clock from the slave chip 102, and the slave chip 102 has an enable control corresponding to the response data from the slave chip 102.

[0098] In an example of a read operation, the commands of the host chip 100 are received by the flip-flop block 202 of the host interface 200M. The selected slave chip 102 responds with the requested data to the FIFO block 204A of the host interface 200M.

[0099] In the slave interface 200S of the chip 102, the bonding pattern 220 corresponds to the bonding pattern 208. The commands of the host chip 100 are then received by the flip-flop block 222, and the flip-flop block 222 also controls the clock clk. The flip-flop block 222 in the slave interface 200S then further transfers the commands, such as rx data and / or command, inward to the SRAM of the slave chip 102. In the example, the host chip 100 sends commands to read data from the SRAM of the slave chip 102.

[0100] Then, the slave chip 102 provides the data cluster requested from the host chip 100 to the circuit block 230, and in the example, the data cluster is also indicated by the tx data arriving at the slave chip 102. The circuit block 230 is also controlled by the clock clk and the enable signal tx en. The circuit block 230 includes a flip-flop block 224, an enable flip-flop block 224a, a slave multiplexer 226, and output control blocks 228a, 228b.

[0101] The clock signal clk for control in each slave interface 200S is also provided to the third flip-flop block 222, the fourth flip-flop block 224, the slave multiplexer 226, the enable flip-flop block 224a, and the output control block 228b.

[0102] The trigger block 224 outputs data to the slave multiplexer 226 and then to the output control block 228b. The enable trigger block 224a receives an enable signal tx_en and a clock signal clk and provides a control signal to control the output control block 228a. Then, the data provided by the slave chip 102 is transmitted to the master chip 100 through the bonding part of the bonding pattern 220.

[0103] To perform proper timing control of the clock signal clk in response to the master chip 100, another output control block 228a also receives the original clock clk and is controlled by the enable signal from the enable trigger block 224a.

[0104] Then, the data output from the slave interface 200S is received by the FIFO block 204A in the master interface 200M. For the master interface 200M, the data rx_data is the response of the slave chip 102 to a command, such as command.

[0105] In an embodiment, there are multiple slave chips 102 stacked on top of the master chip 100. The command from the master chip 100 is sent to the owner among the slave chips 102. In this case, the command of the master chip 100 also includes a selected slave identification, and the command is used to select the slave chip 102 to execute the command from the master chip 100. The slave interface 200S also includes the ability to identify the selected slave identification code. Each of the slave interfaces 200S has its own identification code. One of the slave interfaces 200S that matches the selected slave identification code will be activated to respond to the command from the master chip 100 at the time slot allocated by the master command. Interference between slave chips can be effectively avoided.

[0106] Figure 7 FIG. is a schematic diagram showing the circuit structure of the interface between the master chip and the slave chip according to an embodiment of the present invention. Referring to Figure 7 further elaborates on the connection between the slave interface 200S and the SRAM 120 in the example.

[0107] In an example, command 300 may include a command, an address, write data, and a select slave identification. Output the data rx_data from the trigger block 222 of the slave interface 200S to the SRAM 120. However, the slave interface 200S may also include a logic circuit 130 and a fifth trigger block 132. The logic circuit 130 also receives a command output from the third trigger block 222, such as the data rx_data, to determine a type signal of the command / read_data / write_data (CS / RD / WR) and also generates an initial enable signal to the fifth trigger block 132, and the fifth trigger block 132 accordingly outputs an enable signal to the enable trigger block 224a. The SRAM 120 receives the type signal of the CS / RD / WR in response to a command from the main chip 100. Once the slave chip 102 (such as the SRAM 120) completes the command, the result of the read command (such as the data rd_data) is responded to the slave interface 200S as the input data tx_data of the slave interface 200S.

[0108] As further shown, in the structure of the present invention including an interface connected to multiple slave chips 102 (such as 16 slave chips), write commands and read commands may overlap and then be executed simultaneously. Except for some reserved bits, the size of the data bus may be 256 bits. The main bonding pattern 208 and the slave bonding pattern 220 have many bondings required to transmit data signals in the main interface 200M and the slave interface 200S, and the many bondings are grouped into multiple bonding slices 150S, 150M, as shown next in Figure 8 as shown. Additionally, bonding slices 170 as shown in Figure 8 may also be included to transmit other control signals for actual operations.

[0109] Since 3D packaging technology allows multiple chips to be stacked, the bondings are located at the face surfaces of the chips. However, a TSV structure is included to extend the bondings at the face surfaces to the back surfaces of the chips. To form stacked chips, two chips may be electrically connected at the bonding pattern in a face-to-face manner or a face-to-back manner as an option.

[0110] Figure 8 is a drawing schematically showing a communication mechanism of an interface having a bonding pattern according to an embodiment of the present invention. Referring to Figure 8 and also referring to Figure 5 , the main bonding pattern 208 of the main interface 200M includes a plurality of bondings 152. The bondings 152 may be as in Figure 5The components seen in are grouped into multiple bonding pads 150. Among them, the bonding pads 150 belonging to the main interface 200M can also be called bonding pads 150M, and the bonding pads 150 belonging to the slave interface 200S can also be called bonding pads 150S. Taking the bonding pad 150M as an example, a bonding pad 150M includes a set of bonding components. In the example, the set of bonding components is used to transmit a set of data signals, voltage signals, data parity signals, and control signals. The data signals in the example include 16-bit data, but are not limited thereto. The voltage bonding components 154M, 156M can include system high voltage (such as VDD) and ground voltage (such as VSS). The bonding component having a constant function of transmitting voltage signals, data parity signals, and control signals can be called a functional bonding component 158M. The functional bonding component 158M includes the voltage bonding components 154M, 156M and is located at the central row in a bonding pad 150M. In other words, a bonding pad 150S can include a central row of bonding components having a functional bonding component 158S. The functional bonding component 158S includes the voltage bonding components 154S, 156S. The data bonding component 152 for transmitting data signals can be divided into two parts of data rows, and the two parts are symmetric with respect to the central row in the geometric position. Details will be elaborated later.

[0111] In an embodiment, depending on the operation of the interface, a bonding pad 170 may also be included for transmitting or receiving various control signals as needed during the operation between the main chip 100 and the slave chip 102. Among them, a clock signal indicated by a thin arrow may be included in the bonding pad 170 for transmitting or receiving. Arrow 160 represents the vertical connection at the bonding component pattern 208 of the main interface 200M and the bonding component pattern 220 of the slave interface 200S. The vertical connection is used for communication between the main chip 100 and the slave chip 102 through the bonding component pattern 208 in the main interface 200M and the bonding component pattern 220 in the slave interface 200S. For the main interface 200M, the thick arrow pointing inward represents a command issued by the main device (such as a processor). The command is vertically transmitted downward through the bonding component pattern 208 of the main interface 200M and the bonding component pattern 220 of the slave interface 200S to the slave device. The thick arrow of the output represents transmitting the command to the slave device, such as SRAM. The slave interface 200S then receives data from the slave device according to the command, and then transmits the data to the main interface 200M. The main interface 200M provides the data to the main device as shown by the thick arrow with the output direction.

[0112] The bonding chips 150M and 150S are configured to have a center row and data rows divided into two parts, and the two parts are located on both sides of the center row at symmetric positions. This configuration of the bonding member allows the main chip and the plurality of slave chips to be easily packaged together in face-to-face, face-to-back, and back-to-back manners, where the bonding member with the flipable or non-flipable bonding patterns 208 and 220 is adapted to the face-to-face, face-to-back, or back-to-back manners.

[0113] In the foregoing description, the interface is well set. The slave chip 102 may further include a management circuit to manage the address of the slave chip. The addresses of the slave chips may be set one by one. The total number of slave chips may also be detected. Since the operation commands from the main chip are passed from one slave chip to the next, the main chip does not need to have a high driving ability. In an example, the main chip may be designed to only pass the operation commands of the zero level of the slave chip. However, currently, it is sufficient for a slave chip to only drive the next slave chip. Therefore, the slave chips can be activated one by one until the target slave chip is identified. In addition, the management commands will stop being passed to the remaining slave chips. The number of slave chips can be increased more flexibly.

[0114] Figure 9A FIG. is a schematic diagram showing a management mechanism for addressing slave chips through an interface in an initialization stage according to an embodiment of the present invention. Referring to Figure 9A , the slave chips S0 and S1 can be stacked in a face-to-face, face-to-back, or back-to-back structure, where the front side is indicated by F and the back side is indicated by B. The bonding member 400 with TSV 402 relates to the master / slave interface to stack the chips as described in the foregoing description. For example, the number of slave chips S0 and S1 is two, but the present invention is not limited to the number of slave chips. The main chip M is taken as an example to communicate with the slave chips S0 and S1.

[0115] In an embodiment, each of the slave chips S0 and S1 includes a management circuit 500. The management circuit 500 further includes a comparison circuit 500a. In an embodiment, the main chip M may issue an operation command 404, and in an embodiment, the operation command 404 includes a set address of the slave in the initialization stage or a target address of the slave in the actual operation. The operation command 404 is passed through the bonding member 400 of the interface to the slave chip S0, which is also the zero level of the slave chip.

[0116] In operation, in the initialization stage, all the slave chips S0 and S1 can be counted and the allocated addresses can be set for all the slave chips S0 and S1. Then, in the actual operation, the slave chips S0 and S1 can respond to the data requested by the main chip M according to the actual operation command, or only pass the command to the next slave chip until the target slave chip is reached. Additionally, the command will stop passing the command to the next slave chip.

[0117] First, the management mechanism in the initialization stage is described. During the initialization stage, the main chip M can issue an operation command 404 by issuing a sequence starting from a set address 406 by the main chip M in the initialization stage, where the sequence starting from the set address 406 is incremented by one each time. The set address 406 of the operation command 404 is received by the management circuit 500 of the slave chip S0 which is at the zero level in the instance. If the address of the slave chip S0 has not been set, the slave chip S0 uses the set address 406 of the operation command 404 as its set address. The set address 406 can start from 0 and increment by one each time until a certain number. The total number of slave chips can also be found at the end of the initialization stage. In the embodiment, the set address 406 is "0" for the first time and "1" for the next time, with an increment of 1, and then "2", "3",... and so on. If the set address of the slave chip S0 has been set, the slave chip S0 can transfer the address from the set address 407 to the next slave chip in the slave chip S0 according to the enable signal 408, which indicates that the address of S0 has been set.

[0118] Figure 9B is a diagrammatic view showing the management mechanism for responding to the master device through the interface in the initialization stage according to an embodiment of the present invention. Referring to Figure 9B , in the initialization stage, the main chip M may need to count the slave chips actually stacked on top of the main chip M. The management circuit 500 also includes a multiplexing circuit 500b to transfer the signal back to the main chip M. In the initialization stage, the management circuit 500 can respond with response data 410 to the main chip M to at least ensure that the current one of the slave chips exists at the main chip M. According to the enable signal 408, the response 414 after the multiplexing circuit 500b is transferred to the main chip M as response data 416 through the binder 400 of the interface.

[0119] Subsequently, two situations are expected to occur. In the first situation, it may still be necessary to set the address for the next slave chip S1. The second situation is that the current slave chip is the last slave chip in the stacked slave chips, and the total number of slave chips will be determined.

[0120] For the first situation, in the embodiment, the main chip M knows that the slave chip S1 is still stacked on top of the slave chip S0, and then issues the next set address "1", and "1" is incremented by one from "0". Using the mechanism described above, the set address 407 of "1" is greater than or not equal to the address of the slave chip S0 which has been set to "0", and then the comparison circuit 500a transfers only the set address 407 of "1" as the set address 406 regarding the slave chip S1 to the next slave chip S1. Since the address has been set, the address of the slave chip S0 is not set. The comparison and response mechanisms for each of the slave chips S0 and S1 are the same.

[0121] Thus, the main chip M receives a response from the slave chip S1. In the example, the main chip M issues a slave set address 406 with the content "2". Since the slave set address 406 with the content "2" is greater than or equal to the slave set address 406 of "0" of the slave chip S0 and the slave set address 406 of "1" of the slave chip S1, the slave set address 406 with the content "2" in the slave chip S1 does not set the address of the slave chip S1, but attempts to be passed to the coupler 400 at the top. In the embodiment, no additional slave chip is stacked on top of the slave chip S1. The main chip M will not receive a response. Then, as a second case, the main chip M knows that the slave chip S1 in the embodiment is the last slave chip S1. Then, the number of the slave chips S0 and S1 is determined. In addition, the addresses of the slave chip S0 and the slave chip S1 are set by incrementing by one. Here, the increment is not necessarily one and can be 2, 3, or other increment values according to the actual design.

[0122] It should also be noted that the increment addresses assigned to the slave chips are only examples. Depending on the detection mechanism employed, other mechanisms can be used to assign addresses to the slave chips. However, the address command is passed from one slave chip to another slave chip without the need to simultaneously pass the address command to all slave chips in the slave chips. In other words, the main chip does not need to issue an address command with high driving ability to reach all slave chips or the maximum number of slave chips simultaneously. In the present invention, it is sufficient for the current slave chip to drive only the next slave chip. Then, the number of slave chips is more flexible without restricting the driving ability of the main chip.

[0123] Once the initialization phase is completed, all slave chips are assigned identification (ID) addresses and the total number of slave chips is also known to the main chip M. The main chip can also reach the target slave chip based on the management circuit 500. Figure 10A FIG. is a diagram schematically showing a management mechanism for setting addresses of slave chips through an interface in an operation phase according to an embodiment of the present invention. Figure 10B FIG. is a diagram schematically showing a management mechanism for responding to a main device through an interface in an operation phase according to an embodiment of the present invention.

[0124] Refer to Figure 10A, when the main chip M issues an operation command 404’ with a slave target address to access the target slave chip S0, the operation command 404’ is passed to the slave chip S0 through the coupling member 400. The comparison circuit 500a of the management circuit 500 compares the slave set address 406’ of the operation command 404’ with the chip address assigned to the slave chip S0 again, for example, 0. In the example, the slave set address 406’ can be 0 or 1. If the slave set address 406’ is 0, the comparison circuit 500a of the management circuit 500 recognizes that the slave chip S0 is to be accessed by the main chip M, and according to the state of the enable signal 408’, the slave set address 406’ stops being passed to the next slave chip S1.

[0125] Refer to Figure 10B , in the embodiment, the management circuit 500 activates the slave chip S0 in response to the response data 410’ requested by the main chip M. The multiplexing circuit 500b passes the response data 410’ as the response 414’, and the response 414’ is passed back to the main chip M as the actual response data 416’ of the main chip M through the coupling member 400. Here, the enable signal 408’ will control the multiplexing circuit 500b to pass the response data 410’ but not the previous response 412’ as a result of the comparison circuit 500a. Since the slave set address 406’ stops being passed to the slave chip S1 and no slave set address 407’ is generated to drive or activate the slave chip S1, the previous response 412’ actually does not exist either. In this case, the slave chip S1 is blocked.

[0126] In another case where the slave set address 406’ is 1, the management circuit 500 determines that the slave set address 406’ of 1 is greater than or not equal to the slave chip address of 0 of the slave chip S0, and the slave chip S0 is regarded as the current slave chip among the slave chips. The management circuit 500 then only passes the slave set address 407’ to the next slave chip S1 regarded as the next slave chip among the slave chips. At this stage, Figure 10B the multiplexing circuit 500b of the management circuit 500 in

[0127] In this case, it is recognized from chip S1 that chip S1 is the target slave chip for operation command 404'. The multiplexing circuit 500b of the management circuit 500, according to the state of the enable signal 408' in chip S1, in the multiplexing circuit 500b, selects the response data 410' for slave chip S0 by the enable signal 408' and transmits it back to slave chip S0 through the multiplexing circuit 500b. The state of the enable signal 408' in slave chip S0 controls the multiplexing circuit 500b in slave chip S0 to select the response data 412' as the response data 414' of the master chip M. In other words, the multiplexing circuit 500b will select either the previously transmitted response data 412' from slave chip S1 or the currently prepared response data 410' in slave chip S0 according to the enable signal 408' and continue to transmit it back towards the master chip M.

[0128] In this mechanism, the slave chips are driven one by one, and not all slave chips are always activated. In this case of the embodiment, it will not be necessary to activate the slave chips behind the target slave chip.

[0129] According to the foregoing description, in one access operation, not all slave chips in the slave chips may be activated. The slave chips are activated up to the target slave chip. Signals can be transmitted chip by chip. The signal bus may not pass globally through the entire slave chips, but through each chip one by one.

[0130] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations that fall within the scope of the above claims and their equivalents.

Claims

1. A semiconductor device having an interface, characterized in that, Comprising: A main device, including a main interface; And A plurality of slave devices, stacked one by one on the main device in a three-dimensional stack, wherein each of the slave devices includes a slave interface and a management circuit, and the main interface and the slave interface form the interface for transmitting communication signals between the main device and the slave devices, Wherein the management circuit of the current slave device among the slave devices drives the next slave device among the slave devices through the interface, Wherein the operation command received at the current slave device among the slave devices is transmitted only through the interface to the next slave device among the slave devices, Wherein the response from the current slave device among the slave devices is transmitted back to the main device through the interface.

2. The semiconductor device according to claim 1, wherein During the initialization phase, the main device issues the operation command including the slave set address in the increment sequence to set the slave address for each of the slave devices.

3. The semiconductor device according to claim 2, characterized in that, Wherein when the address of the current slave device among the slave devices has not been set, the management circuit sets the slave set address of the current slave device among the slave devices and issues the response to the main device through the interface, Wherein when the address of the current slave device among the slave devices has been set, the management circuit of the current slave device among the slave devices transmits the slave set address to the next slave device among the slave devices.

4. The semiconductor device according to claim 3, wherein When the main device does not receive a response to the command to increment the slave set address from the slave device, the main device determines the number of slave devices stacked on the main device.

5. The semiconductor device according to claim 3, characterized in that, The management circuit includes a comparison circuit to compare the slave set address with the slave address set as the current slave device among the slave devices, Wherein when the slave set address is not equal to the slave address of the current slave device among the slave devices, the management circuit transmits the slave set address to the next slave device among the slave devices; Wherein the management circuit sets the slave set address as the slave address of the current slave device among the slave devices.

6. The semiconductor device according to claim 1, wherein During the operation phase, the main device issues the operation command including the slave target address to the target slave device among the slave devices, and the management circuit compares the slave target address with the slave address of the current slave device.

7. The semiconductor device according to claim 6, characterized in that, Wherein when the slave target address is not equal to the slave address of the current slave device among the slave devices, the management circuit transmits the slave target address to the next slave device among the slave devices; Wherein when the slave target address is equal to the slave address of the current slave device among the slave devices, the management circuit stops transmitting the slave target address.

8. The semiconductor device according to claim 7, wherein, Each of the management circuits includes a multiplexing circuit under control to transfer response data from the current one of the slave devices or only transfer response data from the previous one of the slave devices.

9. A management method for a semiconductor device with an interface, characterized in that, The semiconductor device includes a master device and a plurality of slave devices stacked one by one in a three-dimensional stack on the master device, and the management method includes: Configuring the master device to have a master interface; and Configuring each of the slave devices to have a slave interface and a management circuit, the master interface and the slave interface forming the interface for transferring communication signals between the master device and the slave devices, wherein the management circuit of the current one of the slave devices drives the next one of the slave devices through the interface, wherein an operation command received at the current one of the slave devices is transferred only through the interface to the next one of the slave devices, wherein a response from the current one of the slave devices is transferred back to the master device through the interface.

10. The management method according to claim 9, characterized in that During an initialization phase, the master device issues the operation command including the slave set address in an increment sequence to set a slave address for each of the slave devices.

11. The management method according to claim 10, wherein, Further when the address of the current one of the slave devices has not been set, configuring the management circuit to set the slave set address of the current one of the slave devices and issue the response to the master device through the interface, when the address of the current one of the slave devices has been set, configuring the management circuit of the current one of the slave devices to transfer the slave set address to the next one of the slave devices.

12. The management method according to claim 11, characterized in that When the master device does not receive a response to a command to increment the slave set address from the slave devices, the master device determines the number of slave devices stacked on the master device.

13. The management method according to claim 11, wherein Further configuring the management circuit to have a comparison circuit to compare the slave set address with the slave address set as the current one of the slave devices, wherein when the slave set address is not equal to the slave address of the current one of the slave devices, the management circuit transfers the slave set address to the next one of the slave devices; wherein when the slave address has not been set, the management circuit sets the slave set address as the slave address of the current one of the slave devices.

14. The management method according to claim 9, wherein, During an operation phase, the master device issues the operation command including the slave target address to the target slave device among the slave devices, and the management circuit compares the slave target address with the slave address of the slave device.

15. The management method according to claim 14, wherein Further including: when the slave target address is not equal to the slave address of the current one of the slave devices, configuring the management circuit to transfer the slave target address to the next one of the slave devices; and When the slave destination address is equal to the slave address of the current one of the slave devices, configure the management circuit to stop transmitting the slave destination address.

16. The management method according to claim 15, characterized in that, Each of the management circuits is configured to include a multiplexing circuit under control to transmit response data from the current one of the slave devices, or only transmit response data from the previous one of the slave devices.

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