Encapsulation Structure and Manufacturing Method

Abstract

The present invention provides a packaging structure and a manufacturing method, comprising: an electrically connected lower packaging body and an upper packaging body; the lower packaging body comprises a prefabricated interconnected silicon core stacking structure and a first plastic packaging layer surrounding the periphery of the prefabricated interconnected silicon core stacking structure; the prefabricated interconnected silicon core stacking structure comprises a silicon interconnection layer, the silicon interconnection layer comprises a first surface and a second surface opposite to each other; a back-end redistribution stacking layer and a first prefabricated redistribution stacking layer are stacked on the first surface, the back-end redistribution stacking layer and the first prefabricated redistribution stacking layer are electrically connected; a passivation layer is arranged on the second surface; the silicon interconnection layer comprises a silicon substrate and a plurality of first prefabricated conductive pillars in a plurality of silicon through holes embedded in the silicon substrate, each first prefabricated conductive pillar comprises a first end and a second end opposite to each other, the first end is exposed from the first surface, and the second end is exposed from a side of the passivation layer away from the second surface; the upper packaging body is arranged above the first prefabricated redistribution stacking layer and is electrically connected to the first prefabricated redistribution stacking layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging structure and a manufacturing method. Background Art

[0002] The rapid development of high-speed computing and artificial intelligence (AI) is placing higher demands on the packaging of semiconductor chips and packages, particularly on the packaging substrates. These substrates typically require narrower line widths and line spacings and better voltage drop control. Traditional laminated substrate wiring typically has a line width and line spacing of around 15µm / 15µm, which is increasingly unable to meet the high-density packaging requirements of electronic components used in high-speed computing and AI applications.

[0003] In addition, traditional laminate substrate technology faces great difficulties in 1) the supply of stacked dielectric materials; 2) manufacturing cycle; 3) yield control of wiring with a line width of less than 10um and embedded chips; and 4) the balance between substrate thickness and hardness.

[0004] Therefore, it is necessary to propose a new packaging structure and preparation method to overcome the fact that traditional laminated substrates cannot meet the high-density packaging requirements required for electronic components used in high-speed computing and artificial intelligence due to factors such as thickness, line width and line spacing. Summary of the Invention

[0005] The purpose of the present invention is to provide a packaging structure and a preparation method for overcoming the defects of traditional laminated substrates and meeting the requirements of high-density packaging required by electronic components.

[0006] In order to solve the above problems, the technical solution of the present invention provides a packaging structure, which includes: a lower packaging body, an upper packaging body arranged above the lower packaging body, and the lower packaging body and the upper packaging body are electrically connected; the lower packaging body includes a prefabricated interconnected silicon core stacking structure and a first plastic sealing layer arranged around the periphery of the prefabricated interconnected silicon core stacking structure; the prefabricated interconnected silicon core stacking structure includes a silicon interconnection layer, and the silicon interconnection layer includes a first surface and a second surface opposite to each other; on the first surface, a back-end redistribution stacking layer and a first prefabricated redistribution stacking layer are sequentially stacked The back-end redistribution stacking layer is electrically connected to the first prefabricated redistribution stacking layer; a passivation layer is arranged on the second surface; the silicon interconnection layer includes a silicon substrate and a plurality of first prefabricated conductive pillars embedded in a plurality of silicon through holes in the silicon substrate, each of the first prefabricated conductive pillars includes a first end and a second end relative to each other, the first end is exposed from the first surface, and the second end is exposed from the side of the passivation layer away from the second surface; wherein the upper package body is arranged above the first prefabricated redistribution stacking layer and is electrically connected to the first prefabricated redistribution stacking layer.

[0007] As an optional technical solution, the packaging structure also includes a back side redistribution stacking layer, which is arranged below the prefabricated interconnected silicon core stacking structure; wherein, the back side redistribution stacking layer is arranged on the side of the passivation layer away from the second surface, and the back side redistribution stacking layer is electrically connected to the silicon interconnection layer.

[0008] As an optional technical solution, the edge of the back side redistribution stacking layer protrudes from the edge of the prefabricated interconnected silicon core stacking structure and extends to be stacked on the first plastic encapsulation layer, and / or the edge of the passivation layer protrudes from the edge of the silicon interconnection layer and extends to be stacked on the first plastic encapsulation layer.

[0009] As an optional technical solution, the prefabricated interconnected silicon core stacking structure also includes a second prefabricated redistribution stacking layer, which is arranged on the side of the passivation layer away from the second surface, and the second prefabricated redistribution stacking layer and the second end of each first prefabricated conductive column in the silicon interconnection layer are electrically connected.

[0010] As an optional technical solution, the lower package body also includes at least one first functional block and / or at least one second functional block; the at least one first functional block is buried in the first substrate layer of the first prefabricated redistribution stacking layer; the at least one second functional block is buried in the second substrate layer of the second prefabricated redistribution stacking layer; wherein, the upper package body includes a chip and / or device package body; in the thickness direction of the package structure, the at least one first functional block is stacked below the corresponding chip and / or device package body; the at least one second functional block is stacked below the corresponding chip and / or device package body.

[0011] As an optional technical solution, the lower packaging body also includes: a prefabricated chip packaging layer, the prefabricated chip packaging layer includes: a number of second prefabricated conductive columns, a first chip and a prefabricated plastic packaging layer, the number of second prefabricated conductive columns and the first chip are respectively buried in the prefabricated plastic packaging layer, and the first plastic packaging layer is also covered on the outside of the prefabricated plastic packaging layer; wherein, the prefabricated chip packaging layer is arranged on the side of the first prefabricated redistribution stacking layer away from the silicon interconnection layer; or, the prefabricated chip packaging layer is arranged on the side of the second prefabricated redistribution stacking layer away from the silicon interconnection layer, and the thickness of the prefabricated plastic packaging layer is between 50-200um.

[0012] As an optional technical solution, the lower package body also includes a third prefabricated redistribution stacking layer, which is arranged between the prefabricated chip packaging layer and the back side redistribution stacking layer, and the third prefabricated redistribution stacking layer is electrically connected to the prefabricated chip packaging layer and the back side redistribution stacking layer.

[0013] As an optional technical solution, the prefabricated plastic packaging layer further includes an embedded third functional block, and the third functional block and the first chip are horizontally arranged side by side in the prefabricated plastic packaging layer.

[0014] As an optional technical solution, the lower package body also includes a solder resist layer, which is arranged between the first prefabricated redistribution stacking layer and the upper package body, wherein the elastic modulus or tensile elongation at break of the solder resist layer is the same as or different from the elastic modulus or tensile elongation at break of the dielectric layer in the first prefabricated redistribution stacking layer.

[0015] As an optional technical solution, the packaging structure further includes: a first redistribution stacking layer disposed between the upper package body and the lower package body, wherein the first redistribution stacking layer electrically connects the upper package body and the lower package body.

[0016] As an optional technical solution, it also includes: a second redistribution stacking layer and an interconnection chip packaging layer arranged between the lower package body and the first redistribution stacking layer; the second redistribution stacking layer is arranged above the lower package body; the interconnection chip packaging layer is arranged above the second redistribution stacking layer; the interconnection chip packaging layer includes: a number of conductive columns, an interconnection chip and a second plastic packaging layer, the number of conductive columns and the interconnection chip are respectively buried in the second plastic packaging layer, and the opposite ends of each conductive column are electrically connected to the first redistribution stacking layer and the second redistribution stacking layer, and the thickness of the second plastic packaging layer is between 150-780um; the interconnection chip includes an interconnection redistribution stacking layer and a connecting bump located above the interconnection redistribution stacking layer, the connecting bump is electrically connected to the first redistribution stacking layer and the interconnection redistribution stacking layer, the minimum line width and line spacing of the interconnection redistribution stacking layer is less than 2μm, and the interconnection redistribution stacking layer includes at least one capacitor.

[0017] As an optional technical solution, an auxiliary structure is further included, and the auxiliary structure is arranged at the edge and / or corner of the first redistribution stack layer.

[0018] As an optional technical solution, the silicon interconnect layer further includes a trench silicon capacitor, and the trench silicon capacitor is electrically connected to the back-end redistribution stack layer.

[0019] As an optional technical solution, the number of the prefabricated interconnected silicon core stacking structures in the first plastic encapsulation layer is two or more, and the two or more prefabricated interconnected silicon core stacking structures are arranged horizontally side by side and are all encapsulated by the first plastic encapsulation layer, wherein the sizes of the two or more prefabricated interconnected silicon core stacking structures are the same or different.

[0020] As an optional technical solution, the lower package body also includes a first prefabricated substrate, the first prefabricated substrate includes a third surface and a fourth surface opposite to each other, the prefabricated interconnected silicon core stacking structure is arranged on the third surface and / or the fourth surface, and is electrically connected to the first prefabricated substrate respectively; wherein, the prefabricated interconnected silicon core stacking structure and the prefabricated substrate constitute a first prefabricated unit, and the first plastic encapsulation layer encapsulates the first prefabricated unit to constitute the lower package body.

[0021] As an optional technical solution, the lower package body further includes an underfill layer, and the underfill layer is filled between the prefabricated interconnected silicon core stacking structure and the first prefabricated substrate.

[0022] As an optional technical solution, the lower package body also includes a second prefabricated substrate and / or a third prefabricated substrate, and the second prefabricated substrate and / or the third prefabricated substrate are respectively arranged horizontally side by side with the prefabricated interconnected silicon core stacking structure and constitute a second prefabricated unit, and the first plastic encapsulation layer encapsulates the second prefabricated unit to constitute the lower package body; wherein, the base material layer material of the second prefabricated substrate and the base material layer material of the third prefabricated substrate can be the same or different.

[0023] The present invention also provides a method for manufacturing a packaging structure, the method comprising:

[0024] Providing a silicon interconnect layer, the silicon interconnect layer including a first surface and a second surface opposite to each other, the silicon interconnect layer including a silicon substrate, the silicon substrate including a plurality of through-silicon vias and first prefabricated conductive vias embedded in the plurality of through-silicon vias, each of the first prefabricated conductive vias including a first end and a second end opposite to each other, the first end being exposed from the first surface, and the second end being exposed from the second surface;

[0025] forming a back-end redistribution stack layer on the first surface, wherein the first end is electrically connected to the back-end redistribution stack layer;

[0026] forming a passivation layer on the second surface and thinning the passivation layer, with the second end exposed from the passivation layer;

[0027] forming a first prefabricated redistribution stack layer above the back-end redistribution stack layer;

[0028] Cutting the silicon interconnect layer including the first prefabricated redistribution stack layer, the back-end redistribution stack layer and the passivation layer to form a single prefabricated interconnected silicon core stack structure;

[0029] Plastic encapsulate the plurality of prefabricated interconnected silicon core stacking structures of the single particle to form a first plastic encapsulation layer, constituting a plurality of lower packaging bodies; and

[0030] An upper package body is packaged onto the corresponding lower package body, and the upper package body is electrically connected to the first prefabricated redistribution stack layer.

[0031] As an optional technical solution, before the step of cutting the silicon interconnect layer including the first prefabricated redistribution stack layer, the back-end redistribution stack layer and the passivation layer to form a single-grain prefabricated interconnected silicon core stack structure, the step further includes:

[0032] A second prefabricated redistribution stack layer is formed on the passivation layer; and a prefabricated chip packaging layer is formed on one side of the second prefabricated redistribution stack layer or the first prefabricated redistribution stack layer.

[0033] As an optional technical solution, before the step of encapsulating the upper package body onto the corresponding lower package body, the step further includes:

[0034] A first redistribution stack layer is formed above the lower package body; and the upper package body is packaged above the first redistribution stack layer.

[0035] Compared with the prior art, the present invention provides a packaging structure and a manufacturing method, in which a reconstructed substrate is manufactured by a prefabricated interconnected silicon core stacking structure of a plastic-sealed single particle. Since the prefabricated interconnected silicon core stacking structure can stack a prefabricated redistribution stacking layer on the silicon interconnection layer, on the one hand, the prefabricated redistribution stacking layer can have a narrower line width and line spacing, and a thinner thickness, and therefore can effectively meet the packaging requirements of high density and small packaging volume; on the other hand, stacking the prefabricated redistribution stacking layer and other more redistribution stacking layers on the silicon interconnection layer can significantly improve the manufacturing yield of the packaging structure.

[0036] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this does not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 It is a cross-sectional schematic diagram of the packaging structure provided in the first embodiment of the present invention.

[0039] Figure 2 Schematic cross-sectional view of a packaging structure provided in a second embodiment of the present invention.

[0040] Figure 3Schematic cross-sectional view of a packaging structure provided in a third embodiment of the present invention.

[0041] Figure 4 It is a cross-sectional schematic diagram of a packaging structure provided in a fourth embodiment of the present invention.

[0042] Figure 5 It is a cross-sectional schematic diagram of a packaging structure provided in a fifth embodiment of the present invention.

[0043] Figure 6 It is a cross-sectional schematic diagram of a packaging structure provided in a sixth embodiment of the present invention.

[0044] Figure 7 FIG. 1 is a cross-sectional schematic diagram of a packaging structure provided in a seventh embodiment of the present invention.

[0045] Figure 8 It is a cross-sectional schematic diagram of the packaging structure provided in the eighth embodiment of the present invention.

[0046] Figure 9 FIG. 1 is a cross-sectional schematic diagram of a packaging structure provided in a ninth embodiment of the present invention.

[0047] Figure 10 FIG. 1 is a cross-sectional schematic diagram of a packaging structure provided in a tenth embodiment of the present invention.

[0048] Figure 11 It is a cross-sectional schematic diagram of the packaging structure provided in the eleventh embodiment of the present invention.

[0049] Figure 12 It is a cross-sectional schematic diagram of the packaging structure provided in the twelfth embodiment of the present invention.

[0050] Figure 13 It is a cross-sectional schematic diagram of the packaging structure provided in the thirteenth embodiment of the present invention.

[0051] Figure 14 It is a cross-sectional schematic diagram of the packaging structure provided in the fourteenth embodiment of the present invention.

[0052] Figure 15 It is a cross-sectional schematic diagram of the packaging structure provided in the fifteenth embodiment of the present invention.

[0053] Figure 16 It is a cross-sectional schematic diagram of the packaging structure provided in the sixteenth embodiment of the present invention.

[0054] Figure 17 It is a cross-sectional schematic diagram of the packaging structure provided in the seventeenth embodiment of the present invention.

[0055] Figure 18 A schematic diagram of a method for manufacturing a packaging structure provided by the present invention.

[0056] Figure 19 Schematic cross-sectional view of the manufacturing process of the prefabricated interconnected silicon core structure of the packaging structure in the first embodiment of the present invention.

[0057] Figure 20 Schematic cross-sectional view of the manufacturing process of the prefabricated chip packaging layer of the packaging structure in the first embodiment of the present invention.

[0058] Figure 21 FIG. 1 is a cross-sectional diagram illustrating the manufacturing process of the lower packaging body of the packaging structure in the first embodiment of the present invention.

[0059] Figure 22 FIG. 4 is a cross-sectional diagram illustrating the manufacturing process of the first redistribution stack layer of the package structure in the first embodiment of the present invention.

[0060] Figure 23 and Figure 24 Schematic cross-sectional view of the manufacturing process of the upper package body and metal bump or solder ball implantation of the package structure in the first embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the embodiments and drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0062] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the present invention.

[0063] One of the purposes of the present invention is to provide a packaging structure, which includes an electrically connected lower packaging body and an upper packaging body, the lower packaging body includes a prefabricated interconnected silicon core stacking structure, a first plastic packaging layer arranged around the periphery of the prefabricated interconnected silicon core stacking structure, and a plurality of metal protrusions arranged below the prefabricated interconnected silicon core stacking structure, and the plurality of metal protrusions are electrically connected to the prefabricated interconnected silicon core stacking structure; the prefabricated interconnected silicon core stacking structure includes a silicon interconnection layer, a back-end redistribution stacking layer and a passivation layer arranged on two opposite surfaces of the silicon interconnection layer, and a first prefabricated redistribution stacking layer arranged on one side of the back-end redistribution stacking layer; the silicon interconnection layer includes a silicon substrate, a plurality of silicon through-holes formed in the silicon substrate and a plurality of first prefabricated conductive columns embedded in the plurality of silicon through-holes, the opposite ends of each first prefabricated conductive column being exposed from the surface of the silicon substrate and the surface of the passivation layer respectively; wherein the upper packaging body is arranged above the first prefabricated redistribution stacking layer and is electrically connected to the first prefabricated redistribution stacking layer.

[0064] In this embodiment, a reconstructed substrate is manufactured by a prefabricated interconnected silicon core stacking structure of a plastic-encapsulated single particle. Since the prefabricated interconnected silicon core stacking structure can stack a prefabricated redistribution stacking layer on the silicon interconnection layer, on the one hand, the prefabricated redistribution stacking layer can have a narrower line width and line spacing and a thinner thickness, and therefore can effectively meet the packaging requirements of high density and small packaging volume; on the other hand, stacking the prefabricated redistribution stacking layer on the silicon interconnection layer can significantly improve the manufacturing yield of the prefabricated redistribution stacking layer.

[0065] In addition, more redistribution stacking layers can be made on the reconstructed substrate, and more redistribution stacking layers and prefabricated redistribution stacking layers and post-process redistribution stacking layers in the reconstructed substrate are stacked on each other, which can be used as a voltage control circuit, such as an inductor. Inductors mainly play the role of filtering, oscillating, delaying, trapping, etc. in the circuit, and also have the functions of screening signals, filtering noise, stabilizing current and suppressing electromagnetic interference. In addition, the inductor also has the characteristic of preventing alternating current from passing through and allowing direct current to pass smoothly. Preferably, the silicon substrate also includes optional trench silicon capacitors, and the trench silicon capacitors, post-process redistribution stacking layers in the reconstructed substrate, prefabricated redistribution stacking layers and redistribution stacking layers above the reconstructed substrate are stacked on each other, which can be used as a decoupling and voltage control circuit.

[0066] Furthermore, an interconnect chip packaging layer can be made on the reconstructed substrate. The capacitors and inductors formed between any two or three of the vertically interconnected conductive columns, interconnect chips and plastic packaging layers in the interconnect chip packaging layer, the interconnect redistribution stacking layer on the interconnect chip, the prefabricated redistribution stacking layer in the reconstructed substrate, and the redistribution stacking layer above the reconstructed substrate can also be used as filters or electrostatic protection structures.

[0067] The following will be combined Figures 1 to 17 The various packaging structures provided by the present invention are described in detail.

[0068] like Figure 1 As shown, a first embodiment of the present invention provides a packaging structure 100, comprising a lower packaging body 110 and an upper packaging body 120 that are electrically connected, wherein the lower packaging body 110 comprises a prefabricated interconnected silicon core stacking structure 111 and a first plastic encapsulation layer 112 disposed around the periphery of the prefabricated interconnected silicon core stacking structure 111; the prefabricated interconnected silicon core stacking structure 111 comprises a silicon interconnection layer 1111, which comprises a first surface 1111a and a second surface 1111b opposite to each other; a back-end redistribution stacking layer 1112 and a first prefabricated redistribution stacking layer 1111 are sequentially stacked on the first surface 1111a. 114, the back-end redistribution stack layer 1112 and the first prefabricated redistribution stack layer 1114 are electrically connected; a passivation layer 1113 is set on the second surface 1111b; the silicon interconnect layer 1111 includes a silicon substrate, forming a plurality of silicon vias in the silicon substrate and a plurality of first prefabricated conductive pillars 1116 embedded in the plurality of silicon vias, each first prefabricated conductive pillar 1116 includes a first end and a second end relative to each other, the first end is exposed from the first surface 1111a and is electrically connected to the back-end redistribution stack layer 1112; the second end is exposed from the side of the passivation layer 1113 away from the second surface.

[0069] In this embodiment, the upper package body 120 is disposed above the first prefabricated redistribution stack layer 1114 and is electrically connected to the first prefabricated redistribution stack layer 1114. The upper package body 120 is indirectly electrically connected to the first prefabricated redistribution stack layer 1114 from top to bottom via the first redistribution stack layer 130 and the prefabricated chip packaging layer 113. In other embodiments of the present invention, the upper package body may also be directly electrically connected to the first prefabricated redistribution stack layer.

[0070] In a preferred embodiment, the passivation layer 1113 is, for example, a silicon nitride passivation layer, and the silicon nitride passivation layer can be formed on the second surface 1111 b by vapor deposition.

[0071] In a preferred embodiment, the first prefabricated conductive pillar 1116 is, for example, a copper pillar or other metal pillar, and a passivation layer and a diffusion barrier metal layer (not shown) are provided between the first prefabricated conductive pillar 1116 and the silicon body.

[0072] Continue to refer to Figure 1 The prefabricated interconnected silicon core stacking structure 111 also includes a second prefabricated redistribution stacking layer 1115, which is arranged on the side of the passivation layer 1113 away from the second surface 1111b, and the second ends of the second prefabricated redistribution stacking layer 1115 and several first prefabricated conductive pillars 1116 in the silicon interconnection layer 1111 are electrically connected.

[0073] Preferably, the second prefabricated redistribution stack layer 1115 , the passivation layer 1113 , the silicon interconnect layer 1111 , the back-end redistribution stack layer 1112 and the first prefabricated redistribution stack layer 1114 are stacked from bottom to top to form a prefabricated interconnected silicon core stack structure 111 .

[0074] It should be noted that the second prefabricated redistribution stacking layer 1115, the passivation layer 1113, the silicon interconnection layer 1111, the back-end redistribution stacking layer 1112 and the first prefabricated redistribution stacking layer 1114 are respectively manufactured using wafer-level or panel-level packaging processes, and can be cut to form a single-grain prefabricated interconnected silicon core stacking structure 111.

[0075] Continue to refer to Figure 1 The lower package body 110 also includes a prefabricated chip packaging layer 113, which is arranged above the first prefabricated redistribution stacking layer 1114, and includes: a plurality of second prefabricated conductive pillars 1131, a first chip 1133 and a prefabricated plastic packaging layer 1132, wherein the plurality of second prefabricated conductive pillars 1131 are made above the first prefabricated redistribution stacking layer 1114, and the plurality of second prefabricated conductive pillars 1131 are electrically connected to the first prefabricated redistribution stacking layer 1114; the first chip 1133 is upright bonded above the first prefabricated redistribution stacking layer 1114; the prefabricated plastic packaging layer 1132 plastic-encapsulates the plurality of second prefabricated conductive pillars 1131 and the first chip 1133 above the first prefabricated redistribution stacking layer 1114, and the thickness of the prefabricated plastic packaging layer 1132 is between 50-200um.

[0076] The prefabricated chip packaging layer 113 is, for example, first fabricated using a wafer-level or panel-level packaging process on top of a wafer-level interconnected silicon core stack structure that has not been cut into individual pieces. This reconstructed substrate, which is also cut into individual pieces, includes the stacked prefabricated interconnected silicon core stack structure 111 and the prefabricated chip packaging layer 113. The reconstructed substrate is then encapsulated with a first plastic encapsulation layer 112 to form the lower package body 110.

[0077] In this embodiment, the first chip 1133 is, for example, an interconnect chip, which is bonded face-up above the first pre-fabricated redistribution stack 1114. The surface of the first chip 1133 facing the first redistribution stack 130 includes a pre-fabricated interconnection redistribution stack 1134 and connection bumps 1135 disposed above the pre-fabricated interconnection redistribution stack 1134. The connection bumps 1135 electrically connect the first redistribution stack 130 and the first chip 1133. The pre-fabricated interconnection redistribution stack 1134 has a minimum line width and line spacing of less than 2 μm, and the pre-fabricated interconnection redistribution stack 1134 includes at least one capacitor.

[0078] like Figure 1As shown, the packaging structure 100 also includes a first redistribution stacking layer 130 arranged between the upper package body 120 and the lower package body 110, and the first redistribution stacking layer 130 is electrically connected to the upper package body 120 and the lower package body 110, wherein the first redistribution stacking layer 130 is arranged above the prefabricated chip packaging layer 113, and the first redistribution stacking layer 130 is electrically connected to a number of second prefabricated conductive pillars 1131.

[0079] In a preferred embodiment, a chip mounting layer 1136 is filled between the first chip 1133 and the first prefabricated redistribution stack layer 1114. The chip mounting layer 1136 makes the fixed connection between the first chip 1133 and the first prefabricated redistribution stack layer 1114 more stable and / or serves as an electrode connection and heat dissipation enhancement, and can also prevent the first chip 1133 from being affected by harmful operating environments such as moisture and vibration.

[0080] In a preferred embodiment, the minimum line width and line spacing of the back-end redistribution stack layer 1112 is less than 2 μm; the minimum line width and line spacing of the first prefabricated redistribution stack layer 1114 is less than 10 μm; and the minimum line width and line spacing of the first redistribution stack layer 130 is less than 5 μm.

[0081] Among them, the capacitors and inductors formed between any two or three of the first redistribution stacking layer 130 (minimum line width and line spacing is less than 5μm), the prefabricated interconnection redistribution stacking layer 1134 (minimum line width and line spacing is less than 2μm), and the first prefabricated redistribution stacking layer 1114 (minimum line width and line spacing is less than 10μm) stacked from top to bottom can be used as filters, electrostatic protection structures or voltage control structures.

[0082] In addition, the silicon interconnect layer 1111 also includes a trench silicon capacitor 1117 arranged in the silicon substrate, wherein a decoupling and voltage control circuit is formed between any two, three, or four of the first redistribution stack layer 130 (with a minimum line width and line spacing of less than 5 μm), the first pre-fabricated redistribution stack layer 1114 (with a minimum line width and line spacing of less than 10 μm), the back-end redistribution stack layer 1112 (with a minimum line width and line spacing of less than 2 μm), and the trench silicon capacitor 1117 stacked from top to bottom.

[0083] like Figure 1 As shown, the upper package 120 includes a chip 121 and / or a device package 121. The chip 121 and / or the device package 121 are, for example, flip-chip bonded to and electrically connected to the first redistribution stack 130. A second plastic encapsulation layer 122 encapsulates the chip 121 and / or the device package 121 above the first redistribution stack 130. The second plastic encapsulation layer 122 is optional and has a thickness between 150 and 780 μm.

[0084] Preferably, an underfill material layer 123 is filled between the chip 121 and / or the device package 121 and the first redistribution stack layer 130. The underfill material layer 123 makes the fixed connection between the chip 121 and / or the device package 121 and the first redistribution stack layer 130 more stable, and can also prevent the chip 121 and / or the device package 121 from being affected by harmful operating environments such as moisture and vibration.

[0085] A metal block or frame 101 is buried in the second plastic layer 122 of the upper package body 120. The metal block or frame 101 can be a metal or silicon block with a metal surface coating, or a silicon wafer, which is connected to the first redistribution stacking layer 130 by metal bonding or adhesive bonding. It is arranged above the first redistribution stacking layer 130, preferably located at the edge and / or corner of the first redistribution stacking layer 130, and is used to improve the warping, heat dissipation and electromagnetic interference shielding of the packaging structure 100.

[0086] In addition, a functional device 102 may be embedded in the second plastic packaging layer 122 . The functional device 102 is electrically connected to the first redistribution stack layer 130 , and may be a functional device such as a capacitor or an inductor.

[0087] like Figure 1 As shown, the packaging structure 100 also includes a metal bump or solder ball 140 arranged under the second prefabricated redistribution stack layer 1115, and the metal bump or solder ball 140 is electrically connected to the conductive layer in the second prefabricated redistribution stack layer 1115 to enable the packaging structure 100 to transmit electrical signals.

[0088] In this embodiment, the various structures of the upper package body 120 are, for example, manufactured through wafer-level packaging or board-level packaging on a reconstructed substrate formed after the pre-molded prefabricated interconnected silicon core stacking structure 111 and the pre-molded chip packaging layer 113, but the present invention is not limited thereto. In the packaging structures provided in other embodiments of the present invention, the upper package body can also be a pre-packaged independent unit. When the pre-molded interconnected silicon core stacking structure and the pre-molded chip packaging layer are molded to form a reconstructed substrate, and the first redistribution stacking layer is manufactured on the reconstructed substrate, the two independent units are bonded to each other to achieve electrical connection, and this stacking connection of independent units helps to improve the yield of the overall packaging structure.

[0089] like Figure 2 As shown, the second embodiment of the present invention further provides a package structure 200, which differs from the package structure 100 in that: 1) in the prefabricated interconnected silicon core stacking structure 211 in the package structure 200, the back-end redistribution stacking layer 1112 is provided on the second surface 1111b (such as the second surface 1111b) of the silicon interconnection layer 1111. Figure 1 ), and the passivation layer 1113 is provided on the first surface 1111a of the silicon interconnect layer 1111 (as shown Figure 12) trench silicon capacitor 1117 and located on the second surface 1111b (as shown); Figure 1 ) The back-end redistribution stacking layer 1112 on one side is electrically connected; 3) The prefabricated chip packaging layer 113 is arranged above the second prefabricated redistribution stacking layer 1115 and is electrically connected to the second prefabricated redistribution stacking layer 1115; 4) A back-side redistribution stacking layer 250 is also provided below the lower package body 110, which is electrically connected to the second prefabricated redistribution stacking layer 1115; 5) The metal bumps or solder balls 140 are arranged below the back-side redistribution stacking layer 250 and are electrically connected to the conductive layer in the back-side redistribution stacking layer 250.

[0090] It should be noted that the backside redistribution stack 250 is not a prefabricated structure. After the stacked prefabricated interconnected silicon core stack 111 and prefabricated chip packaging layer 113 are cut into individual pieces, they are encapsulated with the first plastic encapsulation layer 112 to form a reconstructed substrate. Subsequently, through wafer-level or panel-level packaging processes, the backside redistribution stack 250 is formed on the backside of this reconstructed substrate. Preferably, the minimum line width and line spacing of the backside redistribution stack 250 is less than or equal to 5μm.

[0091] In addition, combined Figure 1 and Figure 2 It can be seen that the lower packaging bodies 110 and 210 both include a prefabricated chip packaging layer 113, wherein, based on the stacking position of the first prefabricated redistribution stacking layer 1114 and the second prefabricated redistribution stacking layer 1115 in the prefabricated interconnected silicon core stacking structure 111 and 211, the prefabricated chip packaging layer 113 can be arranged on one side of the first prefabricated redistribution stacking layer 1114 or on one side of the second prefabricated redistribution stacking layer 1115.

[0092] In this embodiment, the prefabricated chip packaging layer 113 is located above the prefabricated interconnected silicon core stacking structure 111, 211, that is, sandwiched between the upper packaging body 120 and the prefabricated interconnected silicon core stacking structure 111, 211, but is not limited thereto. Figure 3 and Figure 4 In the packaging structures 300 and 400 of the third and fourth embodiments shown in FIG, similar prefabricated chip packaging layers 313 and 413 may also be disposed below the prefabricated interconnected silicon core stacking structure 111, that is, at the bottom of the entire packaging structure.

[0093] In other words, in the packaging structure provided by the present invention, the prefabricated chip packaging layer can be arranged on one side of the first prefabricated redistribution stacking layer, or, be arranged on one side of the second prefabricated redistribution stacking layer, wherein the prefabricated chip packaging layer is located between the upper packaging body and the first prefabricated redistribution stacking layer, or, the prefabricated chip packaging layer is sandwiched between the upper packaging body and the second prefabricated redistribution stacking layer, or, the prefabricated chip packaging layer is sandwiched between the prefabricated interconnected silicon core stacking structure and the back side redistribution stacking layer, and is located at the bottom of the packaging structure.

[0094] also, Figure 2 Zhongyu Figure 1 The same reference numerals represent the same components with similar functions and are not described in detail.

[0095] like Figure 3 As shown, a packaging structure 300 is further provided in the third embodiment of the present invention, which is different from the packaging structure 100 in that: 1) in the packaging structure 300, the lower packaging body 310 includes a prefabricated interconnected silicon core stacking structure 111 and a prefabricated chip packaging layer 313 stacked below the prefabricated interconnected silicon core stacking structure 111, and the prefabricated chip packaging layer 313 is electrically connected to the second prefabricated redistribution stacking layer 1115 in the prefabricated interconnected silicon core stacking structure 111 through a second prefabricated conductive column 3131; 2) a back side redistribution stacking layer 350 is further provided below the lower packaging body 310, which is electrically connected to the second prefabricated conductive column 3131 in the prefabricated chip packaging layer 313; 3) a metal bump or solder ball 140 is provided below the back side redistribution stacking layer 350 and is electrically connected to the conductive layer in the back side redistribution stacking layer 350; 4) the prefabricated chip packaging layer 313 is electrically connected to the second prefabricated conductive column 3131. A third functional block 303 is embedded in the plastic layer 3132, and the third functional block 303 is electrically connected to the second prefabricated redistribution stacking layer 1115 and the back redistribution stacking layer 350; preferably, the third functional block 303 includes but is not limited to a magnetic block, an inductor, an antenna, a silicon capacitor chip, an embedded composite block with a high-k thin film capacitor, a ceramic (PZT) sensor, a capacitor package, etc.; 5) Auxiliary structures 301 and functional devices 302 are also embedded in the upper package 120, and the auxiliary structure 301 includes a metal block, a reinforcement block, a heat dissipation block, etc., which is arranged above the first redistribution stacking layer 130, preferably located at the edge and / or corner of the first redistribution stacking layer 130, for improving the warping, heat dissipation and electromagnetic interference shielding of the packaging structure 300; the functional device 302 is electrically connected to the first redistribution stacking layer 130, and can be a functional device such as a capacitor and an inductor.

[0096] In this embodiment, the prefabricated chip packaging layer 313 is located at the bottom of the lower package body 310, sandwiched between the second prefabricated redistribution stack layer 1115 and the backside redistribution stack layer 350, and located at the bottom of the package structure 300. The prefabricated plastic encapsulation layer 3132 in the prefabricated chip packaging layer 313 encapsulates the first chip 1133 and a plurality of second prefabricated conductive pillars 3131 on one side of the second prefabricated redistribution stack layer 1115. A chip attach layer 1136 is filled between the first chip 1133 and the second prefabricated redistribution stack layer 1115. Furthermore, the side of the first chip 1133 facing the backside redistribution stack layer 350 includes a prefabricated interconnect redistribution stack layer 1134 and connection bumps 1135. The connection bumps 1135 electrically connect the prefabricated interconnect redistribution stack layer 1134 to the backside redistribution stack layer 350.

[0097] also, Figure 3 Zhongyu Figure 1 The same reference numerals represent the same components with similar functions and are not described in detail.

[0098] like Figure 4 As shown, the fourth embodiment of the present invention further provides a packaging structure 400, which is different from the packaging structure 100 in that: 1) in the packaging structure 400, the upper packaging body 120 is directly electrically connected to the first prefabricated redistribution stacking layer 1114 in the prefabricated interconnected silicon core stacking structure 111 in the lower packaging body 410; 2) the lower packaging body 410 further includes a solder resist layer 440, which is arranged above the first prefabricated redistribution stacking layer 1114 and is plastic-sealed by the first plastic sealing layer 412; 3) the lower packaging body 410 includes the prefabricated interconnected silicon core stacking structure 111 and the prefabricated interconnected silicon core stacking structure 111. The prefabricated chip packaging layer 413 below the stacking structure 111 is electrically connected to the second prefabricated redistribution stacking layer 1115 in the prefabricated interconnected silicon core stacking structure 111 through the second prefabricated conductive column 4131; 4) A back redistribution stacking layer 450 is also provided below the lower packaging body 410, which is electrically connected to the second prefabricated conductive column 4131 in the prefabricated chip packaging layer 413; 5) Metal bumps or solder balls 140 are arranged below the back redistribution stacking layer 450 and are electrically connected to the conductive layer in the back redistribution stacking layer 450.

[0099] In this embodiment, the prefabricated chip packaging layer 413 is located at the bottom of the lower package body 410, sandwiched between the second prefabricated redistribution stack layer 1115 and the backside redistribution stack layer 450, and located at the bottom of the package structure 400. The prefabricated plastic encapsulation layer 4132 in the prefabricated chip packaging layer 413 encapsulates the first chip 1133 and a plurality of second prefabricated conductive pillars 4131 on one side of the second prefabricated redistribution stack layer 1115. A chip attach layer 1136 is filled between the first chip 1133 and the second prefabricated redistribution stack layer 1115. Furthermore, the side of the first chip 1133 facing the backside redistribution stack layer 450 includes a prefabricated interconnect redistribution stack layer 1134 and connection bumps 1135. The connection bumps 1135 electrically connect the prefabricated interconnect redistribution stack layer 1134 to the backside redistribution stack layer 450.

[0100] In addition, a third functional block 403 is embedded in the prefabricated plastic layer 4132 of the prefabricated chip packaging layer 413, and the third functional block 403 is electrically connected to the second prefabricated redistribution stack layer 1115 and the back redistribution stack layer 450; preferably, the third functional block 403 includes but is not limited to a magnetic block, an inductor, an antenna, a silicon capacitor chip, an embedded composite block with a high-k thin film capacitor, a ceramic (PZT) sensor, a capacitor package, etc.

[0101] An auxiliary structure 401 and a functional device 402 are also buried in the upper package body 120. The auxiliary structure 401 includes a metal block, a reinforcement block, a heat dissipation block, etc., which is arranged above the lower package body 410, preferably located at the edge and / or corner of the lower package body 410, and is used to improve the warping, heat dissipation and electromagnetic interference shielding of the package structure 400; the functional device 402 is electrically connected to the first prefabricated redistribution stack layer 1114, which can be a functional device such as a capacitor and an inductor.

[0102] also, Figure 4 Zhongyu Figure 1 The same reference numerals represent the same components with similar functions and are not described in detail.

[0103] like Figure 5As shown, the fifth embodiment of the present invention also provides a packaging structure 500, which is different from the packaging structure 100 in that: 1) in the packaging structure 500, the prefabricated chip packaging layer 513 of the lower packaging body 510 also includes a second chip 504 buried in the prefabricated plastic packaging layer 5132, and the second chip 504 and the first chip 1133 are arranged horizontally side by side, respectively arranged above the first prefabricated redistribution stacking layer 1114, wherein the second chip 504 includes but is not limited to a silicon capacitor chip, on the surface of which the interconnected redistribution stacking layer 5041 and the connecting bump 5042 are arranged on the side facing the first redistribution stacking layer 130, and the connecting bump 5042 is electrically connected to the first redistribution stacking layer 130 and the interconnected redistribution stacking layer 5041; in addition, a trench capacitor 5043 is arranged inside the silicon capacitor chip, and the trench capacitor 5043 is electrically connected to the interconnected redistribution stacking layer 5041; 2) the second chip 504 and the first prefabricated redistribution stacking layer 1114 are arranged horizontally side by side, and are respectively arranged above the first prefabricated redistribution stacking layer 1114, wherein the second chip 504 includes but is not limited to a silicon capacitor chip, and the interconnected redistribution stacking layer 5041 and the connecting bump 5042 are arranged on the surface of the silicon capacitor chip A chip mounting layer 5044 is filled between the wiring stacking layers 1114. The chip mounting layer 5044 enables the second chip 504 to be stably connected above the first prefabricated redistribution stacking layer 1114, and can also prevent the second chip 504 from being affected by harmful operating environments such as moisture and vibration; 3) The upper package body includes a chip 521 and / or a device package body 521, which is flip-chip bonded above the first redistribution stacking layer 130, and a bottom filling material layer 523 is filled between the chip 521 and / or the device package body 521 and the first redistribution stacking layer 130; 4) Auxiliary structures 501 and functional devices 502 are set at the edges and / or corners of the first redistribution stacking layer 130. The auxiliary structure 501 includes a metal block, a reinforcement block, a heat dissipation block, etc., which is used to improve the warping, heat dissipation and electromagnetic interference shielding of the packaging structure 500; the functional device 502 is electrically connected to the first redistribution stacking layer 130, and can be a functional device such as a capacitor and an inductor.

[0104] In this embodiment, the prefabricated chip packaging layer 513 is stacked above the prefabricated interconnected silicon core stack structure 111 and sandwiched between the first redistribution stack layer 130 and the first prefabricated redistribution stack layer 1114. The prefabricated chip packaging layer 513 is electrically connected to the first redistribution stack layer 130 and the first prefabricated redistribution stack layer 1114 via the second prefabricated conductive pillars 5131.

[0105] also, Figure 5 Zhongyu Figure 1 The same reference numerals represent the same components with similar functions and are not described in detail.

[0106] like Figure 6As shown, the sixth embodiment of the present invention further provides a packaging structure 600, which differs from the packaging structure 100 in that: 1) in the packaging structure 600, the lower packaging body 610 includes a prefabricated interconnected silicon core stacking structure 611 and a first plastic packaging layer 612 arranged around the periphery of the prefabricated interconnected silicon core stacking structure 611; the second prefabricated redistribution stacking layer 1115, the passivation layer 1113, the silicon interconnection layer 1111, the back-end redistribution stacking layer 1112 and the first prefabricated redistribution stacking layer 6114 stacked from bottom to top constitute the prefabricated interconnected silicon core stacking structure 611; 2) the first prefabricated redistribution stacking layer 6114 The stack 6114 includes a first substrate layer 6114a, in which at least one first functional block 601 is embedded. The first functional block 601 includes but is not limited to a magnetic block, an inductor, an antenna, a silicon capacitor chip, an embedded composite block with a high-k thin film capacitor, a ceramic (PZT) sensor, a capacitor package, etc. Preferably, along the thickness direction or stacking direction of the package structure 600, the first functional block 601 is, for example, stacked below the corresponding chip 121 and / or device package 121 in the upper package 120; 3) the upper package 120 and the lower package A second redistribution stacking layer 620 and an interconnection chip packaging layer 630 are provided between the package body 610; the second redistribution stacking layer 620 is formed above the lower package body 610 and is electrically connected to the first prefabricated redistribution stacking layer 6114; the interconnection chip packaging layer 630 is provided above the second redistribution stacking layer 620, and the interconnection chip packaging layer 630 is electrically connected to the first redistribution stacking layer 130 and the second redistribution stacking layer 620; 4) the interconnection chip packaging layer 630 includes a plurality of conductive pillars 631, a third plastic packaging layer 632, an interconnection chip 633, and a plurality of conductive pillars 631 are formed on the second redistribution stacking layer Above the wire stack layer 620, one end of each conductive column 631 is electrically connected to the solder pad exposed from the dielectric layer in the second redistribution stack layer 620; the interconnection chip 633 is mounted upright on the second redistribution stack layer 620, and the surface of the interconnection chip 633 facing the first redistribution stack layer 130 is provided with an interconnection redistribution stack layer 634 and a connecting bump 635, and the connecting bump 635 electrically connects the first redistribution stack layer 130 and the interconnection redistribution stack layer 634; the third plastic encapsulation layer 632 plastic encapsulates a plurality of conductive columns 631 and the interconnection chip 633 above the second redistribution stack layer 620.

[0107] The minimum line width and line spacing of the interconnect redistribution stack layer 634 is less than 2 μm, and it also includes at least one capacitor; the minimum line width and line spacing of the second redistribution stack layer 620 is less than 10 μm.

[0108] In this embodiment, the first prefabricated redistribution stack layer 6114 (minimum line width and line spacing is less than 10μm), the second redistribution stack layer 620 (minimum line width and line spacing is less than 10μm), the interconnection redistribution stack layer 634 (minimum line width and line spacing is less than 10μm) and the second redistribution stack layer 620 (minimum line width and line spacing is less than 5μm) are stacked from bottom to top, among which the capacitors and inductors formed between any two or three of them can be used as filters, electrostatic protection structures or voltage control structures.

[0109] also, Figure 6 and Figure 1 The same reference numerals represent the same components with similar functions and are not described in detail.

[0110] like Figure 7 As shown, the seventh embodiment of the present invention further provides a packaging structure 700, which is different from the packaging structure 600 in that, in the packaging structure 700, the lower packaging body 710 includes a prefabricated interconnected silicon core stacking structure 711 and a first plastic packaging layer 712 arranged around the prefabricated interconnected silicon core stacking structure 711; wherein, the second prefabricated redistribution stacking layer 7115, the passivation layer 1113, the silicon interconnection layer 1111, the back-end redistribution stacking layer 1112 and the first prefabricated redistribution stacking layer 1114 stacked from bottom to top constitute the prefabricated interconnected silicon core stacking structure 611.

[0111] The second prefabricated redistribution stacking layer 7115 includes a second substrate layer 7115a, in which at least one second functional block 701 is embedded. The second functional block 701 includes but is not limited to a magnetic block, an inductor, an antenna, a silicon capacitor chip, an embedded composite block with a high-k thin film capacitor, a ceramic (PZT) sensor, a capacitor package, etc. Preferably, along the thickness direction or stacking direction of the packaging structure 700, the second functional block 701 is, for example, stacked below the corresponding chip 121 and / or device package 121 in the upper package 120.

[0112] Figure 6 and Figure 7 In the package structures 600 and 700 shown in FIG, at least one first functional block 601 and at least one second functional block 701 are respectively embedded in a first pre-fabricated redistribution stack layer 6114 and a second pre-fabricated redistribution stack layer 7115 above or below the silicon interconnect layer 1111. It should be noted that in other embodiments of the present invention, functional blocks may be embedded in both the first pre-fabricated redistribution stack layer and the second pre-fabricated redistribution stack layer, depending on actual needs.

[0113] In other words, in the lower package body, the corresponding first functional block and / or second functional block can be buried in the first prefabricated redistribution stacking layer and / or the second prefabricated redistribution stacking layer located on the first surface and the second surface opposite to the silicon interconnection layer. Preferably, in the thickness direction of the packaging structure, the first functional block and / or the second functional block are stacked below the corresponding chip and / or device package in the upper package body.

[0114] also, Figure 7 and Figure 6 The same reference numerals represent the same components with similar functions and are not described in detail.

[0115] like Figure 8 As shown, the eighth embodiment of the present invention further provides a packaging structure 800, which is different from the packaging structure 100 in that:

[0116] 1) In the package structure 800, two prefabricated interconnected silicon core stacking structures 111 are plastic-sealed in the first plastic sealing layer 812 of the lower package body 810. The film layer structures of the two prefabricated interconnected silicon core stacking structures 111 are similar, but the difference is that they are different in size. Corresponding prefabricated chip packaging layers are respectively arranged above the two prefabricated interconnected silicon core stacking structures 111. For the convenience of description, the corresponding prefabricated chip packaging layers are defined as the first prefabricated chip packaging layer 113 and the second prefabricated chip packaging layer 813. The first prefabricated chip packaging layer 113 The first prefabricated stacking unit 801 is disposed above one of the two prefabricated interconnected silicon core stacking structures 111 and constitutes a first prefabricated stacking unit 801; the second prefabricated chip packaging layer 813 is disposed above the other of the two prefabricated interconnected silicon core stacking structures 111 and constitutes a second prefabricated stacking unit 802; the first plastic encapsulation layer 812 encapsulates the first prefabricated stacking unit 801 and the second prefabricated stacking unit 802 to constitute a lower package body 810; the first prefabricated stacking unit 801 and the second prefabricated stacking unit 802 are respectively electrically connected to the first redistribution stacking layer 130;

[0117] 2) The second prefabricated chip packaging layer 813 includes a third chip 8120, which is electrically connected to the first prefabricated redistribution stack layer 1114 in the first prefabricated interconnected silicon core stack structure 111 via a conductive material layer 8121. The function of the third chip 8120 is different from that of the first chip 1133.

[0118] 3) Beneath the lower package body 810, a backside redistribution stack 850 is provided. This is electrically connected to the second prefabricated redistribution stack 1115 in the first prefabricated interconnected silicon core stack 111 and the second prefabricated redistribution stack 1115 in the second prefabricated interconnected silicon core stack 111, respectively. Metal bumps or solder balls 140 are disposed on the backside of the backside redistribution stack 850 and are electrically connected thereto. The first prefabricated stack unit 801 and the second prefabricated stack unit 802 are electrically connected to the backside redistribution stack 850, respectively.

[0119] In this embodiment, in the packaging structure 800, the first plastic packaging layer 812 plastic-seales two first prefabricated stacking units 801 and second prefabricated stacking units 802 with different functions to form a lower packaging body 810. Since the first prefabricated stacking unit 801 and the second prefabricated stacking unit 802 are respectively manufactured in a wafer-level or panel-level packaging process and pre-cut into single particles, after completing performance testing, they are plastic-sealed to form a reconstructed substrate. On the one hand, the reconstructed substrate can have multiple functions; on the other hand, the yield of the embedded chip in the reconstructed substrate can be improved; that is, plastic-sealing and reconstructing the reconstructed substrate through the prefabricated module (block) with the embedded chip helps to improve the functional diversity of the packaging structure and the yield of the chip embedding.

[0120] It should be noted that in other embodiments of the present invention, the first plastic encapsulation layer may also be formed by encapsulating two or more prefabricated stacked units with similar functions and the same or different sizes to form a lower package body. Furthermore, within the prefabricated stacked units, the prefabricated chip encapsulation layer may also be stacked below the prefabricated interconnected silicon core stack structure, located at the bottom of the package structure or the lower package body.

[0121] also, Figure 8 and Figure 1 The same reference numerals represent the same components with similar functions and are not described in detail.

[0122] like Figure 9 As shown, the ninth embodiment of the present invention further provides a packaging structure 900, which is different from the packaging structure 100 in that:

[0123] 1) In the package structure 900, two prefabricated interconnected silicon core stack structures 111 are encapsulated in the first plastic encapsulation layer 912 to form a lower package body 910; wherein the film layer structures of the two prefabricated interconnected silicon core stack structures 111 can be the same or different, and the sizes can be the same or different;

[0124] 2) A second redistribution stack layer 920 is disposed above the lower package body 910, with a minimum line width and line spacing of less than 10 μm. An interconnect chip packaging layer 930 is disposed above the second redistribution stack layer 920; a first redistribution stack layer 130 is disposed above the interconnect chip packaging layer 930, with a minimum line width and line spacing of less than 5 μm; and an upper package body 120 is disposed above the first redistribution stack layer 130;

[0125] 3) The interconnect chip packaging layer 930 includes a plurality of conductive pillars 931, a third plastic encapsulation layer 932, and an interconnect chip 933. The plurality of conductive pillars 931 are formed above the second redistribution stack layer 920, with one end of each conductive pillar 931 electrically connected to a pad exposed from the dielectric layer in the second redistribution stack layer 920. The interconnect chip 933 is mounted upright on the second redistribution stack layer 920. An interconnect redistribution stack layer 934 and a connection bump 935 are provided on the surface of the interconnect chip 933 facing the first redistribution stack layer 130. The connection bump 935 electrically connects the first redistribution stack layer 130 and the interconnect redistribution stack layer 934. The third plastic encapsulation layer 932 encapsulates the plurality of conductive pillars 931 and the interconnect chip 933 above the second redistribution stack layer 920.

[0126] 4) The two prefabricated interconnected silicon core stack structures 111 are electrically connected to the second redistribution stack layer 920 respectively;

[0127] 5) Another auxiliary structure 901 is embedded in the second plastic encapsulation layer 122 of the upper package body 120, including but not limited to a metal block, a heat sink block, and a reinforcement block. The auxiliary structure 901 is disposed at the edge and / or corner of the first redistribution stack layer 130 to improve warpage of the package structure 900, dissipate heat, and shield against electromagnetic interference.

[0128] 6) A composite multi-layer metal heat sink 904 is also provided on the surface of the upper package body 120 away from the first redistribution stack layer 130. The composite multi-layer metal heat sink 904 includes a patterned metal layer and / or a patterned dielectric layer, wherein the patterned metal layer and / or the patterned dielectric layer are used to avoid warping of the package structure 900 and balance stress.

[0129] also, Figure 9 and Figure 8 The same reference numerals represent the same components with similar functions and are not described in detail.

[0130] like Figure 10 As shown, the tenth embodiment of the present invention further provides a packaging structure 1000, which is different from the packaging structure 900 in that:

[0131] 1) A passivation layer 1113', a silicon interconnect layer 1111, a back-end redistribution stack layer 1112, and a first prefabricated redistribution stack layer 1114 are stacked from bottom to top to form a prefabricated interconnected silicon core stack structure 1011; wherein the edge of the passivation layer 1113' protrudes beyond the edge of the silicon interconnect layer 1111 and is partially stacked above one side surface of the first plastic encapsulation layer 1012; preferably, a flattening layer 1020 is provided between the edge of the passivation layer 1113' and the first plastic encapsulation layer 1012, and the flattening layer 1020 is used to prevent the edge of the lower package body 1010 from warping at high temperatures;

[0132] 2) The silicon interconnect layer 1111 is provided with a second surface 1111b of the passivation layer 1113 (eg Figure 1 ) protrudes from the back side of the first plastic packaging layer 1012;

[0133] 3) The first plastic encapsulation layer 1012 encapsulates the two prefabricated interconnected silicon core stacking structures 1011 to form a lower package body 1010; wherein the film layer structures of the two prefabricated interconnected silicon core stacking structures 1011 can be the same or different, and the sizes can be the same or different;

[0134] 4) Also included is a backside redistribution stack layer 1050 disposed below the lower package body 1010, with metal bumps or solder balls 140 disposed on the back side of the backside redistribution stack layer 1050 and electrically connected to the conductive layer in the backside redistribution stack layer 1050; wherein the edge of the backside redistribution stack layer 1050 protrudes from the edge of the prefabricated interconnected silicon core stack structure 1011 and covers the edge of the passivation layer 1113';

[0135] 5) Two prefabricated interconnected silicon core stack structures 1011 are electrically connected to the second redistribution stack layer 920 and the backside redistribution stack layer 1050, respectively.

[0136] also, Figure 10 and Figure 9 The same reference numerals represent the same components with similar functions and are not described in detail.

[0137] like Figure 11 As shown, the eleventh embodiment of the present invention further provides a package structure 2000, which is different from the package structure 900 in that:

[0138] 1) In the package structure 2000, the lower package body 2010 includes a prefabricated interconnected silicon core stacking structure 111 and a first prefabricated substrate 2013. The first prefabricated substrate 2013 and the prefabricated interconnected silicon core stacking structure 111 are stacked on top of each other to form a first prefabricated unit 2001. The first plastic encapsulation layer 2012 encapsulates the first prefabricated unit 2001 to form the lower package body 2010. The first prefabricated substrate 2013 is, for example, a laminate substrate including a base material layer and conductive layers and dielectric layers alternately stacked on the base material layer.

[0139] 2) The prefabricated interconnected silicon core stack structure 111 is electrically connected to the first prefabricated substrate 2013 and the second redistribution stack layer 920 , wherein the prefabricated interconnected silicon core stack structure 111 and the first prefabricated substrate 2013 are electrically connected by, but not limited to, tin-gold bonding or copper-copper diffusion bonding;

[0140] 3) Metal bumps or solder balls 140 are formed on the back side of the first prefabricated substrate 2013 .

[0141] In other embodiments of the present invention, a bottom filling material layer can also be filled between the prefabricated interconnected silicon core stacking structure and the first prefabricated substrate. The bottom filling material fixes the prefabricated interconnected silicon core stacking structure on the first prefabricated substrate to form a first prefabricated unit with better stability. The first prefabricated unit is then sealed by the first plastic sealing layer to form a reconstructed substrate.

[0142] It should be noted that in other embodiments of the present invention, according to actual needs, the prefabricated interconnected silicon core stacking structure can also be stacked below the first prefabricated substrate and constitute a first prefabricated unit. In other words, according to actual needs, the prefabricated interconnected silicon core stacking structure is arranged on at least one side of the third surface and the fourth surface opposite to the first prefabricated substrate, and constitutes a first prefabricated unit with the first prefabricated substrate, and the first plastic encapsulation layer encapsulates this first prefabricated unit to constitute a reconstructed substrate or a lower packaging body.

[0143] also, Figure 11 and Figure 9 The same reference numerals represent the same components with similar functions and are not described in detail.

[0144] like Figure 12 As shown, the twelfth embodiment of the present invention further provides a package structure 3000, which is different from the package structure 2000 in that:

[0145] In the packaging structure 3000, two horizontally arranged prefabricated interconnected silicon core stacking structures 111 are stacked on top of the first prefabricated substrate 2013. The two horizontally arranged prefabricated interconnected silicon core stacking structures 111 and the first prefabricated substrate 2013 constitute a first prefabricated unit 3001, which is then plastic-sealed by a first plastic layer 3012 to form a lower packaging body 3010.

[0146] The two horizontally arranged prefabricated interconnected silicon core stack structures 111 are electrically connected to the first prefabricated substrate 2013 and the second redistribution stack layer 920 .

[0147] also, Figure 12 and Figure 11 The same reference numerals represent the same components with similar functions and are not described in detail.

[0148] like Figure 13As shown, the thirteenth embodiment of the present invention further provides a package structure 4000, which is different from the package structure 2000 in that:

[0149] In the packaging structure 4000, a prefabricated interconnected silicon core stacking structure 111 and a second prefabricated substrate 4002 are stacked on top of the first prefabricated substrate 2013. The prefabricated interconnected silicon core stacking structure 111 and the second prefabricated substrate 4002 are horizontally arranged on the surface of one side of the first prefabricated substrate 2013, wherein the substrate layer 4003 of the second prefabricated substrate 4002 is different from the substrate layer of the first prefabricated substrate 2013.

[0150] The prefabricated interconnected silicon core stacking structure 111 and the second prefabricated substrate 4002 are respectively bonded to the first prefabricated substrate 2013 and are respectively electrically connected to the first prefabricated substrate 2013. In addition, the prefabricated interconnected silicon core stacking structure 111 and the second prefabricated substrate 4002 are also respectively electrically connected to the second redistribution stack layer 920.

[0151] The second prefabricated substrate 4002 is also, for example, a laminate substrate, and the material of the base material layer 4003 can be selected from glass, ceramics, and the like.

[0152] In addition, the base material layer of the first prefabricated substrate 2013 may be filled with functional materials, including heat-resistant fillers, magnetic fillers, and the like.

[0153] In this embodiment, the first prefabricated substrate 2013 , the second prefabricated substrate 4002 and the prefabricated interconnected silicon core stacking structure 111 constitute a first prefabricated unit 4001 , and the first plastic encapsulation layer 4012 encapsulates the first prefabricated unit 4001 to form a lower package body 4010 .

[0154] also, Figure 12 and Figure 11 The same reference numerals represent the same components with similar functions and are not described in detail.

[0155] like Figure 14 As shown, the fourteenth embodiment of the present invention further provides a packaging structure 5000, which is different from the packaging structure 4000 in that:

[0156] In the packaging structure 5000, the first prefabricated unit 4001 is encapsulated in the first plastic layer 5012 to form a lower packaging body 5010, wherein a functional block 5001 is buried in the first plastic layer 5012. The functional block 5001 is a larger inductor or other component, and the functional block 5001 is electrically connected to the second redistribution stacking layer 920.

[0157] also, Figure 14 and Figure 13 The same reference numerals represent the same components with similar functions and are not described in detail.

[0158] like Figure 15 As shown, the fifteenth embodiment of the present invention further provides a package structure 6000, which differs from the package structure 3000 in that:

[0159] 1) Two prefabricated interconnected silicon core stack structures 211 (refer to Figure 2 The packaging structure 200 is provided below the first prefabricated substrate 2013 to form a first prefabricated unit 6001. The first plastic sealing layer 6012 seals the first prefabricated unit 6001 to form a lower packaging body 6010.

[0160] 2) The metal bumps or solder balls 140 are electrically connected to the conductive layer in the first prefabricated redistribution stack layer 1114 ;

[0161] 3) A build-up substrate 6002 is embedded in the first plastic encapsulation layer 6012 . The build-up substrate 6002 is electrically connected to the second redistribution stack layer 920 and the metal bumps or solder balls 140 . The build-up substrate 6002 can be used to achieve flexible interconnection.

[0162] In this embodiment, the functions of the two prefabricated interconnected silicon core stack structures 211 may be the same or different, and they are located at the bottom of the lower package body 6010 .

[0163] also, Figure 15 and Figure 12 The same reference numerals represent the same components with similar functions and are not described in detail.

[0164] like Figure 16 As shown, the sixteenth embodiment of the present invention further provides a package structure 7000, which differs from the package structure 900 in that:

[0165] The lower package body 7010 includes a prefabricated interconnected silicon core stacking structure 111, a first prefabricated substrate 2013 distributed on the right side of the prefabricated interconnected silicon core stacking structure 111 in the horizontal direction, and a third prefabricated substrate 7013 distributed on the left side of the prefabricated interconnected silicon core stacking structure 111.

[0166] In this embodiment, the prefabricated interconnected silicon core stacking structure 111 , the first prefabricated substrate 2013 and the third prefabricated substrate 7013 are arranged horizontally side by side to form a second prefabricated unit 7001 , which is then sealed with a first plastic sealing layer 7012 to form a lower package body 7010 .

[0167] The substrate layer 7014 of the third prefabricated substrate 7013 and the substrate layer of the first prefabricated substrate 2013 may be different or the same. Preferably, the substrate layer 7014 is filled with functional materials, including heat-resistant fillers, magnetic fillers, and the like.

[0168] In addition, since the prefabricated interconnected silicon core stacking structure 111, the first prefabricated substrate 2013 and the third prefabricated substrate 7013 are arranged horizontally side by side, they can be arranged in the same layer on the wafer in the wafer-level or panel-level fan-out packaging process and can be filled with different filler layers.

[0169] Furthermore, the dummy elements 7002 and silicon capacitors 7003 in the interconnect chip packaging layer 930 are arranged in the same layer and are electrically connected to the first redistribution stack layer 130 and the second redistribution stack layer 920 with small line width and line spacing.

[0170] like Figure 17 As shown, the seventeenth embodiment of the present invention further provides a packaging structure 9000, which differs from the packaging structure 100 in that, in the packaging structure 9000, the prefabricated interconnected silicon core stacking structure 111 is molded by the first plastic molding layer 112 to form a lower packaging body 110, and a first redistribution stacking layer 130 is arranged above the lower packaging body 110, wherein the chip 121 and / or the device packaging body 121 is flip-chip mounted above the first redistribution stacking layer 130 and is electrically connected to the first redistribution stacking layer 130.

[0171] An underfill material layer 123 is filled between the chip 121 and / or the device package 121 and the first redistribution stack layer 130 .

[0172] Optionally, a metal block or frame 101 is set at the edge and / or corner of the first redistribution stacking layer 130. The metal block or frame 101 can be a metal or silicon block with a metal surface coating, or a silicon wafer, which is connected to the first redistribution stacking layer 130 by metal bonding or adhesive bonding. It is arranged above the first redistribution stacking layer 130, preferably located at the edge and / or corner of the first redistribution stacking layer 130, and is used to improve the warping, heat dissipation and electromagnetic interference shielding of the packaging structure 100.

[0173] In addition, the functional device 102 is disposed above the first redistribution stack layer 130 and is electrically connected to the first redistribution stack layer 130 . The functional device 102 may be a capacitor, an inductor, or other functional device.

[0174] Furthermore, optionally, a plastic encapsulation material may be disposed above the first redistribution stack layer 130 to encapsulate the chip 121 and / or the device package 121 , the metal block or frame 101 , and the functional device 102 .

[0175] Figure 17 Zhongyu Figure 1 Other identical reference numerals represent identical components with similar functions and are not described in detail herein.

[0176] like Figure 18 As shown, the present invention also provides a method 8000 for manufacturing a packaging structure, which includes:

[0177] Providing a silicon interconnect layer, the silicon interconnect layer comprising a silicon substrate, the silicon substrate comprising a plurality of through-silicon vias and a plurality of first prefabricated conductive pillars embedded in the plurality of through-silicon vias, the silicon substrate comprising a first surface and a second surface opposite to each other, each of the first prefabricated conductive pillars comprising a first end and a second end opposite to each other, the first end being exposed from the first surface and the second end being exposed from the second surface;

[0178] forming a back-end redistribution stack layer on the first surface, wherein the first end is electrically connected to the back-end redistribution stack layer;

[0179] forming a passivation layer on the second surface and thinning the passivation layer so that the second end is exposed from the passivation layer;

[0180] forming a first prefabricated redistribution stack layer above the back-end redistribution stack layer;

[0181] Cutting the silicon substrate including the first prefabricated redistribution stack layer, the back-end redistribution stack layer and the passivation layer to form a single prefabricated interconnected silicon core stack structure;

[0182] A plurality of prefabricated interconnected silicon core stacking structures of a plastic-encapsulated single particle form a first plastic-encapsulation layer, constituting a plurality of lower packaging bodies; and

[0183] The upper package body is packaged above the corresponding lower package body, wherein the upper package body is located above the first prefabricated redistribution stack layer and is electrically connected to the first prefabricated redistribution stack layer.

[0184] In a preferred embodiment, before the step of cutting the silicon interconnect layer including the first prefabricated redistribution stack layer, the back-end redistribution stack layer and the passivation layer to form a single prefabricated interconnected silicon core stack structure, the step further includes:

[0185] A second prefabricated redistribution stack layer is formed on the passivation layer; and a prefabricated chip packaging layer is formed on one side of the second prefabricated redistribution stack layer or the first prefabricated redistribution stack layer.

[0186] In a preferred embodiment, before the step of packaging the upper package body onto the corresponding lower package body, the step further includes:

[0187] A first redistribution stacking layer is formed above the lower package body; and an upper package body is packaged above the first redistribution stacking layer.

[0188] The following will be Figure 1 Taking the package structure 100 in FIG. 1 as an example, the following is described in detail. Figure 18 Each step of the production method 7000.

[0189] like Figure 19 As shown, the manufacturing process of the prefabricated interconnected silicon core stack structure 111 includes:

[0190] First, a silicon interconnect layer 1111 is provided, comprising a wafer-level silicon substrate including a plurality of through-silicon vias (TSVs), wherein a plurality of first prefabricated conductive vias 1116 are embedded in the TSVs. The silicon substrate includes a first surface 1111a and a second surface 1111b, which are opposed to each other. The second surface 1111b is located within the bulk of the silicon wafer before the back-end redistribution stack 1112 and the first prefabricated redistribution stack 1114 are formed, and before the back of the first prefabricated conductive vias 1116 are exposed. For simplicity, these surfaces are not shown in the figure. Each first prefabricated conductive via 1116 includes a first end and a second end, with the first end exposed from the first surface 1111a and the second end exposed from the second surface 1111b. Preferably, the silicon substrate also includes a plurality of trench silicon capacitors 1117.

[0191] Secondly, a back-end redistribution stacking layer 1112 is formed on the first surface 1111a of the wafer-level silicon substrate, and the minimum line width and line spacing in the back-end redistribution stacking layer 1112 is less than 2μm; a passivation layer 1113 is formed on the second surface 1111b, and the passivation layer 1113 is thinned so that the second end of the first prefabricated conductive column 1116 is exposed from the passivation layer 1113.

[0192] Then, a first prefabricated redistribution stack layer 1114 is formed on the back-end redistribution stack layer 1112. The first prefabricated redistribution stack layer 1114 is electrically connected to the back-end redistribution stack layer 1112. At this point, the silicon interconnect layer 1111, the back-end redistribution stack layer 1112, the passivation layer 1113, and the first prefabricated redistribution stack layer 1114 constitute a prefabricated interconnected silicon core stack structure.

[0193] Continue to refer to Figure 1 In this embodiment, a second prefabricated redistribution stacking layer 1115 is fabricated on one side of the passivation layer 1113, wherein the silicon interconnection layer 1111, the back-end redistribution stacking layer 1112, the passivation layer 1113, the first prefabricated redistribution stacking layer 1114 and the second prefabricated redistribution stacking layer 1115 together constitute a prefabricated interconnection silicon core stacking structure 111.

[0194] Furthermore, a single prefabricated interconnected silicon core stack structure 111 is obtained by cutting a wafer-level silicon substrate (not shown).

[0195] like Figure 20 As shown, the process of manufacturing the prefabricated chip packaging layer 113 on the prefabricated interconnected silicon core stack structure 111 includes:

[0196] A prefabricated chip packaging layer 113 is continued to be manufactured on the wafer-level silicon substrate with a prefabricated interconnected silicon core stacking structure and no cutting, including: forming a second prefabricated conductive column 1131 on the first prefabricated redistribution stacking layer 1114; using a chip mounting layer 1136 to mount the first chip 1133 on the first prefabricated redistribution stacking layer 1114, the first chip 1133 including a prefabricated interconnected redistribution stacking layer 1134 and a connecting bump 1135 arranged thereon; applying a prefabricated molding compound on the first prefabricated redistribution stacking layer 1114 to mold the second prefabricated conductive column 1131 and the first chip 1133, and forming a prefabricated molding layer 1132 after the prefabricated molding compound is cured; thinning the prefabricated molding layer 1132 so that the upper end of the second prefabricated conductive column 1131 is exposed from the front of the prefabricated molding layer 1132, at which time the prefabricated chip packaging layer 113 is completed. As another alternative, the manufacturing process of the first prefabricated conductive pillar 1116, the passivation layer 1113 and the second prefabricated redistribution stack layer 1115 can be performed with an optional temporary carrier process after the prefabricated plastic layer 1132 is completed.

[0197] Furthermore, the prefabricated chip packaging layer 113 and the prefabricated interconnected silicon core stacking structure 111 are cut together into a single prefabricated unit, which includes the stacked prefabricated chip packaging layer 113 and the prefabricated interconnected silicon core stacking structure 111 .

[0198] It should be noted that in other embodiments of the present invention, the prefabricated chip packaging layer can also be manufactured separately in another wafer-level or board-level packaging process, and after being cut into single particles, it can be bonded to the prefabricated interconnected silicon core stacking structure to improve the yield of the embedded first chip.

[0199] like Figure 21 As shown, the manufacturing process of the lower package body 110 of the prefabricated unit of the plastic-encapsulated single pellet includes:

[0200] Provide an optional temporary carrier plate or carrier tape 10 to hold several single-grain prefabricated units ( Figure 20 Only one is shown in the figure) is temporarily bonded to the carrier 10; a first molding compound is applied to cover the plurality of single prefabricated units. After the first molding compound is cured, a first molding layer 112 covering the plurality of single prefabricated units is formed; the front surface of the first molding layer 112 is thinned to expose the upper end of the second prefabricated conductive pillar 1131 and the connection bump 1135 on the first chip 1133; at this time, the first molding layer 112 and the single prefabricated unit constitute the lower package body 110.

[0201] like Figure 21 As shown, a first redistribution stack layer 130 is continuously formed on the lower package body 110 , and a minimum line width and line spacing of the first redistribution stack layer 130 is less than 5 μm.

[0202] like Figure 22 and Figure 23 As shown, the manufacturing process of packaging the upper package body 120 above the first redistribution stack layer 130 includes:

[0203] Flip-chip bonding the chip 121 and / or device package 121 to the top of the first redistribution stacking layer 130; optionally, bonding metal blocks or frames 101 and functional devices 102 to the edges and / or corners of the first redistribution stacking layer 130; filling the underfill material layer 123 between the chip 121 and / or device package 121 and the first redistribution stacking layer 130; applying a second plastic encapsulation material to the top of the first redistribution stacking layer 130, and covering the chip 121 and / or device package 121, the optional metal blocks or frames 101, and the functional devices 102, and forming a second plastic encapsulation layer 122 after the second plastic encapsulation layer is cured.

[0204] The carrier 10 and the lower package body 110 are debonded, and metal bumps or solder balls 140 are implanted on one side of the second prefabricated redistribution stack layer 1115 . The metal bumps or solder balls 140 are electrically connected to the conductive layer of the second prefabricated redistribution stack layer 1115 .

[0205] Finally, the front side of the second plastic encapsulation layer 122 is thinned to expose the back side of the chip 121 and / or the device package 121 .

[0206] In summary, the present invention provides a packaging structure and a manufacturing method, in which a reconstructed substrate is manufactured by a prefabricated interconnected silicon core stacking structure of a plastic-sealed single particle. Since the prefabricated interconnected silicon core stacking structure can stack a prefabricated redistribution stacking layer on the silicon interconnection layer, on the one hand, the prefabricated redistribution stacking layer can have a narrower line width and line spacing, and a thinner thickness, and therefore can effectively meet the packaging requirements of high density and small packaging volume; on the other hand, stacking the prefabricated redistribution stacking layer and other more redistribution stacking layers on the silicon interconnection layer can significantly improve the manufacturing yield of the packaging structure.

[0207] The present invention has been described by the above-mentioned embodiments. However, the above-mentioned embodiments are merely examples of the present invention. In addition, the technical features involved in the different embodiments of the present invention described above may be combined with each other as long as they do not conflict with each other. It must be pointed out that the present invention may also have various other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention. However, such corresponding changes and modifications shall fall within the scope of protection of the claims appended to the present invention.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: A lower package body, and an upper package body disposed above the lower package body, the lower package body and the upper package body being electrically connected; The lower package body includes a prefabricated interconnected silicon core stacking structure and a first plastic packaging layer arranged around the periphery of the prefabricated interconnected silicon core stacking structure; The prefabricated interconnected silicon core stacking structure includes a silicon interconnection layer, the silicon interconnection layer including a first surface and a second surface opposite to each other; a back-end redistribution stacking layer and a first prefabricated redistribution stacking layer are sequentially stacked on the first surface, the back-end redistribution stacking layer and the first prefabricated redistribution stacking layer being electrically connected; and a passivation layer is provided on the second surface; The silicon interconnect layer includes a silicon substrate and a plurality of first prefabricated conductive vias embedded in a plurality of through-silicon vias (TSVs) in the silicon substrate, each of the first prefabricated conductive vias including a first end and a second end opposite to each other, wherein the first end is exposed from the first surface, and the second end is exposed from a side of the passivation layer away from the second surface; The upper package body is disposed above the first prefabricated redistribution stack layer and is electrically connected to the first prefabricated redistribution stack layer; The prefabricated interconnected silicon core stack structure further includes a second prefabricated redistribution stack layer, the second prefabricated redistribution stack layer is disposed on a side of the passivation layer away from the second surface, and the second prefabricated redistribution stack layer is electrically connected to the second end of each first prefabricated conductive pillar in the silicon interconnect layer; The lower package body further includes: a prefabricated chip packaging layer, the prefabricated chip packaging layer including: a plurality of second prefabricated conductive pillars, a first chip and a prefabricated plastic packaging layer, the plurality of second prefabricated conductive pillars and the first chip are respectively embedded in the prefabricated plastic packaging layer, and the first plastic packaging layer is also coated on the outside of the prefabricated plastic packaging layer; The prefabricated chip packaging layer is arranged on a side of the first prefabricated redistribution stack layer away from the silicon interconnection layer; or the prefabricated chip packaging layer is arranged on a side of the second prefabricated redistribution stack layer away from the silicon interconnection layer; The silicon interconnect layer in the prefabricated interconnected silicon core stacking structure includes a first surface and a second surface facing each other, a silicon substrate, a plurality of through silicon vias formed in the silicon substrate, and a plurality of first prefabricated conductive columns embedded in the plurality of through silicon vias.

2. The packaging structure according to claim 1, wherein: The packaging structure further includes a backside redistribution stacking layer, which is arranged below the prefabricated interconnected silicon core stacking structure; The back side redistribution stack layer is arranged on a side of the passivation layer away from the second surface, and the back side redistribution stack layer is electrically connected to the silicon interconnect layer.

3. The packaging structure according to claim 2, wherein: The edge of the backside redistribution stacking layer protrudes from the edge of the prefabricated interconnected silicon core stacking structure and extends to be stacked on the first plastic encapsulation layer, and / or the edge of the passivation layer protrudes from the edge of the silicon interconnection layer and extends to be stacked on the first plastic encapsulation layer.

4. The packaging structure according to claim 1, wherein: The lower package body further includes at least one first functional block and / or at least one second functional block; The at least one first functional block is embedded in the first substrate layer of the first prefabricated redistribution stack layer; the at least one second functional block is embedded in the second substrate layer of the second prefabricated redistribution stack layer; In which, the upper package body includes a chip and / or device package body; in the thickness direction of the package structure, the at least one first functional block is stacked below the corresponding chip and / or device package body; the at least one second functional block is stacked below the corresponding chip and / or device package body.

5. The packaging structure according to claim 2, wherein: The lower package body also includes a third prefabricated redistribution stacking layer, which is arranged between the prefabricated chip packaging layer and the back side redistribution stacking layer, and the third prefabricated redistribution stacking layer is electrically connected to the prefabricated chip packaging layer and the back side redistribution stacking layer.

6. The packaging structure according to claim 1, wherein: The prefabricated plastic packaging layer further includes an embedded third functional block, and the third functional block and the first chip are horizontally arranged side by side in the prefabricated plastic packaging layer.

7. The packaging structure according to claim 1, wherein: The lower package body also includes a solder resist layer, which is arranged between the first prefabricated redistribution stack layer and the upper package body, wherein the elastic modulus or tensile elongation at break of the solder resist layer is the same as or different from the elastic modulus or tensile elongation at break of the dielectric layer in the first prefabricated redistribution stack layer.

8. The packaging structure according to claim 1, wherein: The package structure further includes a first redistribution stack layer disposed between the upper package body and the lower package body, wherein the first redistribution stack layer electrically connects the upper package body and the lower package body.

9. The packaging structure according to claim 8, wherein: Also includes: a second redistribution stack layer and an interconnect chip packaging layer disposed between the lower package body and the first redistribution stack layer; The second redistribution stack layer is disposed above the lower package body; The interconnect chip packaging layer is arranged above the second redistribution stacking layer; The interconnect chip packaging layer includes: a plurality of conductive pillars, an interconnect chip, and a second plastic packaging layer, wherein the plurality of conductive pillars and the interconnect chip are respectively buried in the second plastic packaging layer, and opposite ends of each conductive pillar are electrically connected to the first redistribution stack layer and the second redistribution stack layer, and the thickness of the second plastic packaging layer is between 150 μm and 780 μm; The interconnect chip includes an interconnect rewiring stack layer and a connecting bump located above the interconnect rewiring stack layer, the connecting bump electrically connects the first rewiring stack layer and the interconnect rewiring stack layer, the minimum line width and line spacing of the interconnect rewiring stack layer is less than 2μm, and the interconnect rewiring stack layer includes at least one capacitor.

10. The packaging structure according to claim 8, wherein: It also includes an auxiliary structure, which is arranged at an edge and / or corner of the first redistribution stack layer.

11. The packaging structure according to claim 1, wherein: The silicon interconnect layer further includes a trench silicon capacitor, and the trench silicon capacitor is electrically connected to the back-end redistribution stack layer.

12. The packaging structure according to any one of claims 1, wherein: The number of the prefabricated interconnected silicon core stacking structures in the first plastic encapsulation layer is two or more, and the two or more prefabricated interconnected silicon core stacking structures are arranged horizontally side by side and are all encapsulated by the first plastic encapsulation layer, wherein the sizes of the two or more prefabricated interconnected silicon core stacking structures are the same or different.

13. The packaging structure according to claim 1, wherein: The lower package body also includes a first prefabricated substrate, which includes a third surface and a fourth surface opposite to each other. The prefabricated interconnected silicon core stacking structure is arranged on the third surface and / or the fourth surface and is electrically connected to the first prefabricated substrate respectively; wherein the prefabricated interconnected silicon core stacking structure and the prefabricated substrate constitute a first prefabricated unit, and the first plastic layer encapsulates the first prefabricated unit to constitute the lower package body.

14. The packaging structure according to claim 13, wherein: The lower package body further includes an underfill layer, and the underfill layer is filled between the prefabricated interconnected silicon core stacking structure and the first prefabricated substrate.

15. The packaging structure according to any one of claims 1 to 7, characterized in that: The lower package body also includes a second prefabricated substrate and / or a third prefabricated substrate, which are respectively arranged horizontally side by side with the prefabricated interconnected silicon core stacking structure and constitute a second prefabricated unit, and the first plastic encapsulation layer encapsulates the second prefabricated unit to constitute the lower package body; wherein the base material layer material of the second prefabricated substrate is the same as or different from the base material layer material of the third prefabricated substrate.

16. A method for manufacturing a packaging structure, characterized in that: The production method comprises: Providing a silicon interconnect layer, the silicon interconnect layer including a first surface and a second surface opposite to each other, the silicon interconnect layer including a silicon substrate, the silicon substrate including a plurality of through-silicon vias and first prefabricated conductive vias embedded in the plurality of through-silicon vias, each of the first prefabricated conductive vias including a first end and a second end opposite to each other, the first end being exposed from the first surface, and the second end being exposed from the second surface; forming a back-end redistribution stack layer on the first surface, wherein the first end is electrically connected to the back-end redistribution stack layer; forming a passivation layer on the second surface and thinning the passivation layer, with the second end exposed from the passivation layer; forming a first prefabricated redistribution stack layer above the back-end redistribution stack layer; Cutting the silicon interconnect layer including the first prefabricated redistribution stack layer, the back-end redistribution stack layer and the passivation layer to form a single prefabricated interconnected silicon core stack structure; Plastic encapsulate the plurality of prefabricated interconnected silicon core stacking structures of the single particle to form a first plastic encapsulation layer, constituting a plurality of lower packaging bodies; and Encapsulating an upper package body onto the corresponding lower package body, wherein the upper package body is electrically connected to the first prefabricated redistribution stack layer; Before the step of cutting the silicon interconnect layer including the first prefabricated redistribution stack layer, the back-end redistribution stack layer and the passivation layer to form a single prefabricated interconnected silicon core stack structure, the step further includes: forming a second prefabricated redistribution stack layer on the passivation layer; and A prefabricated chip packaging layer is formed on one side of the second prefabricated redistribution stack layer or the first prefabricated redistribution stack layer.

17. The method for manufacturing a packaging structure according to claim 16, wherein: Before the step of packaging the upper package body onto the corresponding lower package body, the method further includes: forming a first redistribution stack layer above the lower package body; and The upper package body is packaged above the first redistribution stack layer.

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