A thin film transistor based capacitorless dram cell structure and method of manufacture

Abstract

The application relates to a thin-film transistor-based capacitorless DRAM cell structure and a manufacturing method. The capacitorless DRAM cell structure comprises, from bottom to top, a semiconductor substrate, a first isolation layer, a first electrode layer, a second isolation layer, a second electrode layer, a first channel layer, a first gate dielectric layer, a first gate layer, a third isolation layer, a third electrode layer, a second channel layer, a second gate dielectric layer and a second gate layer; wherein the first electrode layer, the second isolation layer and the second electrode layer are conformal and only cover the surface of the central part of the first isolation layer; the first channel layer covers the side surface of the first electrode layer, the side surface of the second isolation layer, the upper surface and the side surface of the second electrode layer and the remaining upper surface of the first isolation layer; and the second channel layer covers the side surface of the third isolation layer, the side surface and the upper surface of the third electrode layer. The application adopts a double-layer transistor vertical stacking technology, saves the cell area and is beneficial to improving the integration density of the circuit.

Description

Technical Field

[0001] This invention relates to the field of memory, and in particular to a capacitor-free DRAM cell structure and manufacturing method based on thin-film transistors. Background Technology

[0002] Currently, the common structure of Dynamic Random Access Memory (DRAM) cells is a transistor with a capacitor connected to its drain. This structure requires constantly refreshing the charge in the capacitor to prevent data loss, and the charge in the capacitor needs to be released during reading, and then rewritten after the read is complete, resulting in high power consumption. Furthermore, the large area required for capacitor manufacturing makes miniaturization a challenge.

[0003] Dual-transistor capacitorless dynamic random access memory (2Transistor 0Capacitor 2T0C) uses two transistors as its cell structure, such as... Figure 1 As shown, the drain of one transistor is connected to the gate of another transistor, using the gate capacitance to store charge and changing the transconductance of the transistor to store information.

[0004] In recent years, 2T0C memory using indium gallium zinc oxide (IGZO) channels has become increasingly popular due to the extremely low off-state current of IGZO thin-film transistors (TFTs), which significantly reduces leakage current in 2T0C DRAM cells. However, existing IGZO TFT-based 2T0C DRAM cells typically use two horizontally channeled TFTs connected on the same plane, resulting in a larger footprint and lower integration density. Summary of the Invention

[0005] The main objective of this invention is to provide a capacitor-free DRAM cell structure and manufacturing method based on thin-film transistors, which adopts a double-layer transistor vertical stacking technology, saves cell area, and helps to improve circuit integration density.

[0006] To achieve the above objectives, the present invention provides the following technical solutions.

[0007] The first aspect of the present invention provides a capacitor-free DRAM cell structure based on thin-film transistors, comprising, from bottom to top, the following layers stacked in sequence: a semiconductor substrate, a first isolation layer, a first electrode layer, a second isolation layer, a second electrode layer, a first channel layer, a first gate dielectric layer, a first gate layer, a third isolation layer, a third electrode layer, a second channel layer, a second gate dielectric layer, and a second gate layer.

[0008] The first electrode layer, the second isolation layer and the second electrode layer are conformal and only cover the surface of the central part of the first isolation layer; the first channel layer covers the side surface of the first electrode layer, the side surface of the second isolation layer, the upper surface and the side surface of the second electrode layer, and the remaining upper surface of the first isolation layer; the first channel layer, the first gate dielectric layer and the first gate electrode layer are conformal; the second channel layer covers the side surface of the third isolation layer, the side surface and the upper surface of the third electrode layer; the second channel layer, the second gate dielectric layer and the second gate electrode layer are conformal.

[0009] The first isolation layer, the second isolation layer and the third isolation layer are all insulating materials.

[0010] The second aspect of the present application provides a manufacturing method of a thin film transistor-based capacitorless DRAM unit structure, comprising:

[0011] providing a semiconductor substrate;

[0012] forming a first isolation layer, a first electrode layer, a second isolation layer and a second electrode layer on the surface of the semiconductor substrate from bottom to top;

[0013] etching the first electrode layer, the second isolation layer and the second electrode layer so that the three layers are conformal, and the surface of the first isolation layer close to the two side edges is exposed;

[0014] forming a first channel layer, a first gate dielectric layer and a first gate electrode layer in sequence and conformally, wherein the first channel layer covers the side surface of the first electrode layer, the side surface of the second isolation layer, the upper surface and the side surface of the second electrode layer, and the remaining upper surface of the first isolation layer;

[0015] forming a third isolation layer and a third electrode layer on the upper surface of the first gate electrode layer in sequence;

[0016] etching the third isolation layer and the third electrode layer so that the upper surface of the first gate electrode layer close to the two side edges is exposed;

[0017] forming a second channel layer, a second gate dielectric layer and a second gate electrode layer in sequence and conformally, wherein the second channel layer covers the side surface of the second isolation layer, the upper surface and the side surface of the third electrode layer, and the exposed surface of the first channel layer.

[0018] Compared with the prior art, the present application achieves the following technical effects:

[0019] (1) The double-layer transistor vertical stacking technology is used instead of the same plane spreading technology, and the vertical channel is used instead of the traditional horizontal channel, so that the unit area can be saved, and the integration density of the circuit can be improved;

[0020] (2) At the same time, the gate of the lower layer transistor is used as the drain of the upper layer transistor, which can further reduce the area of the storage unit and minimize the vertical height occupied. BRIEF DESCRIPTION OF DRAWINGS

[0021] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments and are not intended to limit the scope of the application.

[0022] Figure 1 Structure diagram of a prior art double-transistor capacitorless dynamic random access memory (2T0C DRAM);

[0023] Figure 2 Structure diagram of a capacitorless DRAM unit provided by the present application;

[0024] Figure 3 Structure diagram of a capacitorless DRAM unit provided by the present application; Figure 2 Structure diagram of a capacitorless DRAM unit provided by the present application;

[0025] Figures 4 to 17 Structure diagram of a capacitorless DRAM unit provided by the present application; DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known functions and constructions are omitted to avoid obscuring the concept of the present disclosure in unnecessary detail.

[0027] In the drawings, various structure diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity and others are omitted. The shapes and relative sizes of the various regions, layers, and elements illustrated in the drawings are exemplary only and can vary depending on the manufacturing technology or design criteria. The skilled person can design regions / layers with different shapes, sizes, and relative positions according to the actual needs.

[0028] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, it can be directly on the other layer / element, or there can be an intervening layer / element between them. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0029] The prior art 2T0C DRAM unit generally uses 2 horizontal channel TFTs to be connected in the same plane, which occupies a large area and is not conducive to improving the integration density.

[0030] To this end, the present application provides a thin-film transistor based capacitorless DRAM cell structure as shown in Figure 1 The structure can be functionally divided into three parts from bottom to top: substrate, first layer transistor and second layer transistor, as follows.

[0031] The substrate 101 can be any substrate known to those skilled in the art for carrying the components of a semiconductor integrated circuit, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, germanium silicon, gallium arsenide or germanium-on-insulator, etc., with the corresponding top semiconductor material being silicon, germanium, germanium silicon or gallium arsenide, etc. The substrate 101 is formed with a first isolation layer 102, which can be made of high-k dielectric materials such as typical silicon oxide, silicon oxynitride, etc.

[0032] Above the first isolation layer 102 is the first layer transistor, which adopts a vertically stacked structure including, from bottom to top, a first electrode layer 103, a second isolation layer 104, a second electrode layer 105, a first channel layer 106, a first gate dielectric layer 107 and a first gate layer 108. Among them, the first electrode layer 103, the second isolation layer 104 and the second electrode layer 105 are conformal and cover only the surface of the central part of the first isolation layer 102, the first channel layer 106 covers the side surface of the first electrode layer 103, the side surface of the second isolation layer 104, the upper surface and side surface of the second electrode layer 105, and the remaining upper surface of the first isolation layer 102; the first channel layer 106, the first gate dielectric layer 107 and the first gate layer 108 are conformal.

[0033] In the first layer transistor, the first electrode layer 103 serves as the source, and the second electrode layer 105 serves as the drain. At the same time, the first channel layer 106 surrounds the first electrode layer 103, the second isolation layer 104 and the second electrode layer 105, thereby forming a vertical channel between the first electrode layer 103 and the second electrode layer 105. In this way, the source, drain, channel and gate of the first layer transistor are vertically stacked to realize the function of the read tube. In addition, the first gate layer 108 in the first layer transistor is also the drain of the second layer transistor above, i.e., the first layer transistor and the second layer transistor share an electrode.

[0034] The second-layer transistor comprises, from bottom to top, vertically stacked elements: a third isolation layer 109, a third electrode layer 110, a second channel layer 111, a second gate dielectric layer 112, and a second gate layer 113. The third isolation layer 109 covers the top surface of the first gate layer 108, and the second channel layer 111 covers the side surfaces of the third isolation layer 109, the side surfaces of the third electrode layer 110, and the top surface. The second channel layer 111, the second gate dielectric layer 112, and the second gate layer 113 are conformally oriented. The third electrode layer 110 serves as the source of the second-layer transistor, thus enabling the second-layer transistor to possess a source, a drain (i.e., the gate of the first-layer transistor), and a gate, thereby achieving a write transistor function.

[0035] Between the first and second transistor layers, the first gate layer 108 and the first channel layer 106 are conformally oriented and both have a boss-shaped structure. This results in blank areas on both sides of the first gate layer before the second transistor layer is formed. In order to reduce raw material costs and simplify the process, these blank areas are preferably not filled by the second channel layer, that is, the side surface of the first gate layer is not covered by the second channel layer, but is preferably covered by an insulating material 109a such as silicon oxide. This insulating material can be formed simultaneously with the third isolation layer 109, that is, the same material is used.

[0036] like Figure 1 The DRAM cell structure shown has the following two prominent features:

[0037] First, the vertical stacking of dual-layer transistors and zero-capacitance connection solves the problem of large area occupation of planar channel 2T0C DRAM cells and improves integration density.

[0038] Secondly, the first-layer transistor and the second-layer transistor share a single electrode (the former is the drain and the latter is the gate), which saves space for one electrode layer and is more conducive to the miniaturization of integrated circuits.

[0039] The working principle of the DRAM cell structure described above in this invention is as follows: Figure 3 As shown (the positions of the transistors in the figure are only for illustrative purposes and do not represent the actual layout), the first layer of transistors acts as the read transistor, and the second layer of transistors acts as the write transistor. The gate of the former and the drain of the latter are on the same electrode. By changing the charge in the gate capacitance of the read transistor through the write transistor, the resistance state between the source and drain of the read transistor is affected, thereby realizing the distinction between "0" and "1". The specific principle is as follows.

[0040] During the writing "1" process, a positive voltage (greater than the threshold voltage Vth) is applied to the gate electrode of the read transistor (i.e., the write word line WWL) to turn on the write transistor, and a positive voltage is applied to the source electrode of the write transistor (i.e., the write bit line WBL) to inject charge into the gate capacitor of the read transistor (i.e., the memory node). After charge injection, the gate and source voltages of the write transistor are removed, and the "1" state is preserved.

[0041] Read "1" process, read the drain electrode plus read voltage, due to the gate capacitor in a certain charge, read the tube in a lower resistance state, get a larger current, and then by peripheral circuit amplification identification after the completion of the read "1" process;

[0042] Write "0" process, read the gate electrode (i.e. write word line WWL) plus positive voltage (greater than threshold voltage Vth) so that the write tube open, write the source electrode (i.e. write bit line WBL) plus negative voltage to read the gate capacitor (i.e. storage node) extraction charge. Charge extraction after removing the gate and source voltage of the write tube, save "0" state;

[0043] Read "0" process, read the drain electrode plus read voltage, due to the gate capacitor in no charge, read the tube in a higher resistance state, get a smaller current, and then by peripheral circuit amplification identification after the completion of the read "0" process.

[0044] The above unit structure in the material selection, each layer can use any material to achieve its basic function, but in order to further improve the electrical performance and use effect of the memory, each layer has its preferred material.

[0045] For example, the first channel layer 106 and the second channel layer 111 can each independently preferably use IGZO material. IGZO thin film transistor has very low off-state leakage, so the information of the storage node can be maintained for a long time.

[0046] The first gate dielectric layer 107 and the second gate dielectric layer 112 play an insulating role between the gate and the channel. Preferably, materials with wide band gap and high dielectric constant, or materials suitable for making extremely small devices, such as HfO2, are selected.

[0047] The first electrode layer 103, the second electrode layer 105, the third electrode layer 110, the first gate layer 108 and the second gate layer 113 are electrodes to be connected to the power supply. Preferably, they are made of metal materials or doped semiconductor materials with good conductivity. Considering the low temperature processing technology of the present application, metal materials are preferred, which can be formed by sputtering. Common metal materials with good performance include but are not limited to Mo, Ti or W. In addition, considering the speed and stability of current transmission between electrodes, the first electrode layer 103, the second electrode layer 105, the third electrode layer 110, the first gate layer 108 and the second gate layer 113 preferably use the same material or materials with very close performance.

[0048] The first isolation layer 102, the second isolation layer 104 and the third isolation layer 109 for isolating the three functional areas preferably use silicon oxide, which is easy to deposit in large area.

[0049] This invention also provides a method for manufacturing the above-mentioned capacitor-free DRAM cell structure based on thin-film transistors. This method features low-temperature 3D integration processing, which can reduce quality defects caused by high-temperature processing. Figures 4 to 17 The specific process is as follows.

[0050] First, in such Figure 4 A first isolation layer 102 is formed on the surface of the semiconductor substrate 101 shown, resulting in the following: Figure 5 The structure is shown. As mentioned above, the first isolation layer 102 is preferably made of silicon oxide, which can be deposited by in-situ oxidation, PECVD, ALCVD and other deposition methods.

[0051] Next, metal or other electrode material layers are sputtered onto the surface of the first isolation layer 102 to serve as the first electrode layer 103, such as... Figure 6 As shown, this is the source of the first-layer transistor. Sputtering can be achieved at low temperatures.

[0052] Then a second isolation layer 104 is formed, such as Figure 7 As shown. Taking silicon oxide as an example, it can be deposited using methods such as oxidation, PECVD, and ALCVD.

[0053] Then a second electrode layer 105 is formed to serve as the drain of the first-layer transistor, such as Figure 8 As shown. Taking metallic Mo as an example, it can be achieved by sputtering, which meets the requirements of low-temperature processing. Compared with traditional doped semiconductor materials, this invention does not require high-temperature annealing.

[0054] Next, the first electrode layer 103, the second isolation layer 104, and the second electrode layer 105 are patterned using photolithography and etching. This exposes the surfaces of the first isolation layer 102 near its two edges, leaving space for the first channel layer, and simultaneously forming a vertically stacked structure of electrode / isolation / electrode, resulting in... Figure 9 The structure shown is then finalized by removing the photoresist.

[0055] Then, the first channel layer 106 is formed. Taking IGZO as an example, it is preferably formed using methods such as PVD, ALD, and CVD to obtain the desired result. Figure 10 The structure shown.

[0056] exist Figure 10 On this basis, a first gate dielectric layer 107 is deposited to obtain the following: Figure 11 The structure is shown. Taking HfO2 as an example, it was deposited using the ALD method.

[0057] Then the first gate layer 108 is formed, such as Figure 12As shown, the first gate layer 108 is conformally oriented with the first gate dielectric layer 107 and the first channel layer 106, and all surround the first electrode layer 103, the second isolation layer 104 and the second electrode layer 105. The gate layer is preferably made of a metal material such as Mo and is formed by sputtering.

[0058] A thicker third isolation layer 109 is then formed, preferably thick enough to cover all outer surfaces of the first gate layer 108, such as... Figure 13 As shown.

[0059] Based on the above, a third electrode layer 110 is sputtered as the source of the second-layer transistor, such as... Figure 14 As shown, metallic materials are preferred.

[0060] Next, the third electrode layer 110 and the third isolation layer 109 are patterned using photolithography and etching, exposing the upper surface of the first gate layer 108 near its two side edges to create space for the second channel layer. This forms a vertically stacked transistor structure of electrode / isolation / electrode. Meanwhile, in this structure, a portion of the isolation layer material 109a is still retained on the side surface of the first gate layer 108. Figure 15 As shown.

[0061] Then, the second channel layer 111 is formed. Taking IGZO as an example, it is preferably formed using methods such as PVD, ALD, and CVD to obtain the desired result. Figure 16 The structure shown.

[0062] exist Figure 16 On top of this, a second gate dielectric layer 112 is deposited to obtain the following: Figure 17 The structure is shown. Taking HfO2 as an example, it is deposited using the ALD method.

[0063] Then a second gate layer 113 is formed, such as Figure 2 As shown, the second gate layer is conformally formed with the second gate dielectric layer and the second channel layer, and surrounds the second electrode layer and the third isolation layer. The gate layer is preferably made of a metal material such as Mo and is formed by sputtering.

[0064] Finally, necessary follow-up processes are performed, such as electrode extraction and encapsulation.

[0065] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A capacitor-free DRAM cell structure based on thin-film transistors, characterized in that, It includes, from bottom to top, the following layers stacked in sequence: semiconductor substrate, first isolation layer, first electrode layer, second isolation layer, second electrode layer, first channel layer, first gate dielectric layer, first gate layer, third isolation layer, third electrode layer, second channel layer, second gate dielectric layer, and second gate layer; In this configuration, the first electrode layer, the second isolation layer, and the second electrode layer are conformally oriented and only cover the surface of the central portion of the first isolation layer; the first channel layer covers the side surface of the first electrode layer, the side surface of the second isolation layer, the upper surface and side surface of the second electrode layer, and the remaining upper surface of the first isolation layer; the first channel layer, the first gate dielectric layer, and the first gate layer are conformally oriented; the second channel layer covers the side surface of the third isolation layer, the side surface of the third electrode layer, and the upper surface; the second channel layer, the second gate dielectric layer, and the second gate layer are conformally oriented. The first isolation layer, the second isolation layer, and the third isolation layer are all insulating materials.

2. The capacitor-free DRAM cell structure according to claim 1, characterized in that, The first trench layer and / or the second trench layer are made of IGZO material.

3. The capacitor-free DRAM cell structure according to claim 1, characterized in that, The first gate dielectric layer and / or the second gate dielectric layer are made of HfO2.

4. The capacitor-free DRAM cell structure according to claim 1, characterized in that, The first electrode layer, the second electrode layer, the third electrode layer, the first gate layer, and the second gate layer all use the same electrode material.

5. The capacitor-free DRAM cell structure according to claim 4, characterized in that, The electrode material is selected from Mo, Ti, or W.

6. The capacitor-free DRAM cell structure according to claim 1, characterized in that, The first, second, and third isolation layers are made of silicon oxide.

7. The capacitor-free DRAM cell structure according to any one of claims 1-5, characterized in that, The first electrode layer, the second isolation layer, the second electrode layer, and the third electrode layer are projected at the same position on the semiconductor substrate.

8. The capacitor-free DRAM cell structure according to claim 7, characterized in that, The side surface of the first gate layer is not covered by the second channel layer.

9. The capacitor-free DRAM cell structure according to claim 8, characterized in that, The side surface of the first gate layer is covered with silicon oxide or with the same material as the third isolation layer.

10. A method for manufacturing a capacitor-free DRAM cell structure based on thin-film transistors, characterized in that, include: Provide semiconductor substrates; A first isolation layer, a first electrode layer, a second isolation layer, and a second electrode layer are formed sequentially from bottom to top on the surface of the semiconductor substrate; The first electrode layer, the second isolation layer, and the second electrode layer are etched to make the three layers conformal, and the surface of the first isolation layer near the two side edges is exposed. A first channel layer, a first gate dielectric layer, and a first gate layer are conformally formed in sequence. The first channel layer covers the side surface of the first electrode layer, the side surface of the second isolation layer, the upper surface and side surface of the second electrode layer, and the remaining upper surface of the first isolation layer. A third isolation layer and a third electrode layer are sequentially formed on the upper surface of the first gate layer; The third isolation layer and the third electrode layer are etched to expose the upper surface of the top of the first gate layer near the two side edges; A second channel layer, a second gate dielectric layer, and a second gate layer are conformally formed in sequence. The second channel layer covers the side surface of the second isolation layer, the upper surface and side surface of the third electrode layer, and the exposed surface of the first channel layer.

11. The manufacturing method according to claim 10, characterized in that, The etching step involved in the manufacturing method employs photolithography and etching processes.

12. The manufacturing method according to claim 10, characterized in that, The first isolation layer, the second isolation layer, and the third isolation layer are formed using the PECVD method.

13. The manufacturing method according to claim 10, characterized in that, The first gate dielectric layer and the second gate dielectric layer are formed using the ALD method.

14. The manufacturing method according to claim 10, characterized in that, The first electrode layer, the second electrode layer, the third electrode layer, the first gate layer, and the second gate layer are formed by sputtering.

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