NAND flash memory and method for manufacturing the same
By forming grooves between the channel stacks and filling the insulator stacks to form a vertical gate, the problems of deterioration of vertical gate etching accuracy and poor insulation or short circuit in the prior art are solved, and higher processing accuracy and insulation stability are achieved.
Patent Information
- Application Number
- CN202111041855.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-10-09
- Filing Date
- 2021-09-07
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2041-09-07
AI Technical Summary
When the NAND flash memory with a conventional three-dimensional structure forms a vertical gate, there is a risk of deterioration in etching accuracy and poor insulation or short circuit, especially when there is a depression in the etching surface of the multi-layer active region.
By forming grooves between the channel stacks, the insulator stack is filled and thus the space is filled to form a vertical gate, direct etching of the vertical gate is avoided, etching accuracy is improved, and short circuits are prevented.
Short circuits between gates extending in the vertical direction are effectively prevented, processing accuracy of the vertical gates is improved, and stability of the insulating layer is enhanced.
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Figure CN114334997B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a NAND (Not AND) type flash memory, and more particularly to a three-dimensional NAND type flash memory and a method for manufacturing the same. Background Art
[0002] In recent years, in order to improve the integration degree of memory cells, a three-dimensional NAND type flash memory in which memory cell arrays are stacked in a direction perpendicular to the substrate surface has been put into practical use. A three-dimensional NAND flash memory using a vertical gate structure has been proposed in Non-Patent Document 1. Figure 1 FIG. (a) shows a perspective view of the three-dimensional structure of the memory cell array, Figure 1 and FIG. (b) shows a plan view thereof. Figure 2 is Figure 1 the equivalent circuit of the memory cell array of FIG. (a).
[0003] At the bottom of the memory cell array, a plurality of bit lines BL extending horizontally in the column direction are formed. In the row direction orthogonal thereto, a plurality of word lines WL, a plurality of select gate lines SSL, GSL, and a common source line CSL extending horizontally are formed. A plurality of long strip-shaped multi-active layers are formed on these bit lines BL, word lines WL, select gate lines SSL, and select gate lines GSL. One multi-active layer is a stacked structure of active regions of a plurality of polysilicon layers and an interlayer dielectric (ILD) formed between each of the plurality of active regions, and each multi-active layer extends in the column direction. In the space between the multi-active layers, a plurality of vertical gates separated in the column direction are formed. Each of the plurality of vertical gates is allocated from the word line WL, the select gate line SSL, and the select gate line GSL. In addition, a bit line vertically allocated from the bit line BL is connected to one end of the multi-active layer, and a source line vertically allocated from the common source line CSL is connected to the other end of the multi-active layer. One active region in the horizontal direction of the multi-active layer provides a channel for one NAND string.
[0004] Figure 3 represents for forming Figure 1Process steps of the memory cell array in (a). In the initial step of (1), bit lines BL extending in the column direction, word lines WL, select gate lines SSL, select gate lines GSL, and common source lines CSL extending in the row direction are formed on a substrate. However, these processes can be changed to subsequent steps. In the step of (2), a stack of a polysilicon layer and an insulating layer is deposited on the substrate, and the stack of the polysilicon layer and the insulating layer is etched to form strip-shaped multi-layer active regions extending in the column direction. In the step of (3), a stack of insulators is deposited in the space between the multi-layer active regions. The stack of insulators includes at least three layers, and the middle layer stores charges. In the step of (4), a low-resistance gate material is deposited in the space between the multi-layer active regions stacked with insulators. Thus, the space between the multi-layer active regions is filled with the stack of insulators and the gate material. Moreover, the gate material is patterned to form a plurality of vertical gates separated in the column direction. In the step of (5), vertical plugs connected to the bit line BL and the source line CSL are formed.
[0005] [Prior Art Documents]
[0006] [Non-Patent Documents]
[0007] [Non-Patent Document 1] Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage, Wonjoo Kim et al., Symposium on VLSI Technology Digest of Technical Papers, 2009, P188-189 Summary of the Invention
[0008] As Figure 1 in (a) to Figure 3 The three-dimensional NAND flash memory with the vertical gate structure shown has the following problems. Figure 4 (A) of is a perspective view showing a schematic structure of a vertical gate and a multi-layer active region, Figure 4 (B) of is Figure 4Cross-sectional view in the direction of line A-A of (A). The patterning of the elongated multi-layer active region 10 including the polysilicon layer 12 and the insulating layer 14 is performed, for example, by anisotropic dry etching. The polysilicon layer 12 provides a channel, and the insulating layer 14 insulates between the stacked polysilicon layers 12. The etched surface of the patterned multi-layer active region 10 in the vertical direction is not necessarily a straight line. For example, if the etching rate of the insulating layer 14 in the horizontal direction of the multi-layer active region 10 is faster than that of the polysilicon layer 12, the etched surface of the insulating layer 14 is slightly recessed compared to the etched surface of the polysilicon layer 12. After the patterning of the multi-layer active region 10, an insulator 22 including a charge storage layer is deposited over the entire surface, and then a gate material is deposited over the entire surface. Thereafter, the gate material is patterned to form the vertical gate 20. The patterning of the gate material is performed by anisotropic dry etching, but as Figure 4 shown in (B), if there is a depression in the etched surface of the multi-layer active region 10, the film thickness of the gate material is not necessarily uniform, and it is difficult to etch the vertical gate with high precision. In addition, if etching is performed for a time corresponding to the thick part of the film thickness of the gate material, the insulating layer 14 of the multi-layer active region 10 is further over-etched in the horizontal direction, and there is a concern of insulation failure or short circuit between the vertical gates 20 facing each other on both sides of the multi-layer active region 10. Furthermore, there is a concern that the deterioration of the etching accuracy of the vertical gate 20 causes a short circuit between the adjacent vertical gates 20 in the extending direction (the direction orthogonal to the line A-A) of the multi-layer active region 10.
[0009] An object of the present invention is to solve such a conventional problem and provide a NAND flash memory capable of preventing a short circuit between gates extending in the vertical direction and a manufacturing method thereof.
[0010] The manufacturing method of the NAND flash memory of the present invention includes: a step of forming a plurality of channel stacks in which a first insulating layer and a channel layer are alternately stacked on a substrate, the channel stack having a first side surface and a second side surface opposite to the first side surface, and the first side surface and the second side surface extending in a first direction; a step of forming a second insulating layer between the first side surface and the second side surface of each of the plurality of channel stacks; a step of forming a plurality of grooves at a fixed pitch in the first direction of the second insulating layer; a step of forming an insulator including a charge storage layer so as to cover at least the inner walls of the respective grooves; and a step of forming a plurality of gates extending in the second direction so as to fill the spaces in the respective grooves in a second direction orthogonal to the first direction.
[0011] The NAND flash memory of the present invention includes: a substrate; a plurality of channel stacks formed on the substrate, the channel stacks having a first side surface and a second side surface opposite to the first side surface, the first side surface and the second side surface extending in a first direction; an insulating layer formed between the first side surfaces and the second side surfaces of adjacent channel stacks; a plurality of grooves formed at a fixed pitch in the first direction of the insulating layer; an insulator including a charge storage layer formed so as to cover at least the side walls of each groove; and a plurality of gates extending in the second direction so as to fill the space in each groove in a second direction orthogonal to the first direction.
[0012] According to the present invention, since the gates are formed in the spaces in the grooves formed between the channel stacks, short circuits between adjacent gates can be prevented in the first direction and the second direction. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 FIG. (a) is a perspective view showing the structure of a conventional three-dimensional storage cell array; Figure 1 FIG. (b) is a top view thereof;
[0014] Figure 2 is Figure 1 the equivalent circuit of the storage cell array shown in FIG. (a);
[0015] Figure 3 is for explaining Figure 1 a schematic cross-sectional view of the manufacturing process of the storage cell array shown in FIG. (a);
[0016] Figure 4 FIGS. (A) and Figure 4 FIG. (B) are diagrams for explaining problems of a conventional three-dimensional flash memory; Figure 4 FIG. (A) is a perspective view showing the connection relationship between a vertical gate and a multi-layer active region; Figure 4 FIG. (B) is a cross-sectional view taken along line A-A of FIG. (A); Figure 4 when cutting along line A-A of FIG. (A);
[0017] Figure 5 is a plan view of a three-dimensional NAND flash memory according to an embodiment of the present invention.
[0018] Figure 6A is Figure 5 a cross-sectional view taken along line A1-A1;
[0019] Figure 6B is Figure 5 a cross-sectional view taken along line A2-A2;
[0020] Figure 7 is Figure 5 a cross-sectional view taken along line B-B;
[0021] Figures 8A - 8C It is a diagram showing the manufacturing steps of a three-dimensional structure NAND flash memory according to an embodiment of the present invention;
[0022] Figure 9A (A) of is a plan view of a mask for forming a trench, Figure 9A and (B) of is a plan view when a mask is formed on a channel stack;
[0023] Figure 9B (A) of is a plan view when a trench has been formed, Figure 9B and (B) of is a cross-sectional view taken along the C-C line thereof;
[0024] Figure 9C (A) of is a plan view of a D-D line cross-section when an insulator stack including a charge storage layer has been formed, Figure 9C and (B) of is a cross-sectional view corresponding to the C-C line;
[0025] Figure 9D (A) of is a plan view of a D-D line cross-section when a gate material has been deposited, Figure 9D and (B) of is a cross-sectional view corresponding to the C-C line.
[0026] [Description of Symbols]
[0027] 10: Multi-layer active region
[0028] 12, 122, 122A, 122B: Polysilicon layer
[0029] 14, 124, 124A, 124B, 170, ILD: Insulating layer
[0030] 20, 130: Vertical gate
[0031] 22: Insulator
[0032] 100: Substrate
[0033] 110: Lower insulating layer
[0034] 120: Channel stack
[0035] 140: Interlayer insulating film
[0036] 150: Bit line
[0037] 152, 162: Contact hole
[0038] 154, 164: Conductive plug
[0039] 160, CSL: Common source line
[0040] 180: Trench
[0041] 190: Insulator stack
[0042] 200: Etching mask (mask pattern)
[0043] 210: Opening
[0044] BL: Bit line
[0045] GSL, SSL: Select gate line
[0046] S1: First side
[0047] S2: Second side
[0048] WL: Word line Detailed implementation mode
[0049] The three-dimensional structure NAND type flash memory of the present invention is used as a storage medium in various semiconductor devices (for example, a microcontroller, a microprocessor, a logic device, etc. in which such a flash memory is embedded).
[0050] Subsequently, embodiments of the present invention will be described with reference to the accompanying drawings. The dimensions of the accompanying drawings are exaggerated for easy understanding of the invention, and it should be noted that they do not necessarily represent the dimensions of actual products.
[0051] Please refer to Figure 5 、 Figure 6A 、 Figure 6B And Figure 7 , the NAND type flash memory of this embodiment includes: a substrate 100; a lower insulating layer 110 formed on the substrate 100; a plurality of channel stacks 120 formed on the lower insulating layer 110 and extending in the X direction; a plurality of vertical gates 130 extending vertically in a manner covering the sides of the plurality of channel stacks 120 and extending in the Y direction on the plurality of channel stacks 120; a plurality of bit lines 150 electrically connected to one end of each channel stack 120 and extending in the X direction; and a common source line 160 electrically connected to the other end of each channel stack 120 in a common manner and extending in the Y direction.
[0052] The substrate 100 is not particularly limited, for example, it is a silicon substrate. The lower insulating layer 110 is not particularly limited, for example, it is silicon oxide or silicon nitride.
[0053] A channel stack 120 has a first side surface S1 extending in a vertical direction from a substrate 100 and a second side surface S2 opposite to the first side surface S1, and the first side surface S1 and the second side surface S2 extend in the X direction. A channel stack 120 is fin-shaped or sheet-shaped, and has a rectangular shape or an elongated shape in a planar shape viewed from the Y direction. The channel stack 120 is a structure in which a polysilicon layer 122 serving as a channel layer providing a channel region and an insulating layer 124 are alternately stacked, and a plurality of such channel stacks 120 are arranged at a fixed pitch in the Y direction.
[0054] An insulating layer 170 is formed between the plurality of channel stacks 120, and a plurality of grooves 180 are formed in the insulating layer 170 to reach the lower insulating layer 110. That is, the grooves 180 are formed at a fixed pitch in the X direction of the insulating layer 170 so as to expose the first side surface S1 and the second side surface S2 of the adjacent channel stacks 120. Therefore, the respective grooves 180 are also arranged in the Y direction. In Figure 6A the example, the planar shape of one groove 180 is a rectangular shape.
[0055] In each groove 180, an insulator stack 190 is formed so as to cover the bottom surface and the side surfaces of the groove 180. The insulator stack 190 covers the first side surface S1 and the second side surface S2 of the channel stack 120 exposed in the groove 180. The insulator stack 190 is a structure in which three or more insulating layers including a charge storage layer are stacked. The insulator stack 190 includes, for example, an oxide layer / nitride layer / oxide layer (ONO), and the nitride layer accumulates charges at the interface with the oxide layer. Alternatively, the insulator stack 190 includes a conductive polysilicon layer in the center instead of the nitride layer, and the polysilicon layer accumulates charges. The charge storage layer can accumulate negative or positive charges generated by a programming operation or an erasing operation. The film thickness of the insulator stack 190 is smaller than the dimensions of the groove 180 in the X direction and the Y direction, and after the insulator stack 190 is formed, a space surrounded by the insulator stack 190 is formed in the groove 180.
[0056] A plurality of vertical gates 130 are formed so as to cover the grooves 180 in a direction intersecting with the plurality of channel stacks 120, that is, in the Y direction. The vertical gates 130 fill the space remaining by the insulator stack 190 in the groove 180. Therefore, the vertical gates 130 extend in a vertical direction from the substrate in the groove 180, and extend in the vertical direction along the first side surface S1 and the second side surface S2 of the channel stack 120 with the insulator stack 190 interposed therebetween. Each of the plurality of vertical gates 130 constitutes a selection gate line, a word line of a plurality of bit line side selection transistors, memory cells, and source line side selection transistors of a NAND string.
[0057] An interlayer insulating film 140 is formed on a plurality of channel stacks 120. On the interlayer insulating film 140, a common source line 160 extending in the Y direction is formed. The common source line 160 includes a conductive material such as metal, for example. At positions where the common source line 160 intersects with each channel stack 120, as Figure 5 , Figure 7 shown, an interlayer insulating film 140, an insulator stack 190, and a contact hole 162 penetrating from the uppermost insulating layer 124A to the lowermost insulating layer 124B of the channel stack 120 are formed, and a conductive plug 164 is filled in the contact hole 162. Thus, the common source line 160 is electrically connected in common to the other end portions of the channel stack 120 from the uppermost polysilicon layer 122A to the lowermost polysilicon layer 122B via the conductive plug 164.
[0058] The interlayer insulating film 140 is further formed to cover the common source line 160. On the interlayer insulating film 140, a plurality of bit lines 150 extending in the X direction are formed. The bit lines 150 include a conductive material such as metal, for example, and each bit line 150 is patterned so as to extend directly above the plurality of channel stacks 120 in parallel with the channel stacks 120. At positions at the ends of the respective bit lines 150, as Figure 5 , Figure 7 shown, an interlayer insulating film 140, an insulator stack 190, and a contact hole 152 penetrating from the uppermost insulating layer 124A to the lowermost insulating layer 124B of the channel stack 120 are formed, and a conductive plug 154 is filled in each contact hole 152. Thus, each bit line 150 is electrically connected to one of the end portions of the channel stack 120 from the uppermost polysilicon layer 122A to the lowermost polysilicon layer 122B via each conductive plug 154.
[0059] One or more vertical gates 130 adjacent to the contact holes 152 on the bit line side constitute the select gate lines of one or more bit line side select transistors of the NAND string, one or more vertical gates 130 adjacent to the common source line 160 constitute the select gate lines of one or more source line side select transistors of the NAND string, and the remaining plurality of vertical gates 130 constitute the word lines of the plurality of memory cells.
[0060] In a NAND flash memory, a read operation or a program operation is performed in units of pages, and an erase operation is performed in units of blocks. One polysilicon layer 122 in the X direction of one channel stack 120 corresponds to one NAND string. Therefore, the number of NAND strings corresponding to the number of stacked layers of the polysilicon layer 122 is formed in one channel stack 120. In addition, selection of one NAND string is performed by selectively driving a plurality of bit line side selection transistors. Selection of a page or a block is well known, and thus detailed description thereof is omitted here.
[0061] Next, a method for manufacturing a three-dimensional structure NAND flash memory according to the present embodiment will be described. Figures 8A - 8C Indicates Figure 5 The manufacturing steps of the A1-A1 line profile corresponding to. As Figure 8A shown, a lower insulating layer 110 is formed on a silicon substrate 100, and a precursor of a channel stack in which a polysilicon layer 122 and an insulating layer 124 are alternately stacked is formed on the lower insulating layer 110. Next, the precursor is patterned by anisotropic etching to form a plurality of channel stacks 120 in a sheet shape or a fin shape. The first side surface S1 and the second side surface S2 of each channel stack 120 extend in the X direction.
[0062] Next, as Figure 8B shown, an insulating layer 170 is entirely deposited so as to fill the space between the channel stacks 120. The material or deposition method of the insulating layer 170 is not particularly limited, and a material or method having excellent step coverage such as covering the step difference of the channel stack 120 is selected.
[0063] Next, as Figure 8C shown, the insulating layer 170 is etched until the uppermost insulating layer 124A of the channel stack 120 is exposed. The etching step may also include planarization of the insulating layer 124A and the insulating layer 170.
[0064] Refer to Figure 9A of (A) to Figure 9D The following steps will be described. Figure 9A (A) of is a plan view of an etching mask for forming a groove in the insulating layer 170. The etching mask 200 has a plurality of openings 210 formed at fixed intervals in the X direction, and each opening 210 extends in the Y direction. Figure 9A (B) of is a plan view when the etching mask 200 is formed after the step of Figure 8C .
[0065] When the mask pattern 200 is formed on the upper surfaces of the channel stacks 120 and the insulating layer 170, an opening 210 extending in the Y direction exposes the insulating layer 170 between the insulating layers 124A of each channel stack 120 as shown. The opening 210 positions the groove 180 formed in the insulating layer 170.
[0066] Subsequently, anisotropic etching is performed through the etching mask 200. Here, in order for the insulating layer 124A of the channel stack 120 to also function as an etching mask, an etchant with a large etch selectivity between the insulating layer 170 and the insulating layer 124A is used. The etching is performed until the lower insulating layer 110 is exposed. Through this etching, a part of the insulating layer 170 exposed through the opening 210 is removed, and the groove 180 is formed here. In addition, the etching mask 200 is not necessarily limited to Figure 9A the structure shown in (A) of Figure 9A and (B) of
[0067] Figure 9B (A) is a plan view after removing the etching mask 200, Figure 9B (B) is a cross-sectional view taken along the C-C line thereof. As shown, in the Y direction of adjacent channel stacks 120, grooves 180 exposing the first side surface S1 and the second side surface S2 are formed. In the internal space of the groove 180, an insulator stack 190 or a vertical gate 130 is filled as described later. The dimensions of the groove 180 in the X direction and the Y direction are appropriately selected corresponding to the pitch in the Y direction of the channel stacks 120.
[0068] Subsequently, on the entire surface of the substrate including the groove 180, an insulator stack 190 including at least three or more layers including a charge storage layer is deposited. Figure 9C (A) of Figure 9C is a plan view of the cross-section taken along the D-D line of Figure 9C (B) of Figure 9B and (B) of
[0069] Subsequently, a low-resistance gate material (e.g., conductive polysilicon) is formed over the entire surface of the substrate including the groove 180. Thereafter, the gate material is patterned so as to extend over the groove 180 in the Y direction, thereby forming the vertical gate 130. Figure 9D (A) of Figure 9D is a plan view of the D-D line cross-section of (B) of Figure 9D (B) of Figure 9B is a cross-sectional view taken along the C-C line of (A) of . The vertical gate 130 extends vertically within the groove 180 and is surrounded by the insulator stack 190. One side surface of the vertical gate 130 faces the first side surface S1 of the channel stack 120 with the insulator stack 190 interposed therebetween, and the other side surface faces the second side surface S2 of the adjacent channel stack 120.
[0070] After forming the vertical gate 130, an interlayer insulating film 140 is formed. Subsequently, after forming the contact hole 162, a conductive plug 164 is formed within the contact hole 162. Thereafter, a common source line 160 connected to the conductive plug 164 is formed. Subsequently, an interlayer insulating film 140 is formed so as to cover the common source line 160. Subsequently, after forming the contact hole 152, a conductive plug 154 is formed within the contact hole 152. Thereafter, a bit line 150 connected to the conductive plug 154 is formed. Thus, the process of the memory cell array is completed.
[0071] Thus, according to the present embodiment, since the groove for forming the vertical gate is formed in advance and the vertical gate is formed within the groove, etching for patterning the vertical gate facing the side surface of the channel stack is not required, and the processing accuracy of the vertical gate can be improved. Further, since the insulator stack is formed within the groove, the vertical gate is surrounded by the insulator stack within the groove, and thus short circuits between adjacent vertical gates can be prevented in the X direction and the Y direction.
[0072] In addition, in the above-described embodiment, the bit line 150 and the common source line 160 are formed after forming the channel stack 120, but it is not limited thereto. The bit line 150 and the common source line 160 may be buried in the lower insulating layer 110 before forming the channel stack 120. In this case, the conductive plug 154 for electrically connecting each bit line 150 to one end of the polysilicon layer of the channel stack 120 and the conductive plug 164 for electrically connecting the common source line 160 to the other end of the polysilicon layer of the channel stack 120 are filled into the contact holes 152 and 162 of the interlayer insulating film 140.
[0073] In addition, the memory cell may be a single layer cell (SLC) type for storing one bit (binary data), or may be a type for storing multiple bits.
[0074] Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments and can be variously modified and changed within the scope of the gist of the invention described in the claims.
Claims
1. A manufacturing method of a NAND flash memory, characterized in that, Comprising: The step of forming a plurality of channel stacks on a substrate, in which a first insulating layer and a channel layer are alternately stacked, wherein in this step, the channel stack has a first side surface and a second side surface opposite to the first side surface, and the first side surface and the second side surface extend along a first direction; The step of forming a second insulating layer between the first side surface and the second side surface of each of the plurality of channel stacks; The step of forming a plurality of grooves at a fixed pitch in the first direction of the second insulating layer; The step of forming an insulator containing a charge storage layer in such a manner as to cover at least the inner walls of the respective grooves, and the insulator covers the upper surface of the channel stack and the upper surface of the second insulating layer; And The step of forming a plurality of gates extending along the second direction in such a manner as to fill the spaces in the respective grooves in a second direction orthogonal to the first direction.
2. The manufacturing method according to claim 1, wherein, Wherein the gate extends vertically from the substrate in the groove and is surrounded by the insulator.
3. The manufacturing method according to claim 1 or 2, characterized in that, Wherein in the groove, the gate covers the first side surface and the second side surface of the adjacent channel stack with the insulator intervening therebetween.
4. The manufacturing method according to claim 1, characterized in that, Wherein the step of forming the groove exposes at least the first side surface and the second side surface of the channel stack from the uppermost channel layer to the lowermost channel layer.
5. The manufacturing method according to claim 1, characterized in that, Wherein the step of forming the groove removes a part of the second insulating layer formed between the plurality of channel stacks via an etching mask.
6. The manufacturing method according to claim 1, characterized in that, Wherein the manufacturing method further includes: the step of forming bit lines electrically connected to one end of each channel layer of the channel stack, and the step of forming source lines electrically connected to the other end of each channel layer of the channel stack.
7. The manufacturing method according to claim 6, characterized in that, Wherein the step of forming the bit line includes forming a first conductive plug in contact holes from the uppermost channel layer to the lowermost channel layer at one end of the channel stack, and the step of forming the source line includes forming a second conductive plug in contact holes from the uppermost channel layer to the lowermost channel layer at the other end of the channel stack.
8. The manufacturing method according to claim 1, characterized in that, Wherein the manufacturing method further includes: the step of forming a channel layer and a first insulating layer alternately stacked on the substrate; and The step of patterning the alternately stacked channel layer and first insulating layer by etching to form a plurality of fin-shaped channel stacks.
9. A NAND flash memory, characterized in that, Comprising: A substrate; A plurality of channel stacks formed on the substrate, the channel stack having a first side surface and a second side surface opposite to the first side surface, and the first side surface and the second side surface extend along a first direction; An insulating layer formed between the first side surface and the second side surface of adjacent channel stacks; A plurality of grooves formed at a fixed pitch in the first direction of the insulating layer; An insulator containing a charge storage layer formed in such a manner as to cover at least the side walls of the respective grooves, and the insulator covers the upper surface of the channel stack and the upper surface of the insulating layer; And A plurality of gates extending along the second direction in such a manner as to fill the spaces in the respective grooves in a second direction orthogonal to the first direction.
10. The NAND flash memory according to claim 9, characterized in that, Wherein the gate extends vertically from the substrate in the groove and is surrounded by the insulator.
11. The NAND flash memory according to claim 9 or 10, characterized in that, Wherein the gate is within the trench, separated by the insulator and covering the first side and the second side of the adjacent channel stack.
12. The NAND flash memory according to claim 9, characterized in that, Wherein the trench exposes at least from the uppermost channel layer to the lowermost channel layer of the first side and the second side of the channel stack.
13. The NAND flash memory according to claim 9, wherein The NAND flash memory further includes: a bit line electrically connected to an end of one side of each channel layer of the channel stack, and a source line electrically connected to an end of the other side of each channel layer of the channel stack.
14. The NAND flash memory according to claim 13, wherein Wherein the bit line is connected to a first conductive plug within a contact hole from the uppermost channel layer to the lowermost channel layer formed at an end of one side of the channel stack, and the source line is connected to a second conductive plug within a contact hole from the uppermost channel layer to the lowermost channel layer formed at an end of the other side of the channel stack.
Citation Information
Patent Citations
Semiconductor memory and manufacturing method thereof
JP2008078404A