Array substrate, display panel and display device

Abstract

The present disclosure relates to the technical field of display, and discloses an array substrate, a display panel and a display device. The array substrate comprises a first driving thin film transistor, a second driving thin film transistor and a connecting wire. The first driving thin film transistor comprises a first active layer, and the first active layer comprises a first channel region and first and second conductorization regions located at two ends of the first channel region. The second driving thin film transistor comprises a second active layer, and the second active layer comprises a second channel region and third and fourth conductorization regions located at two ends of the second channel region. The connecting wire extends from the third conductorization region to the first conductorization region, and opposite ends of the connecting wire are connected to the third and first conductorization regions. The array substrate reduces the area of the wiring region and improves the aperture ratio.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate, a display panel, and a display device. Background Technology

[0002] To increase the brightness of a display panel, it is necessary to ensure the aperture ratio of the display panel; to ensure the aperture ratio, it is necessary to reduce the opaque area of ​​the thin-film transistor; however, at present, there are great difficulties in reducing the opaque area of ​​the display panel to increase the aperture ratio.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art in having a low aperture ratio, and to provide an array substrate, display panel, and display device with a high aperture ratio.

[0005] According to one aspect of this disclosure, an array substrate is provided, comprising:

[0006] A first driving thin-film transistor includes a first active layer, the first active layer including: a first channel region, and a first conductive region and a second conductive region located at both ends of the first channel region;

[0007] The second driving thin film transistor is disposed on one side of the first driving thin film transistor. The second driving thin film transistor includes a second active layer, which includes a second channel region and a third conductive region and a fourth conductive region located at both ends of the second channel region.

[0008] A connecting wire extends from the third conductor region to the first conductor region, and its opposite ends are connected to the third conductor region and the first conductor region respectively.

[0009] In one exemplary embodiment of this disclosure, the connecting wire is an extension of the third conductor region extending toward the side of the first driving thin-film transistor.

[0010] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0011] A power line is disposed on the side of the first driving thin film transistor away from the second driving thin film transistor and extends along a first direction, and the first conductive region is connected to the power line.

[0012] The first driving thin-film transistor further includes: a first gate, a first source, and a first drain; the first conductive region overlaps with and is connected to the first drain; the first drain is connected to the power line; the second conductive region overlaps with and is connected to the first source; and the first channel region overlaps with the first gate.

[0013] The second driving thin-film transistor further includes: a second gate and a second source, the fourth conductive region overlaps with and is connected to the second source, and the second channel region overlaps with the second gate.

[0014] In one exemplary embodiment of this disclosure, the connecting wire is disposed in the same layer and made of the same material as the first gate.

[0015] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0016] Two data lines are arranged side by side between the first driving thin-film transistor and the second driving thin-film transistor, and extend along the first direction;

[0017] A first switching thin-film transistor and a second switching thin-film transistor, each comprising a third gate, a third active layer, a third source, and a third drain. The third active layer comprises a third channel region, and a fifth conductive region and a sixth conductive region located at both ends of the third channel region. The fifth conductive region overlaps with and is connected to the third source, and the sixth conductive region overlaps with and is connected to the third drain. The third source of the first switching thin-film transistor overlaps with and is connected to the first gate, and the third source of the second switching thin-film transistor overlaps with and is connected to the second gate. The two third drains are correspondingly connected to the two data lines.

[0018] A gate line is connected to the third gate, the gate line extending along a second direction that intersects the first direction.

[0019] In one exemplary embodiment of this disclosure, the gate line includes:

[0020] Multiple first parts are configured as a double-line structure and extend along a second direction;

[0021] Multiple second portions are configured as single-wire structures and extend along a second direction, with each second portion connected between two adjacent first portions, and the third gate being a part of the second portions.

[0022] In an exemplary embodiment of this disclosure, the first switching thin-film transistor is disposed on the first direction side of the first driving thin-film transistor, the second switching thin-film transistor is disposed on the first direction side of the second driving thin-film transistor, and the first switching thin-film transistor and the second switching thin-film transistor are located between the data line and the power line.

[0023] In one exemplary embodiment of this disclosure, the first gate includes:

[0024] The first gate body portion is disposed opposite to the first channel region;

[0025] A first gate extension is connected to the first gate body portion and is located on the side of the first gate body portion closer to the data line.

[0026] The second gate includes:

[0027] The second gate body portion is disposed opposite to the second channel region;

[0028] The second gate extension is connected to the second gate body and is located on the side of the second gate body closer to the data line.

[0029] In an exemplary embodiment of this disclosure, the extension direction of the third active layer intersects the extension direction of the gate line, the third source of the first switching thin film transistor overlaps and connects with the end of the first gate extension near the data line, and the third source of the second switching thin film transistor overlaps and connects with the end of the second gate extension near the data line.

[0030] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0031] A first detection thin-film transistor and a second detection thin-film transistor, the first detection thin-film transistor and the second detection thin-film transistor including a fourth gate, a fourth active layer, a fourth source and a fourth drain, the fourth active layer including a fourth channel region, and a seventh conductor region and an eighth conductor region located at both ends of the fourth channel region, the seventh conductor region overlapping and connected to the fourth source, the eighth conductor region overlapping and connected to the fourth drain, the first detection thin-film transistor being disposed on the side of the first driving thin-film transistor away from the first switching thin-film transistor, and the second detection thin-film transistor being disposed on the side of the second driving thin-film transistor away from the second switching thin-film transistor;

[0032] A reference voltage line is provided on the side of the second driving thin film transistor away from the first driving thin film transistor and extends along the first direction;

[0033] The sensing control signal line is located on the side of the first driving thin film transistor away from the first switching thin film transistor and extends along the second direction;

[0034] A reference connection wire is disposed on the side of the sensing control signal line away from the first driving thin film transistor, and the reference connection wire is connected to the reference voltage line;

[0035] Wherein, the fourth source of the first detection thin-film transistor is connected to the first source, the fourth source of the second detection thin-film transistor is connected to the second source, the fourth drain is connected to the reference voltage line through the reference connection wire, and the fourth gate is connected to the sensing control signal line.

[0036] In one exemplary embodiment of this disclosure, the sensing control signal line includes:

[0037] Multiple third parts are configured as a double-line structure and extend along the second direction;

[0038] Multiple fourth portions are configured as single-line structures and extend along a second direction, wherein the fourth portions are connected between two adjacent third portions, and the fourth gate is a part of the fourth portions.

[0039] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0040] A first light-shielding layer, a first driving thin-film transistor overlapping the first light-shielding layer, and the first light-shielding layer forming a capacitor with the first gate;

[0041] The second light-shielding layer overlaps with the second driving thin-film transistor, and the second light-shielding layer forms a capacitor with the second gate.

[0042] In one exemplary embodiment of this disclosure, the first light-shielding layer, the second light-shielding layer, and the reference connection wire are disposed in the same layer and made of the same material; the first active layer, the second active layer, the third active layer, and the fourth active layer are disposed in the same layer and made of the same material; the gate line, the sensing control signal line, the first gate, the second gate, the third gate, and the fourth gate are disposed in the same layer and made of the same material; the first source, the first drain, the second source, the third source, the third drain, the fourth source, the fourth drain, the data line, the power line, and the reference voltage line are disposed in the same layer and made of the same material.

[0043] According to another aspect of this disclosure, a display panel is provided, comprising: an array substrate as described in any one of the preceding claims.

[0044] According to another aspect of this disclosure, a display device is provided, comprising: the display panel described above.

[0045] In the array substrate disclosed herein, connecting wires extend from a third conductive region to a first conductive region, with the opposite ends of the connecting wires corresponding to the third conductive region and the first conductive region. By directly connecting the third conductive region and the first conductive region through the connecting wires, it is not necessary to provide side wiring on the first and second driving thin film transistors to connect the third conductive region and the first conductive region, thereby reducing the area of ​​the wiring region of the array substrate, thereby increasing the aperture ratio of the array substrate and thus improving the display brightness.

[0046] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0048] Figure 1 This is a schematic diagram of the structure of an array substrate in related technologies.

[0049] Figure 2 for Figure 1 A schematic diagram of the structure at the intersection of the second drain stage and the grid line.

[0050] Figure 3 The circuit structure diagram of the driving circuit for a sub-pixel.

[0051] Figure 4 This is a schematic diagram of an example embodiment of the array substrate disclosed herein.

[0052] Figure 5 for Figure 4 A schematic diagram of the structure of the reference connecting wire and the light-shielding layer.

[0053] Figure 6 In order to be in Figure 5 This is a schematic diagram of the structure after the active layer is formed based on the above.

[0054] Figure 7 In order to be in Figure 6 This is a schematic diagram of the structure formed by the gate, gate lines, etc.

[0055] Figure 8 This is a schematic diagram of another example embodiment of the array substrate disclosed herein.

[0056] Explanation of reference numerals in the attached figures:

[0057] 1. Reference connecting wire; 101. Connecting wire;

[0058] 21. First light-blocking layer; 22. Second light-blocking layer; 23. Third light-blocking layer; 24. Fourth light-blocking layer;

[0059] 31. First active layer; 311. First channel region; 312. First conductor region; 313. Second conductor region;

[0060] 32. Second active layer; 321. Second channel region; 322. Third conductor region; 323. Fourth conductor region;

[0061] 33. Third active layer; 331. Third channel region; 332. Fifth conductor region; 333. Sixth conductor region;

[0062] 34. Fourth active layer; 341. Fourth channel region; 342. Seventh conductor region; 343. Eighth conductor region;

[0063] 35. Fifth active layer; 351. Fifth channel region; 352. Ninth conductor region; 353. Tenth conductor region;

[0064] 36. Sixth active layer; 361. Sixth channel region; 362. Eleventh conductor region; 363. Twelfth conductor region;

[0065] 37. Connect the wires;

[0066] 41. First gate; 411. First gate body portion; 412. First gate extension portion;

[0067] 42. Second gate; 421. Second gate body portion; 422. Second gate extension portion;

[0068] 43. Third gate; 44. Fourth gate;

[0069] 45. Fifth gate; 451. Fifth gate body; 452. Fifth gate extension;

[0070] 46. ​​Sixth gate; 461. Sixth gate body; 462. Sixth gate extension;

[0071] 47. Grid line; 471. First part; 472. Second part;

[0072] 48. Sensing control signal line; 481. Part Three; 482. Part Four;

[0073] 51. First source; 52. First drain; 53. Second source; 54. Third source; 55. Third drain; 56. Fourth source; 57. Fourth drain; 58. Fifth source; 59. Sixth source; 60. Sixth drain; 61. Power line; 62. Data line; 63. Reference voltage line; 64. Second drain;

[0074] 71. First driving thin-film transistor; 72. Second driving thin-film transistor; 73. Third driving thin-film transistor; 74. Fourth driving thin-film transistor;

[0075] 81. First switching thin-film transistor; 82. Second switching thin-film transistor; 83. Third switching thin-film transistor; 84. Fourth switching thin-film transistor;

[0076] 91. First detection thin-film transistor; 92. Second detection thin-film transistor; 93. Third detection thin-film transistor; 94. Fourth detection thin-film transistor. Detailed Implementation

[0077] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0078] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0079] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0080] In related technologies, WOLED (White Organic Electroluminescence Display) display panels consist of four sub-pixels forming a pixel unit. Therefore, it is very difficult to reduce the opaque area of ​​WOLED display panels to increase the aperture ratio.

[0081] Reference Figure 1 As shown, in related technologies, the first conductive region 312 of the first driving thin-film transistor 71 is directly connected to the power line 61. This direct connection refers to a direct connection through a via on the insulating layer. The third conductive region 322 of the second driving thin-film transistor 72 is connected to the connection line 101 via the second drain 64, and then connected to the power line 61 via the connection line 101. The second drain 64 overlaps with the gate line 47, and the data line 62 also overlaps with the connection line 101. The connection line 101 increases the area of ​​the wiring region on the array substrate, thereby reducing the aperture ratio of the array substrate and consequently reducing the display brightness. (Refer to...) Figure 2 As shown, an insulating layer is provided between the second drain 64 and the gate line 47. The gate line 47 is relatively thick. Therefore, in the overlapping part of the second drain 64 and the gate line 47, the width of the second drain 64 is relatively thin, which can easily cause a short circuit in the second drain 64. The thin insulating layer will cause a short circuit between the second drain 64 and the gate line 47, which will lead to product defects.

[0082] It should be noted that the terms "overlap" and "interlock" mentioned in this specification refer to the overlap or interlocking of the orthographic projections on the substrate.

[0083] This disclosure provides an array substrate according to exemplary embodiments, with reference to... Figure 4 As shown, the array substrate may include a first driving thin-film transistor 71, a second driving thin-film transistor 72, connecting wires, and a power supply (Vdd) line 61; the first driving thin-film transistor 71 may include a first active layer 31, which may include a first channel region 311, and a first conductive region 312 and a second conductive region 313 located at both ends of the first channel region 311; the second driving thin-film transistor 72 is disposed on one side of the first driving thin-film transistor 71, and the second driving thin-film transistor 72 may include a second active layer 32, a second active layer 312, and a second active layer 313. The source layer 32 may include a second channel region 321, and a third conductive region 322 and a fourth conductive region 323 located at both ends of the second channel region 321; a power supply (Vdd) line 61 is disposed on the side of the first driving thin film transistor 71 away from the second driving thin film transistor 72 and extends along the first direction Y; the first conductive region 312 is connected to the power supply line 61; a connecting wire 37 extends from the third conductive region 322 to the first conductive region 312, and its opposite ends are connected to the third conductive region 322 and the first conductive region 312 respectively.

[0084] In the array substrate disclosed herein, the first driving thin-film transistor 71 and the second driving thin-film transistor 72 share a power line 61; and the third conductive region 322 and the first conductive region 312 are directly connected by a connecting wire 37, eliminating the need for side wiring of the first driving thin-film transistor 71 and the second driving thin-film transistor 72 to connect the third conductive region 322 and the first conductive region 312, thereby reducing the area of ​​the wiring region of the array substrate, thereby increasing the aperture ratio of the array substrate, and thus improving the display brightness.

[0085] A WOLED display panel consists of four sub-pixels forming a pixel unit. (Refer to...) Figure 3 As shown, the driving circuit for one sub-pixel may include three thin-film transistors (first driving thin-film transistor 71, first switching thin-film transistor 81, and first detection thin-film transistor 91) and a capacitor C. The driving circuits for the four sub-pixels are respectively a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit; that is, the first driving circuit, the second driving circuit, the third driving circuit, and the fourth driving circuit constitute the driving circuit of the pixel unit. The first driving circuit, the second driving circuit, the third driving circuit, and the fourth driving circuit are all disposed on the array substrate. The following description uses one pixel unit as an example.

[0086] Reference Figure 4 As shown, the array substrate may also include power lines 61, data lines 62, reference voltage lines 63, gate lines 47, and sensing control signal lines 48.

[0087] The first driving circuit, the second driving circuit, the third driving circuit, and the fourth driving circuit are arranged sequentially along the second direction X, wherein the first driving circuit and the second driving circuit form the first group, and the third driving circuit and the fourth driving circuit form the second group.

[0088] The Vdd (power) line 61, data line 62, and reference voltage line 63 all extend along the first direction Y, and the gate line 47 and sensing control signal line 48 all extend along the second direction X. The first direction Y and the second direction X intersect, for example, the first direction Y and the second direction X can be perpendicular.

[0089] In a pixel unit, there are two power lines 61. The two power lines 61 are located on opposite sides of the second direction X of the driving circuit. The first driving circuit and the second driving circuit share one power line 61, and the third driving circuit and the fourth driving circuit share one power line 61.

[0090] The data lines 62 are configured as four, with two data lines 62 arranged side by side between the first and second drive circuits, and the other two data lines 62 arranged side by side between the third and fourth drive circuits.

[0091] A reference voltage line 63 is set as one line, and the reference voltage line 63 is set between the second drive circuit and the third drive circuit.

[0092] The gate line 47 and the sensing control signal line 48 are arranged on opposite sides of the first direction Y of the drive circuit.

[0093] In this exemplary embodiment, the array substrate may include a substrate, and the first driving circuit, the second driving circuit, the third driving circuit, and the fourth driving circuit are all disposed on one side of the substrate. The substrate material may include inorganic materials, such as glass, quartz, or metal. The substrate material may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate may be formed from multiple material layers; for example, the substrate may include multiple base layers, and the base layers may be made of any of the aforementioned materials. Alternatively, the substrate may be a single layer, and may be any of the aforementioned materials.

[0094] In this example implementation, refer to Figure 4 and Figure 5 As shown, a light-shielding layer is disposed on one side of the substrate. The light-shielding layers are a first light-shielding layer 21, a second light-shielding layer 22, a third light-shielding layer 23, and a fourth light-shielding layer 24, and the material of the light-shielding layers can be metal. The four light-shielding layers are arranged along the second direction X. The light-shielding layer can also serve as an electrode of capacitor C. The orthographic projection of the four driving thin-film transistors on the substrate corresponds to the orthographic projection of the four light-shielding layers on the substrate. Light entering the active layer from the substrate will generate photogenerated carriers in the active layer, thereby affecting the characteristics of the driving thin-film transistors and ultimately affecting the display quality of the display device. The light-shielding layers can block the light entering from the substrate, thereby avoiding the influence on the characteristics of the driving thin-film transistors and avoiding the impact on the display quality of the display device.

[0095] A reference connection wire 1 is also provided on one side of the substrate. That is, the reference connection wire 1 is disposed in the same layer and with the same material as the light-shielding layer. In other words, the reference connection wire 1 and the light-shielding layer are formed by the same patterning process. The reference connection wire 1 extends along the second direction X and is located on the side of the sensing control signal line 48 away from the first driving thin film transistor 71.

[0096] In this example embodiment, a buffer layer is provided on the side of the light-shielding layer away from the substrate. The buffer layer serves to block water vapor and impurity ions in the substrate (especially organic materials) and to increase hydrogen ions for the subsequently formed active layer. The buffer layer is made of an insulating material, which can insulate and isolate the light-shielding layer from the active layer.

[0097] An active layer is disposed on the side of the buffer layer away from the substrate, as shown in the figure. Figure 4 and Figure 6 As shown, the active layer may include a connecting wire 37, a first active layer 31, a second active layer 32, a third active layer 33, a fourth active layer 34, a fifth active layer 35, and a sixth active layer 36. That is, the connecting wire 37, the first active layer 31, the second active layer 32, the third active layer 33, the fourth active layer 34, the fifth active layer 35, and the sixth active layer 36 are disposed in the same layer and made of the same material. In other words, the connecting wire 37, the first active layer 31, the second active layer 32, the third active layer 33, the fourth active layer 34, the fifth active layer 35, and the sixth active layer 36 are formed through the same patterning process.

[0098] There are four third active layers 33 and four fourth active layers 34. The first active layer 31, the second active layer 32, the fifth active layer 35, and the sixth active layer 36 are arranged sequentially along the first direction Y. Among them, the first active layer 31, one third active layer 33, and one fourth active layer 34 belong to the driving circuit of one sub-pixel, for example, the driving circuit of a white sub-pixel; the second active layer 32, one third active layer 33, and one fourth active layer 34 belong to the driving circuit of another sub-pixel, for example, the driving circuit of a red sub-pixel; the fifth active layer 35, one third active layer 33, and one fourth active layer 34 belong to the driving circuit of yet another sub-pixel, for example, the driving circuit of a green sub-pixel; and the sixth active layer 36, one third active layer 33, and one fourth active layer 34 belong to the driving circuit of yet another sub-pixel, for example, the driving circuit of a blue sub-pixel.

[0099] The first active layer 31 may include a first channel region 311, and a first conductive region 312 and a second conductive region 313 located at both ends of the first channel region 311. The first conductive region 312 and the second conductive region 313 are located at both ends of the first channel region 311 in a first direction Y. Specifically, the first active layer 31 may include a first rectangular region and a second rectangular region. The first rectangular region extends along a second direction X, and the second rectangular region extends along a first direction Y. The second rectangular region is connected to the side of the first rectangular region near the gate line 47. The middle part of the second rectangular region is the first channel region 311, the part of the second rectangular region away from the first rectangular region is the first conductive region 312, and the part of the second rectangular region near the first rectangular region forms the second conductive region 313 together with the first rectangular region. The area of ​​the second conductive region 313 is larger than the area of ​​the first conductive region 312.

[0100] The second active layer 32 may include a second channel region 321, and a third conductive region 322 and a fourth conductive region 323 located at both ends of the second channel region 321. The third conductive region 322 and the fourth conductive region 323 are located at both ends of the second channel region 321 in the first direction Y. Specifically, the second active layer 32 may include a third rectangular region and a fourth rectangular region, the third rectangular region extending along the second direction X, and the fourth rectangular region extending along the first direction Y. The fourth rectangular region is connected to the side of the third rectangular region near the gate line 47. The middle part of the fourth rectangular region is the second channel region 321.

[0101] The portion of the fourth rectangular region furthest from the third rectangular region forms the third conductive region 322, while the portion of the fourth rectangular region closest to the third rectangular region, together with the third rectangular region, forms the fourth conductive region 323. The area of ​​the fourth conductive region 323 is larger than the area of ​​the third conductive region 322.

[0102] The connecting wire 37 can be elongated and straight, extending along the second direction X from the third conductive region 322 to the first conductive region 312, connecting the third conductive region 322 and the first conductive region 312. The third conductive region 322, the connecting wire 37, and the first conductive region 312 are connected together during fabrication. Essentially, the connecting wire 37 is an extension of the third conductive region 322 towards the first driving thin-film transistor 71, or an extension of the first conductive region 312 towards the second driving thin-film transistor 72. Of course, in other exemplary embodiments of this disclosure, the connecting wire 37 can also be curved, as long as its main direction extends from the third conductive region 322 to the first conductive region 312. Furthermore, due to the positions of the third conductive region 322 and the first conductive region 312, the connecting wire 37 can also be inclined, meaning its extension direction can form a set angle with the second direction X.

[0103] The fifth active layer 35 may include a fifth channel region 351, and a ninth conductive region 352 and a tenth conductive region 353 located at both ends of the fifth channel region 351. The ninth conductive region 352 and the tenth conductive region 353 are located at both ends of the fifth channel region 351 in the first direction Y. Specifically, the fifth active layer 35 may include a fifth rectangular region and a sixth rectangular region, the fifth rectangular region extending along the second direction X, and the sixth rectangular region extending along the first direction Y. The sixth rectangular region is connected to the side of the fifth rectangular region near the gate line 47. The middle part of the sixth rectangular region is the fifth channel region 351.

[0104] The portion of the sixth rectangular region furthest from the fifth rectangular region forms the ninth conductive region 352, while the portion of the sixth rectangular region closest to the fifth rectangular region, together with the fifth rectangular region, forms the tenth conductive region 353. The area of ​​the tenth conductive region 353 is larger than the area of ​​the ninth conductive region 352.

[0105] The sixth active layer 36 may include a sixth channel region 361, and an eleventh conductive region 362 and a twelfth conductive region 363 located at both ends of the sixth channel region 361. The eleventh conductive region 362 and the twelfth conductive region 363 are located at both ends of the sixth channel region 361 in the first direction Y. Specifically, the sixth active layer 36 may include a seventh rectangular region and an eighth rectangular region. The seventh rectangular region extends along the second direction X, and the eighth rectangular region extends along the first direction Y. The eighth rectangular region is connected to the side of the seventh rectangular region near the gate line 47. The middle part of the eighth rectangular region is the sixth channel region 361, the part of the eighth rectangular region away from the seventh rectangular region is the eleventh conductive region 362, and the part of the eighth rectangular region near the seventh rectangular region forms the twelfth conductive region 363 together with the seventh rectangular region.

[0106] The area of ​​the twelfth conductor region 363 is larger than the area of ​​the eleventh conductor region 362.

[0107] The connecting wire 37 can be configured as a long strip, and this strip is straight. The connecting wire 37 extends along the second direction X, from the ninth conductive region 352 to the eleventh conductive region 362, connecting the ninth conductive region 352 and the eleventh conductive region 362. The ninth conductive region 352, the connecting wire 37, and the eleventh conductive region 362 are connected together during manufacturing. That is, the connecting wire 37 is an extension of the ninth conductive region 352 extending towards the sixth driving thin film transistor 76, or the connecting wire 37 is an extension of the eleventh conductive region 362 extending towards the fifth driving thin film transistor 75. Of course, in other exemplary embodiments of this disclosure, the connecting wire 37 can also be configured as a curved shape, as long as the main direction extends from the ninth conductive region 352 to the eleventh conductive region 362; and due to the position of the ninth conductive region 352 and the eleventh conductive region 362, the connecting wire 37 can also be inclined, that is, the extension direction of the connecting wire 37 can form a set angle with the second direction X.

[0108] It should be noted that the first active layer 31, the second active layer 32, the fifth active layer 35 and the sixth active layer 36 can also be configured with other structures. For example, they can include a circular or elliptical main body, with strip-shaped protrusions on the circular or elliptical body. One part of the protrusion is a channel region, and the other part of the protrusion is a conductor region. The main body is a conductor region.

[0109] The third active layer 33 may include a third channel region 331, and a fifth conductive region 332 and a sixth conductive region 333 located at both ends of the third channel region 331. The third active layer 33 is rectangular in shape and extends along a first direction Y. The fifth conductive region 332 and the sixth conductive region 333 are located at opposite ends of the third channel region 331 along the first direction Y. The third active layer 33 is disposed on the side of the first active layer 31 away from the reference connection wire 1, and four third active layers 33 are arranged sequentially along a second direction X. In other exemplary embodiments of this disclosure, the third active layer 33 may be disposed on the side of the first active layer 31 closer to the data line.

[0110] The fourth active layer 34 may include a fourth channel region 341, and a seventh conductive region 342 and an eighth conductive region 343 located at both ends of the fourth channel region 341. The fourth active layer 34 is rectangular in shape and extends along a first direction Y. The seventh conductive region 342 and the eighth conductive region 343 are located at opposite ends of the fourth channel region 341 in the first direction Y. All four fourth active layers 34 are disposed between the first active layer 31 and the reference connection wire 1, and the four fourth active layers 34 are arranged sequentially along a second direction X. In other exemplary embodiments of this disclosure, the fourth active layer 34 may be disposed on the side of the first active layer 31 closer to the data line.

[0111] A gate insulating layer is provided on the side of the active layer away from the substrate. The gate insulating layer is used to insulate and isolate the active layer from the subsequently formed gate, gate line 47 and sensing control signal line 48. The gate insulating layer may cover the entire array substrate or only cover the portion where the gate, gate line 47 and sensing control signal line 48 are provided.

[0112] A gate, gate line 47, and sensing control signal line 48 are disposed on the side of the gate insulating layer away from the substrate. (Refer to...) Figure 4 and Figure 7 As shown, the gate may include a first gate 41, a second gate 42, a third gate 43, a fourth gate 44, a fifth gate 45, and a sixth gate 46. The gate line 47, the sensing control signal line 48, the first gate 41, the second gate 42, the third gate 43, the fourth gate 44, the fifth gate 45, and the sixth gate 46 are disposed in the same layer and made of the same material, that is, they are formed by the same patterning process.

[0113] Both the third gate 43 and the fourth gate 44 are configured as four; wherein, the first gate 41, one third gate 43 and one fourth gate 44 belong to the driving circuit of one sub-pixel, for example, the driving circuit of a white sub-pixel; the second gate 42, one third gate 43 and one fourth gate 44 belong to the driving circuit of another sub-pixel, for example, the driving circuit of a red sub-pixel; the fifth gate 45, one third gate 43 and one fourth gate 44 belong to the driving circuit of yet another sub-pixel, for example, the driving circuit of a green sub-pixel; and the sixth gate 46, one third gate 43 and one fourth gate 44 belong to the driving circuit of yet another sub-pixel, for example, the driving circuit of a blue sub-pixel.

[0114] The first gate 41 may extend along the second direction X. The first gate 41 may include a first gate body portion 411 and a first gate extension portion 412. The first gate body portion 411 is disposed opposite to the first channel region 311. The first gate extension portion 412 is connected to the first gate body portion 411 and is located on the side of the first gate body portion 411 near the data line 62. The first gate body portion 411 and the first gate extension portion 412 are connected in the second direction X. The end of the first gate extension portion 412 near the data line 62 overlaps with the third source electrode 54, and the width of this end portion is greater than the width of the rest. The first gate 41 may also serve as another electrode of a capacitor C.

[0115] The second gate 42 may extend along the second direction X. The second gate 42 may include a second gate body portion 421 and a second gate extension portion 422. The second gate body portion 421 is disposed opposite to the second channel region 321; the second gate extension portion 422 is connected to the second gate body portion 421 and is located on the side of the second gate body portion 421 closest to the data line 62. The second gate body portion 421 and the second gate extension portion 422 are connected in the second direction X. The width of the portion of the second gate 42 overlapping with the third source 54 is greater than the width of the remaining portion. The second gate 42 may also serve as another electrode of the capacitor C.

[0116] The fifth gate 45 may extend along the second direction X. The fifth gate 45 may include a fifth gate body portion 451 and a fifth gate extension portion 452. The fifth gate body portion 451 is disposed opposite to the fifth channel region 351; the fifth gate extension portion 452 is connected to the fifth gate body portion 451 and is located on the fifth side of the fifth gate body portion 451 near the data line 62; the fifth gate body portion 451 and the fifth gate extension portion 452 are connected in the second direction X. The width of the portion of the fifth gate 45 overlapping with the third source 54 is greater than the width of the remaining portion. The fifth gate 45 may also serve as another electrode of the capacitor C.

[0117] The sixth gate 46 may extend along the second direction X. The sixth gate 46 may include a sixth gate body portion 461 and a sixth gate extension portion 462. The sixth gate body portion 461 is disposed opposite to the sixth channel region 361; the sixth gate extension portion 462 is connected to the sixth gate body portion 461 and is located on one of the six sides of the sixth gate body portion 461 near the data line 62; the sixth gate body portion 461 and the sixth gate extension portion 462 are connected in the second direction X. The width of the portion of the sixth gate 46 overlapping with the third source 54 is greater than the width of the remaining portion. The sixth gate 46 may also serve as another electrode of the capacitor C.

[0118] By configuring the first gate 41, the second gate 42, the fifth gate 45, and the sixth gate 46 in this way, the four third active layers 33 can be positioned close to the data lines 62, and the four third drains 55 connecting the four data lines 62 and the four third active layers 33 can be positioned shorter, thereby improving electrical performance and reducing various risks.

[0119] Both the gate line 47 and the sensing control signal line 48 extend along the second direction X. The gate line 47 is located on the side of the first driving thin-film transistor 71 away from the first detection thin-film transistor 91. The sensing control signal line 48 is located on the side of the first driving thin-film transistor 71 away from the first switching thin-film transistor 81.

[0120] The gate line 47 may include multiple first portions 471 and multiple second portions 472. The first portions 471 are configured as a double-wire structure, meaning each first portion 471 may include two conductors whose main bodies are substantially parallel, and whose conductive ends are connected together. This configuration ensures that even if one conductor is broken, the other conductor can still conduct electricity, thus guaranteeing the conductivity of the gate line 47. The second portions 472 are configured as a single-wire structure, meaning each second portion 472 may include one conductor. The second portions 472 are connected between two adjacent first portions 471, specifically at their respective ends.

[0121] The first part 471 extends along the second direction X, and the second part 472 also extends along the second direction X, so that the entire gate line 47 extends along the second direction X.

[0122] The third gate 43 is disposed opposite to the third channel region 331. The third gate 43 may be a part of the gate line 47 or a part of the second part 472, so that both ends of the third gate 43 are connected to the gate line 47.

[0123] The sensing control signal line 48 may include multiple third parts 481 and multiple fourth parts 482. The third parts 481 are configured as a two-wire structure, meaning each third part 481 may include two wires whose main bodies are substantially parallel, and whose conductive ends are connected together. This configuration ensures that even if one wire is broken, the other wire can still conduct electricity, thus guaranteeing the conductivity of the sensing control signal line 48. The fourth parts 482 are configured as a single-wire structure, meaning each fourth part 482 may include a single wire. The fourth parts 482 are connected between two adjacent third parts 481, specifically, the fourth parts 482 are connected to the two ends of two adjacent third parts 481.

[0124] The third part 481 extends along the second direction X, and the fourth part 482 also extends along the second direction X, so that the sensing control signal line 48 extends along the second direction X as a whole.

[0125] The fourth gate 44 is disposed opposite to the fourth channel region 341. The fourth gate 44 may be part of the sensing control signal line 48, or part of the fourth portion 482, such that both ends of the fourth gate 44 are connected to the sensing control signal line 48.

[0126] In other exemplary embodiments of this disclosure, the connecting wire 37 can be disposed in the same layer and with the same material as the first gate 41, that is, the connecting wire 37 can be formed with the first gate 41 through the same patterning process. The structure of the connecting wire 37 is the same as described above, except that it is disposed in a different conductive layer. One connecting wire 37 can be connected to the first conductive region 312 and the third conductive region 322 through a via on the gate insulating layer, and another connecting wire 37 can be connected to the ninth conductive region 352 and the eleventh conductive region 362 through a via on the gate insulating layer.

[0127] An insulating layer is provided on the side of the gate, gate line 47 and sensing control signal line 48 away from the substrate. The insulating layer covers the entire array substrate. Multiple vias are provided on the insulating layer so that the source and drain of each thin film transistor can be connected to the conductor region of the active layer and the reference connection wire 1.

[0128] Reference Figure 4As shown in the figure, the dashed circles represent vias. Power lines 61, data lines 62, reference voltage (V-Ref) lines 63, and the source and drain electrodes of each thin-film transistor are disposed on the side of the insulating layer away from the substrate. The power lines 61, data lines 62, reference voltage (V-Ref) lines 63, and the source and drain electrodes of each thin-film transistor (first source 51, first drain 52, second source 53, third source 54, third drain 55, fourth source 56, fourth drain 57, fifth source 58, sixth source 59, and sixth drain 60) are disposed on the same layer and made of the same material, meaning they are formed through the same patterning process.

[0129] The power line 61, data line 62, and reference voltage line 63 all extend along the first direction Y.

[0130] In a pixel unit, there are two power lines 61. The two power lines 61 are located on opposite sides of the second direction X of the driving circuit. The first driving circuit and the second driving circuit share one power line 61, and the third driving circuit and the fourth driving circuit share one power line 61.

[0131] Specifically, as described in the above description of the active layer, a connecting wire 37 extends along the second direction X from the third conductive region 322 toward the first conductive region 312 until the third conductive region 322 and the first conductive region 312 are connected. Another connecting wire 37 extends along the second direction X from the ninth conductive region 352 toward the eleventh conductive region 362 until the ninth conductive region 352 and the eleventh conductive region 362 are connected.

[0132] The first drain 52 extends along the second direction X. One end of the first drain 52 is directly connected to the power line 61, and the first drain 52 and the power line 61 are connected together during manufacturing. The other end of the first drain 52 is connected to the first conductive region 312 through a via on the insulating layer. This allows the first driving circuit and the second driving circuit to share a single power line 61.

[0133] The sixth drain 60 extends along the second direction X. One end of the sixth drain 60 is directly connected to another power line 61, and the sixth drain 60 and the other power line 61 are connected together during manufacturing. The other end of the sixth drain 60 is connected to the eleventh conductive region 362 through a via on the insulating layer. This allows the third and fourth drive circuits to share a single power line 61.

[0134] The third source 54 of the first switching thin film transistor 81 extends substantially along the first direction Y. One end of the third source 54 overlaps with and is connected to the first gate 41 through a via on the insulating layer, and the other end of the third source 54 overlaps with and is connected to the fifth conductive region 332 of the first switching thin film transistor 81 through a via on the insulating layer.

[0135] The third source 54 of the second switching thin film transistor 82 extends substantially along the first direction Y. One end of the third source 54 overlaps with and is connected to the second gate 42 through a via on the insulating layer, and the other end of the third source 54 overlaps with and is connected to the fifth conductive region 332 of the second switching thin film transistor 82 through a via on the insulating layer.

[0136] The third source 54 of the third switching thin film transistor 83 extends substantially along the first direction Y. One end of the third source 54 overlaps with and is connected to the fifth gate 45 through a via on the insulating layer, and the other end of the third source 54 overlaps with and is connected to the fifth conductive region 332 of the third switching thin film transistor 83 through a via on the insulating layer.

[0137] The third source 54 of the fourth switching thin film transistor 84 extends substantially along the first direction Y. One end of the third source 54 overlaps with and is connected to the sixth gate 46 through a via on the insulating layer, and the other end of the third source 54 overlaps with and is connected to the fifth conductive region 332 of the fourth switching thin film transistor 84 through a via on the insulating layer.

[0138] The data lines 62 are configured as four, with two data lines 62 arranged side by side between the first and second drive circuits, and the other two data lines 62 arranged side by side between the third and fourth drive circuits.

[0139] The third drain 55 of the first switching thin film transistor 81 extends substantially along the second direction X. One end of the third drain 55 overlaps with and is connected to the sixth conductive region 333 of the first switching thin film transistor 81 through a via on the insulating layer. The other end of the third drain 55 is directly connected to the data line 62 near the first switching thin film transistor 81. The third drain 55 and the data line 62 are connected together during fabrication.

[0140] The third drain 55 of the second switching thin film transistor 82 extends substantially along the second direction X. One end of the third drain 55 overlaps with and is connected to the sixth conductive region 333 of the second switching thin film transistor 82 through a via on the insulating layer. The other end of the third drain 55 is directly connected to the data line 62 near the second switching thin film transistor 82. The third drain 55 and the data line 62 are connected together during fabrication.

[0141] The third drain 55 of the third switching thin film transistor 83 extends substantially along the second direction X. One end of the third drain 55 overlaps with and is connected to the sixth conductive region 333 of the third switching thin film transistor 83 through a via on the insulating layer. The other end of the third drain 55 is directly connected to the data line 62 near the third switching thin film transistor 83. The third drain 55 and the data line 62 are connected together during fabrication.

[0142] The third drain 55 of the fourth switching thin film transistor 84 extends substantially along the second direction X. One end of the third drain 55 overlaps with and is connected to the sixth conductive region 333 of the fourth switching thin film transistor 84 through a via on the insulating layer. The other end of the third drain 55 is directly connected to the data line 62 near the fourth switching thin film transistor 84. The third drain 55 and the data line 62 are connected together during fabrication.

[0143] A single reference voltage line 63 is provided, positioned between the second and third drive circuits. The reference voltage line 63 is connected to the reference connection wire 1 via a via in the insulating layer.

[0144] The fourth drain 57 of the first detection thin film transistor 91 extends substantially along the second direction X. One end of the fourth drain 57 overlaps with and is connected to the eighth conductor region 343 of the first detection thin film transistor 91 through a via on the insulating layer. The other end of the fourth drain 57 is connected to the reference connection wire 1 through a via on the insulating layer, so that the fourth drain 57 of the first detection thin film transistor 91 is connected to the reference voltage line 63 through the reference connection wire 1.

[0145] The fourth drain 57 of the second detection thin film transistor 92 extends substantially along the second direction X. One end of the fourth drain 57 overlaps with and is connected to the eighth conductor region 343 of the second detection thin film transistor 92 through a via on the insulating layer. The other end of the fourth drain 57 is connected to the reference connection wire 1 through a via on the insulating layer, so that the fourth drain 57 of the second detection thin film transistor 92 is connected to the reference voltage line 63 through the reference connection wire 1.

[0146] The fourth drain 57 of the third detection thin film transistor 93 extends substantially along the second direction X. One end of the fourth drain 57 overlaps with and is connected to the eighth conductor region 343 of the third detection thin film transistor 93 through a via on the insulating layer. The other end of the fourth drain 57 is connected to the reference connection wire 1 through a via on the insulating layer, so that the fourth drain 57 of the third detection thin film transistor 93 is connected to the reference voltage line 63 through the reference connection wire 1.

[0147] It should be noted that the fourth drain 57 of the second detection thin-film transistor 92 can be directly connected to the reference voltage line 63, and the fourth drain 57 of the third detection thin-film transistor 93 can also be directly connected to the reference voltage line 63.

[0148] The fourth drain 57 of the fourth detection thin film transistor 94 extends substantially along the second direction X. One end of the fourth drain 57 overlaps with and is connected to the eighth conductor region 343 of the fourth detection thin film transistor 94 through a via on the insulating layer. The other end of the fourth drain 57 is connected to the reference connection wire 1 through a via on the insulating layer, so that the fourth drain 57 of the fourth detection thin film transistor 94 is connected to the reference voltage line 63 through the reference connection wire 1.

[0149] The fourth source 56 of the first detection thin-film transistor 91 extends substantially along the second direction X. One end of the fourth source 56 overlaps with and is connected to the seventh conductive region 342 of the first detection thin-film transistor 91 through a via in the insulating layer. The other end of the fourth source 56 is connected to the first source 51 of the first driving thin-film transistor 71. The first source 51 of the first driving thin-film transistor 71 extends substantially along the first direction Y. One end of the first source 51 overlaps with and is connected to the second conductive region 313 of the first driving thin-film transistor 71 through a via in the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the first source 51. The fourth source 56 and the first source 51 are connected together during fabrication. Furthermore, the fourth source 56 and the first source 51 of the first detection thin-film transistor 91 are connected to the first light-shielding layer 21 through a via in the insulating layer. The first light-shielding layer 21 serves as one electrode of the capacitor C. Therefore, both the fourth source 56 and the first source 51 of the first detection thin-film transistor 91 are connected to one electrode of the capacitor C.

[0150] The fourth source 56 of the second detection thin-film transistor 92 extends substantially along the second direction X. One end of the fourth source 56 overlaps with and is connected to the seventh conductive region 342 of the second detection thin-film transistor 92 through a via in the insulating layer. The other end of the fourth source 56 is connected to the second source 53 of the second driving thin-film transistor 72. The second source 53 of the second driving thin-film transistor 72 extends substantially along the first direction Y. One end of the second source 53 overlaps with and is connected to the fourth conductive region 323 of the second driving thin-film transistor 72 through a via in the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the second source 53. The fourth source 56 and the second source 53 are connected together during fabrication. Furthermore, the fourth source 56 and the second source 53 of the second detection thin-film transistor 92 are connected to the second light-shielding layer 22 through a via in the insulating layer. The second light-shielding layer 22 serves as one electrode of the capacitor C. Therefore, both the fourth source 56 and the second source 53 of the second detection thin-film transistor 92 are connected to one electrode of the capacitor C.

[0151] The fourth source 56 of the third detection thin-film transistor 93 extends substantially along the second direction X. One end of the fourth source 56 overlaps with and is connected to the seventh conductive region 342 of the third detection thin-film transistor 93 through a via in the insulating layer. The other end of the fourth source 56 is connected to the fifth source 58 of the third driving thin-film transistor 73. The fifth source 58 of the third driving thin-film transistor 73 extends substantially along the first direction Y. One end of the fifth source 58 overlaps with and is connected to the tenth conductive region 353 of the third driving thin-film transistor 73 through a via in the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the fifth source 58. The fourth source 56 and the fifth source 58 are connected together during fabrication. Furthermore, the fourth source 56 and the fifth source 58 of the third detection thin-film transistor 93 are connected to the third light-shielding layer 23 through a via in the insulating layer. The third light-shielding layer 23 serves as one electrode of the capacitor C. Therefore, both the fourth source 56 and the fifth source 58 of the third detection thin-film transistor 93 are connected to one electrode of the capacitor C.

[0152] The fourth source 56 of the fourth detection thin-film transistor 94 extends substantially along the second direction X. One end of the fourth source 56 overlaps with and is connected to the ninth conductive region 352 of the fourth detection thin-film transistor 94 through a via in the insulating layer. The other end of the fourth source 56 is connected to the sixth source 59 of the fourth driving thin-film transistor 74. The sixth source 59 of the fourth driving thin-film transistor 74 extends substantially along the first direction Y. One end of the sixth source 59 overlaps with and is connected to the twelfth conductive region 363 of the fourth driving thin-film transistor 74 through a via in the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the sixth source 59. The fourth source 56 and the sixth source 59 are connected together during fabrication. Furthermore, the fourth source 56 and the sixth source 59 of the fourth detection thin-film transistor 94 are connected to the fourth light-shielding layer 24 through a via in the insulating layer. The fourth light-shielding layer 24 serves as one electrode of the capacitor C. Therefore, both the fourth source 56 and the sixth source 59 of the fourth detection thin-film transistor 94 are connected to one electrode of the capacitor C.

[0153] In the array substrate disclosed herein, the first conductive region 312 and the third conductive region 322 are directly connected as a single unit during the formation of the active layer, avoiding the need for the second drain stage 64 and the connecting line 101. This reduces the area of ​​the wiring region of the array substrate, thereby increasing the aperture ratio of the array substrate and thus improving the display brightness. Furthermore, there is no overlap between the second drain stage 64 and the gate line 47, avoiding the open circuit of the second drain stage 64 and the short circuit between the second drain stage 64 and the gate line 47, thus improving product yield. In addition, although the connecting wire 37 overlaps with the data line 62, a relatively thick insulating layer is provided between the connecting wire 37 and the data line 62, and the thickness of the connecting wire 37 is relatively thin, eliminating the risk of the data line 62 being open or short-circuited. Moreover, since the power line 61 is connected to a DC voltage, the use of the connecting wire 37 does not affect the driving of the thin-film transistor.

[0154] In other exemplary embodiments of this disclosure, the driving circuit for a sub-pixel may include two thin-film transistors and a capacitor C. In this case, the reference connection wire 1, the reference voltage line 63, and the sensing control signal line 48 may not be provided. Furthermore, the driving circuit for a sub-pixel may also include more thin-film transistors and a capacitor C.

[0155] In some additional exemplary embodiments of this disclosure, a pixel unit may also include three sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The driving circuits for two of these sub-pixels may share a power line 61. That is, the array substrate may include a first driving thin-film transistor 71, a second driving thin-film transistor 72, and a third driving thin-film transistor 73. A connecting wire 37 extends from the third conductive region 322 of the second driving thin-film transistor 72 to the first conductive region 312 of the first driving thin-film transistor 71, and the opposite ends of the connecting wire 37 are connected to the third conductive region 322 and the first conductive region 312, respectively. The first conductive region 312 is connected to the power line 61. The specific structure has been described in detail above, and therefore will not be repeated here.

[0156] Based on the same inventive concept, this disclosure provides an example embodiment of a display panel, which may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0157] The display panel may further include a first electrode, a pixel fixing layer, a light-emitting layer, a second electrode, and an encapsulation layer assembly. The first electrode is disposed on the side of the protective layer away from the substrate, and is connected to the source or drain electrode through a third via on the protective layer. The first electrode can be an anode, and its material can be a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), etc. The pixel fixing layer is disposed on the side of the first electrode away from the substrate, and has a fourth via connected to the first electrode, exposing a portion of the first electrode. The light-emitting layer is disposed within the fourth via and is connected to the first electrode. The second electrode is disposed on the side of the light-emitting layer away from the substrate, and can be a cathode.

[0158] The encapsulation layer group is located on the side of the second electrode away from the substrate. The encapsulation layer group may include organic layers and inorganic layers. The number of organic and inorganic layers and their stacking method can be set as needed, and will not be elaborated here.

[0159] Based on the same inventive concept, this disclosure provides a display device that may include the display panel described above. The specific structure of the display panel has been described in detail above, and therefore will not be repeated here.

[0160] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated here.

[0161] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts. Taking the display as an example, these may include the casing, circuit board, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0162] Compared with the prior art, the beneficial effects of the display panel and display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0163] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, characterized by, The array substrate comprises: a first drive thin film transistor comprising a first active layer, the first active layer comprising: a first channel region, and a first conductorization region and a second conductorization region located at two ends of the first channel region; a second drive thin film transistor located at one side of the first drive thin film transistor, the second drive thin film transistor comprising a second active layer, the second active layer comprising: a second channel region, and a third conductorization region and a fourth conductorization region located at two ends of the second channel region; a connecting wire extending from the third conductorization region to the first conductorization region, and opposite ends of the connecting wire corresponding to the third conductorization region and the first conductorization region are connected; two data lines arranged side by side between the first drive thin film transistor and the second drive thin film transistor and extending along a first direction; a first switch thin film transistor and a second switch thin film transistor, the first switch thin film transistor and the second switch thin film transistor comprising a third gate, a third active layer, a third source and a third drain, the third active layer comprising: a third channel region, and a fifth conductorization region and a sixth conductorization region located at two ends of the third channel region, the fifth conductorization region overlapping and connected with the third source, and the sixth conductorization region overlapping and connected with the third drain; the third source of the first switch thin film transistor overlapping and connected with the first gate of the first drive thin film transistor, the third source of the second switch thin film transistor overlapping and connected with the second gate of the second drive thin film transistor, and the two third drains corresponding to the two data lines; a gate line connected to the third gate, the gate line extending along a second direction intersecting the first direction; the first gate comprises: a first gate body portion arranged opposite to the first channel region; a first gate extension portion connected to the first gate body portion and located at a side of the first gate body portion close to the data line; the second gate comprises: a second gate body portion arranged opposite to the second channel region; a second gate extension portion connected to the second gate body portion and located at a side of the second gate body portion close to the data line; an extension direction of the third active layer intersects an extension direction of the gate line, the third source of the first switch thin film transistor overlaps and is connected with an end portion of the first gate extension portion close to the data line, and the third source of the second switch thin film transistor overlaps and is connected with an end portion of the second gate extension portion close to the data line.

2. The array substrate of claim 1, wherein, The connecting wire is an extension portion of the third conductorization region extending to one side of the first drive thin film transistor.

3. The array substrate of claim 1, wherein, The array substrate further comprises: a power supply line arranged at a side of the first drive thin film transistor away from the second drive thin film transistor and extending along the first direction, and the first conductorization region is connected with the power supply line. The first drive thin film transistor further comprises a first gate, a first source and a first drain, the first conductive region overlaps and connects with the first drain, the first drain connects with the power supply line, the second conductive region overlaps and connects with the first source, and the first channel region overlaps with the first gate; The second drive thin film transistor further comprises a second gate and a second source, the fourth conductive region overlaps and connects with the second source, and the second channel region overlaps with the second gate.

4. The array substrate of claim 3, wherein, The connection wire is arranged in the same layer and of the same material as the first gate.

5. The array substrate of claim 1, wherein, The gate line comprises: a plurality of first portions arranged in a double-line structure and extending along the second direction; a plurality of second portions arranged in a single-line structure and extending along the second direction, the second portions being connected between adjacent two first portions, and the third gate being a part of the second portions.

6. The array substrate of claim 3, wherein, The first switch thin film transistor is arranged on one side of the first drive thin film transistor in the first direction, and the second switch thin film transistor is arranged on one side of the second drive thin film transistor in the first direction, the first switch thin film transistor and the second switch thin film transistor being located between the data line and the power supply line.

7. The array substrate of claim 3, wherein, The array substrate further comprises: a first detection thin film transistor and a second detection thin film transistor, the first detection thin film transistor and the second detection thin film transistor comprising a fourth gate, a fourth active layer, a fourth source and a fourth drain, the fourth active layer comprising a fourth channel region, and a seventh conductive region and an eighth conductive region located at two ends of the fourth channel region, the seventh conductive region overlapping and connecting with the fourth source, and the eighth conductive region overlapping and connecting with the fourth drain, the first detection thin film transistor being arranged on one side of the first drive thin film transistor away from the first switch thin film transistor, and the second detection thin film transistor being arranged on one side of the second drive thin film transistor away from the second switch thin film transistor; a reference voltage line arranged on one side of the second drive thin film transistor away from the first drive thin film transistor and extending along the first direction; a sensing control signal line arranged on one side of the first drive thin film transistor away from the first switch thin film transistor and extending along the second direction; a reference connection wire arranged on one side of the sensing control signal line away from the first drive thin film transistor, the reference connection wire connecting with the reference voltage line; wherein the fourth source of the first detection thin film transistor connects to the first source, the fourth source of the second detection thin film transistor connects to the second source, the fourth drain connects to the reference voltage line through the reference connection wire, and the fourth gate connects to the sensing control signal line.

8. The array substrate of claim 7, wherein, The sensing control signal line comprises: a plurality of third portions arranged in a double-line structure and extending along the second direction; A plurality of fourth parts are arranged in a single line structure and extend in a second direction, the fourth parts being connected between two adjacent third parts, the fourth gate being a part of the fourth part.

9. The array substrate of claim 7, wherein, The array substrate further comprises: A first light-shielding layer, the first driving thin film transistor overlapping the first light-shielding layer, the first light-shielding layer and the first gate forming a capacitor; A second light-shielding layer, the second driving thin film transistor overlapping the second light-shielding layer, the second light-shielding layer and the second gate forming a capacitor.

10. The array substrate of claim 9, wherein, The first light-shielding layer, the second light-shielding layer and the reference connection wire are arranged in the same layer and are made of the same material; the first active layer, the second active layer, the third active layer and the fourth active layer are arranged in the same layer and are made of the same material; the gate line, the sensing control signal line, the first gate, the second gate, the third gate and the fourth gate are arranged in the same layer and are made of the same material; the first source, the first drain, the second source, the third source, the third drain, the fourth source, the fourth drain, the data line, the power line and the reference voltage line are arranged in the same layer and are made of the same material.

11. A display panel, characterized by, The array substrate comprises: The array substrate of any one of claims 1-10.

12. A display device comprising: The display panel comprises: The display panel of claim 11.

Images