Power semiconductor device and manufacturing method thereof

Abstract

The present invention provides a power semiconductor device and a manufacturing method thereof, wherein a plurality of second resistance field plate structures are arranged in a terminal region of an epitaxial layer, penetrating the epitaxial layer along a first direction and extending into a substrate, and the plurality of second resistance field plate structures are radially arranged in a first plane, extending from a side close to a cell region to a side far from the cell region. The plurality of tightly coupled second resistance field plate structures form a more uniform three-dimensional electric field distribution that diverges in all directions, thereby optimizing the guiding and binding effect on charges in a spatial depletion region of the cell region and improving the voltage resistance performance of the entire power semiconductor device; the second resistance field plate structure in the terminal region and the first resistance field plate structure in the cell region are both second-generation super junction technology based on internal resistance field plates, with process compatibility, low manufacturing cost, and low process difficulty; a modern 2.5-dimensional stereo processing technology based on deep trench etching is adopted, which is conducive to structural miniaturization and high-density design, and is more adapted to the development direction of modern integrated semiconductor devices exceeding Moore's Law.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices and integrated circuits, and in particular relates to a power semiconductor device and a manufacturing method thereof. Background Art

[0002] Inspired by superjunction technology based on charge balance in PN junctions, researchers have discovered that internal resistive field plates (RFPs) can function similarly to PN junctions and superjunctions. They have proposed several active device structures based on RFPs, which offer some performance advantages over PN junctions and superjunctions. Since the 1970s, RFPs have been used in high-voltage power semiconductor devices, primarily on their surfaces or edges, with limited use within the device itself.

[0003] At the same time, the active cell structure of the high-voltage power semiconductor device withstands a high voltage. In order to improve its voltage resistance, it is necessary to set a voltage-resistant terminal structure on the periphery of the active cell structure; however, like the PN junction and superjunction structure, in the device structure, the active cell structure precedes the voltage-resistant terminal structure, and a voltage-resistant terminal structure based on an internal resistive field plate has not been found in the prior art.

[0004] Therefore, how to propose a voltage-resistant terminal structure based on an internal resistive field plate is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a technical solution for an internal resistor field plate terminal voltage-resistant structure to solve the above-mentioned technical problems.

[0006] In order to achieve the above-mentioned purpose and other related purposes, the technical solutions provided by the present invention are as follows.

[0007] A power semiconductor device, comprising:

[0008] a substrate having a front surface and a back surface disposed opposite to each other;

[0009] an epitaxial layer, disposed on the front surface of the substrate, comprising a cell region and a terminal region adjacently disposed in a first plane, wherein the terminal region surrounds the cell region;

[0010] an active region, disposed in the cell region and located on top of the epitaxial layer, with a cell structure formed therein;

[0011] a plurality of first resistive field plate structures, disposed in a cell region of the epitaxial layer, extending through the epitaxial layer along a first direction into the substrate, and extending within the first plane along a second direction;

[0012] a plurality of second resistive field plate structures, disposed in a terminal region of the epitaxial layer, extending through the epitaxial layer along the first direction and into the substrate, wherein the plurality of second resistive field plate structures are radially arranged in the first plane, extending from a side close to the cell region to a side away from the cell region;

[0013] a first electrode, disposed on a cell region of the epitaxial layer and in ohmic contact with each of the first resistive field plate structures;

[0014] a second electrode, disposed on a side of the terminal region of the epitaxial layer close to the cell region, in ohmic contact with each of the second resistive field plate structures, and surrounding the first electrode;

[0015] a third electrode, disposed on a side of the terminal region of the epitaxial layer away from the cell region, in ohmic contact with each of the second resistive field plate structures, and surrounding the second electrode;

[0016] a fourth electrode, disposed on the back surface of the substrate and in ohmic contact with each of the first resistive field plate structures and each of the second resistive field plate structures through the substrate;

[0017] The first plane is parallel to the front surface of the substrate, and the first direction is perpendicular to the first plane.

[0018] Optionally, in the first plane, the second resistive field plate structure at the corner of the terminal region is arranged to form an angle of 45° with the second direction.

[0019] Optionally, in the first plane, transitioning from a corner of the terminal region to a flat edge of the terminal region, at least one of the second resistive field plate structures is in a Y-shape.

[0020] Optionally, within the first plane, a minimum distance between the third electrode electrical contact and the second electrode electrical contact is greater than or equal to a dimension of the first resistive field plate structure along the first direction.

[0021] Optionally, within the first plane, multiple first resistive field plate structures are arranged at equal intervals along a third direction according to a first spacing, and the minimum distance between two adjacent second resistive field plate structures is less than or equal to the first spacing, wherein the third direction is perpendicular to the second direction.

[0022] Optionally, the power semiconductor device further includes a channel-blocking layer, which is arranged in a terminal region of the epitaxial layer and located on top of the epitaxial layer, and the doping type of the channel-blocking layer is the same as that of the epitaxial layer.

[0023] Optionally, the power semiconductor device further includes a RESURF doped region, which is arranged in the terminal region of the epitaxial layer and located on the top of the epitaxial layer. Within the first plane, the RESURF doped region surrounds the active region, the inner edge of the RESURF doped region is equal to the potential of the cellular structure in the active region, and the outer edge of the RESURF doped region is surrounded by the third electrode.

[0024] Optionally, the power semiconductor device further includes at least one of a voltage-resistant ring, a resistive field plate, a field plate, and a variable doping terminal structure.

[0025] Optionally, the cellular structure includes at least: a diode cellular structure, a MOSFET cellular structure, a triode cellular structure and an IGBT cellular structure.

[0026] A method for manufacturing a power semiconductor device, comprising the steps of:

[0027] Providing a substrate having a front side and a back side opposite to each other, and forming an epitaxial layer on the front side of the substrate, wherein the epitaxial layer includes a cell region and a terminal region adjacent to each other in a first plane, wherein the terminal region surrounds the cell region;

[0028] forming an active region in a cell region of the epitaxial layer, and forming a cell structure in the active region;

[0029] forming a plurality of first trenches in a cell region of the epitaxial layer and forming a plurality of second trenches in a terminal region of the epitaxial layer, wherein the first trenches pass through the active region and the epitaxial layer along a first direction and enter the substrate, and the second trenches pass through the epitaxial layer along the first direction to the substrate;

[0030] forming a first resistive field plate structure in the first trench and forming a second resistive field plate structure in the second trench;

[0031] forming a first electrode, a second electrode, and a third electrode independently of each other on the epitaxial layer, and forming a fourth electrode on the back side of the substrate, wherein the first electrode is in ohmic contact with each of the first resistive field plate structures, the second electrode is in ohmic contact with each of the second resistive field plate structures, the third electrode is in ohmic contact with each of the second resistive field plate structures, and the fourth electrode is in ohmic contact with each of the first resistive field plate structures and each of the second resistive field plate structures through the substrate;

[0032] The first plane is parallel to the front surface of the substrate, the first direction is perpendicular to the first plane, and the first trench and the second trench are formed by the same process.

[0033] Optionally, after providing the substrate and forming the epitaxial layer, and before forming the first trench and the second trench, the method for manufacturing the power semiconductor device further includes the following steps:

[0034] forming a RESURF doped region in a termination region of the epitaxial layer, wherein in the first plane, the RESURF doped region surrounds the active region, an inner edge of the RESURF doped region coincides with an inner edge of the termination region, and an outer edge of the RESURF doped region is surrounded by an outer edge of the termination region;

[0035] A channel-stop layer is formed in a termination region of the epitaxial layer, wherein the channel-stop layer coincides with an outer edge of the termination region.

[0036] Optionally, within the first plane, multiple first grooves extend along the second direction within the first plane, and multiple first grooves are arranged at equal intervals along the third direction according to the first spacing, and multiple second grooves are arranged radially within the first plane, extending from the side close to the cell area to the side away from the cell area, and the minimum distance between two adjacent second grooves is less than or equal to the first spacing, wherein the third direction is perpendicular to the second direction.

[0037] Optionally, in the first plane, the second groove at the corner of the terminal area is arranged to form an angle of 45° with the second direction.

[0038] Optionally, in the first plane, at least one of the second grooves is in a Y-shape at the transition from the corner of the terminal area to the flat edge of the terminal area.

[0039] Optionally, the step of forming a first resistive field plate structure in the first trench and forming a second resistive field plate structure in the second trench includes:

[0040] forming a field plate dielectric layer in the first trench and the second trench respectively;

[0041] removing the field plate dielectric layer at the bottom of the first trench and the bottom of the second trench;

[0042] Semi-insulating polysilicon material is filled into the first trench and the second trench respectively. The semi-insulating polysilicon material in the first trench and the field plate dielectric layer at the sidewall position constitute the first resistive field plate structure. The semi-insulating polysilicon material in the second trench and the field plate dielectric layer at the sidewall position constitute the second resistive field plate structure.

[0043] Optionally, the step of forming a first electrode, a second electrode, and a third electrode independently of each other on the epitaxial layer, and forming a fourth electrode on the back side of the substrate includes:

[0044] forming an isolation dielectric layer on the epitaxial layer;

[0045] Etching the isolation dielectric layer to form a plurality of first openings on the cell region of the epitaxial layer, and forming a second opening and a third opening independent of each other on the terminal region of the epitaxial layer, wherein the third opening surrounds the second opening, the plurality of first openings correspondingly expose the tops of the plurality of first resistive field plate structures, and the second opening and the third opening respectively expose the tops of the respective second resistive field plate structures;

[0046] forming a first metal layer on the isolation dielectric layer;

[0047] Etching the first metal layer to form the first electrode, the second electrode, and the third electrode, wherein the first electrode passes through the first opening to make ohmic contact with the top of each first resistive field plate structure, the second electrode passes through the second opening to make ohmic contact with the top of each second resistive field plate structure, and the third electrode passes through the third opening to make ohmic contact with the top of each second resistive field plate structure;

[0048] A second metal layer is formed on the back surface of the substrate to obtain the fourth electrode, and the fourth electrode is in ohmic contact with the bottom of each first resistive field plate structure and the bottom of each second resistive field plate structure through the substrate.

[0049] Optionally, a plurality of first openings extend in the first plane along the second direction, and a plurality of first openings are spaced apart in the first plane along the third direction.

[0050] Optionally, within the first plane, a minimum distance between the third opening and the second opening is greater than or equal to a dimension of the first resistive field plate structure along the first direction.

[0051] As described above, the power semiconductor device and the manufacturing method thereof of the present invention have the following beneficial effects:

[0052] 1) In the terminal region of the epitaxial layer, a plurality of second resistive field plate structures are provided, extending along a first direction through the epitaxial layer and into the substrate. The plurality of second resistive field plate structures are radially arranged in a first plane, extending from a side close to the cell region to a side away from the cell region. The plurality of tightly coupled second resistive field plate structures form a more uniform three-dimensional electric field distribution that radiates in all directions, thereby optimizing the guiding and confining effect of the terminal region on the charge in the spatial depletion region of the cell region, thereby improving the withstand voltage performance of the entire power semiconductor device.

[0053] 2) The second resistive field plate structure in the terminal region and the first resistive field plate structure in the cell region are both second-generation superjunction technology based on in-vivo resistive field plates, making the processes of the cell region and the terminal region compatible, with low manufacturing cost and low process difficulty;

[0054] 3) In terms of technology, a modern 2.5-dimensional stereo processing technology based on deep trench etching is adopted, which is conducive to the miniaturization and high-density design of the structure, and is more in line with the development direction of More than Moore of modern integrated semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Shown is a schematic structural diagram of a power semiconductor device in Embodiment 1 of the present invention.

[0056] Figure 2-Figure 6 It shows a schematic diagram of the shape structure of the second electrode 7 and the third electrode 8 on the power semiconductor device in other optional embodiments of the present invention.

[0057] Figure 7 Shown is a schematic diagram of the steps of a method for manufacturing a power semiconductor device in a first embodiment of the present invention.

[0058] Figure 8-Figure 39 Shown is a process flow chart of a method for manufacturing a power semiconductor device in a first embodiment of the present invention.

[0059] Figure 40 Shown is a schematic structural diagram of a power semiconductor device in the second embodiment of the present invention.

[0060] Explanation of Figure Numbers

[0061] 1—substrate, 2—epitaxial layer, 3—active region, 4—first resistive field plate structure, 5—second resistive field plate structure, 6—first electrode, 7—second electrode, 8—third electrode, 9—fourth electrode, 10—channel stop layer, 11—isolation dielectric layer, 12—first metal layer, 13—second metal layer, 14—RESURF doping, 00—field plate dielectric layer, 01—semi-insulating polysilicon material, 20—top dielectric layer, a—cell region of epitaxial layer 2, b—terminal region of epitaxial layer 2, T1 —first trench, T2—second trench, D1—dimension of the first trench T1 along the third direction (trench width), L1—dimension of the first trench T1 along the first direction, L2—minimum length of the second trench T2 in the first plane, W1—distance between two adjacent first resistive field plate structures 4 in the first plane (first spacing), W2—minimum distance between two adjacent second resistive field plate structures 5 (or second trenches T2) in the first plane, K1—first opening, K2—second opening, K3—third opening. DETAILED DESCRIPTION

[0062] The inventors have found that in current superjunction structure devices or quasi-superjunction structure devices, the optimization of the device breakdown voltage is mostly concentrated inside the cellular structure, while the peripheral terminal structure is mostly set on the surface of the device, which has limited effect on improving the device's voltage resistance performance.

[0063] Based on this, the present invention proposes a terminal voltage-withstanding technology solution based on an internal resistance field plate: multiple internal resistance field plate structures are formed in the peripheral terminal area surrounding the cell area, and starting from the outer edge of the cell area, multiple second resistance field plate structures are radially arranged to the surrounding areas. Through multiple tightly coupled second resistance field plates, a more uniform three-dimensional electric field distribution radiating to the surrounding areas is formed to optimize the guiding and binding effect of the terminal area on the charge in the spatial depletion area of ​​the cell area, thereby improving the voltage-withstanding performance of the power semiconductor device.

[0064] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] See also Figures 1 to 40 . It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention rather than being drawn according to the number, shape and size of the components during actual implementation. During actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated. The structure, proportion, size, etc. illustrated in the illustrations of this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no technical significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention.

[0066] Example 1

[0067] like Figure 1 As shown, an embodiment of the present invention provides a power semiconductor device, which includes:

[0068] A substrate 1 having a front surface and a back surface opposite to each other;

[0069] An epitaxial layer 2 is provided on the front surface of the substrate 1 and includes a cell region a and a terminal region b adjacent to each other in a first plane, wherein the terminal region b surrounds the cell region a;

[0070] The active region 3 is arranged in the cell region a and is located on top of the epitaxial layer 2, and an active region cell structure is formed therein;

[0071] A plurality of first resistive field plate structures 4 are arranged in the cell region a of the epitaxial layer 2 and extend along a first direction ( Figure 1 The Z-axis direction) extends through the epitaxial layer 2 to the substrate 1, and the plurality of first resistive field plates 4 are arranged along the second direction ( Figure 1 Y-axis direction) in the first plane (i.e. Figure 1 Extends within the XY plane in the

[0072] a plurality of second resistive field plate structures 5, disposed in the terminal region b of the epitaxial layer 2, extending through the epitaxial layer 2 along the first direction into the substrate 1, wherein the plurality of second resistive field plate structures 5 are radially arranged in the first plane, extending from a side close to the cell region a to a side away from the cell region a;

[0073] A first electrode 6 is provided on the cell region a of the epitaxial layer 2 and is in ohmic contact with each first resistive field plate structure 4;

[0074] The second electrode 7 is provided on a side of the terminal region b of the epitaxial layer 2 close to the cell region a, and is in ohmic contact with each second resistive field plate structure 5 , and the second electrode 7 surrounds the first electrode 6 ;

[0075] The third electrode 8 is arranged on a side of the terminal region b of the epitaxial layer 2 away from the cell region a, and is in ohmic contact with each second resistive field plate structure 5, and the third electrode 8 surrounds the second electrode 7;

[0076] a fourth electrode 9 , disposed on the back surface of the substrate 1 , and in ohmic contact with each of the first resistive field plate structures 4 and each of the second resistive field plate structures 5 through the substrate 1 ;

[0077] The first plane is parallel to the front surface of the substrate 1 , and the first direction is perpendicular to the first plane.

[0078] In detail, such as Figure 1 As shown, the epitaxial layer 2 includes a cell region a and a terminal region b adjacently arranged in a first plane, and the terminal region b surrounds the cell region a. It should be noted that, Figure 1 Only 1 / 4 of the complete power semiconductor device is shown, and the structure of the remaining part is the same as that of the 1 / 4 part.

[0079] In detail, such as Figure 1 As shown, an active area 3 is formed in the cell area a of the epitaxial layer 2, and a cellular structure is formed in the active area 3. The cellular structure includes at least a diode cellular structure, a MOSFET cellular structure, a triode cellular structure and an IGBT cellular structure, etc., which are not limited here.

[0080] In detail, such as Figure 1 As shown, the power semiconductor device further includes a channel blocking layer 10, which is arranged in the terminal region b of the epitaxial layer 2 and located on the top of the epitaxial layer 2. The channel blocking layer 10 has the same doping type as the epitaxial layer 2 and is substantially at the same potential as the third electrode 9 when the device is turned off.

[0081] In detail, such as Figure 1 As shown, in the first plane, the second resistive field plate structure 5 at the corner of the terminal region b is arranged at a 45° angle to the second direction (Y-axis direction); in the first plane, from the corner of the terminal region b to the flat edge of the terminal region b, at least one second resistive field plate structure 5 is Y-shaped.

[0082] In detail, such as Figure 1 As shown, in the first plane, the minimum distance L2 between the electrical contact of the third electrode 8 and the electrical contact of the second electrode 7, that is, the energized distance of the second resistive field plate structure 5 in the first plane, is greater than or equal to the dimension L1 of the first resistive field plate structure 4 along the first direction.

[0083] In detail, such as Figure 1 As shown, in the first plane, a plurality of first resistive field plate structures 4 are arranged along the third direction ( Figure 1 The second resistive field plate structures 5 are arranged at equal intervals according to the first interval W1 in the X-axis direction, and the minimum distance W2 between two adjacent second resistive field plate structures 5 is less than or equal to the first interval W1, wherein the third direction is perpendicular to the second direction.

[0084] In detail, in the first plane, the shape of the second electrode 7 at the corner is not limited to Figure 1 The broken line shown can also be a quarter arc, a quarter ellipse or a cut angle, etc., instead of a right angle, such as Figure 2-Figure 6 As shown, the electric field distribution at the corner is optimized and the tip discharge effect is reduced. Correspondingly, the shape of the third electrode 8 at the corner is not limited to Figure 1 The right angle shape shown in FIG can also be an arc, an ellipse, a broken line or a cut corner, such as Figure 2-Figure 6 As shown, there is no limitation here, and it only needs L2 ≥ L1.

[0085] At the same time, if Figure 7 As shown, an embodiment of the present invention further provides a method for manufacturing a power semiconductor device, which includes the steps of:

[0086] S1. Providing a substrate 1 having a front side and a back side opposite to each other, and forming an epitaxial layer 2 on the front side of the substrate 1, wherein the epitaxial layer 2 includes a cell region a and a terminal region b adjacent to each other in a first plane, wherein the terminal region b surrounds the cell region a;

[0087] S2. forming an active region 3 in the cell region a of the epitaxial layer 2 and forming a cell structure in the active region 3;

[0088] S3. Form a plurality of first trenches T1 in the cell region a of the epitaxial layer 2, and form a plurality of second trenches T2 in the terminal region b of the epitaxial layer 2, wherein the first trenches T1 pass through the active region 3 and the epitaxial layer 2 along the first direction and enter the substrate 1, and the second trenches T2 pass through the epitaxial layer 2 along the first direction and enter the substrate 1;

[0089] S4, forming a first resistive field plate structure 4 in the first trench T1, and forming a second resistive field plate structure 5 in the second trench T2;

[0090] S5. Forming a first electrode 6, a second electrode 7, and a third electrode 8 independently of each other on the epitaxial layer 2, and forming a fourth electrode 9 on the back side of the substrate 1, wherein the first electrode 6 is in ohmic contact with each first resistive field plate structure 4, the second electrode 7 is in ohmic contact with each second resistive field plate structure 5, the third electrode 8 is in ohmic contact with each second resistive field plate structure 5, and the fourth electrode 9 is in ohmic contact with each first resistive field plate structure 4 and each second resistive field plate structure 5 through the substrate 1;

[0091] The first plane is parallel to the front surface of the substrate 1 , the first direction is perpendicular to the first plane, and the first trench T1 and the second trench T2 are formed by the same process.

[0092] The following uses a high-voltage diode (i.e., the cellular structure within the cell region a is a diode cellular structure) as an example to illustrate the implementation of the solution, and other methods that can achieve the content and features of the present invention should not be considered to be different from this solution. The specific process method for forming the deep-grooved internal resistor field plate has been described in detail in our previous published patent application documents, and other processes are familiar to those skilled in the art. The present invention will not specifically describe the specific deep-grooved internal resistor field plate process details here, but will only reasonably describe the main process methods in order to illustrate the necessary process steps and methods for realizing the aforementioned terminal structure in the implementation examples. The processes described in the following examples are all existing mature processes, and are not described in very detailed detail. General technicians in this industry understand and appreciate them.

[0093] Before executing the production manufacturing process, the key dimensions and shape structures of the power semiconductor device are first designed. Through computer-aided design, it is determined that the first spacing W1 between two adjacent first resistive field plate structures 4 in the active area 3 along the third direction is selected as 5 μm; the minimum distance W2 between two adjacent second resistive field plate structures 5 in the terminal area b around the active area 3 is selected as 90% of 5 μm, that is, 4.5 μm; the dimension (or depth) L1 of the first resistive field plate structure 4 (and the second resistive field plate structure 5) along the first direction is taken as 22 μm, and the minimum distance L2 between the third electrode 8 and the second electrode 7 in the first plane is also the minimum length of the second resistive field plate structure 5 in the first plane. According to the rule that L2 is greater than or equal to L1, combined with computer-aided design, L2 is taken as 30 μm; at the corner of the terminal area b, in the first plane, the second resistive field plate structure 5 at the corner of the cell area b is designed to be at a 45° angle to the second direction.

[0094] In detail, such as Figure 8 As shown, in step S1, a substrate 1 is provided as the drain region of the device, which is an N-type doped semiconductor material (such as silicon, silicon carbide, gallium arsenide, etc.); an epitaxial layer 2 is formed on the substrate 1 as the drift region of the device, and the epitaxial layer 2 is also an N-type doped semiconductor material. Among them, the substrate 1 is heavily doped and the epitaxial layer 2 is lightly doped; the thickness of the epitaxial layer 2 can be flexibly designed according to the situation. For example, for a breakdown voltage of 300V, the thickness of the epitaxial layer 2 can be designed to be 20μm to meet the requirement that the bottom of the first resistive field plate structure 4 enters the substrate 1. This is determined by computer-aided design verification, and the doping concentration is selected to be 2.8×10 15 cm -2 .

[0095] In more detail, Figures 1-6 As shown, the epitaxial layer 2 includes a cell region a and a terminal region b adjacently arranged in a first plane, and the terminal region b surrounds the cell region a. It should be noted that, Figure 1 Only 1 / 4 of the complete power semiconductor device is shown, and the structure of the remaining part is the same as that of the 1 / 4 part.

[0096] In detail, between step S1 and step S2, the method for manufacturing the power semiconductor device further includes the step of forming a photolithography alignment mark on the epitaxial layer 2 using an industry-standard method to facilitate alignment in subsequent process steps.

[0097] In detail, such as Figure 9 As shown, between step S1 and step S2, the method for manufacturing the power semiconductor device further includes the step of: oxidizing the top of the epitaxial layer 2 using a general process to obtain a top dielectric layer 20, such as wet oxidation at 950°C for 20 minutes to obtain a top dielectric layer 20 with a thickness of about 60nm±10nm.

[0098] In detail, such as Figure 10 As shown, in step S2 , an active region 3 is formed in the cell region a of the epitaxial layer 2 , and a cell structure (not shown in the figure) is formed in the active region 3 .

[0099] In more detail, Figure 10 As shown, the first ion implantation and the first ion diffusion are performed to form the active region 3 in the cell region a on the top of the epitaxial layer 2: the first ion implantation is performed first. Since a simple diode is used as an example to illustrate the technical solution of the present invention, the active region 3 of the device function can be simply photolithographically performed, such as boron implantation with photoresist, and the implantation conditions are 100Kev, 5×10 14 cm -2 Then, the first ion diffusion is carried out under the protection of an inert gas to diffuse and activate the impurities, such as ion diffusion at 1050°C for 90 minutes, to form an active region 3 in the cell region a at the top of the epitaxial layer 2.

[0100] Among them, the cell structure formed in the active area 3 can be a diode cell structure, a MOSFET cell structure, a triode cell structure with small minority carrier injection, and an IGBT cell structure (in the case of IGBT, the substrate is at least partially P-type doped), which is not limited here.

[0101] In detail, such as Figure 11 As shown, between step S2 and step S3, the method for manufacturing a power semiconductor device further includes the following steps: firstly, photolithography of the channel blocking layer 10 is performed, photoresist is used as a shielding mask, and phosphorus ion implantation is performed, and the implantation condition is 5×10 15 cm -2 , 170keV, a channel stop layer 10 is formed in the terminal region b of the epitaxial layer 2, and the channel stop layer 10 coincides with the outer edge of the terminal region b.

[0102] In detail, such as Figure 12 As shown, in step S3, a plurality of first trenches T1 are formed in the cell region a of the epitaxial layer 2, and a plurality of second trenches T2 are formed in the terminal region b of the epitaxial layer 2. The first trenches T1 pass through the active region 3 and the epitaxial layer 2 along the first direction into the substrate 1, and the second trenches T2 pass through the epitaxial layer 2 along the first direction into the substrate 1.

[0103] In more detail, Figure 12-13As shown, a photolithography machine and a corresponding photomask are used to expose the positions of the first resistive field plate structure 4 and the second resistive field plate structure 5, and then a dry etching process is used to sequentially etch the field plate dielectric layer 20, the epitaxial layer 2 and the substrate 1, and simultaneously form a first trench T1 and a second trench T2. The first trench T1 (or the second trench T2) vertically penetrates the epitaxial layer 2 and the substrate 1 to a depth L1 of 22 μm and a trench width D1 of 0.8 to 1.2 μm. It should be noted that the multiple second trenches T2 in the terminal region b do not necessarily have to pass through the channel blocking layer 10, although Figure 13 It is given in the way of passing through.

[0104] In more detail, Figure 14 As shown, in the first plane, multiple first trenches T1 extend in the first plane along the second direction, and multiple first trenches T1 are arranged at equal intervals along the third direction according to the first spacing W1. In the terminal area b, multiple second trenches T2 are arranged radially, extending from the side close to the cell area a to the side away from the cell area a, and the minimum distance W2 between two adjacent second trenches T2 is less than or equal to the first spacing W1.

[0105] In more detail, Figure 12-14 As shown, the first spacing W1 along the third direction between two adjacent first trenches T1 in the active area 3 is selected to be 5 μm. The minimum distance W2 between two adjacent second trenches T2 in the terminal region b around the active area 3 is selected to be 90% of 5 μm, that is, 4.5 μm. That is, W1>W2.

[0106] In more detail, as shown in Figure 14, the minimum length L2 of the second groove T2 in the first plane is 30 μm, which is greater than the depth L1 of the first groove T1 (or the second groove T2) along the first direction; at the corner of the terminal area b, in the first plane, the second groove T2 at the corner of the cell area b is designed to form a 45° angle with the second direction; at the same time, in the first plane, from the corner of the terminal area b to the flat edge of the terminal area b, at least one second groove T2 has a Y-shape.

[0107] In detail, such as Figures 15-21 As shown, step S4 of forming the first resistive field plate structure 4 in the first trench T1 and forming the second resistive field plate structure 5 in the second trench T2 includes:

[0108] S41, such as Figure 15-16 As shown, a field plate dielectric layer 00 is formed in the first trench T1 and the second trench T2 respectively;

[0109] S42, such as Figure 17-18 As shown, the field plate dielectric layer 00 at the bottom of the first trench T1 and the bottom of the second trench T2 is removed;

[0110] S43, such as Figures 19-21As shown, semi-insulating polysilicon material 01 is filled into the first trench T1 and the second trench T2 respectively. The semi-insulating polysilicon material 01 in the first trench T1 and the field plate dielectric layer 00 at the sidewall position constitute a first resistive field plate structure 4. The semi-insulating polysilicon material 01 in the second trench T2 and the field plate dielectric layer 00 at the sidewall position constitute a second resistive field plate structure 5.

[0111] In more detail, Figure 15-16 As shown, in step S41, the bottom and sidewalls of the first trench T1 and the second trench T2 are oxidized by a common process to obtain a field plate dielectric layer 00, such as wet oxidation at 950°C for 90 minutes to obtain a field plate dielectric layer 00 with a thickness of about 200nm±10nm.

[0112] In more detail, Figure 17-18 As shown, in step S42 , the field plate dielectric layer 00 at the bottom of the first trench T1 and the second trench T2 is removed by anisotropic dry etching, but the field plate dielectric layer 00 at the sidewalls of the first trench T1 and the second trench T2 is retained.

[0113] In more detail, Figures 19-21 As shown, in step S43, the first trench T1 and the second trench T2 are filled with a semi-insulating polysilicon material 01, such as by using a low-pressure chemical vapor deposition process, with a deposition thickness of 1.1 μm ± 0.1 μm; the semi-insulating polysilicon material 01 except the first trench T1 and the second trench T2 is removed, or a photomask is used to retain the semi-insulating polysilicon material 01 on the surface between the second electrode 7 and the third electrode 8 in the terminal region b so as not to be reverse etched (not shown in the figure).

[0114] In more detail, Figures 22-39 As shown, step S5 of forming a mutually independent first electrode 6, a second electrode 7 and a third electrode 8 on the epitaxial layer 2 and forming a fourth electrode 9 on the back side of the substrate 1 further includes:

[0115] S51, such as Figure 22-24 As shown, an isolation dielectric layer 11 is formed on the epitaxial layer 2;

[0116] S52, such as Figure 25-27 As shown, the isolation dielectric layer 11 is etched to form a plurality of first openings K1 on the cell region a of the epitaxial layer 2, and a second opening K2 and a third opening K3 that are independent of each other are formed on the terminal region b of the epitaxial layer 2. The third opening K3 surrounds the second opening K2. The plurality of first openings K1 expose the tops of the plurality of first resistive field plate structures 4 in a one-to-one correspondence, and the second openings K2 and the third openings K3 expose the tops of the respective second resistive field plate structures 5.

[0117] S53, such as Figures 28-30As shown, a first metal layer 12 is formed on the isolation dielectric layer 11;

[0118] S54, such as Figures 31-36 As shown, the first metal layer 12 is etched to form a first electrode 6, a second electrode 7 and a third electrode 8. The first electrode 6 passes through the first opening K1 to make ohmic contact with the top of each first resistive field plate structure 4, the second electrode 7 passes through the second opening K2 to make ohmic contact with the top of each second resistive field plate structure 5, and the third electrode 8 passes through the third opening K3 to make ohmic contact with the top of each second resistive field plate structure 5.

[0119] S55, such as Figure 37-Figure 39 As shown, a second metal layer 13 is formed on the back side of the substrate 1 to obtain a fourth electrode 9 , which is in ohmic contact with the bottom of each first resistive field plate structure 4 and the bottom of each second resistive field plate structure 5 through the substrate 1 .

[0120] In step S54, if Figures 31-36 As shown, multiple first openings K1 extend in the first plane along the second direction, and multiple first openings K1 are spaced apart in the first plane along the third direction. In the first plane, the minimum distance between the third opening K3 and the second opening K2 is greater than or equal to the dimension L1 of the first resistive field plate 4 structure along the first direction.

[0121] in, Figure 33 Shown along Figure 32 The cross-sectional view of AA', Figure 34-Figure 35 To follow Figure 32 The cross-sectional view of BB', Figure 34 The second resistive field plate structure 5 passes through the channel blocking layer 10, and Figure 35 The second resistive field plate structure 5 does not pass through the channel blocking layer 10 . These are two different structural designs, which can be selected according to the actual situation.

[0122] Correspondingly, in step S55, Figure 37 Shown along Figure 32 The cross-sectional view of AA', Figure 38-Figure 39 To follow Figure 32 The cross-sectional view of BB', Figure 38 The second resistive field plate structure 5 passes through the channel blocking layer 10, and Figure 39 The second resistive field plate structure 5 does not pass through the channel blocking layer 10 . These are two different structural designs, which can be selected according to the actual situation.

[0123] Finally, we get Figure 39 or Figure 1The power semiconductor device shown in the figure is a power semiconductor device of the present invention. A plurality of second resistive field plate structures 5 are arranged in the terminal region b of the epitaxial layer, extending through the epitaxial layer 2 in the first direction and into the substrate 1. The plurality of second resistive field plate structures 5 are radially arranged in the first plane, extending from the side close to the cell region a to the side away from the cell region a. The plurality of tightly coupled second resistive field plate structures 5 form a more uniform three-dimensional electric field distribution that diverges in all directions, thereby optimizing the guiding and binding effect of the terminal region b on the charge in the spatial depletion region of the cell region a, thereby improving the voltage resistance performance of the entire power semiconductor device. The second resistive field plate structure 5 in the terminal region b and the first resistive field plate structure 4 in the cell region a are both second-generation super junction technology based on internal resistive field plates, so that the processes of the cell region a and the terminal region b are compatible, the manufacturing cost is low, and the process difficulty is low. In terms of process, a modern 2.5-dimensional stereo processing technology based on deep trench etching is adopted, which is conducive to structural miniaturization design and high-density design, and is more adapted to the development direction of modern integrated semiconductor devices beyond Moore's Law.

[0124] It should be noted that the above steps are only one sequence for implementing the deep-trench internal resistive field plate power semiconductor device technology solution. Other sequences that can also achieve similar structures and their inherent functions are also feasible. For example, steps S3-S4 for forming the first resistive field plate structure 4 and the second resistive field plate structure 5 can be interchanged with step S2, and similar structures and effects can be achieved without changing other steps. Furthermore, there are countless other specific implementation sequences and combinations of specific process parameters and sequences that can achieve almost identical structures and functions, which are not listed here. In addition, the steps in the above embodiment omit well-known and obvious simple processes and conditions such as general industry cleaning. These are well known to those skilled in the art and will not be described in detail here.

[0125] Example 2

[0126] On the basis of the first embodiment of the present invention, in order to further optimize the terminal withstand voltage protection effect of the power semiconductor device, the surface semi-insulating polysilicon material 01 between the second electrode 7 and the third electrode 8 in the terminal region b can be retained, and a RESURF doped region can be formed in the terminal region b.

[0127] In detail, such as Figure 40As shown, an embodiment of the present invention provides a power semiconductor device, which includes a RESURF doping region 14. The RESURF doping region 14 is arranged in the terminal region b of the epitaxial layer 2 and is located on the top of the epitaxial layer 2. In a first plane, the RESURF doping region 14 surrounds the active region 3. The inner edge of the RESURF doping region 14 coincides with the inner edge of the terminal region b, and the outer edge of the RESURF doping region is surrounded by the outer edge of the terminal region b, so that the inner edge of the RESURF doping region 14 is equal to the potential of the cell structure in the active region 3. The outer edge of the RESURF doping region 14 is surrounded by the third electrode 8.

[0128] Correspondingly, an embodiment of the present invention provides a method for manufacturing a power semiconductor device. After providing a substrate 1 and forming an epitaxial layer 2, and before forming a first trench T1 and a second trench T2, the method for manufacturing a power semiconductor device further includes the following steps:

[0129] Stp1. A RESURF doped region 14 is formed in the terminal region b of the epitaxial layer 2. In the first plane, the RESURF doped region 14 surrounds the active region 3. The inner edge of the RESURF doped region 14 coincides with the inner edge of the terminal region b, and the outer edge of the RESURF doped region 14 is surrounded by the outer edge of the terminal region b.

[0130] Specifically, in step Stp1, the RESURF doping region 14 is first photolithographically formed, and a photoresist is used as a shielding mask to perform boron ion implantation. The implantation conditions are (2-5)×10 12 cm -2 , 170kev; and then perform impurity diffusion activation. The impurity diffusion activation of the RESURF doped region 14 can be performed synchronously with the impurity diffusion activation of the active region 3.

[0131] It can be understood that the power semiconductor device can also include at least one of a voltage-resistant ring, a resistive field plate, a field plate, and a variable doping terminal structure to reduce the peak electric field at the corner of the PN junction, which are traditional planar process terminal structures, and are used to replace or combine with the RESURF doping area 14 to achieve similar voltage-resistant function improvements, which are effective to varying degrees.

[0132] It should be noted that the other structures of the power semiconductor device of the embodiment of the present invention are the same as those of the first embodiment, and the other process steps of the method for manufacturing the power semiconductor device of the embodiment of the present invention can refer to the first embodiment and will not be repeated here. In summary, the present invention provides a power semiconductor device and a method for manufacturing the same, in which a plurality of second resistive field plate structures are arranged in the terminal region of the epitaxial layer along the first direction, extending through the epitaxial layer into the substrate, and the plurality of second resistive field plate structures are arranged radially in the first plane, extending from the side close to the cell region to the side away from the cell region, and the plurality of tightly coupled second resistive field plate structures form a more uniform three-dimensional electric field distribution that diverges in all directions, thereby optimizing the guiding and binding effect of the charge in the spatial depletion region of the cell region and improving the voltage resistance of the entire power semiconductor device; the second resistive field plate structure in the terminal region and the first resistive field plate structure in the cell region are both second-generation super junction technology based on internal resistive field plates, with process compatibility, low manufacturing cost, and low process difficulty; the modern 2.5-dimensional stereo processing technology based on deep trench etching is adopted, which is conducive to structural miniaturization and high-density design, and is more adapted to the development direction of modern integrated semiconductor devices beyond Moore's law.

[0133] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A power semiconductor device, characterized in that: include: a substrate having a front surface and a back surface disposed opposite to each other; an epitaxial layer, disposed on the front surface of the substrate, comprising a cell region and a terminal region adjacently disposed in a first plane, wherein the terminal region surrounds the cell region; an active region, disposed in the cell region and located on top of the epitaxial layer, with a cell structure formed therein; a plurality of first resistive field plate structures, disposed in a cell region of the epitaxial layer, extending through the epitaxial layer along a first direction into the substrate, and extending within the first plane along a second direction; a plurality of second resistive field plate structures, disposed in a terminal region of the epitaxial layer, extending through the epitaxial layer along the first direction and into the substrate, wherein the plurality of second resistive field plate structures are radially arranged in the first plane, extending from a side close to the cell region to a side away from the cell region; a first electrode, disposed on a cell region of the epitaxial layer and in ohmic contact with each of the first resistive field plate structures; a second electrode, disposed on a side of the terminal region of the epitaxial layer close to the cell region, in ohmic contact with each of the second resistive field plate structures, and surrounding the first electrode; a third electrode, disposed on a side of the terminal region of the epitaxial layer away from the cell region, in ohmic contact with each of the second resistive field plate structures, and surrounding the second electrode; a fourth electrode, disposed on the back surface of the substrate and in ohmic contact with each of the first resistive field plate structures and each of the second resistive field plate structures through the substrate; Wherein, the first plane is parallel to the front surface of the substrate, and the first direction is perpendicular to the first plane; The first resistive field plate structure and the second resistive field plate structure both include a field plate dielectric layer and a semi-insulating polysilicon material, and the field plate dielectric layer is located on both sides of the semi-insulating polysilicon material.

2. The power semiconductor device according to claim 1, wherein: In the first plane, the second resistive field plate structure at the corner of the terminal region is arranged at an angle of 45° to the second direction.

3. The power semiconductor device according to claim 1, wherein: In the first plane, at a transition point from a corner of the terminal region to a flat edge of the terminal region, at least one of the second resistive field plate structures is in a Y-shape.

4. The power semiconductor device according to claim 1, wherein: In the first plane, a minimum distance between the third electrode electrical contact and the second electrode electrical contact is greater than or equal to a dimension of the first resistive field plate structure along the first direction.

5. The power semiconductor device according to claim 1, wherein: In the first plane, multiple first resistive field plate structures are arranged at equal intervals along a third direction according to a first spacing, and a minimum distance between two adjacent second resistive field plate structures is less than or equal to the first spacing, wherein the third direction is perpendicular to the second direction.

6. The power semiconductor device according to claim 5, characterized in that The power semiconductor device further includes a channel-blocking layer, which is arranged in a terminal region of the epitaxial layer and located on top of the epitaxial layer. The doping type of the channel-blocking layer is the same as that of the epitaxial layer.

7. The power semiconductor device according to claim 5, characterized in that The power semiconductor device also includes a RESURF doped region, which is arranged in the terminal region of the epitaxial layer and located on the top of the epitaxial layer. In the first plane, the RESURF doped region surrounds the active region, the inner edge of the RESURF doped region is equal to the potential of the cellular structure in the active region, and the outer edge of the RESURF doped region is surrounded by the third electrode.

8. The power semiconductor device according to claim 5, characterized in that The power semiconductor device further includes at least one of a voltage-resistant ring, a resistive field plate, a field plate, and a variable doping terminal structure.

9. The power semiconductor device according to any one of claims 1 to 8, characterized in that: The cell structure includes at least: a diode cell structure, a MOSFET cell structure, a triode cell structure and an IGBT cell structure.

10. A method for manufacturing a power semiconductor device, characterized in that: Including steps: Providing a substrate having a front side and a back side opposite to each other, and forming an epitaxial layer on the front side of the substrate, wherein the epitaxial layer includes a cell region and a terminal region adjacent to each other in a first plane, wherein the terminal region surrounds the cell region; forming an active region in a cell region of the epitaxial layer, and forming a cell structure in the active region; forming a plurality of first trenches in a cell region of the epitaxial layer and forming a plurality of second trenches in a terminal region of the epitaxial layer, wherein the first trenches pass through the active region and the epitaxial layer along a first direction and enter the substrate, and the second trenches pass through the epitaxial layer along the first direction to the substrate; forming a first resistive field plate structure in the first trench and forming a second resistive field plate structure in the second trench; forming a first electrode, a second electrode, and a third electrode independently of each other on the epitaxial layer, and forming a fourth electrode on the back side of the substrate, wherein the first electrode is in ohmic contact with each of the first resistive field plate structures, the second electrode is in ohmic contact with each of the second resistive field plate structures, the third electrode is in ohmic contact with each of the second resistive field plate structures, and the fourth electrode is in ohmic contact with each of the first resistive field plate structures and each of the second resistive field plate structures through the substrate; The first plane is parallel to the front surface of the substrate, the first direction is perpendicular to the first plane, and the first trench and the second trench are formed by the same process; The step of forming a first resistive field plate structure in the first trench and forming a second resistive field plate structure in the second trench comprises: forming a field plate dielectric layer in the first trench and the second trench respectively; removing the field plate dielectric layer at the bottom of the first trench and the bottom of the second trench; Semi-insulating polysilicon material is filled into the first trench and the second trench respectively. The semi-insulating polysilicon material in the first trench and the field plate dielectric layer at the sidewall position constitute the first resistive field plate structure. The semi-insulating polysilicon material in the second trench and the field plate dielectric layer at the sidewall position constitute the second resistive field plate structure.

11. The method for manufacturing a power semiconductor device according to claim 10, wherein: After providing the substrate and forming the epitaxial layer, and before forming the first trench and the second trench, the method for manufacturing the power semiconductor device further includes the following steps: forming a RESURF doped region in a termination region of the epitaxial layer, wherein in the first plane, the RESURF doped region surrounds the active region, an inner edge of the RESURF doped region coincides with an inner edge of the termination region, and an outer edge of the RESURF doped region is surrounded by an outer edge of the termination region; A channel-stop layer is formed in a termination region of the epitaxial layer, wherein the channel-stop layer coincides with an outer edge of the termination region.

12. The method for manufacturing a power semiconductor device according to claim 10 or 11, wherein: In the first plane, multiple first grooves extend in the first plane along the second direction, and multiple first grooves are arranged at equal intervals along the third direction according to the first spacing. Multiple second grooves are radially arranged in the first plane, extending from the side close to the cell area to the side away from the cell area, and the minimum distance between two adjacent second grooves is less than or equal to the first spacing, wherein the third direction is perpendicular to the second direction.

13. The method for manufacturing a power semiconductor device according to claim 12, wherein: In the first plane, the second groove at the corner of the terminal area is arranged at an angle of 45° to the second direction.

14. The method for manufacturing a power semiconductor device according to claim 12, wherein: In the first plane, at least one of the second grooves is in a Y-shape, transitioning from the corner of the terminal area to the flat edge of the terminal area.

15. The method for manufacturing a power semiconductor device according to claim 12, wherein: The step of forming a first electrode, a second electrode, and a third electrode independently of each other on the epitaxial layer and forming a fourth electrode on the back side of the substrate comprises: forming an isolation dielectric layer on the epitaxial layer; Etching the isolation dielectric layer to form a plurality of first openings on the cell region of the epitaxial layer, and forming a second opening and a third opening independent of each other on the terminal region of the epitaxial layer, wherein the third opening surrounds the second opening, the plurality of first openings correspondingly expose the tops of the plurality of first resistive field plate structures, and the second opening and the third opening respectively expose the tops of the respective second resistive field plate structures; forming a first metal layer on the isolation dielectric layer; Etching the first metal layer to form the first electrode, the second electrode, and the third electrode, wherein the first electrode passes through the first opening to make ohmic contact with the top of each first resistive field plate structure, the second electrode passes through the second opening to make ohmic contact with the top of each second resistive field plate structure, and the third electrode passes through the third opening to make ohmic contact with the top of each second resistive field plate structure; A second metal layer is formed on the back surface of the substrate to obtain the fourth electrode, and the fourth electrode is in ohmic contact with the bottom of each first resistive field plate structure and the bottom of each second resistive field plate structure through the substrate.

16. The method for manufacturing a power semiconductor device according to claim 15, wherein: A plurality of first openings extend in the first plane along the second direction, and a plurality of first openings are spaced apart in the first plane along the third direction.

17. The method for manufacturing a power semiconductor device according to claim 15, wherein: In the first plane, a minimum distance between the third opening and the second opening is greater than or equal to a dimension of the first resistive field plate structure along the first direction.

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