Shielded gate trench transistor with triangularly arranged source regions and method of manufacturing the same

Abstract

The application relates to a shield gate trench transistor with a triangular source region, which comprises a substrate region, a drift region, a base region, a source region, a shield gate, a control gate, an insulating layer, a source electrode, a drain electrode and a metal gate; the drift region, the base region and the source region are sequentially arranged on the top of the substrate region, and the drain electrode is located on the bottom of the substrate region; the control gate and the shield gate are sequentially arranged on the side of the drift region from top to bottom and are respectively connected with the drift region, the base region and the source region through the insulating layer; the source region comprises a P-type source region and an N-type source region; the P-type source region is a triangular source region with a triangular cross section, and the top angle of the triangular source region is connected with the insulating layer; the N-type source region comprises a first N-type source region and a second N-type source region; the first N-type source region and the second N-type source region are arranged on the two sides of the top angle and are respectively connected with the insulating layer. The scheme provided by the application can effectively inhibit the opening of a parasitic triode and effectively improve the avalanche resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a shielded gate trench transistor with a triangularly arranged source region and a method for fabricating the same. Background Technology

[0002] Shielded gate trench field-effect transistors (SGTs) offer advantages such as lower specific on-resistance, lower static and dynamic losses, and faster switching speeds. This is due to their ability to effectively isolate the coupling between the control gate and drain, resulting in significant advantages in channel density, charge compensation effect, and shielded gate structure.

[0003] In traditional SGTs, avalanche tolerance limits the maximum current of the transistor in inductive load applications. Because the substrate region is shorted to the N-type source region of the connecting channel through a heavily doped P-type source region, holes may be generated due to the avalanche effect when the transistor is under forward high voltage blocking or forward high voltage conduction. These holes flow through the substrate region channel, forming a hole current that causes the parasitic transistor to turn on. Since transistor turn-on is the key cause of transistor avalanche failure, suppressing the turn-on of the parasitic transistor in SGTs to improve transistor avalanche tolerance is an urgent problem to be solved in the SGT industry.

[0004] In related technologies, a composite source structure of P-type and N-type source regions is used in transistors, where the P-type source region short-circuits the transistor's base region to the source. This type of source region structure typically employs an interdigitated bar structure, where the P-type and N-type source regions are arranged parallel to each other on the base region. This source region structure limits the area of ​​the source region that can receive avalanche current, thus limiting the transistor's maximum avalanche withstand capability. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this application provides a shielded gate trench transistor with a triangularly arranged source region and its fabrication method, which can effectively suppress parasitic transistor turn-on and effectively improve avalanche tolerance.

[0006] This application provides a shielded gate trench transistor with a triangularly arranged source region, comprising: a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielded gate 5, a control gate 6, an insulating layer 7, a source electrode, a drain electrode 8, and a metal gate; the source electrode is disposed on top of the source region 4, and the metal gate electrode is disposed on top of the control gate 6; the drift region 2, the base region 3, and the source region 4 are sequentially disposed on top of the substrate region 1, and the drain electrode 8 is located at the bottom of the substrate region 1;

[0007] The control gate 6 and the shielding gate 5 are arranged sequentially from top to bottom on the side of the drift region 2, and are respectively connected to the drift region 2, the substrate region 3 and the source region 4 through the insulating layer 7;

[0008] The source region 4 includes a P-type source region 41 and an N-type source region 42; the P-type source region 41 is a triangular source region with a triangular cross-section, and the apex of the triangular source region is in contact with the insulating layer 7.

[0009] The N-type source region 42 includes a first N-type source region and a second N-type source region; the first N-type source region and the second N-type source region are respectively disposed on both sides of the top corner and are respectively connected to the insulating layer 7.

[0010] In one embodiment, the shielded gate trench transistor with triangularly arranged source regions further includes: a P-type superjunction pillar 9;

[0011] The top of the P-type superstructure 9 is attached to the bottom of the P-type source region 41; the side of the P-type superstructure 9 is connected to the matrix region 3 and the drift region 2 respectively.

[0012] In one embodiment, the P-type superstructure 9 and the P-type source region 41 form a triangular prism structure. The matrix region 3 includes a first matrix region and a second matrix region. The first matrix region and the second matrix region are disposed on both sides of the triangular prism structure and are respectively connected to the bottom surfaces of the first N-type source region and the second N-type source region.

[0013] In one embodiment, the P-type source region 41 is an isosceles triangular source region with an isosceles triangle cross-section, and the cross-sections of the first N-type source region and the second N-type source region are both right-angled triangles; the hypotenuses of the first N-type source region and the second N-type source region are respectively attached to the two sides of the P-type source region 41.

[0014] In one embodiment, the height of the P-type superstructure column 9 is less than or equal to the sum of the heights of the matrix region 3 and the drift region 2.

[0015] In one embodiment, the doping concentration of the P-type superjunction pillar 9 is medium doping concentration.

[0016] In one embodiment, the doping concentrations of both the P-type source region 41 and the N-type source region 42 are heavily doped.

[0017] The substrate region 1 is N-type doped, and the doping concentration of the substrate region 1 is a heavily doped concentration.

[0018] The drift region 2 is N-type doped, and the doping concentration of the drift region 2 is medium.

[0019] The substrate region 3 is p-type doped, and the doping concentration of the substrate region 3 is medium.

[0020] The shielding gate 5 and the control gate 6 are doped with P-type or N-type doping, and the doping concentration of the shielding gate 5 and the control gate 6 is a heavily doped concentration.

[0021] A second aspect of this application provides a method for fabricating a shielded gate trench transistor with triangularly arranged source regions, used to fabricate a shielded gate trench transistor with triangularly arranged source regions as described in any of the preceding claims, comprising:

[0022] The substrate region is fabricated using semiconductor materials;

[0023] A drift region is epitaxially formed on the substrate region;

[0024] A matrix region is formed on the drift region by ion implantation or diffusion.

[0025] An N-type source region is formed by doping the substrate region.

[0026] A first groove and a second groove are respectively etched on both sides of the drift region;

[0027] Oxides and polysilicon are deposited in the first trench to form an insulating layer, a shielding gate, and a control gate;

[0028] A P-type source region is formed by doping within the second trench;

[0029] A source electrode is fabricated above the P-type source region and the N-type source region;

[0030] A metal gate is fabricated above the first trench;

[0031] A drain electrode is fabricated at the bottom of the substrate region.

[0032] In one embodiment, in the first trench and the second trench etched on both sides of the drift region, the depth of the second trench is greater than the height of the N-type source region;

[0033] The step of doping to form a P-type source region within the second trench includes:

[0034] P-type superstructure columns and P-type source regions are sequentially deposited within the second trench.

[0035] In one embodiment, the deposition of oxide and polysilicon within the first trench to form an insulating layer, a shielding gate, and a control gate includes:

[0036] Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to form the insulating layer, the shielding gate and the control gate.

[0037] The technical solution provided in this application may include the following beneficial effects:

[0038] The shielded gate trench transistor with a triangularly arranged source region provided in this application includes a P-type source region with a triangular cross-section and a first N-type source region and a second N-type source region disposed on both sides of the P-type source region. Since the apex of the P-type source region is in contact with the insulating layer, and the first N-type source region and the second N-type source region are disposed on both sides of the apex and are respectively in contact with the insulating layer, the P-type source region of the triangularly arranged source region in this application is closer to the trench region than the interdigitated bar structure source region used in traditional shielded gate trench transistors. This shortens the path of hole current flowing from the trench region to the P-type source region when avalanche breakdown occurs, suppresses the turn-on of parasitic transistors, and improves the avalanche tolerance of the shielded gate trench field-effect transistor.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0040] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0041] Figure 1 This is a schematic diagram of the structure of a shielded gate trench transistor with a triangularly arranged source region, as shown in an embodiment of this application.

[0042] Figure 2 This is another schematic diagram of a shielded gate trench transistor with a triangularly arranged source region, as shown in an embodiment of this application;

[0043] Figure 3 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench transistor with a triangularly arranged source region, as shown in an embodiment of this application.

[0044] Figure 4 This is another schematic flowchart illustrating the fabrication method of a shielded gate trench transistor with a triangularly arranged source region, as shown in an embodiment of this application. Detailed Implementation

[0045] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0046] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0047] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0048] Example 1

[0049] In traditional shielded gate trench transistors, the source region structure typically adopts an interdigitated bar structure, that is, the P-type source region and the N-type source region are arranged parallel to each other on the substrate region. The above source region structure will limit the area of ​​the source region to receive avalanche current, thus limiting the maximum avalanche tolerance of the transistor.

[0050] To address the aforementioned issues, this application provides a shielded gate trench transistor with a triangularly arranged source region, which can effectively suppress parasitic transistor turn-on and effectively improve avalanche tolerance.

[0051] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0052] Figure 1 This is a schematic diagram of the structure of a shielded gate trench transistor with a triangularly arranged source region, as shown in an embodiment of this application.

[0053] See Figure 1 A shielded gate trench transistor with a triangularly arranged source region, comprising:

[0054] Substrate region 1, drift region 2, substrate region 3, source region 4, shielding gate 5, control gate 6, insulating layer 7, source, drain 8, and metal gate;

[0055] The source electrode is located at the top of the source region 4, the metal gate electrode is located at the top of the control gate 6, and the drain electrode 8 is located at the bottom of the substrate region 1. The drift region 2, the substrate region 3, and the source region 4 are sequentially located at the top of the substrate region 1. The control gate 6 and the shielding gate 5 are sequentially located on the side of the drift region 2 from top to bottom, and are connected to the drift region 2, the substrate region 3, and the source region 4 respectively through the insulating layer 7.

[0056] The source region 4 includes a P-type source region 41 and an N-type source region 42. The P-type source region 41 is a triangular source region with a triangular cross-section, and the apex of the triangular source region is connected to the insulating layer 7. The N-type source region 42 includes a first N-type source region and a second N-type source region. The first N-type source region and the second N-type source region are located on both sides of the apex and are connected to the insulating layer 7 respectively.

[0057] In this embodiment, the P-type source region 41 is located in the middle of the source region 4 and is connected to the insulating layer 7. This is equivalent to the P-type source region 41 being connected to the trench region of the transistor. Compared with the interdigitated bar structure of the source region used in the traditional shielded gate trench transistor, the P-type source region in this embodiment is closer to the trench region. Furthermore, the apex of the P-type source region, i.e., the triangular source region, is connected to the insulating layer 7, which does not compress the space of the N-type source region. Thus, while ensuring the area of ​​the N-type source region, the path of hole current movement is reduced, effectively suppressing the turn-on of the parasitic transistor and improving the avalanche tolerance of the shielded gate trench field-effect transistor.

[0058] Furthermore, the P-type source region 41 is an isosceles triangular source region with an isosceles triangle cross-section, and the cross-sections of the first N-type source region and the second N-type source region are both right-angled triangles; the hypotenuses of the first N-type source region and the second N-type source region are respectively attached to the two sides of the P-type source region 41.

[0059] In this embodiment, the P-type source region has a symmetrical structure with the height perpendicular to the length of the control gate as the axis of symmetry. Correspondingly, the first N-type source region and the second N-type source region, which are respectively located on both sides of the apex of the triangular source region, form two symmetrical right triangles. This makes the hole current generated in the trench region flow to the P-type source region with the height perpendicular to the length of the control gate as the dividing line. The hole current on both sides of the dividing line flows to the P-type source region with a symmetrical moving path, and this moving path is shorter than that of the transistor in the traditional interdigitated bar structure source region.

[0060] In this embodiment, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped; the substrate region 1 is doped with N-type doping and has a heavily doped concentration; the drift region 2 is doped with N-type doping and has a medium doping concentration; the substrate region 3 is doped with P-type doping and has a medium doping concentration; the shielding gate 5 and the control gate 6 are doped with either P-type or N-type doping and have heavily doped concentrations.

[0061] In this embodiment, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0062] The shielded gate trench transistor with a triangularly arranged source region provided in this application includes a P-type source region with a triangular cross-section and a first N-type source region and a second N-type source region disposed on both sides of the P-type source region. Since the apex of the P-type source region is in contact with the insulating layer, and the first N-type source region and the second N-type source region are disposed on both sides of the apex and are respectively in contact with the insulating layer, the P-type source region of the triangularly arranged source region in this application is closer to the trench region than the interdigitated bar structure source region used in traditional shielded gate trench transistors. This shortens the path of hole current flowing from the trench region to the P-type source region when avalanche breakdown occurs, suppresses the turn-on of parasitic transistors, and improves the avalanche tolerance of the shielded gate trench field-effect transistor.

[0063] Example 2

[0064] Based on the shielded gate trench transistor with triangularly arranged source regions provided in Embodiment 1 above, this application provides another shielded gate trench transistor with triangularly arranged source regions, which can improve the electric field distribution in the drift region through the charge compensation principle, thereby improving the breakdown voltage.

[0065] See Figure 2 The shielded gate trench transistor with a triangularly arranged source region includes:

[0066] Substrate region 1, drift region 2, substrate region 3, source region 4, shielding gate 5, control gate 6, insulating layer 7, source, drain 8, metal gate and P-type superjunction pillar 9;

[0067] The structures of substrate region 1, drift region 2, base region 3, source region 4, shielding gate 5, control gate 6, insulating layer 7, source, drain 8, and metal gate are the same as in Embodiment 1 above, and will not be repeated here.

[0068] The difference is that, in this embodiment of the application, the shielded gate trench transistor with a triangularly arranged source region further includes a P-type superjunction pillar 9, the top of which is attached to the bottom of the P-type source region 41; the side of the P-type superjunction pillar 9 is connected to the substrate region 3 and the drift region 2 respectively.

[0069] That is, a P-type superjunction pillar 9 is also provided in the drift region 2. The P-type superjunction pillar 9 forms a P-type compensation region in the drift region 2, which is used to suppress the lateral impurity diffusion in the drift region 2 during the high temperature process. The electric field distribution in the drift region 2 is improved through the charge compensation principle, so that the electric field that was originally densely distributed at the corner of the shielding gate tends to be uniformly distributed, thereby improving the breakdown voltage.

[0070] Furthermore, the P-type superstructure pillar 9 and the P-type source region 41 form a triangular prism structure. The matrix region 3 includes a first matrix region and a second matrix region. The first matrix region and the second matrix region are disposed on both sides of the triangular prism structure and are respectively connected to the bottom surfaces of the first N-type source region and the second N-type source region.

[0071] This application does not limit the shape of the P-type superjunction pillar 9. In practical applications, the P-type superjunction pillar 9 can be set as a quadrangular prism or other shapes. Preferably, the P-type superjunction pillar 9 is set as a triangular prism, and the cross-section of the triangular prism is consistent with the cross-section of the P-type source region 41, so that the bottom surface of the P-type source region 41 and the top surface of the P-type superjunction pillar 9 can be completely fitted to form a triangular prism structure, thereby forming a regular hole current flow channel.

[0072] Furthermore, the height of the P-type superstructure column 9 is less than or equal to the sum of the heights of the matrix region 3 and the drift region 2.

[0073] In practical applications, the P-type superjunction pillar 9 can be configured such that its bottom surface is connected to the substrate region 1 to form a superjunction structure that penetrates the drift region 2; or its bottom surface can be connected to the drift region 2. The specific structure adopted can be selected according to the actual situation and is not limited here.

[0074] In this embodiment, the doping type of the P-type superjunction pillar 9 is P-type doping, and its doping concentration is medium doping concentration.

[0075] The shielded gate trench transistor with a triangularly arranged source region provided in this application effectively suppresses the lateral impurity diffusion of the P-type and N-type doped regions during high-temperature processes, i.e., the lateral diffusion of the drift region, by introducing a P-type superjunction pillar connected to the substrate region and the drift region below the P-type source region. The electric field distribution in the drift region is improved through the charge compensation principle, thereby making the electric field that was originally densely distributed at the corner of the shielded gate tend to be uniformly distributed, thereby improving the breakdown voltage.

[0076] Example 3

[0077] Corresponding to the shielded gate trench transistor with triangularly arranged source regions in Embodiment 1 above, this application also provides a method for fabricating a shielded gate trench transistor with triangularly arranged source regions and corresponding embodiments.

[0078] Figure 3 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench transistor with a triangularly arranged source region, as shown in an embodiment of this application.

[0079] See Figure 3 The method for fabricating the shielded gate trench transistor with triangularly arranged source regions includes:

[0080] 301. Fabricating the substrate region using semiconductor materials;

[0081] In the embodiments of this application, the substrate region is prepared using N-type heavily doped semiconductor material, that is, the doping type of the substrate region is set to N-type doping, and the doping concentration is the heavy doping concentration.

[0082] 302. A drift region is epitaxially formed on the substrate region;

[0083] In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0084] 303. A matrix region is formed on the drift region by ion implantation or diffusion;

[0085] Ion implantation is a process of doping silicon materials. In practical applications, the power device is placed at one end of the ion implanter, and the dopant ion source is placed at the other end. At the dopant ion source, the dopant atoms are ionized, thus acquiring a certain charge. They are then accelerated to ultra-high speed by an electric field, penetrating the product surface and using their momentum to implant the dopant atoms into the power device, forming a doped region.

[0086] Diffusion is a process of incorporating pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine are usually used as ion sources, and pure impurity atoms are incorporated into the surface of silicon materials through intermittent diffusion or substitutional diffusion.

[0087] It should be noted that the embodiments of this application do not have strict limitations on the preparation method of the substrate region. In actual process, different processes described above can be selected to complete the preparation of the substrate region according to actual needs.

[0088] 304. An N-type source region is formed by doping the substrate region;

[0089] In this embodiment, an N-type source region is formed by doping an N-type heavily doped semiconductor material on a substrate region. At this time, the top surface of the substrate region is completely covered by the N-type heavily doped semiconductor material, that is, the N-type source region completely covers the substrate region. Subsequently, a portion of the N-type source region is etched away by an etching process to expose the space for doping to form a P-type source region with a triangular cross-section.

[0090] 305. A first groove and a second groove are respectively etched on both sides of the drift area;

[0091] In this embodiment, the second trench is triangular prism-shaped, and its depth is equal to the height of the N-type source region.

[0092] 306. Deposit oxide and polysilicon in the first trench to form an insulating layer, a shielding gate, and a control gate;

[0093] In this embodiment, oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to form the insulating layer, the shielding gate and the control gate.

[0094] In this embodiment, the polysilicon can be P-type doped polysilicon or N-type doped polysilicon, and the doping concentration of the polysilicon is medium doping concentration or heavy doping concentration. Preferably, the polysilicon is heavily doped polysilicon.

[0095] 307. A P-type source region is formed by doping within the second trench;

[0096] In this embodiment, since the second trench is triangular prism-shaped and its depth is equal to the height of the N-type source region, a triangular source region is formed in the second trench by doping with P-type heavily doped semiconductor material, thus obtaining a P-type source region. The apex of the triangular source region is connected to the insulating layer, which makes the P-type source region in the transistor of this embodiment closer to the first trench than that of a conventional transistor with an interdigitated bar structure, thereby shortening the movement path of hole current during avalanche and achieving the effect of improving the avalanche tolerance of the transistor.

[0097] 308. Fabricate a source electrode above the P-type source region and the N-type source region;

[0098] 309. Fabricate a metal gate above the first trench;

[0099] In this embodiment of the application, a metal gate is fabricated above the first trench such that the metal gate is located on top of the control gate.

[0100] 310. A drain electrode is formed at the bottom of the substrate region.

[0101] In this embodiment of the application, the execution order of steps 308 to 310 is not strictly limited. That is, in actual application, steps 308 to 310 can be executed in any order, or all three can be executed in parallel.

[0102] It should be noted that, in practical applications, the following steps can be used to form the triangular arrangement source region of the transistor described in Embodiment 1:

[0103] A P-type source region is formed by doping a P-type semiconductor material on a substrate region. A portion of the P-type source region is removed by an etching process, leaving the remaining P-type source region in the shape of a triangular prism. This forms two trenches on the substrate region for doping to form an N-type source region. The trenches are then filled with an N-type doped semiconductor material to obtain the N-type source region.

[0104] This application provides a method for fabricating a shielded gate trench transistor with a triangularly arranged source region. After forming an N-type source region by doping on a substrate region, a portion of the N-type source region is etched away using an etching process to form a triangular prism-shaped second trench. P-type semiconductor material is doped in the second trench to obtain a P-type source region with a triangular cross-section, and the apex of the P-type source region is connected to the insulating layer. This makes the P-type source region in the transistor of this application embodiment closer to the first trench, thereby shortening the path of hole current flowing from the trench region to the P-type source region when avalanche breakdown occurs, suppressing the turn-on of the parasitic transistor, and improving the avalanche tolerance of the shielded gate trench field-effect transistor.

[0105] Example 4

[0106] Corresponding to the shielded gate trench transistor with triangularly arranged source regions in Embodiment 2 above, this application also provides a method for fabricating a shielded gate trench transistor with triangularly arranged source regions and corresponding embodiments.

[0107] Figure 4 This is another schematic flowchart illustrating the fabrication method of a shielded gate trench transistor with a triangularly arranged source region, as shown in an embodiment of this application.

[0108] See Figure 4The method for fabricating the shielded gate trench transistor with triangularly arranged source regions includes:

[0109] 401. Fabricating the substrate region using semiconductor materials;

[0110] 402. A drift region is epitaxially formed on the substrate region;

[0111] 403. A matrix region is formed on the drift region by ion implantation or diffusion;

[0112] 404. An N-type source region is formed by doping the substrate region;

[0113] In this embodiment, steps 401 to 404 are the same as steps 301 to 304 in the above embodiment 3, and will not be repeated here.

[0114] 405. First grooves and second grooves are etched on both sides of the drift area, respectively;

[0115] In this embodiment, the depth of the second trench is greater than the height of the N-type source region.

[0116] 406. Deposit oxide and polysilicon in the first trench to form an insulating layer, a shielding gate, and a control gate;

[0117] In this embodiment, oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to form the insulating layer, the shielding gate and the control gate.

[0118] In this embodiment, the polysilicon can be P-type doped polysilicon or N-type doped polysilicon, and the doping concentration of the polysilicon is medium doping concentration or heavy doping concentration. Preferably, the polysilicon is heavily doped polysilicon.

[0119] 407. A P-type superstructure column and a P-type source region are sequentially deposited in the second trench;

[0120] In this embodiment, a P-type superjunction pillar is deposited in the second trench using a P-type medium-doped semiconductor material, such that the top surface of the P-type superjunction pillar is flush with the top surface of the substrate region, and a P-type source region is deposited on the top surface of the P-type superjunction pillar using a P-type heavily doped semiconductor material.

[0121] In practical applications, the depth of the second trench can be set to the sum of the heights of the N-type source region and the drift region, so that the bottom surface of the deposited P-type superjunction pillar is in contact with the top surface of the substrate region.

[0122] 408. Fabricate a source electrode above the P-type source region and the N-type source region;

[0123] 409. Fabricate a metal gate above the first trench;

[0124] 410. A drain electrode is formed at the bottom of the substrate region.

[0125] In this embodiment of the application, the execution order of steps 408 to 410 is not strictly limited. That is, in actual application, steps 408 to 410 can be executed in any order, or all three can be executed in parallel.

[0126] This application provides a method for fabricating a shielded gate trench transistor with a triangularly arranged source region. After forming an N-type source region by doping on a substrate region, a portion of the N-type source region is etched away using an etching process to form a second trench. In the second trench, P-type medium-doped semiconductor material and P-type heavily doped semiconductor material are doped sequentially to obtain a P-type superjunction pillar and a P-type source region with a triangular cross-section. The apex of the P-type source region is in contact with the insulating layer, making the P-type source region in the transistor of this application embodiment closer to the first trench. This shortens the path of hole current flowing from the trench region to the P-type source region when avalanche breakdown occurs, suppressing the turn-on of parasitic transistors and improving the avalanche tolerance of the shielded gate trench field-effect transistor.

[0127] Furthermore, by introducing a P-type superjunction pillar, the electric field distribution in the drift region is improved using the charge compensation principle, thereby making the electric field, which was originally densely distributed at the corner of the shielding grid, tend to be uniformly distributed, thus improving the breakdown voltage.

[0128] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different emphases; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.

[0129] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0130] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate trench transistor with a triangularly arranged source region, characterized in that, include: The substrate region (1), drift region (2), base region (3), source region (4), shielding gate (5), control gate (6), insulating layer (7), source electrode, drain electrode (8), and metal gate; the source electrode is disposed on top of the source region (4), and the metal gate electrode is disposed on top of the control gate (6); the drift region (2), the base region (3), and the source region (4) are disposed sequentially on top of the substrate region (1), and the drain electrode (8) is located at the bottom of the substrate region (1); The control gate (6) and the shielding gate (5) are arranged sequentially from top to bottom on the side of the drift region (2), and are connected to the drift region (2), the substrate region (3) and the source region (4) respectively through the insulating layer (7); The source region (4) includes a P-type source region (41) and an N-type source region (42); the P-type source region (41) is a triangular source region with a triangular cross-section, and the apex of the triangular source region is in contact with the insulating layer (7); The N-type source region (42) includes a first N-type source region and a second N-type source region; the first N-type source region and the second N-type source region are respectively disposed on both sides of the top corner and are respectively connected to the insulating layer (7); The shielded gate trench transistor further includes: a P-type superjunction pillar (9); The top of the P-type superstructure (9) is attached to the bottom of the P-type source region (41); the sides of the P-type superstructure (9) are connected to the substrate region (3) and the drift region (2) respectively, and the P-type superstructure (9) and the P-type source region (41) form a triangular prism structure; the P-type superstructure forms a P-type compensation region in the drift region to suppress the lateral impurity diffusion in the drift region during the high-temperature process.

2. The shielded gate trench transistor with a triangularly arranged source region according to claim 1, characterized in that, The matrix region (3) includes a first matrix region and a second matrix region. The first matrix region and the second matrix region are respectively disposed on both sides of the triangular prism structure and are respectively connected to the bottom surface of the first N-type source region and the second N-type source region.

3. The shielded gate trench transistor with a triangularly arranged source region according to claim 1, characterized in that, The P-type source region (41) is an isosceles triangular source region with an isosceles triangle cross-section. The cross-sections of the first N-type source region and the second N-type source region are both right-angled triangles. The hypotenuses of the first N-type source region and the second N-type source region are respectively attached to the two sides of the P-type source region (41).

4. The shielded gate trench transistor with a triangularly arranged source region according to claim 1, characterized in that, The height of the P-type superstructure column (9) is less than or equal to the sum of the heights of the matrix region (3) and the drift region (2).

5. The shielded gate trench transistor with a triangularly arranged source region according to claim 1, characterized in that, The doping concentration of the P-type superjunction pillar (9) is medium doping concentration.

6. The shielded gate trench transistor with a triangularly arranged source region according to claim 1, characterized in that, The doping concentrations of the P-type source region (41) and the N-type source region (42) are both heavily doped. The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavily doped concentration. The drift region (2) is N-type doped, and the doping concentration of the drift region (2) is medium. The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The doping type of the shielding gate (5) and the control gate (6) is P-type doping or N-type doping, and the doping concentration of the shielding gate (5) and the control gate (6) is heavy doping concentration.

7. A method for fabricating a shielded gate trench transistor with a triangularly arranged source region, characterized in that, For fabricating a shielded gate trench transistor with a triangularly arranged source region as described in any one of claims 1-6, comprising: The substrate region is fabricated using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. An N-type source region is formed by doping the substrate region. A first groove and a second groove are respectively etched on both sides of the drift region; Oxides and polysilicon are deposited in the first trench to form an insulating layer, a shielding gate, and a control gate; A P-type source region is formed by doping within the second trench; A source electrode is fabricated above the P-type source region and the N-type source region; A metal gate is fabricated above the first trench; A drain electrode is fabricated at the bottom of the substrate region.

8. The method for fabricating a shielded gate trench transistor with a triangularly arranged source region according to claim 7, characterized in that, In the first trench and the second trench etched on both sides of the drift region, the depth of the second trench is greater than the height of the N-type source region; The step of doping to form a P-type source region within the second trench includes: P-type superstructure columns and P-type source regions are sequentially deposited within the second trench.

9. The method for fabricating a shielded gate trench transistor with a triangularly arranged source region according to claim 7, characterized in that, The deposition of oxide and polysilicon within the first trench to form an insulating layer, a shielding gate, and a control gate includes: Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to form the insulating layer, the shielding gate and the control gate.

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