Logic gates based on topological magnetic structures

Abstract

This invention relates to a logic gate based on a topological magnetic structure. The logic gate includes a nano-double-layer track, comprising a first track and a second track, which are intersected to form an intersection region. The first track includes a first input terminal and a first output terminal; the second track includes a second input terminal. The first and second tracks provide a path for the movement of the topological magnetic structure. This logic gate achieves the logic function of a NOT gate by moving the topological magnetic structure between the first input terminal, the second input terminal, and the first output terminal. Because the topological magnetic structure can stably exist within the nano-double-layer track, the logic gate is small in size; because the topological magnetic structure has a certain topological barrier, it has good stability, thus the logic gate has high stability; simultaneously, the topological magnetic structure has advantages such as low power consumption and non-volatility, retaining its logic value even when power is off, with no standby power consumption, thus the logic gate has low power consumption.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, and in particular to a logic gate based on a topological magnetic structure. Background Technology

[0002] Logic gates are the basic components of logic circuits, and can be broadly classified into three types: basic gates, universal gates, and extension gates. Basic gates can be further divided into AND gates, OR gates, and NOT gates. Logic gates can convert high and low levels of signals into corresponding logic signals, thereby enabling logical operations.

[0003] Traditional logic gates are typically composed of discrete transistors, resistors, and diodes, which are large in size, have high power consumption, cannot retain logic values ​​when power is lost, and have standby power consumption. Summary of the Invention

[0004] Therefore, it is necessary to provide a logic gate based on a topological magnetic structure that is small in size, low in power consumption, and highly stable, in response to the problems mentioned in the background technology above.

[0005] To achieve the above and other objectives, this application provides a logic gate based on a topological magnetic structure, characterized in that it includes:

[0006] A nano-double-layer track, comprising a first track and a second track, which intersect to form an intersection region; wherein, the first track includes a first input end and a first output end; the second track includes a second input end and a second output end; the first track and the second track are used to provide a path for the movement of the topological magnetic structure;

[0007] The logic gate is configured as follows:

[0008] When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the second input terminal does not input the topological magnetic structure, the topological magnetic structure from the first input terminal moves along the first track to the first output terminal, representing that the logic gate input is 0 and output is 1.

[0009] When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the topological magnetic structure is input to the second input terminal, the topological magnetic structure from the first input terminal and the topological magnetic structure from the second input terminal are merged in the intersection region, and the first output terminal has no output of the topological magnetic structure, representing that the logic gate has an input of 1 and an output of 0.

[0010] The logic gate based on a topological magnetic structure provided in this application realizes the logic function of a NOT gate by moving the topological magnetic structure between the first input terminal, the second input terminal, and the first output terminal. Since the topological magnetic structure can stably exist in a nano-double-layer track, the logic gate designed based on the topological magnetic structure is small in size; due to the topological barrier of the topological magnetic structure, it has good stability, thus the logic gate designed based on the topological magnetic structure has high stability; at the same time, the topological magnetic structure has advantages such as high storage density, low power consumption, fast response speed, and non-volatility, and can still retain logic values ​​when power is lost, with no standby power consumption, therefore the logic gate designed based on the topological magnetic structure also has low power consumption.

[0011] In one embodiment, the logic gate is further configured as follows:

[0012] When the topological magnetic structure is input to the first input terminal and the topological magnetic structure is not input to the second input terminal, the first output terminal will not output the topological magnetic structure, which means that the logic gate inputs 1 and 0 and outputs 0.

[0013] When the topological magnetic structure is not input to the first input terminal, and the topological magnetic structure is input to the second input terminal, the first output terminal will not output the topological magnetic structure, which means that the logic gate inputs 0 and 1 and outputs 0.

[0014] When the topological magnetic structure is input to both the first input terminal and the second input terminal, the topological magnetic structure is output from the first output terminal, representing the logic gate input 1 and 1, and output 1.

[0015] The logic gate based on the topological magnetic structure in the above embodiments realizes the logic function of the AND gate by moving the topological magnetic structure between the first input terminal, the second input terminal and the first output terminal.

[0016] In one embodiment, the width of the path is 10-20 nm; the interlayer exchange coupling coefficient between the first track and the second track is 0.7-0.9.

[0017] In one embodiment, the logic gate is further configured as follows:

[0018] When the topological magnetic structure is input to the first input terminal and the topological magnetic structure is not input to the second input terminal, the topological magnetic structure is output to the first output terminal, representing the logic gate input 1 and 0 and output 1;

[0019] When the topological magnetic structure is not input to the first input terminal, and the topological magnetic structure is input to the second input terminal, the topological magnetic structure is output to the first output terminal, representing that the logic gate inputs 0 and 1 and outputs 1;

[0020] When the topological magnetic structure is input to both the first input terminal and the second input terminal, the topological magnetic structure is output from the first output terminal, representing the logic gate input 1 and 1, and output 1.

[0021] The logic gate based on the topological magnetic structure in the above embodiments realizes the logic function of the OR gate by moving the topological magnetic structure between the first input terminal, the second input terminal and the first output terminal.

[0022] In one embodiment, the path width is 30-60 nm; the interlayer exchange coupling coefficient between the first track and the second track is 0.4-0.6.

[0023] In one embodiment, the second track includes a reduction zone;

[0024] The weakening region is configured as follows:

[0025] When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the second input terminal does not input the topological magnetic structure, the weakening region acts, causing the topological magnetic structure from the first input terminal to move along the first track, pass through the weakening region, and reach the first output terminal, representing the logic gate input 0 and output 1;

[0026] When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the topological magnetic structure is input to the second input terminal, the weakening region does not function, so that the topological magnetic structure from the first input terminal and the topological magnetic structure from the second input terminal merge in the intersection region, and the first output terminal has no output of the topological magnetic structure, representing that the logic gate has an input of 1 and an output of 0.

[0027] In the above embodiments, the logic gate based on the topological magnetic structure, by setting a weakening region in the second track, enables the logic gate to perform NOT gate logic operations. When the second input terminal does not input the topological magnetic structure and the first input terminal is activated and inputs the topological magnetic structure to the first input terminal, the topological magnetic structure can split into small domain walls at the weakening region. These small domain walls are disintegrated when passing through the weakening region due to insufficient energy, while the larger ones can reach the first output terminal through the weakening region, accurately realizing the logic gate's input 0 and output 1 logic operation function.

[0028] In one embodiment, the nanobilayer track comprises a layer of nanomaterials coupled with heavy metals.

[0029] The logic gates based on topological magnetic structures in the above embodiments generate antiferromagnetic coupling in the nano-double-layer track by using a layer of nanomaterials coupled with heavy metals. This eliminates the influence of the Hall effect on the working performance of the logic gates, improves the storage density and operation speed of the device, and further reduces power consumption.

[0030] In one embodiment, the heavy metal coupled nanomaterial layer comprises a stacked structure in which a magnetic material layer, a heavy metal material layer, and a magnetic material layer are stacked in sequence.

[0031] In one embodiment, the topological magnetic structure comprises magnetic skyrmions.

[0032] In one embodiment, the logic gate is connected to a power supply;

[0033] The power supply is used to provide current to the logic gate, and the current is used to drive the topological magnetic structure to move along the first track and / or the second track. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a logic gate based on a topological magnetic structure provided in one embodiment of this application;

[0036] Figure 2 A schematic diagram of the structure of the first track and the second track in a logic gate based on a topological magnetic structure provided in an embodiment of this application;

[0037] Figures 3 to 5 A schematic diagram of a logic gate based on a topological magnetic structure with input 0 and output 1 provided in an embodiment of this application;

[0038] Figures 6 to 9 This is a schematic diagram of a logic gate based on a topological magnetic structure with input 1 and output 0, provided in an embodiment of this application.

[0039] Figures 10 to 13 A schematic diagram of a logic gate based on a topological magnetic structure with inputs of 1 and 0 and output of 0, provided in an embodiment of this application;

[0040] Figures 14 to 17 A schematic diagram of a logic gate based on a topological magnetic structure with inputs of 0 and 1 and output of 0, provided in an embodiment of this application;

[0041] Figures 18 to 21 A schematic diagram of a logic gate based on a topological magnetic structure with input 1 and 1 and output 1 provided in an embodiment of this application;

[0042] Figures 22 to 25 A schematic diagram of a logic gate based on a topological magnetic structure with inputs of 1 and 0 and output of 1, provided in an embodiment of this application;

[0043] Figures 26 to 29 A schematic diagram of a logic gate based on a topological magnetic structure provided in an embodiment of this application, with inputs of 0 and 1 and output of 1;

[0044] Figures 30 to 33 This is a schematic diagram of a logic gate based on a topological magnetic structure with inputs 1 and 1 and output 1, provided in an embodiment of this application.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1. First track; 2. Second track; 3. Intersection area; 4. Topological magnetic structure; 101. First input terminal; 102. First output terminal; 201. Second input terminal; 202. Second output terminal. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first input terminal may be referred to as a second input terminal, and similarly, a second input terminal may be referred to as a first input terminal. Both the first input terminal and the second input terminal are input terminals, but they are not the same input terminal.

[0050] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0051] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0052] Please see Figure 1 This application provides a logic gate based on a topological magnetic structure, including a nano-double-layer track. The nano-double-layer track includes a first track 1 and a second track 2, which are cross-connected to form an intersection region 3.

[0053] Please see Figure 2 The first track 1 includes a first input terminal 101 and a first output terminal 102, and the second track 2 includes a second input terminal 201 and a second output terminal 202; the first track 1 and the second track 2 are used to provide a path for the movement of the topological magnetic structure.

[0054] Please continue reading. Figure 1 And see Figures 3 to 9 The logic gates are configured as follows:

[0055] When the first input terminal 101 is activated and the topological magnetic structure 4 is input to the first input terminal 101, if the second input terminal 201 does not input the topological magnetic structure 4, the topological magnetic structure 4 from the first input terminal 101 moves along the first track 1 to the first output terminal 102, representing a logic gate input of 0 and output of 1.

[0056] When the first input terminal 101 is activated and a topological magnetic structure 4 is input to the first input terminal 101, if a topological magnetic structure 4 is input to the second input terminal 201, the topological magnetic structure 4 from the first input terminal 101 and the topological magnetic structure 4 from the second input terminal 201 will be merged in the intersection region 3, and the first output terminal 102 will have no topological magnetic structure 4 output, representing a logic gate input of 1 and output of 0.

[0057] The following is combined with Figures 3 to 5 A detailed explanation of the logic gate's input 0 and output 1 cases is provided:

[0058] When the topological magnetic structure 4 is input to the first input terminal 101, and the second input terminal 201 is not input with the topological magnetic structure 4, the first track 1 is as follows: Figure 3 As shown in Figure (a), the second track 2 is as follows Figure 3 As shown in Figure (b) of the document.

[0059] When the first input terminal 101 is activated, the topological magnetic structure 4 in the first input terminal 101 is also activated. The topological magnetic structure 4 moves along the first track 1 towards the first output terminal 102. At this time, the first track 1 is as follows: Figure 4 As shown in Figure (a), the second track 2 is as follows Figure 4 As shown in Figure (b) of the document.

[0060] The topological magnetic structure 4 moves along the first track 1 to the first output terminal 102, at which point the first track 1 is as follows: Figure 5 As shown in Figure (a), the second track 2 is as follows Figure 5 As shown in Figure (b). At this point, the logic gate has completed the logical operation of input 0 and output 1.

[0061] Specifically, in some examples, when the activated topological magnetic structure 4 moves to the junction region 3, it splits into small domain walls. These small domain walls are disintegrated during the movement due to insufficient energy, while the larger domain walls can reach the first output terminal 102 through the junction region 3.

[0062] The following is combined with Figures 6 to 9 A detailed explanation of the logic gate's input 1 and output 0 cases is provided:

[0063] When the topological magnetic structure 4 is input to the first input terminal 101, and the second input terminal 201 also inputs the topological magnetic structure 4, the first track 1 is as follows: Figure 6 As shown in Figure (a), the second track 2 is as follows Figure 6 As shown in Figure (b) of the document.

[0064] When the first input terminal 101 is activated, the topological magnetic structure 4 in the first input terminal 101 is also activated. The topological magnetic structure 4 of the first input terminal 101 moves along the first track 1 towards the first output terminal 102, and the topological magnetic structure 4 of the second input terminal 201 moves towards the intersection region 3. At this time, the first track 1 is as follows: Figure 7 As shown in Figure (a), the second track 2 is as follows Figure 7 As shown in Figure (b) of the document.

[0065] When the topological magnetic structure 4 of the first input terminal 101 reaches the intersection region 3, the topological magnetic structure 4 of the second input terminal 201 also reaches the vicinity of the intersection region 3. Due to the repulsive effect between the topological magnetic structures 4, the topological magnetic structure 4 of the first input terminal 101 will be pushed out of the intersection region 3 by the topological magnetic structure 4 of the second input terminal 201. At this time, the first track 1 is as follows: Figure 8 As shown in Figure (a), the second track 2 is as follows Figure 8 As shown in Figure (b) of the document.

[0066] Since the topological magnetic structure 4 of the first input terminal 101 is displaced from the intersection region 3 by the topological magnetic structure 4 of the second input terminal 201, the topological magnetic structure 4 of the first input terminal 101 cannot continue to move along the first track 1 to the first output terminal 102. Therefore, no topological magnetic structure 4 will reach the first output terminal 102. At this time, the first track 1 is as follows: Figure 9 As shown in Figure (a), the second track 2 is as follows Figure 9 As shown in Figure (b). At this point, the logic gate has completed the logical operation of input 1 and output 0.

[0067] The logic gate based on the topological magnetic structure in the above embodiments realizes the logic function of a NOT gate by moving the topological magnetic structure between the first input terminal, the second input terminal, and the first output terminal. Since the topological magnetic structure can stably exist in a nano-double-layer track, the logic gate designed based on the topological magnetic structure is small in size; since the topological magnetic structure has a certain topological barrier, it has good stability, thus the logic gate designed based on the topological magnetic structure has high stability; at the same time, the topological magnetic structure has advantages such as high storage density, low power consumption, fast response speed, and non-volatility, and can still retain logic values ​​when power is off, with no standby power consumption, therefore the logic gate designed based on the topological magnetic structure also has low power consumption.

[0068] Please continue reading. Figure 1 and Figure 2 And see Figures 10 to 21 In one embodiment, the logic gate can also be configured as follows:

[0069] When the topological magnetic structure 4 is input to the first input terminal 101 and the topological magnetic structure 4 is not input to the second input terminal 201, the first output terminal 102 will not output the topological magnetic structure 4, which represents the logic gate input being 1 and 0 and outputting 0.

[0070] When the first input terminal 101 does not input the topological magnetic structure 4, and the second input terminal 201 inputs the topological magnetic structure 4, the first output terminal 102 will not output the topological magnetic structure 4, which represents that the logic gate inputs 0 and 1 and outputs 0.

[0071] When the topological magnetic structure 4 is input to both the first input terminal 101 and the second input terminal 201, the first output terminal 102 outputs the topological magnetic structure 4, which represents the logic gate input 1 and 1 and output 1.

[0072] The following is combined with Figures 10 to 13 A detailed explanation of the logic gate's inputs of 1 and 0, and output of 0:

[0073] When the topological magnetic structure 4 is input to the first input terminal 101, and the second input terminal 201 does not input the topological magnetic structure 4, the first track 1 is as follows: Figure 10 As shown in Figure (a), the second track 2 is as follows Figure 10 As shown in Figure (b) of the document.

[0074] The topological magnetic structure 4 is driven to move along the first raceway 1 toward the first output terminal 102. At this time, the first raceway 1 is as follows: Figure 11 As shown in Figure (a), the second track 2 is as follows Figure 11 As shown in Figure (b) of the document.

[0075] When the topological magnetic structure 4 moves along the first track 1 to the vicinity of the intersection region 3, it will gradually disintegrate because its energy is insufficient to penetrate the intersection region 3. Figure 12 As shown in Figure (a), the second track 2 is as follows: Figure 12 As shown in Figure (b) of the document.

[0076] Ultimately, the topological magnetic structure 4 cannot penetrate the intersection region 3 and is completely disintegrated. At this point, the first track 1 is as follows: Figure 13 As shown in Figure (a), the second track 2 is as follows Figure 13 As shown in Figure (b). At this point, the logic gate has completed the operation of inputting 1 and 0 and outputting 0.

[0077] The following is combined with Figures 14 to 17 A detailed explanation of the logic gate's inputs of 0 and 1, and output of 0:

[0078] When the first input terminal 101 does not input the topological magnetic structure 4, and the second input terminal 201 inputs the topological magnetic structure 4, the first track 1 is as follows: Figure 14 As shown in Figure (a), the second track 2 is as follows Figure 14 As shown in Figure (b) of the document.

[0079] The topological magnetic structure 4 is driven to move along the second track 2 towards the intersection region 3, at which time the first track 1 is as follows: Figure 15 As shown in Figure (a), the second track 2 is as follows Figure 15 As shown in Figure (b) of the document.

[0080] When the topological magnetic structure 4 moves along the second track 2 to the vicinity of the intersection region 3, it will not have enough energy to penetrate the intersection region 3. Therefore, the topological magnetic structure 4 will begin to gradually disintegrate, as... Figure 16 As shown in Figure (b), the first track 1 is as follows: Figure 16 As shown in Figure (a).

[0081] Ultimately, the topological magnetic structure 4 cannot penetrate the intersection region 3 and is completely disintegrated. At this point, the first track 1 is as follows: Figure 17 As shown in Figure (a), the second track 2 is as follows Figure 17 As shown in Figure (b). At this point, the logic gate has completed the operation of inputting 0 and 1 and outputting 0.

[0082] The following is combined with Figures 18 to 21 A detailed explanation of the logic gate's inputs of 1 and 2, and output of 1:

[0083] When the topological magnetic structure 4 is input to both the first input terminal 101 and the second input terminal 201, the first track 1 is as follows: Figure 18 As shown in Figure (a), the second track 2 is as follows Figure 18 As shown in Figure (b) of the document.

[0084] Both the topological magnetic structure 4 in the first input terminal 101 and the second input terminal 201 are driven, so that the topological magnetic structure 4 in the first input terminal 101 moves along the first track 1 towards the first output terminal 102, and the topological magnetic structure 4 in the second input terminal 201 moves along the second track 2 towards the intersection region 3. At this time, the first track 1 is as follows: Figure 19 As shown in Figure (a), the second track 2 is as follows Figure 19 As shown in Figure (b) of the document.

[0085] When the topological magnetic structures 4 in both the first input terminal 101 and the second input terminal 201 move to the vicinity of the intersection region 3, the topological magnetic structures 4 in the first input terminal 101 and the second input terminal 201 merge at the intersection region 3. This merging allows them sufficient energy to pass through the intersection region 3 and continue moving in their original direction. At this time, the first track 1... Figure 20 As shown in Figure (a), the second track 2 is as follows Figure 20 As shown in Figure (b) of the document.

[0086] Ultimately, the topological magnetic structure 4 can reach the first output terminal 102, resulting in an output from the first output terminal 102. At this time, the first track 1 is as follows: Figure 21 As shown in Figure (a), the second track 2 is as follows Figure 21 As shown in Figure (b). At this point, the logic gate has completed the operation of inputting 1 and 1 and outputting 1.

[0087] It should be noted that in the logic gate, the amount of energy required for the topological magnetic structure 4 to penetrate the intersection region 3 can be changed by altering the width of the first track 1 and the second track 2 paths and the value of the interlayer exchange coupling coefficient.

[0088] Based on the above embodiments, in some examples, the width of both the first track 1 and the second track 2 can be 10-20 nm; for example, the width of the first track 1 and the second track 2 can be 10 nm, 15 nm, or 20 nm. This application does not specifically limit the width of the first track 1 and the second track 2. In some examples, the value of the interlayer exchange coupling coefficient can be 0.7-0.9; for example, the value of the interlayer exchange coupling coefficient can be 0.7, 0.8, or 0.9. This application does not specifically limit the value of the interlayer exchange coupling coefficient. Specifically, in one embodiment, the width of the first track 1 and the second track 2 is 10 nm, and the value of the interlayer exchange coupling coefficient is 0.8.

[0089] The logic gate provided in the above embodiments can also realize the logic function of an AND gate by moving the topological magnetic structure between the first input terminal, the second input terminal and the first output terminal.

[0090] Please continue reading. Figures 10 to 21 In some embodiments, the second track 2 may further include a second output terminal 202. When the logic gate inputs 1 and 1 and outputs 1, the topological magnetic structure 4 in the first input terminal 101 and the topological magnetic structure 4 in the second input terminal 201 merge at the intersection region 3. The merging allows their energy to pass through the intersection region 3 and continue to move in the original direction. Finally, the topological magnetic structure 4 can reach the first output terminal 102, so that there is a topological magnetic structure 4 output at the first output terminal 102. At this time, the second track 2 is as follows: Figure 21 As shown in Figure (b), the topological magnetic structure 4 in the original second input terminal 201 reaches the second output terminal 202 and is output.

[0091] Please continue reading. Figure 1 and Figure 2 And see Figures 22 to 33 In one embodiment, the logic gate can also be configured as follows:

[0092] When the topological magnetic structure 4 is input to the first input terminal 101 and the topological magnetic structure 4 is not input to the second input terminal 201, the first output terminal 102 outputs the topological magnetic structure 4, representing the logic gate input 1 and 0 and output 1;

[0093] When the first input terminal 101 does not input the topological magnetic structure 4, and the second input terminal 201 inputs the topological magnetic structure 4, the first output terminal 102 outputs the topological magnetic structure 4, representing the logic gate input 0 and 1 and output 1;

[0094] When the topological magnetic structure 4 is input to both the first input terminal 101 and the second input terminal 201, the first output terminal 102 outputs the topological magnetic structure 4, which represents the logic gate input 1 and 1 and output 1.

[0095] The following is combined with Figures 22 to 25 A detailed explanation of the logic gate's inputs of 1 and 0, and output of 1:

[0096] When the topological magnetic structure 4 is input to the first input terminal 101, and the second input terminal 201 does not input the topological magnetic structure 4, the first track 1 is as follows: Figure 22 As shown in Figure (a), the second track 2 is as follows Figure 22 As shown in Figure (b) of the document.

[0097] The topological magnetic structure 4 is driven to move along the first raceway 1 toward the first output terminal 102. At this time, the first raceway 1 is as follows: Figure 23 As shown in Figure (a), the second track 2 is as follows Figure 23 As shown in Figure (b) of the document.

[0098] When the topological magnetic structure 4 moves along the first track 1 to the vicinity of the intersection region 3, its energy is sufficient to penetrate the intersection region 3. Therefore, the topological magnetic structure 4 continues to move in the original direction, as follows: Figure 24 As shown in Figure (a), the second track 2 is as follows: Figure 24 As shown in Figure (b) of the document.

[0099] Finally, the topological magnetic structure 4 penetrates the intersection region 3, at which point the first track 1 is as follows: Figure 25 As shown in Figure (a), the second track 2 is as follows Figure 25 As shown in Figure (b). At this point, the logic gate has completed the operation of inputting 1 and 0 and outputting 1.

[0100] The following is combined with Figures 26 to 29 A detailed explanation of the logic gate's inputs of 0 and 1, and output of 1:

[0101] When the first input terminal 101 does not input the topological magnetic structure 4, and the second input terminal 201 inputs the topological magnetic structure 4, the first track 1 is as follows: Figure 26 As shown in Figure (a), the second track 2 is as follows Figure 26 As shown in Figure (b) of the document.

[0102] The topological magnetic structure 4 is driven to move along the second track 2 towards the intersection region 3, at which time the first track 1 is as follows: Figure 27 As shown in Figure (a), the second track 2 is as follows Figure 27 As shown in Figure (b) of the document.

[0103] When the topological magnetic structure 4 moves along the second track 2 to the vicinity of the intersection region 3, its own energy is sufficient to penetrate the intersection region 3. Therefore, due to the "tunneling" effect, the topological magnetic structure 4 gradually penetrates into the first track 1, as shown below. Figure 28 As shown in Figure (a), the second track 2 is as follows: Figure 28As shown in Figure (b) of the document.

[0104] Finally, the topological magnetic structure 4 completely penetrates into the first track 1, at which point the first track 1 is as follows: Figure 29 As shown in Figure (a), the second track 2 is as follows Figure 29 As shown in Figure (b), the first output terminal 102 outputs the topological magnetic structure 4. At this point, the logic gate has completed the operation of inputting 0 and 1 and outputting 1.

[0105] The following is combined with Figures 30 to 33 A detailed explanation of the logic gate's inputs of 1 and 2, and output of 1:

[0106] When the topological magnetic structure 4 is input to both the first input terminal 101 and the second input terminal 201, the first track 1 is as follows: Figure 30 As shown in Figure (a), the second track 2 is as follows Figure 30 As shown in Figure (b) of the document.

[0107] Both the topological magnetic structure 4 in the first input terminal 101 and the second input terminal 201 are driven, so that the topological magnetic structure 4 in the first input terminal 101 moves along the first track 1 towards the first output terminal 102, and the topological magnetic structure 4 in the second input terminal 201 moves along the second track 2 towards the intersection region 3. At this time, the first track 1 is as follows: Figure 31 As shown in Figure (a), the second track 2 is as follows Figure 31 As shown in Figure (b) of the document.

[0108] When the topological magnetic structures 4 in both the first input terminal 101 and the second input terminal 201 move to the vicinity of the intersection region 3, the topological magnetic structures 4 in the first input terminal 101 and the second input terminal 201 merge at the intersection region 3. This merging allows them sufficient energy to pass through the intersection region 3 and continue moving in their original direction. At this time, the first track 1... Figure 32 As shown in Figure (a), the second track 2 is as follows Figure 32 As shown in Figure (b) of the document.

[0109] Finally, the topological magnetic structure 4 penetrates the intersection region 3 and reaches the first output terminal 102, at which point the first track 1 is as follows: Figure 33 As shown in Figure (a), the second track 2 is as follows Figure 33 As shown in Figure (b). At this point, the logic gate has completed the operation of inputting 1 and 1 and outputting 1.

[0110] Based on the above embodiments, in some examples, the width of both the first track 1 and the second track 2 can be 30-60nm. For example, the width of the first track 1 and the second track 2 can be 30nm, 40nm, 50nm, or 60nm. This application does not specifically limit the width of the first track 1 and the second track 2. In some examples, the value of the interlayer exchange coupling coefficient can be 0.4-0.6. For example, the value of the interlayer exchange coupling coefficient can be 0.4, 0.5, or 0.6. This application does not specifically limit the value of the interlayer exchange coupling coefficient. Specifically, in one embodiment, the width of the first track 1 is 50nm, the width of the second track is 40nm, and the value of the interlayer exchange coupling coefficient is 0.5.

[0111] In one embodiment, the second track 2 may further include a reduction region; the reduction region is configured as follows:

[0112] When the first input terminal 101 is activated and the topological magnetic structure 4 is input to the first input terminal 101, if the second input terminal 201 does not input the topological magnetic structure 4, the weakening region effect will cause the topological magnetic structure 4 from the first input terminal 101 to move along the first track 1, pass through the weakening region, and reach the first output terminal 102, representing the logic gate input 0 and output 1.

[0113] When the first input terminal 101 is activated and a topological magnetic structure 4 is input to the first input terminal 101, if a topological magnetic structure 4 is input to the second input terminal 201, the weakening region will not function, causing the topological magnetic structure 4 from the first input terminal 101 and the topological magnetic structure 4 from the second input terminal 201 to merge in the intersection region 3, and causing the first output terminal 102 to have no topological magnetic structure 4 output, representing a logic gate input of 1 and output of 0.

[0114] Please continue reading. Figure 1 The weakening region can be a cross-shaped intersection similar to the intersection region 3, which acts as a barrier. When the activated topological magnetic structure 4 moves to the intersection region 3, it splits into small domain walls. In the above embodiment, the logic gate based on the topological magnetic structure causes these small domain walls to disintegrate during the movement due to insufficient energy through the weakening region, while the larger domain walls can reach the first output terminal 102 through the weakening region.

[0115] In one embodiment, the nanobilayer track may include, but is not limited to, layers of nanomaterials coupled with heavy metals.

[0116] In one embodiment, the heavy metal coupled nanomaterial layer may include, but is not limited to, a stacked structure in which a magnetic material layer, a heavy metal layer, and a magnetic material layer are stacked in sequence.

[0117] When a heavy metal material layer exists between two magnetic material layers, an antiferromagnetic exchange coupling can occur between the two magnetic material layers. The role of the heavy metal material layer includes generating weak magnetism (Dzyaloshinskii–Moriya interaction, DMI) at the interface between the heavy metal material layer and the magnetic material layer to stabilize the topological magnetic structure.

[0118] In one embodiment, the topological magnetic structure may include, but is not limited to, magnetic skyrmions, double skyrmions, Nell-type skyrmions, anti-skyrmions, or Bloch-type skyrmions. This application does not specifically limit the type of topological magnetic structure, and the industry can decide which topological magnetic structure to use based on the specific implementation of this application in practice.

[0119] Specifically, in one embodiment, the topological magnetic structure includes magnetic skyrmions.

[0120] Magnetic skyrmions are chiral spin structures with vortex structures that can stably exist in bulk magnets with extremely strong spin-track coupling or in nanofilms coupled to heavy metals. Recent research has shown that magnetic skyrmions can be used as carriers of binary information within chips, and chip designs based on magnetic skyrmions hold promise for reducing chip power consumption and size. The logic gates based on topological magnetic structures in the above embodiments, by employing magnetic skyrmions as the topological magnetic structure, can further reduce the size of the logic gates. Magnetic skyrmions are a special type of magnetic domain structure with topological protection, which is more stable than traditional domain walls and can remain stable when external conditions (magnetic fields, temperature, and device defects, etc.) change, thus making the NOT gates based on magnetic skyrmions more stable and able to retain logic values ​​even when power is lost. The initiation current density of magnetic skyrmions is much smaller than that of traditional domain walls, approximately one millionth of that of traditional domain walls, enabling logic gates based on magnetic skyrmions to further reduce power consumption.

[0121] In one embodiment, the driving method of the topological magnetic structure may include, but is not limited to, current driving, electric field driving, spin polarized current driving or magnetocrystalline anisotropy gradient driving methods. This application does not specifically limit the driving method of the topological magnetic structure.

[0122] In one embodiment, the topological magnetic structure can be driven by current. Building upon the above embodiment, the logic gates are connected to a power supply; the power supply provides current to the logic gates, which in turn drives the topological magnetic structure to move along a first track and / or a second track.

[0123] In the description of this specification, references to terms such as "one embodiment," "some examples," or "other embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0124] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A logic gate based on a topological magnetic structure, characterized in that, include: A nano-double-layer track, comprising a first track and a second track, which intersect to form an intersection region; wherein, the first track includes a first input end and a first output end; the second track includes a second input end and a second output end; the first track and the second track are used to provide a path for the movement of the topological magnetic structure; The logic gate is configured as follows: When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the second input terminal does not input the topological magnetic structure, the topological magnetic structure from the first input terminal moves along the first track to the first output terminal, representing that the logic gate input is 0 and output is 1. When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the topological magnetic structure is input to the second input terminal, the topological magnetic structure from the first input terminal and the topological magnetic structure from the second input terminal are merged in the intersection region, and the first output terminal has no output of the topological magnetic structure, representing that the logic gate has an input of 1 and an output of 0. The logic gate is also configured as follows: When the topological magnetic structure is input to the first input terminal and the topological magnetic structure is not input to the second input terminal, the topological magnetic structure is output to the first output terminal, representing the logic gate input 1 and 0 and output 1; When the topological magnetic structure is not input to the first input terminal, and the topological magnetic structure is input to the second input terminal, the topological magnetic structure is output to the first output terminal, representing that the logic gate inputs 0 and 1 and outputs 1; When the topological magnetic structure is input to both the first input terminal and the second input terminal, the topological magnetic structure is output from the first output terminal, representing the logic gate input 1 and 1, and output 1. The second track includes a reduction zone; the reduction zone is configured as follows: When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the second input terminal does not input the topological magnetic structure, the weakening region acts, causing the topological magnetic structure from the first input terminal to move along the first track, pass through the weakening region, and reach the first output terminal, representing the logic gate input 0 and output 1; When the first input terminal is activated and the topological magnetic structure is input to the first input terminal, if the topological magnetic structure is input to the second input terminal, the weakening region does not function, so that the topological magnetic structure from the first input terminal and the topological magnetic structure from the second input terminal merge in the intersection region, and the first output terminal has no output of the topological magnetic structure, representing that the logic gate has an input of 1 and an output of 0.

2. The logic gate according to claim 1, characterized in that, The logic gate is also configured as follows: When the topological magnetic structure is input to the first input terminal and the topological magnetic structure is not input to the second input terminal, the first output terminal will not output the topological magnetic structure, which means that the logic gate inputs 1 and 0 and outputs 0. When the topological magnetic structure is not input to the first input terminal, and the topological magnetic structure is input to the second input terminal, the first output terminal will not output the topological magnetic structure, which means that the logic gate inputs 0 and 1 and outputs 0. When the topological magnetic structure is input to both the first input terminal and the second input terminal, the topological magnetic structure is output from the first output terminal, representing the logic gate input 1 and 1, and output 1.

3. The logic gate according to claim 2, characterized in that, The path width is 10-20nm; the interlayer exchange coupling coefficient between the first track and the second track is 0.7-0.

9.

4. The logic gate according to claim 1, characterized in that, The path width is 30-60nm; the interlayer exchange coupling coefficient between the first track and the second track is 0.4-0.

6.

5. The logic gate according to claim 1, characterized in that, The nano-bilayer track comprises a layer of nanomaterials coupled with heavy metals.

6. The logic gate according to claim 5, characterized in that, The heavy metal coupled nanomaterial layer comprises a stacked structure consisting of a magnetic material layer, a heavy metal layer, and another magnetic material layer stacked sequentially.

7. The logic gate according to any one of claims 1 to 6, characterized in that, The topological magnetic structure includes magnetic skyrmions.

8. The logic gate according to claim 1, characterized in that, The logic gate is connected to the power supply; The power supply is used to provide current to the logic gate, and the current is used to drive the topological magnetic structure to move along the first track and / or the second track.

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