Swap and restore context-specific branch predictor states during context switching in the processor.

Abstract

During context switching in the processor, context-specific branch predictor states are swapped and restored. The branch prediction circuitry in the processor's instruction processing circuitry includes a private branch prediction memory configured to store the branch prediction state of the context of the executing process. The branch prediction circuitry accesses the branch prediction state to predict the results of branch instructions for its process. In some aspects, when a context switch occurs in the processor, the branch prediction state stored in the private branch prediction memory and associated with the current context to be swapped out is swapped out to a shared branch prediction memory. The previously stored (i.e., swapped out) branch prediction state in the shared branch prediction memory and associated with the context to be swapped in for execution is restored in the private branch prediction memory for branch prediction.

Description

Technical Field

[0001] The technology disclosed herein relates to the processing of instructions for execution in a computer processor (“processor”), and more specifically, to branch prediction of branch instructions in a processor. Background Technology

[0002] Microprocessors (also called “processors”) perform computational tasks for various applications. A typical microprocessor includes a central processing unit (CPU), which comprises one or more processor cores, also called “CPU cores.” The CPU executes computer program instructions (“instructions”) (also called “software instructions”) to perform operations based on data and generate results (i.e., produce values). Instructions that generate produce values ​​are “producer” instructions. For example, the produced value can then be stored in memory, provided as output to input / output (“I / O”) devices, or used as input value for another “consumer” instruction executed by the CPU. Therefore, consumer instructions depend on the produced value generated by the producer instructions as input value for execution.

[0003] Processors can employ instruction pipelining as a processing technique, thereby increasing the throughput of executing computer instructions by breaking down the processing of each instruction into a series of steps. These steps are executed in an execution pipeline consisting of multiple stages. Optimal processor performance can be achieved if all stages in the execution pipeline can process instructions simultaneously and sequentially as they are ordered in the instruction pipeline(s). However, structural risks can occur in instruction pipelines where the next instruction cannot be executed without leading to incorrect computation results. For example, control risks can occur due to the execution of control flow instructions that cause precise interruptions in the processor. An example of a control flow instruction that can lead to control risks is a conditional branch instruction. A conditional branch instruction can redirect the flow path of instruction execution based on the result of an evaluation when executing a control branch instruction. As a result, the processor may have to stop fetching additional instructions until the conditional control instruction has been executed, leading to reduced processor performance and increased power consumption.

[0004] One approach to maximizing processor performance involves using prediction circuitry to speculatively predict the outcome of conditional branch instructions. For example, the prediction of the path taken by a conditional branch instruction can be based on program history stored in a private branch prediction memory (e.g., a private branch prediction table) within the instruction pipeline and may include the branch prediction history of previously executed conditional branch instructions. When the conditional branch instruction finally arrives at the execution stage of the instruction pipeline and is executed, the result target address of the conditional branch instruction is verified by comparing it with the target address predicted when the conditional branch instruction was fetched. If the predicted target address matches the actual target address, this indicates a correct prediction, and instruction execution is not delayed because subsequent instructions at the target address are correctly fetched and already present in the instruction pipeline when the conditional branch instruction arrives at the execution stage. Power consumption is also reduced because the processor does not have to stop processing instructions following the conditional branch instruction until the conditional branch instruction is executed. Therefore, performance and power consumption can be improved by employing accurate branch prediction in the processor. However, if the predicted target address does not match the actual target address, there is a risk of mispredicted branches in the instruction pipeline, leading to precise interrupts. As a result, the error prediction recovery process is performed, which flushes the instruction pipeline and redirects the instruction fetch unit to fetch new instructions starting from the target address, leading to latency and performance degradation. Error prediction in instruction processing within the processor can be costly in terms of latency and performance degradation. Therefore, the more accurate the branch prediction, the better the performance and power savings achieved, offsetting any performance and power degradation that occurs during error prediction recovery.

[0005] Generally, branch predictors with larger branch prediction tables are more accurate because they can store more program history for branch prediction. However, processor design and performance constraints (such as cycle time and area constraints) can limit the size of a branch predictor's branch prediction table. One approach to increase the memory size of the branch prediction table without allocating additional memory in the branch predictor within the instruction pipeline is to allocate additional memory to store the branch prediction history in a separate, shared, lower-level memory outside the fetch stage of the instruction pipeline. For example, a larger branch prediction memory could be allocated in main memory or a lower-level cache servicing the processor. The smaller branch prediction table in the instruction pipeline can act as a cache for the branch prediction memory. The branch prediction memory is shared between different contexts of processes (e.g., threads) executing in the processor for storing and accessing branch prediction history. Branch prediction states can be swapped in and out between the smaller branch prediction table in the branch predictor within the instruction pipeline and branch prediction memory such as a cache. Therefore, the effective capacity of the branch prediction table in the branch predictor of the instruction pipeline can be increased to improve branch prediction accuracy without having to increase the branch prediction table in the branch predictor.

[0006] However, providing a larger shared branch prediction memory can be a source of leaked information about applications executing on the processor, thus exposing applications to security vulnerabilities. For example, a malicious attacker's application executing on the processor could initiate a branch predictor to place the branch prediction history in a predefined state. Therefore, later, when the victim application is executed, the predefined branch prediction history state initiated by the attacker's application in the shared branch prediction memory will be cached in the branch predictor's branch prediction table and affect the victim application's speculative execution path. The victim application will cause some branch prediction entries in the branch prediction table to be updated and / or evicted into the shared branch prediction memory. Therefore, when the attacker's application resumes execution, it can access the shared branch prediction memory to detect changes in the branch prediction state due to the victim application's execution and extract information about the victim application. Disabling branch prediction can avoid such a security vulnerability, but this negates the performance advantages of branch prediction. An alternative solution to prevent this security vulnerability might be to flush the branch prediction memory on each context switch, thus preventing the leakage of branch prediction history updates caused by the executing application. However, this would require the branch predictor to be retrained after each context switch, and would lead to a decrease in the accuracy of branch predictions during training. Summary of the Invention

[0007] The aspects disclosed herein include exchanging and restoring context-specific branch predictor states during context switching in a processor. A context is a minimal dataset used by a process (“process”) of an application executing in the processor of a central processing unit (CPU), which is preserved to allow the task to be interrupted and later executed from the same point of interruption. Context switching stores the context state of the interrupted process, allowing the context state to be later restored from the same point and the execution of the process to resume in the processor. Context switching allows multiple processes to share a single processor. In this regard, the processor includes instruction processing circuitry comprising multiple instruction processing stages configured to pipeline the processing and execution of fetched instructions according to data flow execution. The instruction processing circuitry includes fetching circuitry in the fetching stage, configured to fetch instructions from instruction memory to be inserted into the instruction pipeline for execution. Branch predictor circuitry is configured to speculatively predict the result of the fetched branch instruction (e.g., a conditional branch instruction, an indirect branch instruction, a return branch instruction) to determine the next instruction to be fetched by the fetching circuitry into the instruction pipeline. The branch prediction circuit is configured to access the branch prediction state to speculatively predict the outcome of a branch instruction.

[0008] In the exemplary aspects disclosed herein, branch prediction circuitry includes a private branch prediction memory (e.g., branch prediction table circuitry) configured to store the branch prediction state of the context of the currently executing process (“current context”) for use during execution when predicting the result of a branch instruction in the current context. The private branch prediction memory is affected only by the current context and not by the contexts of other processes not currently executing. When a context switch occurs in the processor, the branch prediction state stored in the private branch prediction memory and associated with the current context to be swapped out is swapped out from the private branch prediction memory to a shared branch prediction memory. A shared branch prediction memory is a shared structure configured to store the branch prediction states of multiple contexts for multiple running processes. For example, the shared branch prediction memory may be external to instruction processing circuitry, such as in a cache memory or main memory associated with the processor. Previously stored (i.e., swapped out) branch prediction states in the shared branch prediction memory and associated with the context to be swapped in are restored in the private branch prediction memory for use during execution of the process associated with the swapped-in context. Another context change again restores the associated branch prediction state in the shared branch prediction memory for the newly swapped-in context to the private branch prediction memory, where the branch prediction state of the currently swapped-out context in the private branch prediction memory is stored back to the shared branch prediction memory.

[0009] In this way, the branch prediction history of a process's current context is preserved and not lost when the context is swapped out of the instruction processing circuitry and swapped back in for use later in the execution of its associated process. The size of the private branch prediction memory can be dedicated to storing the branch prediction state of the current context, effectively increasing the size of the branch predictor circuitry for more accurate branch predictions, rather than sharing the private branch prediction memory across multiple different contexts. Moreover, because the shared branch prediction memory can store the branch prediction states of multiple specific shared contexts, there is no need to flush the shared branch prediction memory during context switches to avoid the attacker process leaking information about the victim process's context. Therefore, for example, if the attacker process initiates a branch prediction state in the private branch prediction memory, and then the victim process is subsequently swapped in to execute in place of the attacker process, the initiated branch prediction state is not used for branch prediction of branch instructions in the victim process. The attacker process's branch prediction state is swapped out to the shared branch prediction memory, while the previously stored victim process's branch prediction state is swapped into the private branch prediction memory. Therefore, when the attacker process is swapped back in, the previously initiated branch prediction history is restored in the private branch prediction memory, not the victim process's context branch prediction history. The victim application is unaffected by the initiated branch prediction state associated with the attacker process. Consequently, the attacker process cannot detect how the victim process executes based on how the initiated branch prediction state is affected by the victim process's execution.

[0010] In this regard, in one exemplary aspect, a branch prediction circuit is provided. The branch prediction circuit includes a private branch prediction memory configured to store at least one branch prediction state of the current context of a currently executing process within the instruction processing circuit of a processor. The branch prediction circuit is configured to speculatively predict the outcome of a branch instruction based on a branch prediction state among at least one branch prediction state in the current context of the private branch prediction memory associated with a branch instruction in the currently executing process within the instruction processing circuit. The branch prediction circuit is also configured to receive a process identifier identifying a new context swapped into the instruction processing circuit. In response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuit, the branch prediction circuit is further configured to store at least one branch prediction state associated with the new context as at least one branch prediction state in the private branch prediction memory.

[0011] In another exemplary aspect, a method is provided for predicting the branch result of a branch instruction in a context executed in an instruction processing circuit of a processor. The method includes speculatively predicting the result of the branch instruction based on a branch prediction state among at least one branch prediction state of the current context of the current process in a private branch prediction memory associated with the branch instruction in the current process executing in the instruction processing circuit. The private branch prediction memory is configured to store at least one branch prediction state of the current context of the current process to be executed in the instruction processing circuit of the processor. The method further includes receiving a process identifier identifying a new context swapped into the instruction processing circuit. The method further includes determining whether the process identifier indicates a new context different from the current context swapped into the instruction processing circuit. The method further includes, in response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuit, causing at least one branch prediction state associated with the new context to be stored as at least one branch prediction state in the private branch prediction memory.

[0012] In another exemplary aspect, a processor-based system is disclosed. The processor-based system includes a processor. The processor includes instruction processing circuitry including one or more instruction pipelines, each including fetch circuitry, branch prediction circuitry, and execution circuitry. The fetch circuitry is configured to fetch a plurality of instructions from memory into one or more instruction pipelines for execution by the execution circuitry. The instruction processing circuitry also includes branch prediction circuitry including a private branch prediction memory configured to store at least one branch prediction state of a current context to be executed in the processor's instruction processing circuitry. The branch prediction circuitry is configured to speculatively predict the outcome of a branch instruction based on a branch prediction state in the private branch prediction memory associated with a branch instruction in the current context executed in the instruction processing circuitry. The instruction processing circuitry is configured to receive a process identifier identifying a new context swapped into the instruction processing circuitry, and in response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuitry, to store at least one branch prediction state associated with the new context as at least one branch prediction state in the private branch prediction memory. The processor also includes a shared branch prediction memory configured to store at least one branch prediction state associated with a context in each of a plurality of contexts associated with a corresponding process configured to be executed in the instruction processing circuitry.

[0013] After reading the following detailed description of preferred embodiments associated with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement its additional aspects. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0015] Figure 1 This is an illustration of an exemplary processor-based system including a processor with instruction processing circuitry including one or more instruction pipelines for processing computer instructions for execution, wherein the instruction processing circuitry is configured to retrieve a branch prediction state associated with a swap-in context from a shared branch prediction memory, and swap in and restore the branch prediction state of the branch prediction circuitry retrieved in a private branch prediction memory for branch prediction during the execution of a process associated with the swap-in context.

[0016] Figure 2 It is shown Figure 1 A flowchart illustrating an exemplary process of the instruction processing circuitry in the diagram;

[0017] Figure 3 This is a diagram illustrating a branch prediction memory, which includes a static partitioned memory configured to store branch prediction states by context and a non-partitioned memory configured to store the branch prediction states of the current context of the currently executing process.

[0018] Figure 4 It is shown Figure 1 A flowchart of an alternative exemplary process of the instruction processing circuitry in which, in response to a context switch, the branch prediction state associated with the swapped-in context in the shared branch prediction memory is partially swapped in and restored to the private branch prediction memory for use in branch prediction during the execution of the process associated with the swapped-in context.

[0019] Figure 5 This is an illustration of an alternative exemplary processor-based system including instruction processing circuitry configured to temporarily use an alternative branch prediction scheme in response to a context switch until the retrieved branch prediction state is swapped in and out from shared branch prediction memory to private branch prediction memory for branch prediction in the execution of the process associated with the swapped-in context, until the swapping of the swapped-in context is complete.

[0020] Figure 6 It is shown Figure 5 A flowchart illustrating an exemplary process of the instruction processing circuitry in the diagram;

[0021] Figure 7This is an illustration of another alternative exemplary processor-based system, which includes a processor having instruction processing circuitry including one or more instruction pipelines for processing computer instructions for execution. The instruction processing circuitry includes a main branch prediction circuit and a secondary branch prediction circuit configured to store the corresponding branch prediction state of the current context and the branch prediction state of another next context that may be swapped in after the current context. The instruction processing circuitry is configured to retrieve the branch prediction state associated with the next context from a shared branch prediction memory and swap in and restore the retrieved branch prediction state in the private branch prediction memory of the secondary branch prediction circuit to prepare for branch prediction during execution of the process associated with the next context when the current context is swapped in.

[0022] Figure 8A and Figure 8B It is shown Figure 7 An exemplary flowchart of the instruction processing circuitry in the diagram; and

[0023] Figure 9 This is a block diagram of an exemplary processor-based system including a processor with instruction processing circuitry, the instruction processing circuitry including branch prediction circuitry for predicting the outcome of branch instructions, wherein the instruction processing circuitry is configured to retrieve a branch prediction state associated with a swap-in context from a shared branch prediction memory, and swap in and restore the retrieved branch prediction state of the branch prediction circuitry in a private branch prediction memory for branch prediction during execution in the swap-in context, including but not limited to... Figure 1 , Figure 5 and Figure 7 The instruction processing circuit in the middle. Detailed Implementation

[0024] The aspects disclosed herein include exchanging and restoring context-specific branch predictor states during context switching in a processor. A context is a minimal dataset used by a process of an application (“process”) executing in the processor of a central processing unit (CPU), which is preserved to allow the task to be interrupted and later executed from the same point of interruption. Context switching stores the context state of the interrupted process, allowing the context state to be later restored from the same point and the execution of the process to resume in the processor. Context switching allows multiple processes to share a single processor. In this regard, the processor includes instruction processing circuitry comprising multiple instruction processing stages configured to pipeline the processing and execution of fetched instructions according to data flow execution. The instruction processing circuitry includes fetching circuitry in the fetching stage, configured to fetch instructions from instruction memory to be inserted into the instruction pipeline for execution. Branch predictor circuitry is configured to speculatively predict the result of the fetched branch instruction (e.g., conditional branch instruction, indirect branch instruction, return branch instruction) to determine the next instruction to be fetched by the fetching circuitry into the instruction pipeline. The branch prediction circuit is configured to access the branch prediction state to speculatively predict the outcome of a branch instruction.

[0025] In the exemplary aspects disclosed herein, branch prediction circuitry includes a private branch prediction memory (e.g., branch prediction table circuitry) configured to store the branch prediction state of the context of the currently executing process (“current context”) for use during execution when predicting the result of a branch instruction in the current context. The private branch prediction memory is affected only by the current context and not by the contexts of other processes not currently executing. When a context switch occurs in the processor, the branch prediction state stored in the private branch prediction memory and associated with the current context to be swapped out is swapped out from the private branch prediction memory to a shared branch prediction memory. A shared branch prediction memory is a shared structure configured to store the branch prediction states of multiple contexts for multiple running processes. For example, the shared branch prediction memory may be external to instruction processing circuitry, such as in a cache memory or main memory associated with the processor. Previously stored (i.e., swapped out) branch prediction states in the shared branch prediction memory and associated with the context to be swapped in are restored in the private branch prediction memory for use during execution of the process associated with the swapped-in context. Another context change again restores the associated branch prediction state in the shared branch prediction memory for the newly swapped-in context to the private branch prediction memory, where the branch prediction state of the currently swapped-out context in the private branch prediction memory is stored back to the shared branch prediction memory.

[0026] In this way, the branch prediction history of a process's current context is preserved and not lost when the context is swapped out of the instruction processing circuitry and swapped back in for use later in the execution of its associated process. The size of the private branch prediction memory can be dedicated to storing the branch prediction state of the current context, effectively increasing the size of the branch predictor circuitry for more accurate branch predictions, rather than sharing the private branch prediction memory across multiple different contexts. Moreover, because the shared branch prediction memory can store the branch prediction states of multiple specific shared contexts, there is no need to flush the shared branch prediction memory during context switches to avoid the attacker process leaking information about the victim process's context. Therefore, for example, if the attacker process initiates a branch prediction state in the private branch prediction memory, and then the victim process is subsequently swapped in to execute in place of the attacker process, the initiated branch prediction state is not used for branch prediction of branch instructions in the victim process. The attacker process's branch prediction state is swapped out to the shared branch prediction memory, while the previously stored victim process's branch prediction state is swapped into the private branch prediction memory. Therefore, when the attacker process is swapped back in, the previously initiated branch prediction history is restored in the private branch prediction memory, not the victim process's branch prediction history. The victim application is unaffected by the initiated branch prediction state associated with the attacker process. Consequently, the attacker process cannot detect how the victim process executes based on how the initiated branch prediction state is affected by the victim process's execution.

[0027] On this point, Figure 1 This is a diagram of an exemplary processor-based system 100 including processor 102. Processor 102 may be an ordered or unordered processor (OoP). Processor 102 may also be referred to as a "processor core" or a "central processing unit (CPU) core". Processor-based system 100 may include multiple processors 102. In this example, processor 102 includes instruction processing circuitry 104, which includes one or more instruction pipelines I0-I for processing fetched computer instructions 106F fetched by fetch circuitry 108 for execution. NThe fetch circuit 108 is configured to fetch instruction 106 from instruction memory 110. As an example, instruction memory 110 may be located in or be part of system memory in the processor-based system 100. An instruction cache 112 may also be provided in processor 102 to cache instruction 106 fetched from instruction memory 110, thereby reducing latency in the fetch circuit 108. In this example, the fetch circuit 108 is configured to provide instruction 106 as fetch instruction 106F to one or more instruction pipelines I0-I before the fetched instruction 106F reaches the execution circuit 116 to be executed. N The instruction stream 114 in instruction processing circuit 104 is to be preprocessed. The extracted instructions 106F in instruction stream 114 include producer instructions and consumer instructions. The consumer instructions consume the values ​​generated by the execution of producer instructions by instruction processing circuit 104. Instruction pipeline I0-I N Different processing circuits or stages across instruction processing circuitry 104 are provided to preprocess and process fetch instruction 106F in a series of steps that can be executed simultaneously before execution circuitry 116 executes fetch instruction 106F, in order to increase throughput.

[0028] Continue to refer to Figure 1 The instruction processing circuit 104 includes a decoding circuit 118 configured to decode the fetch instruction 106F fetched by the fetch circuit 108 into a decoded instruction 106D to determine the instruction type and the required action. The instruction type and required action encoded in the decoded instruction 106D can also be used to determine which instruction pipeline I0-I the decoded instruction 106D should be placed in. N In this example, the decoding instruction 106D is placed in instruction pipeline I0-I. N One or more instruction pipelines are then fed into the renaming circuit 120 in the instruction processing circuit 104. The renaming circuit 120 is configured to determine whether any register names in the decoded instruction 106D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The renaming circuit 120 is configured to invoke the register map table (RMT) 122 to rename the logical source register operands and / or write the destination register operands of the decoded instruction 106D to the available physical registers 124(1)-124(X) (P0, P1, ..., PX) in the physical register file (PRF) 126. The RMT 122 contains multiple mapping entries, each mapped to a corresponding logical register R0-R P(That is, associated with it). The mapping entries are configured to store information in the form of address pointers to physical registers 124(1)-124(X) in the physical register file (PRF) 126. Each physical register 124(1)-124(X) in the PRF 126 contains a data entry configured to store data of the source and / or destination register operands of the decode instruction 106D.

[0029] Figure 1 The instruction processing circuitry 104 in the processor 102 also includes a register access (RACC) circuitry 128. The register access circuitry 128 is configured to access the logical registers R0-R0 in the RMT 122 based on the source register operands mapped to the decoded instruction 106D. P The mapping entries are used to access physical registers 124(1)-124(X) in PRF 124 to retrieve the generated value from the executed instruction 106E in execution circuit 116. Register access circuit 128 is also configured to provide the generated value retrieved from the executed decode instruction 106E as the source register operand for the decode instruction 106D to be executed. Moreover, in instruction processing circuit 104, scheduler circuit 130 is set in instruction pipeline I0-I N The system is configured to store the decoded instruction 106D in a reserved entry until all source register operands of the decoded instruction 106D are available. For example, the scheduler circuit 130 is responsible for determining the necessary values ​​of the operands for decoding the consumer instruction 106D in the release channels L0-L among the "K" release channels. K-1 The execution circuit 116 issues a decoded consumer instruction 106D to the execution circuit 116 for execution. The scheduler circuit 130 issues the decoded instruction 106D ready for execution to the execution circuit 116. A write circuit 132 is also provided in the instruction processing circuit 104 to write the generated value from the executed instruction 106E back or commit it to memory, such as PRF 126, cache memory or system memory.

[0030] Continue to refer to Figure 1 The instruction processing circuit 104 also includes a branch prediction circuit 134. The branch prediction circuit 134 is configured to speculatively predict the result of fetching the branch instruction 106F, and whether the path used or not used in the instruction control flow path controlling the instruction flow 114 is fetched into the instruction pipeline I0-I. NThe branch instruction 106F can be used for execution. For example, the branch instruction 106F can be a conditional branch instruction, which includes a condition to be resolved by the instruction processing circuit 104 to determine which control flow path in the instruction flow 114 should be taken. In this way, the result of fetching the branch instruction 106F (in this example, a conditional branch instruction) does not need to be resolved during the execution of the execution circuit 116 before the instruction processing circuit 104 can continue processing the fetch instruction 106F. The prediction made by the branch prediction circuit 134 can be provided by the fetch circuit 108 as prediction information 135 for the fetch circuit 108 to determine the next instruction 106 to be fetched as the fetch instruction 106F. Other examples of branch instructions 106F that can be fetched include indirect branch instructions and return branch instructions. In this example, the branch prediction circuit 134 makes a speculative prediction of the branch instruction 106F based on the branch prediction state stored in the private branch prediction memory 136. As will be discussed in more detail below, the private branch prediction memory 136 is affected only by the context of the currently executing process in the instruction processing circuit 104, and not by the context of other processes that are not currently executing.

[0031] Private branch prediction memory 136 is configured to store branch prediction states 138(0)-138(B), which in this example are "B+1" branch prediction states. For example, private branch prediction memory 136 may be a branch prediction table circuit 140 containing multiple indexable entries 141(0)-141(B) configured to store the corresponding branch prediction states 138(0)-138(B). Branch prediction circuit 134 is configured to speculatively predict the result of fetching branch instruction 106F based on the branch prediction states 138(0)-138(B) retrieved from private branch prediction memory 136, to determine which instruction will be fetched into instruction pipeline I0-I by fetch circuit 108. N The next instruction 106 in the pipeline. For example, if the branch prediction circuit 134 predicts that the result of the branch instruction 106F is that the branch instruction 106F will be resolved into the adopted instruction flow path, then the branch prediction circuit 134 can provide this prediction information 135 to the fetch circuit 108 so that the fetch circuit 108 fetches instruction 106 from the adopted instruction flow path into (multiple) instruction pipelines I0-I N However, if the branch prediction circuit 134 predicts that the branch instruction 106F will be resolved into the adopted instruction flow path, the branch prediction circuit 134 can also provide this prediction information 135 to the fetch circuit 108 so that the fetch circuit 108 fetches the instruction 106 from the adopted instruction flow path into (multiple) instruction pipelines I0-I. NIf, once the branch instruction 106F is executed in the execution circuit 116 to resolve the condition, it is determined that the prediction is an incorrect prediction, then the instruction 106 fetched from the incorrect instruction flow path to the instruction processing circuit 104 can be refreshed, and the instruction 106 from the correct instruction flow path can be fetched.

[0032] As an example, branch prediction states 138(0)-138(B) may include bits using logic state "0" to represent an unadopted branch state and logic state "1" to represent an adopted branch state. Branch prediction table circuit 134 may be configured to store static states as branch prediction states 138(0)-138(B) in branch prediction table circuit 140, which do not change dynamically based on the execution of instruction 106F. Alternatively, branch prediction circuit 134 may be configured to update branch prediction states 138(0)-138(B) in branch prediction circuit 140 based on the execution history of instruction 106F. For example, branch prediction states 138(0)-138(B) may be updated based on the history of the parsing conditions of branch instruction 106F executed in execution circuit 116. Therefore, a larger number of branch prediction states 138(0)-138(B) allows for the storage of more specific historical information about branch instructions, thereby improving the accuracy of branch prediction.

[0033] Figure 1 The processor 102 in the instruction processing circuit 104 can be a multitasking processor capable of swapping in and out running processes (e.g., threads) to be executed in the instruction processing circuit 104. Context information (referred to as "context") is information used and updated by the instruction processing circuit 104 during process execution. For example, the context may include data stored in RMT 122 and / or PRF 126, flag states, and branch prediction states 138(0)-138(B) stored in the branch prediction table circuit 140 when the process is executing in the instruction processing circuit 104. The context in the processor 102 is a minimal dataset used by the process executing in the processor 102, which is preserved to allow the task to be interrupted and later executed from the same interrupt point. Therefore, when a new next process is swapped into the instruction processing circuit 104 to replace the currently executing process, a context switch is performed by the processor 102. Context switching allows multiple processes to share the processor 102. A context switch is the processor storing the context of the current process interrupted, which is then swapped out of instruction processing circuitry 104 to support a new next process. This allows the context to be restored from the same point of interruption and the execution of the previously current process to resume in processor 102. Therefore, a context switch involves restoring the context of the next process swapped into instruction processing circuitry 104 for execution and swapping the next process itself.

[0034] exist Figure 1 In this example of processor 102, it is desirable to set the size of the private branch prediction memory 136 of the branch prediction circuit 134 to store a desired number of branch prediction states 138(0)-138(B) to provide a desired level of prediction accuracy, but within the design and performance constraints of processor 102. For example, processor 102 may be constrained by loop count and area constraints, which may limit the size of the private branch prediction memory 136 in the branch prediction circuit 134. One way to increase the memory size of the private branch prediction memory 136 to improve branch prediction accuracy without increasing the storage in the branch prediction circuit 134 is to allocate additional memory for storing branch prediction states in a separate shared memory. In this respect, as Figure 1 As shown, the processor-based system 100 includes a shared branch prediction memory 142. In this example, the shared branch prediction memory 142 is located outside the branch prediction circuitry 134, thus not consuming area in the branch prediction circuitry 134 and / or its private branch prediction memory 136. The shared branch prediction memory 142 may be located outside the instruction processing circuitry 104. For example, the shared branch prediction memory 142 may be located in a cache memory, including but not limited to a cache inside the processor 102 (e.g., L1 cache), a cache outside the processor 102 (e.g., L3 cache), or the main memory of the processor-based system 100 (e.g., double data rate random access memory (RAM) (DDRAM)). The size of the shared branch prediction memory 142 is configured to store multiple contexts 144(0)-144(C) of different processes that have been executed in the processor 102 and can be swapped into the instruction processing circuitry 104 for further execution. Each context 144(0)-144(C) is configured to store multiple branch prediction states 146(0)(0)-146(C)(B) in the corresponding multiple entries 148, wherein “S” can be equal to “B” for the capacity of branch prediction states 138(0)-138(B) in the private branch prediction memory 136.

[0035] In this example, instruction processing circuitry 104 receives a process identifier (ID) 150, which identifies the new context of the new process swapped into instruction processing circuitry 104 for execution during a process swap. As an example, by identifying the next context to be swapped into instruction processing circuitry 104 via process ID 150, process ID 150 identifies a process that can be associated with its context, or process ID 150 can be used to identify a context. For example, an operating system (OS) executing in processor 102 can control process swapping and cause process ID 150 to be generated. If the process ID is different from the process currently executing in instruction processing circuitry 104, process ID 150 indicates a process swap. In this example, when a context switch occurs in processor 102 in response to a new swap-in process indicated by process ID 150 that is different from the currently executing process in instruction processing circuit 104, instruction processing circuit 104 is configured to swap the branch prediction states 146(0)-146(B) of the context associated with the swap-in process to be executed from shared branch prediction memory 142 to private branch prediction memory 136. Similarly, in order to preserve the current branch prediction states 138(0)-138(B) in private branch prediction memory 136 for use by the swap-out process, instruction processing circuit 104 is configured to first swap the branch prediction states 138(0)-138(B) from private branch prediction memory 136 to its reserved context 144(0)-144(C) in shared branch prediction memory 142. In this way, the branch prediction circuit 134 uses the restored branch condition states 146()(0)-146()(B) for the new process being swapped in to speculatively predict the branch instruction 106F. However, the previous branch condition states 138(0)-138(B) of the swapped-out process are not lost, but are stored in their reserved contexts 144(0)-144(C) in the shared branch prediction memory 142. If the swapped-out process is swapped into the instruction processing circuit 104 again, the previously stored branch condition states 146()(0)-146()(B) of the swapped-out process can be swapped back into the private branch prediction memory 136 as the current branch prediction states 138(0)-138(B) for use by the branch prediction circuit 134 in its execution. This is the opposite of refreshing the branch prediction state 138(0)-138(B) in the private branch prediction memory 136. Refreshing the branch prediction state 138(0)-138(B) in the private branch prediction memory 136 will delete the branch prediction history of the swap-in context and cause the branch prediction circuit 134 to retrain the branch prediction of the swap-in process by updating the refreshed private branch prediction memory 136.

[0036] In this way, the size of the private branch prediction memory 136 can be dedicated to storing the branch prediction states 138(0)-138(B) of the current context of the currently executing process, thereby effectively increasing the size of the branch predictor circuit 134 for more accurate branch prediction, instead of sharing the private branch prediction memory 136 among multiple different contexts. Moreover, because the shared branch prediction memory 142 is capable of storing the branch prediction states 146(0)(0)-146(C)(B) for multiple shared specific contexts 144(0)-144(C), refreshing the shared branch prediction memory 142 during context switching is not necessary to prevent the attacker process from leaking information about the victim process. Therefore, for example, if the attacker process initiates the branch prediction states 138(0)-138(B) in the private branch prediction memory 136, and then the victim process is subsequently swapped into the instruction processing circuit 104 to execute in place of the attacker process, the initiated branch prediction states 138(0)-138(B) are not used for branch prediction of branch instructions in the victim process. The attacker process's branch prediction states 138(0)-138(B) are swapped out to the shared branch prediction memory 142, and the previously stored branch prediction states 146(0)(0)-146(C)(B) of the victim process's specific context 144(0)-144(C) are swapped back to the private branch prediction memory 136. Therefore, when the attacker process is swapped back in, the previously initiated branch prediction history 138(0)-138(B) is restored in the private branch prediction memory 136 to replace the victim process's branch prediction states, and the victim process is not affected by the initiated branch prediction states 138(0)-138(B) associated with the attacker process. Therefore, the attacker process cannot detect how the victim process executes based on how its initiated branch prediction states 138(0)-138(B) are affected by the victim process's execution.

[0037] Figure 2 It is shown Figure 1 The flowchart illustrates an exemplary process 200 of the branch prediction circuit 134 in the instruction processing circuit 104, which is configured to swap the context from shared branch prediction memory 142 into private branch prediction memory 136, rather than swapping the context out of private branch prediction memory 136 into shared branch prediction memory 142. The following is in conjunction with... Figure 1 Let's discuss the instruction processing circuit 104 in the middle. Figure 2 This process 200. At this point, the branch prediction circuit 134 speculatively predicts the result of the branch instruction 106F in the current process being executed in the instruction processing circuit 104. Figure 2(Box 202 in the middle). Speculative prediction is based on the accessed associated branch prediction states 138(0)-138(B) in the private branch prediction memory 136, which are associated with the context of the branch instruction 106F of the current process being executed in the instruction processing circuit 104. Figure 2 (See box 202 in the previous description). As previously described, the private branch prediction memory 136 is configured to store the branch prediction states 138(0)-138(B) of the current context of the current process being executed in the instruction processing circuitry 104 of the processor 102.

[0038] Continue to refer to Figure 2 The branch prediction circuit 134 receives process ID 150, which identifies the new context being swapped into or to be swapped into in the instruction processing circuit 104, indicating a context switch. Figure 2 (Box 204 in the diagram). Branch prediction circuit 134 determines whether process ID 150 indicates a new context that is different from the current context in the swapped-in instruction processing circuit 104. Figure 2 (Box 206 in the middle). In response to process ID 150 indicating a new context different from the current context in the swapped-in instruction processing circuit 104 ( Figure 2 In box 208), branch prediction circuit 134 stores the branch prediction states 146()(0)-146()(B) associated with the new context 144(0)-144(C) in the branch prediction states 138(0)-138(B) in the private branch prediction memory 136 (box 210). Furthermore, in response to process ID 150 indicating a new context different from the current context of the swapped-in instruction processing circuit 104, branch prediction circuit 134 stores the branch prediction states 138(0)-138(B) of the context to be swapped out in the private branch prediction memory 136 as the branch prediction states 146()(0)-146()(B) of its context 144(0)-144(C) in the shared branch prediction memory 142. Figure 2 (Box 212 in the middle).

[0039] In this way, as described above, the branch prediction circuit 134 can access the branch prediction states 138(0)-138(B) in the private branch prediction memory 136 for use in the context of the currently executing process without having to retrain the process's branch prediction states. Furthermore, the shared branch prediction memory 142 does not need to be flushed after a context switch because the size of the shared branch prediction memory 142 is set to store the branch prediction states 146(0)(0)-146(C)(B) for specific different contexts, thus preventing a process from affecting the context and associated branch prediction states of another process. Figure 3This diagram illustrates a branch prediction memory 302 used to store branch prediction states, which will be used by the branch prediction circuit 300 for branch prediction and comparison purposes. The branch prediction memory 302 is divided into two types of memory—a statically partitioned branch prediction memory 304 and a dynamic branch prediction memory 306. The statically partitioned branch prediction memory 304 can be local memory of the branch prediction circuit 300, while the dynamic branch prediction memory 306 can be stored in a separate memory. The statically partitioned branch prediction memory 304 includes one or more branch prediction tables 307(0)-307(T), which are partitioned into memory segments 308(1)-308(X) to isolate the contexts of running processes to prevent one process from influencing the context of another process for security reasons, as described above. The dynamic branch prediction memory 306 includes one or more branch prediction tables 310(0)-310(T), which are not partitioned and can be used to store and update the prediction state of the currently executing process to provide additional branch prediction state capacity compared to the statically partitioned branch prediction memory 304. However, the dynamic branch prediction memory 306 is not partitioned and is flushed during context switches to prevent leakage. The statically partitioned branch prediction memory 304 prevents leakage by partitioning by context, but it is a smaller memory structure and can reduce prediction accuracy if the dynamic branch prediction memory 306 is not used. However, the dynamic branch prediction memory 306 is flushed during context switches, resulting in the loss of branch prediction training (i.e., history) of the context of the swapped-out process.

[0040] Refer again Figure 1 The instruction processing circuit 104 and the branch prediction circuit 134 can be configured to swap out each branch prediction state 138(0)-138(B) in the private branch prediction memory 136 to the shared branch prediction memory 142 in response to a context switch, and to swap in each branch prediction state 146()(0)-146()(B) in the shared branch prediction memory 142 to the private branch prediction memory 136 before making a speculative prediction about the branch instruction 106F. However, this may delay instruction processing because the swapping process of the new context into the private branch prediction memory 136 may not be completed before the branch instruction 106F is fetched for the process associated with the context. In this regard, a “lazy” swapping process can be employed to speculatively predict the outcome of the branch instruction 106F before the swapping of the new context is completed, so as not to delay the processing of the branch instruction 106F that may follow the context switch.

[0041] For example, Figure 4This is a flowchart illustrating an alternative exemplary process 400 of swapping in and restoring branch prediction states 138(0)-138(B) from shared branch prediction memory 142 and private branch prediction memory 136, but the branch prediction circuit 134 is still able to perform branch prediction based on the partial restoration of branch prediction states 138(0)-138(B). Figure 4 The process 400 in the middle can follow, for example Figure 2 In process 200, and in Figure 2 The process of exchanging branches to predict the state in boxes 210 and 212 has begun after it has been initiated. At this point, as... Figure 4 As shown, the branch prediction circuit 134 is configured to determine whether the swapping and storage of the branch prediction states 146()(0)-146()(B) of the swap-in context in the shared branch prediction memory 142 into the private branch prediction memory 136 is complete. Figure 4 (Box 402 in the middle). In response to determining the branch prediction state 146()(0)-146()(B), the storage from the shared branch prediction memory 142 to the private branch prediction memory 136 is not complete ( Figure 4 In box 404, the branch prediction circuit 134 is still configured to speculatively predict the result of the swap-in branch instruction 106F in the current process being executed in the instruction processing circuit 104 based on the alternative branch prediction state. Figure 4 (See box 406 in the diagram). For example, branch prediction circuit 134 can be configured to speculatively predict the result of fetch branch instruction 106F in the current swap-in process executed in instruction processing circuit 104, based on static branch prediction states, such as always adopted or not adopted, before the storage from shared branch prediction memory 142 to private branch prediction memory 136 is completed in branch prediction states 146()(0)-146()(B).

[0042] However, if the storage from the shared branch prediction memory 142 to the private branch prediction memory 136 is completed in response to determining the branch prediction state 146()(0)-146()(B) Figure 4 In box 408), branch prediction circuit 134 can be configured to speculatively predict the result of branch instruction 106F in the current swap-in process being executed in instruction processing circuit 104 using branch prediction states 146()(0)-146()(B) stored as branch prediction states 138(0)-138(B) in private branch prediction memory 136 from shared branch prediction memory 142, as previously described. Figure 4 (in box 410).

[0043] Alternative Figure 4In boxes 404 and 406, another “lazy” swapping method involves branch prediction circuit 134 storing only a subset or a portion of all prediction states 146()(0)-146()(B) associated with the new context 144(0)-144(C) in the private branch prediction memory 136, instead of storing all branch prediction states 146()(0)-146()(B) in the private branch prediction memory 136. Furthermore, branch prediction circuit 134 can be configured to store only a subset or a portion of all prediction states 138(0)-138(B) associated with the current context in the shared branch prediction memory 142. This allows branch prediction circuit 134 to speculatively predict the result of branch instruction 106F without having to swap in and out all branch prediction states of the current and new contexts. Branch prediction circuit 134 can be configured to swap in branch prediction states 146()(0)-146()(B) in private branch prediction memory 136 that are more likely to provide accurate branch predictions for branch instruction 106F.

[0044] Alternatively, the branch prediction circuit 134 can be configured to speculatively predict the result of the branch instruction 106F in the current swap-in process executed in the instruction processing circuit 104 based on the branch prediction state in a separate dedicated shared branch prediction memory 136 before the storage from the shared branch prediction memory 142 to the private branch prediction memory 146()(0)-146()(B) is completed. This is in Figure 5 The processor-based system 500 is illustrated by example. Figure 5 The processor-based system 500 in the middle includes and Figure 1 The same processor 102 in the processor-based system 100. Figure 1 The processor-based system 100 and Figure 5 The same components among the processor-based systems 500 are shown using common element numbering. The above is about... Figure 1 The previous interpretation of these elements applies Figure 5 And will no longer be described.

[0045] like Figure 5 As shown, the processor-based system 500 includes... Figure 1The shared branch prediction memory 142 is similar to the shared branch prediction memory 542. The size of the shared branch prediction memory 542 is set to store multiple contexts 544(0)-544(C) of different processes that have been executed in the processor 102 and can be swapped into the instruction processing circuit 104 for further execution. For the capacity (B) of the branch prediction states 138(0)-138 in the private branch prediction memory 136, each context 544(0)-544(C) is configured to store multiple branch prediction states 546(0)-546(B) in the corresponding multiple entries 148. The shared branch prediction memory 542 also includes a dedicated branch prediction memory 502, which is configured to store multiple branch prediction states 546(0)-546(B) of a single context 544 in the corresponding entries 548(0)-548(B). In this example, the size “S” of entries 548(0)-548(B) in the dedicated branch prediction memory 502 is the same as the number of entries in a single context 544(0)-544(C) in the shared branch prediction memory 542. Therefore, the branch predictor circuit 134 can access the branch prediction states 546(0)-546(B) in the dedicated branch prediction memory 502 to make speculative predictions about the result of the branch instruction 106F until the swapping of the branch prediction state 546()(0) from the shared branch prediction memory 542 to -546()(B) in the private branch prediction memory 136 is complete.

[0046] Figure 6 It is shown Figure 1 A flowchart of an exemplary process 600 of the branch prediction circuit 134 in the instruction processing circuit 104 is provided. This process is configured to swap the context from the shared branch prediction memory 542 into the private branch prediction memory 136, while indicating that the context is swapped out from the private branch prediction memory 136 into the shared branch prediction memory 542, and to perform prediction using the prediction states 546(0)-546(B) in the private branch prediction memory 502 until the swapping process is complete. The following is in conjunction with... Figure 5 Let's discuss the instruction processing circuit 104 in the middle. Figure 6 This process 600. At this point, the branch prediction circuit 134 speculatively predicts the result of the fetch branch instruction 106F in the current process executed in the instruction processing circuit 104. Figure 6 (Box 602 in the middle). Speculative prediction can be based on the accessed associated branch prediction states 138(0)-138(B) in the private branch prediction memory 136, which are associated with the context of the fetched branch instruction 106F of the current process being executed in the instruction processing circuit 104. Figure 6(See box 602 in the previous description). As previously described, the private branch prediction memory 136 is configured to store the branch prediction states 138(0)-138(B) of the current context of the current process being executed in the instruction processing circuitry 104 of the processor 102.

[0047] Continue to refer to Figure 6 The branch prediction circuit 134 receives process ID 150, which identifies the new context being swapped into or to be swapped into in the instruction processing circuit 104, indicating a context switch. Figure 6 (Box 604 in the diagram). Branch prediction circuit 134 determines whether process ID 150 indicates a new context that is different from the current context in the swapped-in instruction processing circuit 104. Figure 6 (Box 606 in the middle). In response to process ID 150 indicating a new context different from the current context in the swapped-in instruction processing circuit 104 ( Figure 6 In box 608), branch prediction circuit 134 causes branch prediction states 546()(0)-546()(B) associated with the new context 544(0)-544(C) to be stored in branch prediction states 138(0)-138(B) in private branch prediction memory 136. Figure 6 (See box 610 in the text). Furthermore, in response to the process ID 150 indicating a new context different from the current context of the swapped-in instruction processing circuit 104, the branch prediction circuit 134 stores the branch prediction states 138(0)-138(B) of the current context to be swapped out in the private branch prediction memory 136 as the branch prediction states 546()(0)-546()(B) of its context 544(0)-544(C) in the shared branch prediction memory 542. Figure 6 (Box 612 in the middle).

[0048] Continue to refer to Figure 6 The branch prediction circuit 134 is configured to determine whether the branch prediction states 546()(0)-546()(B) of the swap-in context in the shared branch prediction memory 542 have been swapped into and stored in the private branch prediction memory 136. Figure 6 (Box 614 in the middle). In response to determining the branch prediction state 546()(0)-546()(B) the storage from the shared branch prediction memory 542 to the private branch prediction memory 136 is not complete ( Figure 6 In box 616), the branch prediction circuit 134 is still configured to speculatively predict the result of the branch instruction 106F in the current swap-in process being executed in the instruction processing circuit 104 based on the branch prediction states 546(0)-546(B) associated with the branch instruction 106F in the dedicated branch prediction memory 502. Figure 6(Box 618 in the middle). However, in response to determining the branch prediction state 546()(0)-546()(B), the storage from the shared branch prediction memory 542 to the private branch prediction memory 136 is completed ( Figure 6 In box 620), branch prediction circuit 134 can be configured to speculatively predict the result of branch instruction 106F in the current swap-in process being executed in instruction processing circuit 104 using branch prediction states 546()(0)-546()(B) stored as branch prediction states 138(0)-138(B) in private branch prediction memory 136 from shared branch prediction memory 542, as previously described. Figure 6 (Box 622 in the middle).

[0049] Figure 7 Another alternative branch prediction circuit is shown, which predicts the result of branch instruction 106F speculatively based on the swap-in branch condition state in a private branch prediction memory in response to a context switch. Figure 7 A processor-based system 700 is shown, which includes components similar to... Figure 1 The processor 102 and instruction processing circuit 704 in the processor-based system 100. Figure 1 The processor-based system 100 and Figure 7 The same components in the processor-based system 700 are shown with common element numbers. The above is about... Figure 1 The previous interpretation of these elements applies Figure 7 And will no longer be described.

[0050] exist Figure 7 In the processor-based system 700, the instruction processing circuit 704 includes two (2) identical branch prediction circuits, which can be derived from... Figure 1The instruction processing circuit 104 includes a branch prediction circuit 134 and a second branch prediction circuit 734. As will be discussed in more detail below, one branch prediction circuit 134, 734 is configured to maintain the branch prediction states 138(0)-138(B), 738(0)-738(B) of the current context of the currently executing process, while the other branch prediction circuit 734, 134 is configured to maintain the branch prediction states 738(0)-738(B), 138(0)-138(B) of the next context of the next process that is more likely to be swapped into the instruction processing circuit 704 for execution. In this way, when a context switch occurs, if the process ID 150 identifying the process to be swapped is associated with the context currently stored in the second branch prediction circuit 734, 134, the second branch prediction circuit 734, 134 can take over the speculative prediction in the instruction processing circuit 704 without delay. The first branch prediction circuits 134 and 734 can be disabled, and the new context of the process predicted to be more likely to be swapped in the next step can be loaded into its entries 140(0)-140(B) and 740(0)-740(B) as its branch prediction states 138(0)-138(B) and 738(0)-738(B). The branch prediction states 138(0)-138(B) in the first branch prediction circuit 134 can be swapped out to the shared branch prediction memory 142, and the new context associated with the new process predicted to be swapped into the instruction processing circuit 104 can then be swapped from the shared branch prediction memory 142 into the branch prediction memory 136, as previously described. However, when a context switch occurs and the process ID 150 of the process to be switched is not associated with the current context stored in the second branch prediction circuits 734, 134, the branch prediction states 138(0)-138(B), 738(0)-738(B) in the second branch prediction circuits 734, 134 can be refreshed, and the branch prediction states 144()(0)-144()(B) of the new context stored in the shared branch prediction memory 142 can be swapped into the first branch prediction circuits 134, 734, including any of the techniques described above.

[0051] Figure 8A and Figure 8B It is shown Figure 7A flowchart of an exemplary process 800 of the instruction processing circuit 704 is provided. The instruction processing circuit 704 includes two branch prediction circuits 134 and 734 and is configured to switch between the branch prediction circuits 134 and 734 to speculatively predict the result of the branch instruction 106F. At this point, assuming that the branch prediction circuit 134 is configured to perform speculative prediction in the instruction processing circuit 704, the branch prediction circuit 134 speculatively predicts the result of the fetch branch instruction 106F in the current process executed in the instruction processing circuit 104. Figure 8A (Box 802 in the middle). Speculative prediction can be based on the accessed associated branch prediction states 138(0)-138(B) in the private branch prediction memory 136, which are associated with the context of the fetched branch instruction 106F of the current process being executed in the instruction processing circuit 104. Figure 8A (in box 802). As previously described, the first private branch prediction memory 136 is configured to store the branch prediction states 138(0)-138(B) of the current context of the current process being executed in the instruction processing circuitry 104 of the processor 102.

[0052] Continue to refer to Figure 8A The instruction processing circuit 704 receives process ID 150, which identifies the new context that has been swapped into or will be swapped into the instruction processing circuit 104, indicating a context switch. Figure 8A (Box 804 in the diagram). Instruction processing circuitry 704 determines whether process ID 150 indicates a new context different from the current context in the swapped-in instruction processing circuitry 104. Figure 8A (Box 806 in the middle). In response to process ID 150 indicating a new context different from the current context in the swapped-in instruction processing circuit 104 ( Figure 8A In box 808), instruction processing circuitry 704 is also configured to determine whether the new context is associated with branch prediction states 738(0)-738(B) stored in the second private branch prediction memory 736 of second branch prediction circuitry 734. Figure 8A (Box 810 in the middle). If so, the instruction processing circuit 704 is configured to switch from the first branch prediction circuit 134 to the second branch prediction circuit 734 so that the second branch prediction circuit 734 speculatively predicts the result of the branch instruction 106F based on the branch prediction states 738(0)-738(B) in the next context in the second private branch prediction memory 736 associated with the branch instruction 106F in the next process executed in the instruction processing circuit 704. Figure 8A(Box 812 in the middle). Therefore, the second private branch prediction memory 736 can begin speculatively predicting the result of the branch instruction 106F of the next process without waiting for the branch prediction state of the next context to be swapped into its second private branch prediction memory 736. Moreover, if the new context is associated with the branch prediction states 738(0)-738(B) stored in the second private branch prediction memory 736 of the second branch prediction circuit ( Figure 8A In box 810), the branch prediction circuit 134 is further configured to stop speculatively predicting the result of the branch instruction 106F in the next process executed in the instruction processing circuit 104. Figure 8B (Block 814 in the middle). Instruction processing circuitry 704 is also configured to swap branch prediction states 138(0)-138(B) in branch prediction memory 136 to branch prediction states 146(0)-146(B) of the current context 144(0)-144(C) in shared branch prediction memory 142, as previously described. Figure 8B (Block 816 in the middle). Instruction processing circuit 704 is further configured to swap the branch prediction states 146(0)-146(B) of the contexts 144(0)-144(C) to be swapped into the next speculative context in shared branch prediction memory 142 into private branch prediction memory 136(B). Figure 8B (Box 818 in the middle).

[0053] However, if the new context is not associated with the branch prediction states 738(0)-738(B) stored in the second private branch prediction memory 736 of the second branch prediction circuit 734 ( Figure 8A If box 810 is in the middle, then instruction processing circuit 704 is configured to refresh the branch prediction states 738(0)-738(B) associated with the next context in the second private branch prediction memory 736. Figure 8B (Box 820 in the middle). This allows the branch prediction states 146(0)-146(B) of the next speculative context 144(0)-144(C) to be swapped in to be loaded into the second private branch prediction memory 736. The branch prediction circuit 134 will continue to speculatively predict the result of the branch instruction 106F of the new process in the instruction processing circuit 704 to be swapped in. Figure 8B (See box 822 in the original text). Instruction processing circuitry 704 is configured to swap branch prediction states 738(0)-738(B) from private branch prediction memory 136 to shared branch prediction memory 142, as previously described. Figure 8B(Block 816 in the middle). The instruction processing circuit 704 is further configured to swap the branch prediction states 146(0)-146(B) of the new context 144(0)-144(C) in the shared branch prediction memory 142 into the private branch prediction memory 136(B). Figure 8B (Box 818 in the middle).

[0054] Note that any of the operations discussed above regarding swapping contexts out of private branch prediction memories 136, 736 to shared branch prediction memories 142, 542, 742 and swapping contexts in from shared branch prediction memories 142, 542, 742 to private branch prediction memories 136, 736 may be performed elsewhere within instruction processing circuitry 104 and / or processors(s) 102, 702.

[0055] Figure 9 This is an exemplary block diagram of a processor-based system 900, which includes a processor 902 (e.g., a microprocessor) and instruction processing circuitry 904. Instruction processing circuitry 904 may be... Figure 1 , Figure 5 and Figure 7 The processor 102 may contain any instruction processing circuitry 104, for example, and includes a branch prediction circuitry 906 configured to speculatively predict the outcome of a branch instruction to be executed, and includes a private branch prediction memory configured to store the branch prediction state accessed to make such a prediction. The processor-based system 900 may be... Figure 1 , Figure 5 and Figure 7 Any of the processor-based systems 100, 500, and 700 in the processor-based systems, as an example, may include a shared branch prediction memory for swapping in and out of context in response to a context switch in processor 902, including... Figure 1 , Figure 5 and Figure 7Shared branch prediction memories 142, 542, and 742 are used as examples. The processor-based system 900 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based system 900 includes a processor 902. Processor 902 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. More specifically, processor 902 can be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for delivering produced values ​​generated by the execution of producer instructions. Processor 902 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 902 includes an instruction cache 908 for temporary fast access memory storage of instructions accessible to instruction processing circuitry 904. Instructions fetched or prefetched from memory (such as system memory 910 via system bus 912) are stored in instruction cache 908. Instruction processing circuitry 904 is configured to process instructions fetched from instruction cache 908 and process the instructions for execution. System memory 910 may include shared branch prediction memory 911, such as... Figure 1 , Figure 5 and Figure 7 Shared branch prediction memories 142, 542, and 742 in the memory are used as examples.

[0056] Processor 902 and system memory 910 are coupled to system bus 912 and can be coupled to peripheral devices included in processor-based system 900. It is known that processor 900 communicates with these other devices by exchanging address, control, and data information via system bus 912. For example, processor 902 can transmit bus transaction requests to memory controller 914 in main memory 910, which is an example of a slave device. Although... Figure 9 Not shown, but multiple system buses 912 may be provided, each forming a different architecture. In this example, memory controller 914 is configured to provide memory access requests to memory array 916 in system memory 910. Memory array 916 includes an array of storage bit cells for storing data. System memory 910 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and static memory (e.g., flash memory, static random access memory (SRAM), etc.), as a non-limiting example.

[0057] Other devices can be connected to system bus 912. For example... Figure 9 As shown, for example, these devices may include system memory 910, one or more input devices 918, one or more output devices 920, modem 922, and one or more display controllers 924. The input devices 918 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 920 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 922 may be any device configured to allow data exchange with network 926. Network 926 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetext. TM Networks and the Internet. Modem 922 can be configured to support any type of desired communication protocol. Processor 902 can also be configured to access multiple display controllers 924 via system bus 912 to control information sent to one or more displays 928. The multiple displays 928 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0058] Figure 9 The processor-based system 900 may include an instruction set 930, which will be executed by the processor 902 for any application desired according to the instructions. The instructions 930 may be stored in system memory 910, the processor 902, and / or instruction cache 908 (as an example of non-transitory computer-readable medium 932). The instructions 930 may also reside wholly or at least partially in system memory 910 and / or in the processor 902 during their execution. The instructions 930 may also be transmitted or received via a network 926 via a modem 922, such that the network 926 includes the computer-readable medium 932.

[0059] Although computer-readable medium 932 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions executable by a processing device and causing the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0060] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be constituted by hardware components or embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with those instructions to perform these steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0061] The embodiments disclosed herein may be provided as a computer program product or software that may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.).

[0062] Unless otherwise specifically stated and clearly understood through the preceding discussion, it should be understood that throughout this specification, the use of terms such as “processing,” “calculating,” “determining,” and “displaying” refers to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the registers of the computer system into other data similarly represented as physical quantities in the computer system’s memory or registers or other such information storage, transmission, or display devices.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used in accordance with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will be clear from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0064] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0065] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0066] The embodiments disclosed herein can be implemented in hardware and with instructions stored in hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0067] It should also be noted that the operational steps described in any exemplary embodiment of the exemplary embodiments herein are described to provide examples and discussion. The described operations can be performed in many different sequences than those shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced in the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0068] Unless otherwise expressly stated, it is not intended to interpret any method described herein as requiring its steps to be performed in a particular order. Therefore, if a method claim does not actually describe the order in which its steps are followed, or if the claims or specification do not otherwise specifically state that these steps are limited to a particular order, then no particular order can be inferred.

[0069] It will be readily apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments that embody the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A branch prediction circuit, comprising: A private branch prediction memory is configured to store at least one branch prediction state for the current context of the current process executing in the processor's instruction processing circuitry. The branch prediction circuit is configured as follows: The result of the branch instruction is speculatively predicted based on the branch prediction state in the private branch prediction memory of the current context associated with the branch instruction in the current process being executed in the instruction processing circuit. The process identifier that is received is swapped into the new context in the instruction processing circuit; and In response to the process identifier indicating a new context different from the current context being swapped into the instruction processing circuitry: At least one branch prediction state associated with the new context is stored as at least one branch prediction state in the private branch prediction memory.

2. The branch prediction circuit of claim 1 is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit, cause at least one branch prediction state in the private branch prediction memory to be stored as at least one branch prediction state in a shared branch prediction memory, the shared branch prediction memory being configured to store at least one branch prediction state associated with a context in each of a plurality of contexts.

3. The branch prediction circuit of claim 1 is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit, prevent the at least one branch prediction state stored in the shared branch prediction memory from being refreshed.

4. The branch prediction circuit of claim 1, configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit: At least one branch prediction state associated with the new context in the shared branch prediction memory is stored as at least one branch prediction state in the private branch prediction memory, which is configured to store at least one branch prediction state associated with a context in each of a plurality of contexts.

5. The branch prediction circuit of claim 4, configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit: Each of the at least one branch prediction states in the shared branch prediction memory associated with the new context is stored as at least one branch prediction state in the private branch prediction memory.

6. The branch prediction circuit of claim 4 is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit, cause at least one branch prediction state in the private branch prediction memory to be stored as at least one branch prediction state in the shared branch prediction memory.

7. The branch prediction circuit of claim 6 is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit: Each branch prediction state in the private branch prediction memory is stored as at least one branch prediction state in the shared branch prediction memory.

8. The branch prediction circuit of claim 4 is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit: Determine whether the at least one branch prediction state stored in the shared branch prediction memory within the private branch prediction memory is complete; and In response to determining that the storage of the at least one branch prediction state from the shared branch prediction memory to the private branch prediction memory is incomplete: The results of branch instructions in the current process being executed in the instruction processing circuit are speculatively predicted based on the static branch prediction state.

9. The branch prediction circuit of claim 8, further configured to: in response to determining that the storage of the at least one branch prediction state from the shared branch prediction memory to the private branch prediction memory is complete: The outcome of the branch instruction is speculatively predicted based on the branch prediction state in at least one of the branch prediction states in the private branch prediction memory associated with the branch instruction in the current process being executed in the instruction processing circuit.

10. The branch prediction circuit of claim 4, further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit: Determine whether the at least one branch prediction state stored in the shared branch prediction memory within the private branch prediction memory is complete; and In response to determining that the storage of the at least one branch prediction state from the shared branch prediction memory to the private branch prediction memory is incomplete: The result of the branch instruction is speculatively predicted based on the branch prediction state in at least one branch prediction state in a cached branch prediction memory for the current context associated with the branch instruction in the current process being executed in the instruction processing circuit, the cached branch prediction memory being configured to store at least one branch prediction state associated with a context including the current context.

11. The branch prediction circuit of claim 10, further configured to: in response to determining that the storage of the at least one branch prediction state from the shared branch prediction memory to the private branch prediction memory has been completed: The outcome of the branch instruction is speculatively predicted based on the branch prediction state in at least one branch prediction state in the private branch prediction memory associated with the branch instruction in the current process being executed in the instruction processing circuit.

12. The branch prediction circuit according to claim 4, wherein: The private branch prediction memory is configured to store multiple branch prediction states for the current context of the current process executing in the instruction processing circuitry of the processor. The branch prediction circuit is configured as follows: The result of the branch instruction is speculatively predicted based on the branch prediction state among the plurality of branch prediction states in the current context in the private branch prediction memory associated with the branch instruction in the current process being executed in the instruction processing circuit; and In response to the process identifier indicating a new context different from the current context being swapped into the instruction processing circuitry: At least one branch prediction state in the shared branch prediction memory, less than all branch prediction states associated with the new context, is stored as at least one branch prediction state in the private branch prediction memory, wherein the shared branch prediction memory is configured to store the multiple branch prediction states associated with a context in each of the multiple contexts.

13. The branch prediction circuit of claim 12 is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit: At least one branch prediction state less than all branch prediction states in the private branch prediction memory is stored as at least one branch prediction state less than all branch prediction states in the shared branch prediction memory.

14. The branch prediction circuit of claim 1, wherein the private branch prediction memory includes a branch prediction table circuit, the branch prediction table circuit including at least one branch prediction entry, each branch prediction entry being configured to store the branch prediction state: The branch prediction circuit is configured to speculatively predict the outcome of the branch instruction based on the branch prediction state of at least one branch prediction entry in the current context of the private branch prediction memory associated with the branch instruction in the current process being executed in the instruction processing circuit.

15. A method for predicting branch instructions for a context executed in an instruction processing circuit of a processor, comprising: The result of the branch instruction is speculatively predicted based on a branch prediction state in a private branch prediction memory associated with a branch instruction in the current process being executed in the instruction processing circuitry, the private branch prediction memory being configured to store at least one branch prediction state for the current context of the current process to be executed in the processor's instruction processing circuitry. The process identifier is received and swapped into the new context in the instruction processing circuit; Determine whether the process identifier indicates that a new context different from the current context has been swapped into the instruction processing circuitry; as well as In response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit, at least one branch prediction state associated with the new context is stored as at least one branch prediction state in the private branch prediction memory.

16. The method of claim 15, further comprising: In response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit, at least one branch prediction state in the private branch prediction memory is stored as at least one branch prediction state in the shared branch prediction memory.

17. The method of claim 15, further comprising: In response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit, the at least one branch prediction state stored in the shared branch prediction memory is not refreshed.

18. A processor-based system, comprising: Processor, including: Instruction processing circuitry, including: One or more instruction pipelines, including fetch circuitry, branch prediction circuitry, and execution circuitry; The fetch circuit is configured to fetch multiple instructions from memory into one of the one or more instruction pipelines for execution by the execution circuit; and The branch prediction circuit includes: A private branch prediction memory is configured to store at least one branch prediction state for the current context to be executed in the instruction processing circuitry of the processor. The branch prediction circuit is configured as follows: The result of the branch instruction is speculatively predicted based on the branch prediction state in the private branch prediction memory of the current context associated with the branch instruction in the current process being executed in the instruction processing circuit. The instruction processing circuit is configured as follows: The process identifier that is received is swapped into the new context in the instruction processing circuit; and In response to the process identifier indicating a new context different from the current context being swapped into the instruction processing circuitry: At least one branch prediction state associated with the new context is stored as at least one branch prediction state in the private branch prediction memory; and A shared branch prediction memory is configured to store at least one branch prediction state associated with each of a plurality of contexts associated with a corresponding process, which is configured to execute in the instruction processing circuitry.

19. The processor-based system of claim 18, wherein the instruction processing circuitry is further configured to: in response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuitry, store at least one branch prediction state in the private branch prediction memory as at least one branch prediction state in the shared branch prediction memory.

20. The processor-based system of claim 18, wherein the processor is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuitry, for each of the associated plurality of contexts, not refresh the at least one branch prediction state.

21. The processor-based system according to claim 19, wherein: The private branch prediction memory includes a branch prediction table circuit, which includes at least one branch prediction entry, and each branch prediction entry is configured to store the branch prediction state. The branch prediction circuit is configured to speculatively predict the outcome of the branch instruction based on the branch prediction state of a branch prediction entry in the private branch prediction memory associated with the branch instruction executed in the current context of the instruction processing circuit. as well as The shared branch prediction memory includes a shared branch prediction table circuit, which includes at least one branch prediction entry, and each branch prediction entry is configured to store the branch prediction state. The instruction processing circuit is further configured to: in response to the process identifier indicating that a new context different from the current context is swapped into the instruction processing circuit, to store at least one branch prediction state in at least one branch prediction entry in the private branch prediction memory as at least one branch prediction state in at least one branch prediction entry in the shared branch prediction table circuit.

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