Methods for restoring register renaming mapping tables

Abstract

Minimize the traversal of the Processor Reorder Buffer (ROB) used for interrupt instruction recovery in the processor. Instructions can be executed out of order in the processor. Information about the logical-to-physical register mappings generated by each instruction is stored in entries in the ROB in program order. When the pipeline is interrupted by an instruction that cannot be executed, altering the program flow, all instructions following the interrupt instruction can be flushed from the processor pipeline. It is important to restore the RMT state to the state it existed when the interrupt instruction entered the pipeline. To restore the RMT state in response to an interrupt instruction, the register mapping information in the ROB entries is traversed to undo newer instructions that entered the pipeline after the interrupt instruction or replay older instructions that entered the pipeline before the interrupt instruction.

Description

Technical Field

[0001] The technology disclosed herein relates to instruction processing in an instruction pipeline in a computer processor (“processor”), and more specifically to restoring the state of the instruction pipeline in the processor after an instruction speculative error prediction of a conditional control (e.g., branch) instruction. Background Technology

[0002] Microprocessors (also called “processors”) perform computational tasks for various applications. A typical microprocessor includes a central processing unit (CPU), which comprises one or more processor cores (also called “CPU cores”). The CPU executes computer program instructions (“instructions”) (also called “software instructions”) to perform operations on data and generate results. The data results generated by the producer instructions of the instruction sequence can be temporary data stored for use by the consumer instructions. To avoid latency caused by storing temporary data in external memory and then reading it back to the processor, the temporary data can be stored in registers within the processor. Consumer instructions can name registers as input operands to consume the generated data stored in the registers.

[0003] The Instruction Set Architecture (ISA) makes a certain number of registers available as operands in instructions. However, it is often desirable to provide more registers than the number specified in the ISA to store temporary data, because there may not be enough available registers in the ISA to avoid multiple instructions in the instruction pipeline naming the same register. In this case, the processor uses a larger number of physical registers than specified in the ISA to store temporary data. Therefore, the registers available in the ISA are logical registers, allowing the processor to assign more than one physical register to logical registers. The processor maps logical registers in processed instructions to physical registers via a register map table to indicate the actual physical register where data is stored. The processor includes register renaming circuitry in the instruction pipeline to rename logical registers to physical registers to access the data in the physical registers for instruction execution. When a physical register becomes obsolete, complete, and no longer in use, the logical register-to-physical register mapping in the register map table is released. Obsolete means that a newer write to the same logical register has been committed. Complete means that the result corresponding to the physical register has been written to the physical register file. No longer in use means that all instructions that require the physical register have passed the point in time for reading the register file. The processor stores the rename information associated with each instruction in the reorder buffer (ROB) in program order and saves the latest rename state in the register map. Once the executed instruction is committed, the logical register-to-physical register renames of the instruction are saved in the committed map (CMT).

[0004] Control risks can occur in the instruction pipeline, where the next instruction in the pipeline fails to execute without causing incorrect computation results. For example, control risks can arise from the execution of control flow instructions that cause precise interrupts in the processor. An example of a control flow instruction that can cause control risks is a conditional branch instruction. A conditional branch instruction can redirect the flow path of instruction execution based on the conditions evaluated when executing the control branch instruction. As a result, the processor may have to suspend the fetching of additional instructions until the conditional branch instruction has been executed, leading to reduced processor performance and increased power consumption. One approach to maximizing processor performance involves using prediction circuitry to speculatively predict the outcome of the conditions for a conditional branch instruction. However, mispredicted branch instructions trigger an error prediction recovery process that must be performed, whereby the instruction pipeline is flushed and the instruction fetch unit is redirected to fetch a new instruction starting from the address of the conditional branch instruction. As part of this error prediction recovery process, the register map table, containing register mapping information for uncommitted instructions in the instruction pipeline, must be returned to its previous register mapping state before the instruction in the correct branch was processed. Because the reorder buffer retains the latest register rename state in the register map for uncommitted instructions, instruction entries in the reorder buffer containing the latest register rename state can be used to restore the previous register map state executed before the speculatively mispredicted instruction. The goal is to restore the processor's register state as quickly as possible during misprediction recovery to minimize performance penalties caused by speculative misprediction. Summary of the Invention

[0005] Exemplary aspects disclosed herein include minimizing traversal of the processor reorder buffer (ROB) for interrupt instruction recovery in the processor. Although instructions can be executed out of order in a pipelined processor, the final result of each instruction regarding the processor state must be committed in program order. As instructions are processed, instructions with register operands gain access to logical registers specified by the processor's instruction set architecture (ISA). To avoid interference between instructions, logical registers for different instructions must be mapped to unique physical registers. The RMT is updated each time a new instruction enters the pipeline, and the most recent logical register-to-physical register mapping is maintained for each logical register of the processor. Information about the logical register-to-physical register mapping generated by each instruction is stored in entries in the ROB in program order. When the pipeline is interrupted by an instruction that cannot be executed as expected, altering the program flow, all instructions following the interrupted instruction can be flushed from the processor pipeline. It is important to return the RMT state to the state it existed when the interrupted instruction entered the pipeline and when an entry for that instruction was allocated in the ROB.

[0006] In the exemplary aspects disclosed herein, to restore the RMT state in response to an interrupt instruction that fails to execute as expected, register mapping information in ROB entries is sequentially traversed to undo the effects of newer instructions that entered the pipeline after the interrupt instruction or replay the effects of older instructions that entered the pipeline before the interrupt instruction. During the traversal, logical register-to-physical register mapping information obtained from the ROB entries is used to restore the RMT state. To minimize the traversal time of entries in the ROB used to restore the RMT state, in some aspects disclosed herein, a register renaming recovery circuit (RRRC) is provided, configured to determine the position of the oldest flushed instruction entry assigned to the oldest flushed instruction in the ROB, and to traverse the ROB in a certain direction starting from the position of the oldest flushed instruction entry. By traversing the ROB starting from the oldest flushed instruction, it is possible to avoid traversing all surviving instruction entries or all flushed instruction entries in the ROB.

[0007] In some embodiments, RRRC is configured to dynamically determine the traversal direction to minimize the traversal of entries in the ROB by minimizing the ROB entries to be traversed to restore the RMT state. For example, fewer ROB entries may be traversed in the first direction by reversing a newer instruction that entered the pipeline after an interrupt instruction, compared to replaying an older instruction that entered the pipeline before an interrupt instruction in the opposite direction, and vice versa. In other aspects, RRRC traverses ROB entries in the ROB in a direction from the instruction entry in the ROB for the oldest flushed instruction entry to the instruction entry in the ROB for the oldest uncommitted instruction. By traversing from the oldest flushed instruction entry, the state of the logical register-to-physical register mapping for logical registers in the RMT may be restored, and they may be made available to the processor more quickly. In other aspects, RRRC is configured to traverse ROB entries in the ROB in a direction from the instruction entry for the oldest flushed instruction to the entry in the ROB for the latest uncommitted instruction. By traversing in this direction, only flushed instructions are traversed, and all updates to the RMT are processed.

[0008] In other aspects, RRRC is configured to dynamically determine whether to traverse ROB entries in a first direction from the oldest flushed instruction entry to the instruction entry for the oldest uncommitted instruction, or to traverse ROB entries in a second direction from the oldest flushed instruction entry to the entry for the latest uncommitted instruction. By dynamically determining the traversal direction, traversal can be minimized. In other aspects, RRRC is configured to traverse ROB entries in the ROB in parallel along the first direction from the oldest flushed instruction entry to the instruction entry for the oldest uncommitted instruction, and along the second direction from the oldest flushed instruction entry to the entry for the latest uncommitted instruction. By traversing in both directions, simultaneously traversing remaining entries and flushed entries, traversal time is minimized and RMT recovery is accelerated. After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will be able to understand the scope of this disclosure and implement its additional aspects.

[0009] This document discloses an exemplary embodiment of a register rename recovery circuit (RRRC) in a processor. The RRRC is configured to receive a flush indicator based on an interrupt instruction that causes a flush of one or more instructions in the processor, the flush indicator indicating a flush of the one or more instructions in the processor, and to receive an interrupt instruction indicator indicating the position of an interrupt instruction entry assigned to the interrupt instruction in the processor's reordering buffer. The RRRC is also configured to determine, based on the interrupt instruction indicator, the position of the oldest flushed instruction entry assigned to the oldest of the one or more instructions indicated for flushing; and to traverse the reordering buffer in the processor in a first direction starting from the position of the oldest flushed instruction entry. In order to traverse the reordering buffer, RRRC is configured to determine whether a first instruction assigned to a first instruction entry in the reordering buffer along a first direction produces a logical register-to-physical register mapping in a mapping entry of a register map in the processor, and in response to determining that the first instruction assigned to a first instruction entry in the reordering buffer along a first direction produces a logical register-to-physical register mapping in a mapping entry of a register map in the processor, restores the logical register-to-physical register mapping of the mapping entry in the register map to the previous logical register-to-physical register mapping prior to the oldest instruction among one or more instructions indicated to be flushed.

[0010] In another embodiment, a method in a register renaming recovery circuit is disclosed. The method includes receiving a flush indicator based on an interrupt instruction that causes a flush of one or more instructions in the processor, the flush indicator indicating a flush of the one or more instructions in the processor, and receiving an interrupt instruction indicator indicating the position of an interrupt instruction entry assigned to the interrupt instruction in a reordering buffer of the processor. The method further includes determining, based on the interrupt instruction indicator, the position of the oldest flushed instruction entry assigned to the oldest of the one or more instructions indicated to be flushed, and traversing the reordering buffer in the processor along a first direction starting from the position of the oldest flushed instruction entry. Traversing the reordering buffer also includes determining whether a first instruction assigned to a first instruction entry in the reordering buffer along the first direction produces a logical register-to-physical register mapping in a mapping entry of a register map in the processor, and in response to determining that the first instruction assigned to the first instruction entry in the reordering buffer along the first direction produces a logical register-to-physical register mapping in a mapping entry of a register map in the processor, restoring the logical register-to-physical register mapping of the mapping entry in the register map to the previous logical register-to-physical register mapping prior to the oldest instruction among one or more instructions indicated to be flushed.

[0011] In another exemplary embodiment, a register renaming recovery circuit in a processor is disclosed. The register renaming recovery circuit is configured to receive a flush indicator based on an interrupt instruction causing a flush of one or more instructions in the processor, the flush indicator indicating a flush of one or more instructions in the processor, and to receive an interrupt instruction indicator indicating the position of an interrupt instruction entry assigned to the interrupt instruction in a reordering buffer of the processor. The register renaming recovery circuit is further configured to determine, based on the interrupt instruction indicator, the position of the oldest flushed instruction entry assigned to the oldest of the one or more instructions indicated for flushing, and to determine whether the number of remaining instruction entries in the reordering buffer is less than the number of flushed instruction entries in the reordering buffer, the remaining instruction entries being from the instruction entry assigned to the next older instruction compared to the oldest of the one or more instructions indicated for flushing to the oldest instruction entry in the reordering buffer for the oldest uncommitted instruction, and the flushed entries being from the oldest flushed instruction entry to the latest instruction entry in the reordering buffer assigned to the latest uncommitted instruction. The register renaming recovery circuit is configured to traverse the reordering buffer in the processor along a first direction from the oldest instruction entry to the next oldest instruction assigned to the instruction that is being flushed, in response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries. In response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries, the register renaming recovery circuit is configured to traverse the reordering buffer in the processor along the first direction from the latest instruction entry to the oldest flushed instruction entry.

[0012] In another exemplary aspect, a method in a register renaming recovery circuit is disclosed, wherein the method includes receiving a flush indicator based on an interrupt instruction causing a flush of one or more instructions in the processor, the flush indicator indicating a flush of one or more instructions in the processor, and receiving an interrupt instruction indicator indicating the position of an interrupt instruction entry assigned to the interrupt instruction in a reordering buffer of the processor. The method further includes determining, based on the interrupt instruction indicator, the position of the oldest flushed instruction entry assigned to the oldest of the one or more instructions indicated to be flushed, and determining whether the number of remaining instruction entries in the reordering buffer is less than the number of flushed instruction entries in the reordering buffer, the remaining instruction entries being from the instruction entry assigned to the next older instruction compared to the oldest of the one or more instructions indicated to be flushed to the oldest instruction entry in the reordering buffer assigned to the oldest uncommitted instruction, and the flushed instruction entries being from the oldest flushed instruction entry to the latest instruction entry in the reordering buffer assigned to the latest uncommitted instruction. The method further includes: in response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries, traversing the reordering buffer in the processor along a first direction from the oldest instruction entry to the next older instruction assigned to compared with the oldest instruction among one or more instructions indicated for flushing. The method further includes: in response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries, traversing the reordering buffer in the processor along the first direction from the latest instruction entry to the oldest flushed instruction entry. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0014] Figure 1 It is an illustration of exemplary instruction processing circuitry including one or more instruction pipelines for processing computer instructions for execution, wherein the instruction processing circuitry includes control flow prediction circuitry configured to speculatively predict the conditions of conditional flow control instructions fetched and processed by the instruction processing circuitry.

[0015] Figure 2 It includes Figure 1 A schematic diagram of certain elements of an exemplary instruction processing circuit, including a register rename map (RMT), a reorder buffer (ROB), a committed map (CMT), and a mapping control circuit including a register rename recovery circuit (RRRC) configured to traverse entries of the ROB to restore the state of the RMT in response to a flush indicator;

[0016] Figure 3A and3B The traversal is shown Figure 1 An exemplary sequence of entries in the ROB of the instruction processing circuit to restore the previous state of the RMT that exists when an interrupt instruction that is not flushed enters the instruction processing circuit.

[0017] Figure 4A and 4B The traversal is shown Figure 1 An exemplary sequence of entries in the ROB of the instruction processing circuit to restore the previous state of the RMT that existed when the interrupt instruction to be flushed entered the processor.

[0018] Figure 5 It shows Figure 1 The ROB in the instruction processing circuit has two exemplary states in response to a flush instruction that restores the RMT to its previous state in the event of an interrupt instruction being flushed.

[0019] Figure 6 It is a flowchart showing a traversal starting from the location of the interrupt instruction entry and proceeding in the first direction. Figure 1 An exemplary process for restoring the RMT to a previous state by entering entries in the ROB in the instruction processing circuit;

[0020] Figure 7 It is a flowchart, which is shown in Figure 1 and 2 An exemplary process for dynamically determining the traversal direction of the ROB in the processing circuitry to minimize the traversal time in RMT recovery;

[0021] Figure 8 This is a block diagram of an exemplary processor-based system, including a processor configured to execute instructions out of order in a pipeline, and a process configured to minimize the traversal time of the ROB in response to instruction flushing to speed up the process. Figure 1 and 2 The register renaming recovery circuit (RRRC) restores the RMT state in the processor. Detailed Implementation

[0022] Exemplary aspects disclosed herein include minimizing traversal of the processor reorder buffer (ROB) for interrupt instruction recovery in the processor. Although instructions can be executed out of order in a pipelined processor, the final result of each instruction regarding the processor state must be committed in program order. As instructions are processed, instructions with register operands gain access to logical registers specified by the processor's instruction set architecture (ISA). To avoid interference between instructions, logical registers for different instructions must be mapped to unique physical registers. The RMT is updated each time a new instruction enters the pipeline and maintains the most recent logical register-to-physical register mapping for each logical register of the processor. Information about the logical register-to-physical register mapping generated by each instruction is stored in entries in the ROB in program order. When the pipeline is interrupted by an instruction that cannot be executed as expected, altering the program flow, all instructions following the interrupted instruction can be flushed from the processor pipeline. It is important to return the RMT state to the state it existed when the interrupted instruction entered the pipeline and when an entry for that instruction was allocated in the ROB.

[0023] In the exemplary aspects disclosed herein, to restore the RMT state in response to an interrupt instruction that fails to execute as expected, register mapping information in ROB entries is sequentially traversed to undo the effects of newer instructions that entered the pipeline after the interrupt instruction or replay the effects of older instructions that entered the pipeline before the interrupt instruction. During the traversal, logical register-to-physical register mapping information obtained from the ROB entries is used to restore the RMT state. To minimize the traversal time of entries in the ROB used to restore the RMT state, in some aspects disclosed herein, a register renaming recovery circuit (RRRC) is provided, configured to determine the position of the oldest flushed instruction entry assigned to the oldest flushed instruction in the ROB, and traverse the ROB in a certain direction starting from the position of the oldest flushed instruction entry. By traversing the ROB starting from the oldest flushed instruction, it is possible to avoid traversing all remaining instruction entries or all flushed instruction entries in the ROB.

[0024] In some embodiments, RRRC is configured to dynamically determine the traversal direction to minimize the traversal of entries in the ROB by minimizing the ROB entries to be traversed to restore the RMT state. For example, fewer ROB entries may be traversed in the first direction by reversing a newer instruction that entered the pipeline after an interrupt instruction, compared to replaying an older instruction that entered the pipeline before an interrupt instruction in the opposite direction, and vice versa. In other aspects, RRRC traverses ROB entries in the ROB in a direction from the instruction entry in the ROB for the oldest flushed instruction entry to the instruction entry in the ROB for the oldest uncommitted instruction. By traversing from the oldest flushed instruction entry, the state of the logical register-to-physical register mapping for logical registers in the RMT may be restored, and they may be made available to the processor more quickly. In other aspects, RRRC is configured to traverse ROB entries in the ROB in a direction from the instruction entry for the oldest flushed instruction to the entry in the ROB for the latest uncommitted instruction. By traversing in this direction, only flushed instructions are traversed, and all updates to the RMT are processed.

[0025] In other aspects, RRRC is configured to dynamically determine whether to traverse ROB entries in a first direction from the oldest flushed instruction entry to the instruction entry for the oldest uncommitted instruction, or to traverse ROB entries in a second direction from the oldest flushed instruction entry to the entry for the latest uncommitted instruction. By dynamically determining the traversal direction, traversal can be minimized. In other aspects, RRRC is configured to traverse ROB entries in the ROB in parallel along the first direction from the oldest flushed instruction entry to the instruction entry for the oldest uncommitted instruction, and along the second direction from the oldest flushed instruction entry to the entry for the latest uncommitted instruction. By traversing in both directions, simultaneously traversing remaining entries and flushed entries, traversal time is minimized and RMT recovery is accelerated. After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will be able to understand the scope of this disclosure and implement its additional aspects.

[0026] Figure 1 It shows in Figure 1 The instruction processing circuit 100 is provided in the CPU core 102 of the processor 104. For example, the instruction processing circuit 100 includes one or more instruction pipelines I0-I N The one or more instruction pipelines I0-I NThis is used to process a fetched computer instruction 106F, which is fetched from a series of instructions 106 stored in the instruction cache memory 110 or the instruction memory 112 by the instruction fetch circuit 108 for execution. The instruction fetch circuit 108 is configured to provide the fetched instruction 106F as an instruction stream 114 in the instruction processing circuit 100 to one or more instruction pipelines I0-I before the fetched instruction 106F arrives at the execution circuit 116 for execution. N Preprocessing is performed in the middle. Instruction pipeline I0-I N Different processing circuits or stages across instruction processing circuitry 100 are provided to preprocess and process the fetched instruction 106F in a series of steps that can be executed concurrently before the execution circuitry 116 executes the fetched instruction 106F, thereby increasing throughput.

[0027] Continue to refer to Figure 1 The instruction processing circuit 100 includes an instruction decoding circuit 118, which is configured to decode the fetched instruction 106F, fetched by the instruction fetch circuit 108, into a decoded instruction 106D to determine the instruction type and the required action. The decoded instruction 106D is placed in the instruction pipeline I0-I. N In one or more instruction pipelines, and subsequently provided to renaming circuit 120 in instruction processing circuitry 100, it is determined whether any register names in the decoded instruction 106D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. Renaming circuitry 120 is configured to call RMT 122 to rename the logical source register operand and / or write the destination register operand of the decoded instruction 106D to available physical registers 124(1)-124(X)(P0, P1, ..., P...) in physical register file (PRF) 126. X The RMT 122 contains multiple mapping entries, each mapped to a corresponding logic register R0-R0. P (That is, associated with it). The mapping entries are configured to store information in the form of address pointers to physical registers 124(1)-124(X) in PRF 126. Each physical register 124(1)-124(X) 126 in PRF is configured to store a data entry for the source and / or destination register operands for the decoded instruction 106D.

[0028] Instruction processing circuitry 100 also includes register access (RACC) circuitry 128, which is configured to access logic registers R0-R0 in RMT 122 based on the source register operands of the decoded instruction 106D. PThe mapping entries are used to access physical registers 124(1)-124(X) in PRF 126 to retrieve the resulting value from the executed instruction 106E in execution circuit 116. Furthermore, in instruction processing circuit 100, scheduler circuit 130 operates on instruction pipelines I0-I N The instruction processing circuit 100 is provided and configured to store the decoded instruction 106D in a reserved entry until all source register operands for the decoded instruction 106D are available. A write circuit 132 is also provided in the instruction processing circuit 100 to write back or commit the value produced from the executed instruction 106E to memory, such as PRF 126, a cache memory system (not shown), or main memory (not shown).

[0029] Continue to refer to Figure 1 The instruction processing circuit 100 also includes a flow control prediction circuit 134. The flow control prediction circuit 134 is configured to speculatively predict the result of a condition of a fetched conditional flow control instruction 106F (such as a conditional branch instruction), which controls whether an adopted or unadopted path in the instruction control flow path of instruction flow 114 is fetched onto instruction pipeline I0-I. N The condition of the fetched flow control instruction 106F does not need to be resolved during execution by the execution circuit 116 before the instruction processing circuit 100 can continue processing the speculatively fetched instruction 106F. The prediction made by the flow control prediction circuit 134 can be provided as prediction information 136 to the instruction fetch circuit 108 for use in determining the next instruction 106 to be fetched.

[0030] However, if it is determined during the execution of the conditional flow control instruction 106F in execution circuit 116 that the condition of the conditional flow control instruction 106F has been incorrectly predicted, then instruction 106F is interrupted. Speculatively fetched instructions 106F processed in instruction processing circuit 100 after the conditional flow control instruction 106F are flushed because the direction of program flow is changed and processing of these instructions will not be included. Load or store instructions 106F, to which the calculated address of a memory location may be invalid or inaccessible for some other reason, may also cause subsequent instructions 106F to be flushed. Under these conditions, program flow in instruction processing circuit 100 is interrupted, and instruction processing circuit 100 returns to its previous state. The previous state to which the processor is restored depends on the type of interrupt instruction and may be a state that existed before or as a result of the interrupted instruction 106F (“interrupt instruction”). In particular, this disclosure aims to restore the previous state of RMT 122 to restore the logical register-to-physical register mapping that has been changed by an instruction (“newer instruction”) that enters the instruction processing circuit 100 after an interrupt instruction.

[0031] Continue to refer to Figure 1 The instruction processing circuit 100 also includes a ROB 136, which contains entries (“ROB entries”) 138 for each instruction 106 that are being processed by the instruction processing circuit 100 but have not yet been submitted. ROB indexes identify the position of each ROB entry 138 within the ROB 136. ROB entries 138 are assigned sequentially to the instructions 106 in program order. When a ROB entry 138 is initially assigned, the ROB index for each instruction 106 is reported back to the instruction processing circuit 100. In this way, the instruction processing circuit 100 can associate the ROB index with interrupt instructions. Regarding the logic registers R0-R1 as a result of instruction 106... P Information regarding changes to the mapping is stored in ROB entry 138 corresponding to instruction 106. ROB 136 includes a read pointer RD_PTR pointing to the ROB index of ROB entry 138, from which information about the oldest uncommitted instruction is read when it is committed. The read pointer RD_PTR is updated each time an uncommitted instruction is committed. ROB 136 also includes a write pointer WR_PTR indicating the ROB index of the last ROB entry 138, into which information about the latest uncommitted instruction is written. When instruction 106 updates the logic registers R0-R in RMT 122... P When mapping logical registers to physical registers, the ROB index of ROB entry 138 in instruction 106 is mapped to the logical registers R0-R... P Related. Therefore, it is related to updating the logic registers R0-R P The last instruction 106 of the mapping corresponds to the ROB index and is related to the logic registers R0-R P The entries are stored together in RMT 122. As will be explained in detail below, the information stored for the uncommitted instruction in ROB entry 138 is used to implement RMT recovery in response to flushing.

[0032] Continue to refer to Figure 1 The instruction processing circuit 100 also includes a submitted mapping table (CMT) 140, which stores each logic register R0-R of the processor 104. P The logical register to physical register mapping is the result of committed instruction 106. CMT 140 is updated only when instruction 106 is committed. CMT 140 is not changed by RMT 122 responding to a flush.

[0033] The instruction processing circuit 100 also includes a mapping control circuit 142, which includes a register rename recovery circuit (RRRC) 144 for controlling RMT flush recovery. The mapping control circuit 142 is configured to assign new ROB entries 138 to pipelines I0-I. N The new instruction 106 is executed, and the write pointer WR_PTR is set accordingly. Therefore, ROB entry 138 can also be referred to as instruction entry 138 in this document. The mapping control circuit 142 also deallocates entry 138 when the oldest uncommitted instruction is committed. This includes moving the read pointer RD_PTR to the next oldest uncommitted instruction. RRRC 144 will refer to Figure 2 Further discussion.

[0034] Figure 2 yes Figure 1 The diagram illustrates components of the instruction processing circuit 100, including RMT 122, ROB 136, CMT 140, and mapping control circuitry 142 including RRRC 144. When a flush occurs due to an interrupt instruction, as described above, the instruction processing circuit 100 provides a flush indicator 146 indicating the flushing of one or more instructions in the instruction processing circuit 100. The instruction processing circuit 100 also provides a ROB index of the ROB entry 138 of the interrupt instruction, which may be referred to herein as the "interrupt instruction indicator." The flush indicator 146 and the interrupt instruction indicator are received by RRRC 144 to control RMT flush recovery. The interrupt instruction indicator points to the ROB index of the ROB entry 138 of the interrupt instruction that caused the flush. Based on the interrupt instruction indicator, the oldest flushed instruction entry, identified by the oldest flushed instruction pointer (OF_PTR), indicates the oldest instruction in ROB 136 to be flushed. During RMT recovery, the oldest flushed instruction indicated by the oldest flushed instruction entry and any newer instructions will be flushed. Depending on the instruction type of the interrupt instruction, the interrupt instruction can be the oldest instruction to be flushed. Alternatively, depending on the instruction type, the interrupt instruction may not be flushed. In this case, the interrupt instruction is the latest remaining instruction. Any logical register-to-physical register mapping changes caused by the flush instruction must be negated (i.e., reverted) to restore RMT 122 to its desired previous state.

[0035] Further reference Figure 2 The example states of RMT 122, ROB 136, and CMT 140 are shown. Figure 2 The example state shown is used as Figures 3A-3B The starting point for the RMT recovery examples shown in 4A-4B and 5A-5B.

[0036] Figure 2 RMT 122 is shown as including R0-R for each logic register.P The table contains rows where logical registers R0-R5 are labeled. For each logical register in R0-R5, the column entries in each row indicate the logical register number (LOG), the physical register number to which logical registers R0-R5 are mapped (PHY), the ROB index (IDX) of instruction 106 that generates the logical register-to-physical register mapping of logical registers R0-R5, and the recovery instruction (RCVR) used in the recovery of RMT122. RCVR is further described below.

[0037] ROB 136 is shown as a table comprising rows of each ROB entry 138. For each ROB entry in ROB entry 138, the column entries in each row indicate the ROB index (IDX) of the ROB entry 138, whose mapping is changed by the logical registers R0-R0 of the instruction 106 associated with the ROB entry 138. P Logical register number (LOG), logical registers R0-R P The new physical register (P_NEW) to which it is mapped, and the logical registers R0-R P The old physical register (P_OLD) that was previously mapped to. Figure 2 In the diagram, ROB 136 is shown as having ROB entry 138, and ROB entry 138 has ROB index AI.

[0038] CMT 140 is also shown as including R0-R for each logic register. P The table contains rows where logic registers R0-R5 are labeled. Each row has a column entry indicating the logic register number (LOG) and the logic registers R0-R5 in the same row. P The corresponding physical register (PHY) to which it is mapped.

[0039] Figure 2 The arrows in the diagram illustrate the bidirectional flow between the mapping control circuit 142 and each of the RMT 122, ROB 136, CMT 140, and instruction processing circuit 100. The purpose of some of these signals may be described below as needed, but generally indicates the flow of control signals and / or data to perform the operations described herein. The instruction processing circuit 100 according to this disclosure is not limited to... Figure 2 The dimensions, content, or labels of the tables shown. RMT122, ROB 136, and CMT 140 according to this disclosure may contain any number of rows, additional columns providing further information for each row, and [other features]. Figure 2 The names shown are different names. The illustration shows those included... Figure 2The entries in the RCVR column of RMT 122 can be maintained and / or stored separately from RMT 122 and still provide the functionality disclosed herein.

[0040] Regarding the logic registers R0-R that have been updated since the last committed instruction. P Information regarding any logical register-to-physical register mappings is stored in ROB entry 138 sequentially. Logical registers R0-R0 are updated as a result of instruction 106, which is to be flushed. P The logical register-to-physical register mapping for each logical register in the ROB must be restored to the mapping state that existed at the time of the interrupt instruction. Each entry 138 contains information about the logical register mapping change caused by the specific instruction 106 assigned to that ROB entry 138. Because the information in entry 138 includes logical registers R0-R P Both the new physical register (P_NEW) and the old physical register (P_OLD) are mapped, so information from ROB entry 138 can be used to negate ("undo") or recreate ("redo") any logical register(s) R0-R0(s) that have been updated since the last committed instruction. P The logical mapping is provided. An example of how RRRC 144 traverses ROB entry 138 for RMT recovery is given.

[0041] All ROB entries from the oldest flushed instruction and the newest ROB index 138 may have altered logic registers R0-R P The logical registers are mapped to physical registers. Therefore, when the flush indicator 146 is received from the instruction processing circuit 100, the ROB index associated with each logical register mapping in RMT 122 is compared with OF_PTR to identify all logical registers in the logical registers to be mapped to the new physical register as the result of the instruction to be flushed.

[0042] Figure 3A and 3B This shows the traversal in response to flush indicator 146. Figure 1 The instruction processing circuit 100 uses ROB entry 138 in ROB 136 to restore the RMT 122 to a previous state that existed before the oldest flushed instruction entered the instruction processing circuit 100. RRRC 144 retrieves information from ROB entry 138 to restore the RMT 122 from a state present when flush indicator 146 is received to a previous state present when the oldest flushed instruction entered the instruction processing circuit 100. CMT 140 is shown for reference but is not affected by the restoration process. Figures 3A-3BThe corresponding combined states of CMT 140, RMT 122, and ROB 136 shown herein are referred to herein as “processor states” 300-306. Since the RMT recovery according to the circuitry and methods disclosed herein does not alter the instruction processing circuitry 100, it is not shown in these examples.

[0043] Starting from processor state 300, ROB entry 138(B) is assigned to the oldest uncommitted instruction, and ROB entry 138(H) is assigned to the latest uncommitted instruction. Since none of the instructions assigned to ROB entry 138 have been committed, these instructions will be referred to as the oldest and latest instructions in ROB 136, respectively. In processor state 300, RRRC 144 receives a flush indicator 146 indicating a flush of one or more instructions in processor 104 based on an interrupt instruction that causes a flush of one or more instructions in processor 104. RRRC 144 also receives an interrupt instruction indicator indicating the position of the interrupt instruction entry 138 for the interrupt instruction in ROB 136 within processor 104.

[0044] RRRC 144 determines the location of the oldest flushed instruction entry OF_PTR based on the interrupt instruction indicator, which is assigned to the oldest instruction among one or more instructions indicated for flushing. The oldest flushed instruction entry OF_PTR is set to point to the oldest flushed instruction. The dashed line highlighting ROB entry 138(E) indicates an interrupt instruction that, depending on the type of interrupt instruction, may be flushed.

[0045] The traversal pointer TR_PTR, used to identify the current entry during the RMT recovery step, is set to the first ROB entry 138 of the oldest instruction to be flushed. RRRC 144 traverses ROB entries 138 in ROB 136 of processor 104 along a first direction, starting from the position of the oldest flushed instruction entry OF_PTR. RRRC 144 traverses ROB entries 138 in ROB 136 by determining whether the first instruction assigned to the first instruction entry 138 in the first direction of ROB 136 produces a logical register-to-physical register mapping in the mapping entry of RMT 122. Since interrupt instructions are not flushed in this example, the traversal pointer TR_PTR is set to point to ROB entry 138(F) for the oldest flushed instruction.

[0046] The ROB index associated with each of the logical registers R0-R5 is compared with ROB index F, as they may have been mapped to new physical registers as a result of a flush instruction. If any logical register R0-R5 has an associated ROB index F or is alphabetically following F, recovery is required. If none of the ROB indices associated with the logical registers R0-R5 in RMT 122 has an associated ROB index F or is alphabetically following F, recovery is not required. Therefore, RRRC 144 is configured to determine that at least one mapping entry in RMT 122 has not been recovered based on the following: the ROB index in that at least one mapping entry in RMT 122 corresponds to the ROB index of ROB entry 138 assigned to an instruction after an interrupt instruction entry was assigned to one or more instructions indicated for flushing.

[0047] In processor state 300, ROB indices G and H indicate that the mapping of logical registers R2 and R4 needs to be restored. In response to determining that at least one mapping entry in RMT 122 has not been restored based on the index of instruction entry 138 in ROB 136, which is assigned to one or more instructions indicated for flushing, RRRC 144 is configured to set the restore indicator RCVR (e.g., set to "R" to indicate restore) for logical registers R2 and R4 for each mapping entry in RMT 122 to indicate that the logical register-to-physical register mapping in that mapping entry needs to be restored. Other mechanisms for tracking which RMT entries have been restored or not are within the scope of this disclosure. Referring to ROB 136, ROB entry 138 with ROB indices F and H shows that logical register R2 is mapped from the old physical register P_OLD 5 to the new physical register P_NEW 14 via an instruction associated with ROB index F, and then to the new physical register P_NEW 9 via an instruction associated with ROB index H. Furthermore, ROB entry 138 with ROB index G shows that logical register R4 is mapped from the old physical register P_OLD 7 to the new physical register P_NEW 8.

[0048] Figures 3A-3BIn the example shown, the RMT recovery is performed by RRRC 144, which is configured to traverse ROB entries 138 in ROB 136 in a first direction, starting from the position of the oldest flushed instruction entry. RRRC 144 determines the position of the oldest flushed instruction entry among the oldest instructions of one or more instructions indicated for flushing, based on the interrupt instruction indicator and also on the type of the interrupt instruction. Starting from ROB entry 138(F), RRRC 144 determines whether the first instruction of the first instruction entry in the first direction (i.e., ROB entry 138(F)) assigned to ROB 136 produces a logical register-to-physical register mapping in the mapping entries of RMT 122. As shown, instruction 106 assigned to ROB entry 138(F) causes a change in the mapping of logical register R2. In response to the determination that the first instruction assigned to the first instruction entry (ROB entry 138(F)) along the first direction produces a logical register to physical register mapping in the mapping entry for logical register R2 in RMT 122, RRRC 144 restores the logical register to physical register mapping of logical register R2 in RMT 122 to the previous logical register to physical register mapping prior to the oldest instruction among one or more instructions indicated to be flushed.

[0049] Move to Figure 3A In processor state 302, based on the old physical register P_OLD value in ROB entry 138(F), i.e., the state after the interrupt instruction completes, the logical register-to-physical register mapping of logical register R2 in RMT 122 is restored to physical register 5. In response to restoring the logical register-to-physical register mapping of the mapping entry in RMT 122 to the previous logical register-to-physical register mapping prior to the oldest instruction among one or more instructions indicated to be flushed, RRRC 144 sets the restoration indicator RCVR for the restored mapping entry to indicate that the logical register-to-physical register mapping in the restored mapping entry has been restored. Therefore, the RCVR associated with logical register R2 is set to indicate that logical register R2 has been restored, which further indicates to instruction processing circuitry 100 that logical register R2 in RMT 122 can be used when program flow continues in a new direction after the interrupt.

[0050] Since the recovery of logical register R2 based on the information in ROB entry 138(F) is complete, the traversal pointer TR_PTR is set to point to ROB entry 138(G). RRRC 144 will determine whether the second instruction assigned to the second ROB entry 138 in the first direction of ROB 136 produces a logical register-to-physical register mapping in the mapping entries of logical registers R0-R5 in RMT 122. In response to such a determination, RRRC 144 determines whether the recovery indicator RCVR in RMT 122 for the mapping entries of logical registers R0-R5 indicates that the logical register-to-physical register mapping in the mapping entries has not been recovered. In response to the determination that such mapping entries have not been recovered, RRRC 144 restores the logical register-to-physical register mapping of the mapping entries of logical registers R0-R5 in RMT 122 to the previous logical register-to-physical register mapping before the oldest instruction among the one or more instructions indicated to be flushed, and sets the recovery indicator RCVR to indicate that the logical register-to-physical register mapping in the mapping entries has been recovered.

[0051] exist Figure 3A In the example, RRRC 144 determines that the instruction assigned to ROB entry 138(G) caused a change to the logical register-to-physical register mapping of logical register R4 in RMT 122. In response, RRRC 144 determines whether the restore indicator RCVR for logical register R4 in RMT 122 indicates that the mapping for logical register R4 needs to be restored. As shown in processor state 302, RRRC 144 determines that the restore indicator RCVR for logical register R4 indicates that the mapping for logical register R4 needs to be restored, therefore RRRC 144 restores the state of the mapping entry for logical register R4 in RMT 122 based on the information in ROB entry 138(G). Specifically, the logical register-to-physical register mapping of logical register R4 is set to map logical register R4 to physical register 11 based on the old physical register P_OLD value in ROB entry 138(G), which is the state of the mapping of logical register R4 after the interrupt instruction caused the change to RMT 122. This restoration of the mapping of logical register R4 is... Figure 3B It is shown in RMT 122 in processor state 304.

[0052] refer to Figure 3BIn processor state 304, the recovery indicator RCVR of logical register R4 is set to indicate that the logical register-to-physical register mapping for logical register (4) in RMT 122 has been recovered. The traversal pointer TR_PTR is also moved to point to the next ROB entry 138(H) along the first direction of traversal. RRRC 144 determines whether instruction 106 assigned to ROB entry 138(H) produces a logical register-to-physical register mapping for logical registers R0-R5 in RMT 122, and if so, determines whether the recovery indicator RCVR corresponding to logical registers R0-R5 in RMT 122 indicates that the logical register-to-physical register mapping for logical registers R0-R5 has been recovered. Alternatively, RRRC 144 may first determine whether any recovery indicator RCVR in RMT 122 is set to "R", and if so, determine whether instruction 106 assigned to ROB entry 138(H) produces a logical register-to-physical register mapping for logical registers R0-R5 in RMT 122. In processor state 304, the recovery indicator RCVR is not set to "R", meaning that no logical registers in RMT 122 need to be recovered. Since the RMT recovery is complete, entries that do not proceed further no longer need to be traversed, and the write pointer WR_PTR is moved to point to ROB entry 138 in the ROB for the latest instruction, i.e., the un-overwritten interrupt instruction. This final recovery state is shown in processor state 306. The mapping control circuitry 142 in processor 104 can then proceed to allocate a new ROB entry 138 for instruction 106 according to the new program flow.

[0053] Figure 4A and 4B This shows the traversal in response to flush indicator 146. Figure 1 ROB entry 138 in ROB 136 of processor 104 is an exemplary sequence for restoring the previous state of RMT 122 that exists when an interrupt instruction that needs to be flushed enters instruction processing circuit 100. Figure 4A and 4B Examples in the text are related to... Figure 3A and 3B The examples in [the example] start with the same processor state, but the difference is that... Figure 4A and 4B In the example, the interrupt instruction is flushed, while Figure 3A and 3B In the example, the interrupt instruction is not flushed. Figure 4A and 4B Examples and Figure 3A and 3B The difference in the example also lies in the direction of traversing ROB entry 138 during RMT recovery by RRRC 144. Figure 4A and 4B In ROB 136, ROB entry 138 is traversed from the location of the interrupt instruction to the location of the oldest instruction associated with ROB entry 138 indicated by the read pointer RD_PTR. Here, the oldest flushed instruction entry OF_PTR points to ROB entry 138(E), and the traversal pointer TR_PTR points to ROB entry 138(D), which is the latest unflushed instruction in processor state 400 and will be the first ROB entry 138 traversed by RRRC 144 during RMT recovery.

[0054] RRRC 144 determines that at least one mapping entry in RMT 122 has not been restored based on a comparison of the ROB index associated with each mapping entry for logical registers R0-R5 in RMT 122 with the oldest flushed instruction entry OF_PTR. Since the interrupt instruction in ROB entry 138(E) is flushed in this example, the state of RMT 122 in processor state 400 is... Figure 3A and 3B The difference in processor state 300 in the example is that the restore indicator RCVR for logical register R1 is set to "R" to indicate that logical register R1 needs to be restored. The restore indicator RCVR for logical register R1 is set to "R" because the flushed interrupt instruction caused a change in the logical register-to-physical register mapping in logical register R1 in RMT 122. RRRC 144 traversal Figure 4A The first instruction entry along the traversal direction, as mentioned above... Figure 3A Specifically, in response to receiving the flush indicator 146, RRRC 144 determines that the instruction assigned to ROB entry 138(D) produces a logical register-to-physical register mapping in the mapping entry of logical register R4 in RMT 122, and restores the logical register-to-physical register mapping in the mapping entry of logical register R4 in RMT 122 to physical register 11 based on the value of the new physical register P_NEW in ROB entry 138(D). As a result, logical register R4 is restored to the state of the mapping entry for logical register R4 that existed when the interrupt instruction entered processor 104, so the restore indicator RCVR for logical register R4 can be set to indicate that logical register R4 in RMT 122 has been restored.

[0055] Therefore, in processor state 402, the recovery indicator RCVR for logical register R4 is no longer set to "R" in RMT 122, and in this example, the traversal pointer TR_PTR has been changed to point to the next ROB entry 138 along the traversal direction (i.e., to ROB entry 138(C)). Before proceeding, RRRC 144 can check the recovery indicators RCVR for each logical register R0-R5 in RMT 122 to see if at least one recovery indicator RCVR is set to indicate that the mapping in the corresponding mapping entry needs to be recovered. RRRC 144 determines whether the instruction assigned to ROB entry 138(C) produces a logical register-to-physical register mapping in the mapping entry of RMT 122. In response to determining that the instruction assigned to ROB entry 138(C) produces a logical register-to-physical register mapping for logical register R2, RRRC 144 checks the recovery indicator RCVR for logical register R2. In response to the recovery indicator RCVR indicating that logical register R2 needs to be recovered, RRRC 144 restores the logical register-to-physical register mapping in the mapping entry of logical register R2 to physical register 5 based on the new physical register P_NEW value in ROB entry 138(C). This is shown in processor state 404. As a result, logical register R2 is restored to the state it existed in when the interrupt instruction entered processor 104, and the recovery indicator RCVR can be set to indicate that logical register R2 has been recovered.

[0056] Finally, along Figure 4A and 4BThe traversal direction in the example continues, and RRRC 144 determines whether the instruction assigned to ROB entry 138(B) produces a logical register-to-physical register mapping in the mapping entry of RMT 122. In response to determining that the instruction assigned to ROB entry 138(B) produces a logical register-to-physical register mapping for logical register R2, RRRC 144 checks the recovery indicator RCVR for logical register R2. In response that the recovery indicator RCVR for logical register R2 indicates that logical register R2 has been recovered (as shown in processor state 406), no recovery is performed. Next, RRRC 144 determines whether the instruction in ROB entry 138(B) is the oldest uncommitted instruction for which an entry was assigned in ROB 136. ROB entry 138(B) is assigned to the oldest uncommitted instruction, as indicated by the read pointer RD_PTR. In response to determining that the instruction in ROB entry 138(B) is the oldest uncommitted instruction, RRRC 144 determines whether the recovery indicator RCVR in RMT 122 for any logical registers R0-R5 indicates that the logical register-to-physical register mapping in any mapping entry in RMT 122 has not been recovered. If any recovery indicator RCVR indicates that the mapping entry for any logical registers R0-R5 in RMT 122 has not been recovered, then for each mapping entry in which the recovery indicator RCVR indicates that the logical register-to-physical register mapping has not been recovered, RRRC 144 determines the logical register-to-physical register mapping in CMT 140 for logical registers R0-R5 that have mappings in the (unrecovered) mapping entry, and sets the logical register-to-physical register mapping in the mapping entry in RMT 122 to the logical register-to-physical register mapping for logical registers R0-R5 in CMT 140.

[0057] To reiterate, when RRRC 144 receives flush indicator 146, if the mapping entries for logic registers R0-R5 have been modified due to any flushed instructions, the restore indicator RCVR for logic registers R0-R5 in RMT 122 is set to "R" to indicate that the mapping entries for logic registers R0-R5 need to be restored. However, those logic registers R0-R5 whose mapping entries have been modified by flushed instructions may not have been modified by any uncommitted instructions that entered the pipeline before the interrupt instruction. As a result, when along... Figure 4A and 4B In the example, when traversing ROB entry 138 and reaching the oldest uncommitted instruction, there may still be some logical registers R0-R5 that need to be restored. To achieve this, the logical register-to-physical register mappings for such logical registers R0-R5 existing in CMT 140 are copied to the corresponding mapping entries in RMT 122.

[0058] This final step of copying the mapping entries from CMT 140 to RMT 122 is crucial for... Figure 3A and 3B In the example, directional traversal of ROB entries 138 is unnecessary. Therefore, in some embodiments disclosed herein, RRRC 144 is configured to dynamically determine the direction for minimizing the traversal of ROB entries in ROB 136 used to recover RMT 122, rather than statically setting the direction for RRRC 144 to traverse ROB entries 138. An example of dynamically determining the traversal direction is as follows... Figure 5 As shown.

[0059] Figure 5 The starting points of Examples 500A and 500B differ from the previous examples in that no instruction is assigned to ROB entry 138(H). In 500A, an interrupt instruction is assigned to ROB entry 138(D) and flushed. Therefore, the oldest flushed instruction entry OF_PTR points to ROB entry 138(D). To dynamically determine the traversal direction, RRRC 144 determines the traversal direction that appears to minimize the time required to traverse ROB entry 138 to complete the RMT recovery. In some embodiments, the method for minimizing the traversal of ROB entry 138 in ROB 136 is to compare the number of entries that can be traversed in each direction and select the direction that appears to complete the traversal in a shorter time or by traversing fewer entries.

[0060] According to the above method, RRRC 144 determines whether the number of remaining ROB entries 138 in ROB 136 from the instruction entry assigned to the next older instruction compared to the oldest instruction among one or more instructions indicated to be flushed to the oldest instruction entry in ROB 136 assigned to the oldest uncommitted instruction is less than the number of flushed ROB entries 138 in ROB 136 from the oldest flushed instruction entry OF_PTR to the latest instruction entry in ROB 136 assigned to the latest uncommitted instruction.

[0061] refer to Figure 5In Example 500A, RRRC 144 compares the number of remaining ROB entries 138 (from ROB entry 138(C) to ROB entry 138(A)) with the number of flushed ROB entries 138 (from ROB entry 138(D) to ROB entry 138(G)). In response to determining that the number of remaining ROB entries 138 is less than the number of flushed ROB entries 138, RRRC 144 traverses ROB 136 in a first direction from the position of the next older instruction compared to the oldest instruction among one or more instructions indicated for flushing to the oldest entry in ROB 136 assigned to the oldest uncommitted instruction (RD_PTR).

[0062] refer to Figure 5 In Example 500B, the interrupt instruction at ROB entry 138(E) is flushed. In this example, RRRC144 determines whether the number of remaining ROB entries 138 in ROB 136 from the position of the instruction entry immediately preceding the oldest flushed instruction entry OF_PTR to the oldest uncommitted entry (read pointer RD_PTR) is less than the number of flushed ROB entries 138 in ROB 136 from the position of the oldest flushed instruction entry OF_PTR to the ROB entry 138 in ROB 136 assigned to the latest uncommitted instruction (write pointer WR_PTR).

[0063] Using the method described above, RRRC 144 dynamically determines that the number of remaining ROB entries 138 from ROB entry 138(C) to ROB entry 138(A) is not less than the number of flushed ROB entries 138 from ROB entry 138(D) to ROB entry 138(G), and in response, it traverses ROB 136 in the direction from the instruction entry immediately adjacent to the oldest flushed instruction OF_PTR to the ROB entry 138 assigned to the latest uncommitted instruction (read pointer WR_PTR). If RRRC 144 determines that the number of remaining ROB entries 138 is not less than the number of flushed ROB entries 138, then RRRC 144 traverses ROB 136 in that direction from the position of the oldest flushed instruction entry OF_PTR to the ROB entry 138 assigned to the latest uncommitted instruction (write pointer WR_PTR).

[0064] In some embodiments, RRRC 144 traverses the ROB 136 in processor 104 in a first direction starting from the position of the oldest flushed instruction entry OF_PTR: from the instruction entry assigned to the next older instruction compared to the oldest instruction among one or more instructions indicated for flushing (i.e., the oldest flushed instruction entry OF_PTR) to the oldest instruction entry in ROB 136 in processor 104.

[0065] In some embodiments, RRRC 144 traverses ROB 136 in processor 104 in a first direction, starting from the position of the oldest flushed instruction entry OF_PTR: traversing ROB 136 in processor 104 in a first direction from the oldest flushed instruction entry OF_PTR to the latest instruction entry.

[0066] In some embodiments, by being configured to determine whether a second instruction assigned to a second instruction entry in ROB 136 along a second direction produces a logical register-to-physical register mapping in a mapping entry of RMT 122 in processor 104, RRRC 144 is configured to traverse ROB 136 in the processor along a second direction from the oldest flushed instruction entry OF_PTR to the latest instruction entry. RRRC 144 is configured to: in response to determining that a second instruction assigned to a second instruction entry in ROB 136 along a second direction produces a logical register-to-physical register mapping in a mapping entry of RMT 122 in processor 104, restore the logical register-to-physical register mapping of the mapping entry in RMT 122 to the previous logical register-to-physical register mapping prior to the oldest instruction among the one or more instructions indicated to be flushed.

[0067] Figure 6 It is shown in Figure 1 A flowchart illustrating an exemplary process in an instruction processing circuit that traverses entries in the Register Name Recovery Block (ROB) in a first direction, starting from the location of an interrupt instruction entry, to restore the Register Name Recovery Block (RMT) to a previous state. The method of the register name recovery circuit includes: receiving a flush indicator based on an interrupt instruction that causes a flush of one or more instructions in the processor, the flush indicator indicating a flush of one or more instructions in the processor. Figure 6 (box 602), and an interrupt instruction indicator that indicates the position of the interrupt instruction entry assigned to the interrupt instruction in the processor's reordering buffer. Figure 6 (frame 604). Figure 6 The method also includes: determining the location of the oldest flushed instruction entry among the oldest instructions of one or more instructions indicated for flushing, based on the interrupt instruction indicator. Figure 6 (box 606), and traverse the reorder buffer in the processor in the first direction starting from the position of the oldest flushed instruction entry. Figure 6 (Frame 608). Figure 6In the method, traversing the reordering buffer further includes: determining whether a first instruction allocated to a first instruction entry in the reordering buffer along a first direction produces a logical register-to-physical register mapping in a mapping entry of a register map table in the processor; and in response to determining that the first instruction allocated to the first instruction entry in the reordering buffer along a first direction produces a logical register-to-physical register mapping in a mapping entry of a register map table in the processor (… Figure 6 The method further includes restoring the logical register-to-physical register mapping of the mapping entries in the register map table to the previous logical register-to-physical register mapping prior to the oldest instruction among one or more instructions indicated for flushing. Figure 6 (frame 612).

[0068] Figure 7 It is shown in Figure 1 and 2 A flowchart illustrating an exemplary process in the processing circuitry of the ROB that dynamically determines the traversal direction for minimizing the traversal time in RMT recovery.

[0069] Figure 7 The method includes: a register renaming recovery circuit determining whether the number of remaining instruction entries in the reordering buffer is less than the number of flushed instruction entries, the remaining instruction entries being from the instruction entry assigned to the next older instruction compared to the oldest instruction among one or more instructions indicated for flushing to the oldest instruction entry in the reordering buffer assigned to the oldest uncommitted instruction, and the flushed instruction entries being from the oldest flushed instruction entry to the latest instruction entry in the reordering buffer assigned to the latest uncommitted instruction, and in response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries ( Figure 7 The decision box 702 traverses the reorder buffers in the processor along the first direction, starting from the position of the oldest flushed instruction entry. Figure 7 Box 704 includes an instruction entry that traverses the reorder buffer in the processor in a first direction from the instruction entry assigned to the next older instruction compared to the oldest instruction among one or more instructions indicated for flushing, to the oldest instruction entry. Figure 7 (Box 706). Alternatively, in response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries ( Figure 7 The decision box 702, the method includes traversing the reorder buffers in the processor along a first direction, starting from the position of the oldest flushed instruction entry. Figure 7 Box 708 includes a reorder buffer that traverses the processor in a first direction from the oldest flushed instruction entry to the latest instruction entry. Figure 7 (frame 710).

[0070] Figure 8 This is a block diagram of an exemplary processor-based system 800, which includes a processor 802 (e.g., a microprocessor) and instruction processing circuitry 804. For example, the processor-based system 800 could be... Figure 1 A processor-based system. For example, the instruction processing circuit 804 could be... Figure 2 The instruction processing circuitry 100 is present in the system. The processor-based system 800 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and can represent, for example, a server or user's computer. In this example, the processor-based system 800 includes a processor 802. Processor 802 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. More specifically, processor 802 can be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for delivering produced values ​​generated by the execution of producer instructions. Processor 802 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 802 includes an instruction cache 808 for temporarily fast-access memory storage of instructions accessible to instruction processing circuitry 804. Instructions fetched or prefetched from memory (such as main memory 810 via system bus 812) are stored in instruction cache 808. The instruction processing circuit 804 is configured to process instructions fetched into the instruction cache 808 and process the instructions for execution.

[0071] Processor 802 may include register renaming recovery circuitry 814 for restoring the state of a register renaming map in instruction processing circuitry 804 in response to a flush instruction indicating that certain instructions in the instruction pipeline have been flushed due to a failed instruction. Processor 802 may be Figure 1 and 2 In any of the diagrams, processor 104 can be configured to minimize the traversal of the reorder buffer during register renaming map recovery.

[0072] Processor 802 and main memory 810 are coupled to system bus 812 and can be coupled to peripheral devices included in processor-based system 800. It is known that processor 800 communicates with these other devices by exchanging address, control, and data information via system bus 812. For example, processor 802 can transmit bus transaction requests to memory controller 819 in main memory 810, which is an example of a slave device. Although Figure 8Not shown, but multiple system buses 812 may be provided, each forming a different architecture. In this example, memory controller 819 is configured to provide memory access requests to memory array 820 in main memory 810. Memory array 820 includes an array of storage bit cells for storing data. Main memory 810 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and static memory (e.g., flash memory, static random access memory (SRAM), etc.), as a non-limiting example.

[0073] Other devices can be connected to system bus 812. For example... Figure 8 As shown, for example, these devices may include main memory 810, one or more input devices 822, one or more output devices 824, modem 826, and one or more display controllers 828. The input devices 822 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 824 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 826 may be any device configured to allow the exchange of data to and from network 830. Network 830 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetexts. TM Networks and the Internet. Modem 826 can be configured to support any type of desired communication protocol. Processor 802 can also be configured to access multiple display controllers 828 via system bus 812 to control information sent to one or more displays 832. The multiple displays 832 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0074] Figure 8 The processor-based system 800 may include a set of instructions 834, which will be executed by the processor 802 for any application desired according to the instructions. The instructions 834 may be stored in main memory 810, the processor 802, and / or instruction cache 808 (as an example of non-transitory computer-readable medium 836). The instructions 834 may also reside wholly or at least partially in main memory 810 and / or in the processor 802 during their execution. The instructions 834 may also be transmitted or received via a network 830 via a modem 826, such that the network 830 includes the computer-readable medium 836.

[0075] Although computer-readable medium 836 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store a set or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions executable by a processing device and causing the processing device to perform any or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0076] The embodiments disclosed herein include various steps. These steps may be formed by hardware components or may be embodied in machine-executable instructions that can be used to perform these steps using a general-purpose or special-purpose processor programmed with those instructions. Alternatively, these steps may be performed by a combination of hardware and software.

[0077] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. Machine-readable media include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.) and so on.

[0078] Unless otherwise specifically stated and apparent from the foregoing discussion, it should be understood that throughout the description, discussions using terms such as “processing,” “computing,” “determining,” and “displaying” refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data and memory represented as physical (electronic) quantities in computer system registers into other data similarly represented as physical quantities in computer system memory or registers or other such information storage, transmission, or display devices.

[0079] The algorithms and displays presented herein are inherently associated with any particular computer or other device. Various systems can be used with the programs based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will become apparent from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0080] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0081] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed by a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller may be a processor. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0082] The embodiments disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0083] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussion. The described operations may be performed in many different orders than those illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0084] Unless otherwise expressly stated, it is not intended to interpret any method described herein as requiring its steps to be performed in a particular order. Therefore, if a method claim does not actually describe the order in which its steps are followed, or if the claims or description do not otherwise specifically specify that these steps are limited to a particular order, it is not intended to infer any particular order. It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments that incorporate the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. An electronic device, comprising: processor; as well as A memory, coupled to the processor, stores executable instructions that, when executed by the processor, cause the electronic device to perform actions, including: A flush indicator is received based on an interrupt instruction that causes a flush of one or more instructions in the processor, the flush indicator indicating the flush of the one or more instructions in the processor; Receive interrupt instruction indicator, the interrupt instruction indicator indicating the position of the interrupt instruction entry assigned to the interrupt instruction in the processor's reordering buffer; The location of the oldest flushed instruction entry assigned to the oldest instruction among the one or more instructions indicated for flushing is determined based on the interrupt instruction indicator; and Starting from the position of the oldest flushed instruction entry, the reorder buffer in the processor is traversed in one direction, which is achieved by being configured as follows: Determine whether the first instruction assigned to the first instruction entry in the reordering buffer along the said direction produces a logical register-to-physical register mapping in a mapping entry of the register map table in the processor; and In response to the first instruction that determines the first instruction entry allocated to the reordering buffer along the direction, a logical register-to-physical register mapping is generated in the mapping entries of the register mapping table in the processor: The logical register-to-physical register mapping of the mapping entry in the register mapping table is restored to the previous logical register-to-physical register mapping prior to the oldest instruction in the one or more instructions that are indicated to be flushed.

2. The electronic device according to claim 1, wherein the action further includes: Based on the correspondence between the index in at least one mapping entry in the register map table and the index in the reordering buffer that is assigned to the one or more instructions indicated for flushing, it is determined that the at least one mapping entry in the register map table has not been recovered.

3. The electronic device according to claim 2, wherein the action further includes: In response to determining that the at least one mapping entry in the register map table has not been recovered based on the index of the at least one mapping entry in the register map table corresponding to the instruction entry in the reordering buffer that was assigned to the one or more instructions indicated for flushing: For each of the at least one mapping entry in the register mapping table, a recovery indicator is set to indicate that the logical register-to-physical register mapping in the mapping entry has not been recovered.

4. The electronic device according to claim 3, wherein the action further includes: Determine whether the second instruction assigned to the second instruction entry in the reordering buffer along the direction produces a logical register-to-physical register mapping in at least one mapping entry of the register mapping table; as well as In response to a second instruction that determines the second instruction entry allocated to the reordering buffer along the direction, a logical register-to-physical register mapping is generated in at least one mapping entry of the register mapping table: Determine whether the recovery indicator for the mapping entry in the register mapping table indicates that the logical register-to-physical register mapping in the mapping entry has not been recovered; and In response to determining that the recovery indicator for the mapping entry in the register mapping table indicates that the logical register-to-physical register mapping in the mapping entry has not been recovered: Restore the logical register-to-physical register mapping of the mapping entry in the register map table to the previous logical register-to-physical register mapping prior to the oldest instruction among the one or more instructions indicated for flushing; and The recovery indicator is set to indicate that the logical register-to-physical register mapping in the mapping entry has been restored.

5. The electronic device according to claim 2, wherein the action further includes: In response to restoring the logical register-to-physical register mapping of the mapping entry in the register mapping table to the previous logical register-to-physical register mapping prior to the oldest instruction in the one or more instructions indicated for flushing: Set a recovery indicator for the mapping entry to which the logical register-to-physical register mapping is restored, to indicate that the logical register-to-physical register mapping in the mapping entry is restored.

6. The electronic device according to claim 3, wherein the action further includes: Determine whether the first instruction is the oldest uncommitted instruction for which an entry has been allocated in the reordering buffer in the processor; as well as In response to determining that the first instruction is the oldest uncommitted instruction for which an entry has been allocated in the reordering buffer in the processor: Determine whether the recovery indicator for any mapping entry in the register map table indicates that the logical register-to-physical register mapping in any mapping entry has not been recovered; and In response to the determination that the recovery indicator for any mapping entry in the register mapping table indicates that the logical register-to-physical register mapping in any mapping entry has not been recovered: For each mapping entry in the logical register-to-physical register mapping that has not been restored, as indicated by the recovery indicator: Determine the logical register-to-physical register mapping in the submitted mapping table for logical registers that have mappings in the mapping entries; and Set the logical register-to-physical register mapping in the mapping entry to the logical register-to-physical register mapping for the logical register in the submitted mapping table.

7. The electronic device according to claim 1, wherein the action further includes: Based on the type of the interrupt instruction, determine the position of the oldest flushed instruction entry assigned to the oldest instruction among the one or more instructions indicated for flushing.

8. The electronic device according to claim 1, wherein the action further includes: Determine whether the number of remaining instruction entries in the reordering buffer is less than the number of flushed instruction entries in the reordering buffer, the remaining instruction entries being from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated to be flushed to the oldest instruction entry in the reordering buffer assigned to the oldest uncommitted instruction, and the flushed instruction entries being from the oldest flushed instruction entry to the latest instruction entry in the reordering buffer assigned to the latest uncommitted instruction. In response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries: The reorder buffer in the processor is traversed along the direction starting from the position of the oldest flushed instruction entry, which is achieved by being configured as follows: The reordering buffer in the processor is traversed in the direction from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated for flushing, to the oldest instruction entry. as well as In response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries: Starting from the position of the oldest flushed instruction entry, the reorder buffer in the processor is traversed along the direction, which is achieved by being configured as follows: The reorder buffer in the processor is traversed along the direction from the oldest flushed instruction entry to the latest instruction entry.

9. The electronic device according to claim 1, wherein the action further includes: The reorder buffer in the processor is traversed along the direction starting from the position of the oldest flushed instruction entry, which is achieved by being configured as follows: The reordering buffer in the processor is traversed in the direction from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated for flushing, to the oldest instruction entry.

10. The electronic device according to claim 1, wherein the action further includes: The reorder buffer in the processor is traversed along the direction starting from the position of the oldest flushed instruction entry, which is achieved by being configured as follows: The reordering buffer in the processor is traversed along the direction from the oldest flushed instruction entry to the latest instruction entry.

11. The electronic device according to claim 10, wherein the action further includes: The reorder buffer in the processor is traversed in another direction from the oldest flushed instruction entry to the latest instruction entry, which is achieved by being configured as follows: Determine whether the second instruction assigned to the second instruction entry in the reordering buffer in the opposite direction produces a logical register-to-physical register mapping in the register mapping table of the processor; as well as In response to determining the second instruction entry allocated to the reordering buffer in the other direction, the second instruction generates a logical register-to-physical register mapping in the register mapping table of the processor: The logical register-to-physical register mapping of the mapping entry in the register mapping table is restored to the previous logical register-to-physical register mapping prior to the oldest instruction in the one or more instructions that were instructed to be flushed.

12. A method for restoring a register renaming recovery table in a processor using a register renaming recovery circuit, comprising: A flush indicator is received based on an interrupt instruction that causes a flush of one or more instructions in the processor, the flush indicator indicating the flush of the one or more instructions in the processor; Receive interrupt instruction indicator, the interrupt instruction indicator indicating the position of the interrupt instruction entry assigned to the interrupt instruction in the processor's reordering buffer; The location of the oldest flushed instruction entry is determined based on the interrupt instruction indicator; as well as Traversing the reorder buffer in the processor in one direction, starting from the position of the oldest flushed instruction entry, further includes: Determine whether the first instruction assigned to the first instruction entry in the reordering buffer along the direction produces a logical register-to-physical register mapping in the register mapping table of the processor; as well as In response to the first instruction that determines the first instruction entry allocated to the reordering buffer along the direction, a logical register-to-physical register mapping is generated in the mapping entries of the register mapping table in the processor: The logical register-to-physical register mapping of the mapping entry in the register mapping table is restored to the previous logical register-to-physical register mapping prior to the oldest instruction in the one or more instructions that are indicated to be flushed.

13. The method of claim 12, further comprising: Based on the correspondence between the index in at least one mapping entry in the register map table and the index in the reordering buffer that is assigned to the one or more instructions indicated for flushing, it is determined that the at least one mapping entry in the register map table has not been recovered.

14. The method of claim 13, further comprising: In response to determining that the at least one mapping entry in the register map table has not been recovered based on the index of the at least one mapping entry in the register map table corresponding to the instruction entry in the reordering buffer that was assigned to the one or more instructions indicated for flushing: For each of the at least one mapping entry in the register mapping table, a recovery indicator is set to indicate that the logical register-to-physical register mapping in the mapping entry has not been recovered.

15. The method of claim 14, further comprising: Determine whether the second instruction assigned to the second instruction entry in the reordering buffer along the direction produces a logical register-to-physical register mapping in at least one mapping entry of the register mapping table; as well as In response to a second instruction that determines the second instruction entry allocated to the reordering buffer along the direction, a logical register-to-physical register mapping is generated in at least one mapping entry of the register mapping table: Determine whether the recovery indicator for the mapping entry in the register mapping table indicates that the logical register-to-physical register mapping in the mapping entry has not been recovered; and In response to determining that the recovery indicator for the mapping entry in the register mapping table indicates that the logical register-to-physical register mapping in the mapping entry has not been recovered: Restore the logical register-to-physical register mapping of the mapping entry in the register map table to the previous logical register-to-physical register mapping prior to the oldest instruction among the one or more instructions indicated for flushing; and The recovery indicator is set to indicate that the logical register-to-physical register mapping in the mapping entry has been restored.

16. The method of claim 14, further comprising: Determine whether the first instruction is the oldest uncommitted instruction for which an entry has been allocated in the reordering buffer in the processor; as well as In response to determining that the first instruction is the oldest uncommitted instruction for which an entry has been allocated in the reordering buffer in the processor: Determine whether the recovery indicator for any mapping entry in the register map table indicates that the logical register-to-physical register mapping in any mapping entry has not been recovered; and In response to the determination that the recovery indicator for any mapping entry in the register mapping table indicates that the logical register-to-physical register mapping in any mapping entry has not been recovered: For each mapping entry in the logical register-to-physical register mapping that has not been restored, as indicated by the recovery indicator: Determine the logical register-to-physical register mapping in the submitted mapping table for logical registers that have mappings in the mapping entries; and Set the logical register-to-physical register mapping in the mapping entry to the logical register-to-physical register mapping for the logical register in the submitted mapping table.

17. The method of claim 13, further comprising: In response to restoring the logical register-to-physical register mapping of the mapping entry in the register mapping table to the previous logical register-to-physical register mapping prior to the oldest instruction in the one or more instructions indicated for flushing: Set a recovery indicator for the mapping entry to which the logical register-to-physical register mapping is restored, to indicate that the logical register-to-physical register mapping in the mapping entry is restored.

18. The method of claim 12, further comprising: Based on the type of the interrupt instruction, determine the position of the oldest flushed instruction entry assigned to the oldest instruction among the one or more instructions indicated for flushing.

19. The method of claim 12, further comprising: Determine whether the number of remaining instruction entries in the reordering buffer is less than the number of flushed instruction entries in the reordering buffer, the remaining instruction entries being from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated to be flushed to the oldest instruction entry in the reordering buffer assigned to the oldest uncommitted instruction, and the flushed instruction entries being from the oldest flushed instruction entry to the latest instruction entry in the reordering buffer assigned to the latest uncommitted instruction. In response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries: Traversing the reorder buffer in the processor along the direction from the position of the oldest flushed instruction entry further includes: The reordering buffer in the processor is traversed in the direction from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated for flushing, to the oldest instruction entry; and In response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries: Starting from the position of the oldest flushed instruction entry, traversing the reorder buffer in the processor along the direction further includes: The reorder buffer in the processor is traversed along the direction from the oldest flushed instruction entry to the latest instruction entry.

20. The method of claim 12, wherein: Traversing the reorder buffer in the processor along the direction from the position of the oldest flushed instruction entry further includes: The reordering buffer in the processor is traversed in the direction from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated for flushing, to the oldest instruction entry.

21. The method according to claim 12, wherein: Traversing the reorder buffer in the processor along the direction from the position of the oldest flushed instruction entry further includes: The reordering buffer in the processor is traversed along the direction from the oldest flushed instruction entry to the latest instruction entry.

22. The method of claim 21, further comprising: Traversing the reorder buffer in the processor in another direction from the oldest flushed instruction entry to the latest instruction entry further includes: Determine whether the second instruction assigned to the second instruction entry in the reordering buffer in the opposite direction produces a logical register-to-physical register mapping in the register map entry of the processor; and In response to determining the second instruction entry allocated to the reordering buffer in the other direction, the second instruction generates a logical register-to-physical register mapping in the register mapping table of the processor: The logical register-to-physical register mapping of the mapping entry in the register mapping table is restored to the previous logical register-to-physical register mapping prior to the oldest instruction in the one or more instructions that were instructed to be flushed.

23. An electronic device, comprising: processor; as well as A memory, coupled to the processor, stores executable instructions that, when executed by the processor, cause the electronic device to perform actions, including: A flush indicator is received based on an interrupt instruction that causes a flush of one or more instructions in the processor, the flush indicator indicating the flush of the one or more instructions in the processor; Receive interrupt instruction indicator, the interrupt instruction indicator indicating the position of the interrupt instruction entry assigned to the interrupt instruction in the processor's reordering buffer; The location of the oldest flushed instruction entry is determined based on the interrupt instruction indicator; Determine whether the number of remaining instruction entries in the reordering buffer is less than the number of flushed instruction entries in the reordering buffer, the remaining instruction entries being from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated to be flushed to the oldest instruction entry in the reordering buffer assigned to the oldest uncommitted instruction, and the flushed instruction entries being from the oldest flushed instruction entry to the latest instruction entry in the reordering buffer assigned to the latest uncommitted instruction. In response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries: The reorder buffer in the processor is traversed in one direction from the oldest instruction entry to the next older instruction assigned compared to the oldest instruction among the one or more instructions indicated for flushing; and In response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries: The reorder buffer in the processor is traversed along the direction from the latest instruction entry to the oldest flushed instruction entry.

24. The electronic device according to claim 23, further comprising: In response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries: Traverse the reorder buffer in the processor in another direction from the latest instruction entry to the oldest flushed instruction entry; and In response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries: The reordering buffer in the processor is traversed in the other direction from the oldest instruction entry to the next older instruction assigned to the instruction entry compared to the oldest instruction among the one or more instructions indicated for flushing.

25. A method for restoring a register renaming recovery table in a processor using a register renaming recovery circuit, comprising: A flush indicator is received based on an interrupt instruction that causes a flush of one or more instructions in the processor, the flush indicator indicating the flush of the one or more instructions in the processor; Receive interrupt instruction indicator, the interrupt instruction indicator indicating the position of the interrupt instruction entry assigned to the interrupt instruction in the processor's reordering buffer; The location of the oldest flushed instruction entry is determined based on the interrupt instruction indicator; Determine whether the number of remaining instruction entries in the reordering buffer is less than the number of flushed instruction entries in the reordering buffer, the remaining instruction entries being from the instruction entry assigned to the next older instruction compared to the oldest instruction among the one or more instructions indicated to be flushed to the oldest instruction entry in the reordering buffer assigned to the oldest uncommitted instruction, and the flushed instruction entries being from the oldest flushed instruction entry to the latest instruction entry in the reordering buffer assigned to the latest uncommitted instruction. In response to determining that the number of remaining instruction entries is less than the number of flushed instruction entries: The reordering buffer in the processor is traversed in one direction from the oldest instruction entry to the next older instruction assigned to the instruction that is compared with the oldest instruction among the one or more instructions that are indicated to be flushed. as well as In response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries: The reorder buffer in the processor is traversed along the direction from the latest instruction entry to the oldest flushed instruction entry.

26. The method of claim 25, further comprising: In response to determining that the number of remaining instruction entries is not less than the number of flushed instruction entries: The reordering buffer in the processor is traversed in another direction from the latest instruction entry to the oldest flushed instruction entry.

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