Method of synchronizing analog data at the output of multiple digital / analog converters

Abstract

A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital / analog converters (DAC) on the active edge of a common reference clock (Clk), said converters comprising at least one conversion core (C1, C2), the method comprising the following steps: a) providing an external synchronization signal (SYNC_ext) to at least one converter and a signal of said common reference clock to said plurality of converters; b) within each converter, generating an internal synchronization signal (SYNC_int) such that all said internal synchronization signals are aligned on the active edge of said common reference clock; c) for each converter, generating a start signal (START1, START2) representing the start of the transmission of digital data and counting the number of clock cycles until the internal synchronization signal is generated; d) applying to each converter core a delay Ri (R1, R2) equal to the difference between the highest number counted in said step c) and the number of said core counted. The invention also relates to a device for implementing this method.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for synchronizing analog data at the output of a plurality of digital / analog converters on the same active edge of a common reference clock. The present invention also relates to a device for synchronizing analog data at the output of a plurality of digital / analog converters on the active edge of a common reference clock to implement the method of the present invention. BACKGROUND

[0002] For certain applications, such as matrix antennas or MIMO ("Multiple Input, Multiple Output") antennas, it is necessary to synchronize the converters with each other using a plurality of digital / analog converters and digital data input in serial links.

[0003] To this end, the synchronization signal provided to the converters can first synchronize the internal clocks of the converters with each other. Given the high sampling frequency of the converters (from 1 to several gigahertz), the synchronization signal must be very fast, i.e. a few picoseconds, and must occur in a time window much smaller than the period of the clock of the converters.

[0004] Secondly, it is necessary to align the data arriving at the input of the converters with each other. However, the propagation time of a signal on a track of an electronic card is of the order of 6 ps / mm. In order to have all the digital data provided at the input of the converters arrive at the same time on all the converters, it is therefore necessary to adjust the length of the tracks on which these data are transmitted. For certain applications, the physical distance between the components makes this adjustment of the length of the tracks very difficult, if not impossible.

[0005] To overcome this problem, various solutions exist to synchronize the converters regardless of the length of the tracks leading to the different converters.

[0006] The first solution consists in sending to all the converters synchronization pulses of the same phase, the distribution of which is designed to take into account the propagation times on each converter so as to have the active clock edges on which the dividers of the converters will be initialized match. That is to say, the pairs of active clock edges will all be separated by a number of periods of the reference clock that is a multiple of N: 0, N, 2N,... Everything is determined by the design of the reference clock on each converter and the path of the distribution of the synchronization signal. This requires an accurate evaluation of the propagation times on each converter. The first solution is easy to implement when the working frequency is low, but when the working frequency is greater than 100 MHz, it becomes increasingly difficult to evaluate the propagation times and to respect the time constraints.

[0007] The other solutions modify the sampling clock, the effect of which is to degrade the performance of the converters due to the problem of jitter.

[0008] Some solutions use a subdivision of the sampling frequency and a master / slave system between the electronic circuits of the converters and the control synchronization signal to generate the synchronization between the converters. Nonetheless, they limit the temperature tolerance of the system and complicate the clock management in the system. SUMMARY

[0009] The aim of the present invention is to overcome the above-mentioned drawbacks of the prior art; more specifically, the aim of the present invention is to propose a solution that makes it possible to synchronize the analog data at the output of the digital / analog converters on the same active edge of a clock that is common to all the converters, the synchronization being carried out inside the converters.

[0010] One subject of the present invention is therefore a method for synchronizing the analog data at the output of a plurality of digital / analog converters on the active edge of a common reference clock, the converters comprising at least one conversion core, characterized in that it comprises the following steps:

[0011] a) providing at least one of the converters of the plurality with an external synchronization signal emitted by a control unit and providing the plurality of converters with a clock signal of the common reference clock;

[0012] b) generating, inside each of the converters of the plurality, an internal synchronization signal from the external synchronization signal, so that all the internal synchronization signals are aligned on the active edge of the common reference clock;

[0013] c) generating, by at least one electronic circuit inside each of the converters of the plurality, a start signal representative of the start of the sending of digital data by the control unit on each core of the plurality of converters and counting the number of clock strokes between the generation of the start signal and the generation of the internal synchronization signal of each core of the plurality of converters;

[0014] d) applying to each core i of the plurality of converters a delay Ri equal to the difference between the highest number counted in step c) and the number of the core i counted in step c), i being an integer between 1 and the number of cores of the plurality of converters.

[0015] According to a particular embodiment of this method:

[0016] - the internal synchronization signal can be generated in step b) by resampling the external synchronization signal.

[0017] - the converters of the plurality of converters can form a serial transmission link of the external synchronization signal and step a) also comprises:

[0018] - initializing a synchronization circuit in each converter of the plurality of converters, the synchronization circuit comprising at least one polarity parameter defined as a polarity of a reference clock edge, for detecting a signal at the input of the synchronization circuit of the converter, the polarity or the opposite polarity of the reference clock active edge; and

[0019] Step b) further comprises:

[0020] - detecting, on a reference clock edge, a synchronization signal at the input of the synchronization circuit of each converter, the polarity of the synchronization signal being defined by the value of the polarity parameter of the synchronization circuit; and

[0021] - aligning the detected signals on a subsequent active edge, so as to provide, at the output of the synchronization circuit of the converter, an internal synchronization signal aligned on a reference clock active edge.

[0022] Another subject of the application is a device for synchronizing analog data at the output of a plurality of digital / analog converters on active edges of a common reference clock to implement the aforementioned method, comprising:

[0023] - a plurality of digital / analog converters comprising:

[0024] - N conversion cores; and

[0025] - N memories,

[0026] each converter comprising at least one digital input, at least one analog output, at least one of the N memories, at least one of the N conversion cores and a synchronization circuit connected to the digital input, the synchronization circuits of the converters being connected to each other in cascade, the memories of the converters each being connected to a conversion core of the converter, and the synchronization circuits of the converters being configured to generate an internal synchronization signal and to align the generated internal synchronization signals on active edges of the common clock, and N being an integer greater than or equal to 1; and

[0027] - a control unit configured to send signals from the common reference clock, the external synchronization signal and the digital data to each converter,

[0028] characterized in that each converter also comprises a data decoding circuit comprising a counter, said data decoding circuit being placed, for each conversion core comprised in said converter, between the output of said synchronization circuit and the input of said memory and configured to generate a start signal representative of the start of the sending of digital data on said conversion core, and each counter being configured to count the number of clock cycles between the generation of said start signal and the generation of said internal synchronization signal of said conversion core, and the i-th memory being configured to apply a delay Ri to the i-th conversion core, i being an integer between 1 and N.

[0029] According to a particular embodiment of the device:

[0030] Said control unit can comprise at least one programmable logic circuit configured to send said external synchronization signal.

[0031] Said control unit can comprise at least one programmable logic circuit configured to send said digital data.

[0032] Said control unit can also be configured to receive the number of clock cycles counted by said N counters, to determine said delays Ri and to provide said N memories with the delay value Ri to be applied to said i-th conversion core.

[0033] Said N memories can be shift registers.

[0034] Said plurality of converters can comprise N converters, each comprising a single conversion core from said N conversion cores. BRIEF DESCRIPTION OF DRAWINGS

[0035] Other features, details and advantages of the invention will become clear after reading the present description, made with reference to the attached drawings given by way of example, which show respectively:

[0036] Figure 1 is a diagram of the steps of the method according to the invention;

[0037] Figure 2 is a device implementing the method according to the invention; and

[0038] Figure 3 is an embodiment of a digital / analog converter having a plurality of conversion cores, which makes it possible to implement the method according to the invention. DETAILED DESCRIPTION

[0039] Figure 1A figure showing the steps of the method according to the application. The first step, step a), consists in providing at least one of the plurality of digital / analog converters with an external synchronization signal SYNC_ext. The external synchronization signal SYNC_ext is emitted by a control unit UC which controls the plurality of converters.

[0040] The second step, step b), consists in generating an internal synchronization signal SYNC_int within each converter. These internal synchronization signals SYNC_int are mutually synchronized on the active edge of a common reference clock Clk.

[0041] The internal synchronization signals can be aligned outside the converters using a delay line between the control unit UC and the converters, this delay line being dedicated to the external synchronization signal SYNC_ext. In this case, all the converters receive the external synchronization signal SYNC_ext directly through the delay line at the same time, and therefore the internal synchronization signals SYNC_int generated by the converters are synchronized on the same clock edge. In this case, the internal synchronization signals SYNC_int are generated directly from the external synchronization signal SYNC_ext inside each converter.

[0042] This alignment can also take place preferentially inside the converters using the method described in French patent No. 1 560 739. This method consists in configuring the plurality of converters into a serial link, the transmission of the external synchronization signal SYNC_ext from one converter to another replacing the distribution of the phase of the synchronization signal SYNC_ext on all the converters in order to reach all the converters in the link from one to another. In other words, only the first converter receives the external synchronization signal SYNC_ext directly and then generates an internal synchronization signal SYNC_int which is transmitted in turn to the next converter which in turn generates an internal synchronization signal which is transmitted in turn to the next converter until the last converter in the link is reached. In this case, the internal synchronization signals SYNC_int are generated indirectly from the external synchronization signal SYNC_ext inside each converter by transmission from one converter to the next.

[0043] This is combined with the parameterization of each converter in the link which reflects the propagation time of the synchronization signal SYNC_ext in the converter link and by virtue of which, at the output of each converter, the internal synchronization signal SYNC_int is transmitted which resynchronizes the next converter.

[0044] In the case of this method, the transducers form a serial transmission link of the synchronization signal, i.e. each transducer comprises a synchronization circuit in series with the other synchronization circuits of the plurality of transducers. Moreover, step a) of the method also comprises initializing, in each transducer of the plurality of transducers, the synchronization circuit (CS, CS1, CS2, CSI) comprising at least one polarity parameter defined as the polarity of the reference clock edge, for detecting the signal at the input of the synchronization circuit of the transducer, the polarity or the opposite polarity of the reference clock active edge.

[0045] Step b) also comprises detecting, at the input of the synchronization circuit of each transducer, on the reference clock edge, the synchronization signal (SYNC_ext, SYNC_int1, SYNC_int2) arriving from the synchronization circuit of the previous transducer in the transmission link (or from the control unit for the first transducer in the link), having the polarity defined by the value of the polarity parameter of the synchronization circuit.

[0046] Then, step b) comprises aligning the detected signal on the next active edge, so as to provide, at the output of the synchronization circuit of the transducer, an internal synchronization signal (SYNC_int1, SYNC_int2, SYNC_intl) aligned on the reference clock active edge.

[0047] In each transducer, the parameterization also makes it possible to select the correct reference clock edge, which restores the signal that reinitializes the sampling clock generator, making it possible for the sampling clock phases of all the transducers to be synchronized.

[0048] Then, the third step of the method according to the application, i.e. step c), comprises generating a start signal START, which represents the start of the sending of digital data by the control unit to each core of the plurality of transducers. This start signal START is an internal signal of each transducer, issued for each conversion core, indicating to all the transducer cores that the next data item received by the core is the first useful data item, and thus the first useful data item to be converted. The start signal is generated by a decoding block of the transducer, comprising one or more decoding circuits Dec depending on the number of conversion cores. This will be described more particularly with reference to Figure 2 and Figure 3 .

[0049] This START signal is generated after the arrival of the first useful data item. In other words, the START signal is generated as soon as the first data item of the serial link sent by the control unit is received by the transducer.

[0050] Then, in this step c), the number of clock travels between the generation of the start signal START of each conversion core and the generation of the internal synchronization signal SYNC int is counted. This can be done by a counter Cpt present in each converter and with respect to each conversion core within the converter.

[0051] Then, in a last step, step d), a delay Ri is applied to each core i of the plurality of converters, the delay being equal to the difference between the highest number counted in step c) and the number of cores i calculated in step c), i being an integer between 1 and the number of cores of the plurality of converters.

[0052] For example, consider three converters, each having a single conversion core. The first converter counts 13 clock travels between the reception of the START signal and its internal synchronization signal SYNC int, the second converter counts 17 clock travels and finally the third converter counts 14 clock travels. The highest number counted is 17, so a delay Ri equal to 17 minus 13 will be applied to the first converter, i.e. a delay of 4 clock travels. For the second converter, its delay R2 will be equal to 0 as it constitutes the reference, and finally, for the third converter, a delay R3 equal to 17 minus 14 will be applied, i.e. a delay of 3 clock travels.

[0053] If the converters comprise several conversion cores, the same principle applies. The number of clock travels between the reception of the START signal and the internal synchronization signal SYNC int is counted for each core of all converters, then a delay equal to the difference between the highest count of all cores and all converters and the count of the core in question is applied to each core.

[0054] Thus, by applying a delay to each core, it is possible to synchronize all the cores on the slowest conversion core, so as to obtain at the output of the conversion cores data converted and synchronized on the same active edge of the common reference clock.

[0055] Figure 2 An embodiment of a synchronization device is presented which makes it possible to implement the method according to the application and which applies the method of French patent No. 1560739 to step b) of the present method.

[0056] The device comprises a control unit UC and a plurality of digital / analog converters DAC1, DAC2, DACI. The control unit UC provides an external synchronization signal SYNC ext to at least one converter DAC1 of the plurality of converters DAC1, DAC2, DACI. It also provides a clock signal from a common reference clock Clk and digital data Data num1, Data num2, Data numl transmitted to the plurality of converters DAC1, DAC2, DACI in a serial link.

[0057] As shown, DAC 1 receives the external synchronization signal SYNC ext, DAC 2 receives the internal synchronization signal SYNC int 1 and DAC I receives the internal synchronization signal SYNC int 2 (which makes it possible to generate the internal synchronization signals SYNC int 1, SYNC int 2, SYNC int 1 according to the method of French patent No. 1 560 739) or the digital data Data num 1, Data num 2, Data num 1 on the converters at the same active edge of the clock Clk are not synchronized.

[0058] Each converter DAC 1, DAC 2, DAC I comprises in the present embodiment a synchronization circuit CS, a data decoding circuit Dec comprising a counter Cpt, a memory M and a conversion core C.

[0059] The synchronization circuits CS of the converters DAC 1, DAC 2 and DAC I form a serial transmission link. Thus, the synchronization circuit of the first converter DAC 1 is connected to the control unit and its output is connected to the input of the synchronization circuit of the second converter DAC 2. The output of the circuit CS of the second converter DAC 2 is connected to the input of the circuit CS of the third converter DAC I.

[0060] The synchronization circuit CS will generate within each converter DAC 1, DAC 2, DAC I the internal synchronization signals SYNC int 1, SYNC int 2, SYNC int 1 so that all the signals SYNC int 1, SYNC int 2, SYNC int 1 of the converters are aligned on the active edge of the common clock Clk, which corresponds to performing step b) of the method according to the application.

[0061] The data decoding circuit Dec receives from the synchronization circuit CS of the converters the internal synchronization signals SYNC int 1 of the converter DAC 1, SYNC int 2 of the converter DAC 2 and SYNC int 1 of the converter DAC I and the digital data (Data num 1 on the converter DAC 1, Data num 2 on the converter DAC 2 and Data num 1 on the converter DAC I) sent by the control unit CS. Upon reception of the digital data, this data decoding circuit Dec generates a START signal (START 1 in the converter DAC 1, START 2 in the converter DAC 2 and START I in the converter DAC I) representative of the fact that the converter has received the first item of digital data.

[0062] The device presented in this figure makes it possible to apply the method of French patent No. 1 560 739, so only the synchronisation circuit CS of the last converter DAC1 receives the external synchronisation signal SYNC ext issued by the control unit UC. The synchronisation circuit CS of DAC1 then generates the internal synchronisation signal SYNC int1 which is transmitted to the decoding circuit Dec of DAC1 and to the synchronisation circuit CS of DAC2. The synchronisation circuit CS of DAC2 then generates the internal synchronisation signal SYNC int2 which is transmitted to the decoding circuit Dec of DAC2 and to the synchronisation circuit CS of DAC1. The synchronisation circuit CS of the last converter DAC1 generates the internal synchronisation signal SYNC intl which is transmitted only to the decoding circuit Dec of the last converter DAC1.

[0063] The counters Cpt present in the decoding circuits Dec are configured to count the number of clock strokes between the generation of the START signal and the generation of the internal synchronisation signal SYNC int by the decoding circuit Dec.

[0064] Thus, the counter Cpt of the converter DAC1 counts the number of clock strokes between the START1 signal and the synchronisation signal SYNC int1, the counter Cpt of the converter DAC2 counts the number of clock strokes between the START2 signal and the synchronisation signal SYNC int2, and the counter Cpt of the converter DAC1 counts the number of clock strokes between the START1 signal and the synchronisation signal SYNC intl.

[0065] The memories M are configured to impose a delay Ri on the transmission of the data to be converted between the data decoding circuit Dec and the conversion core C, this delay Ri being referenced Figure 1 In step d). Thus, it is equal to the difference between the highest number of clock strokes counted by all the counters and the number of clock strokes counted by the converter comprising this memory.

[0066] To calculate this delay, the counters Cpt can send the counted number of clock strokes to the control unit UC which analyses all the received counts to determine which is the slowest converter (in particular conversion core), i.e. the conversion core which provides the analogue data last from all the cores of the plurality of converters. The control unit UC then subsequently controls the delays Ri: R1, R2, RI which are applied by the different memories M.

[0067] Finally, the conversion core C is configured to convert the digital data Data_numl, Data_num2, Data_numl into analog data Data_anal, Data_ana2, Data_anaI which are recovered at the output of the converters DACl, DAC2, DACI. Then, all the analog data Data_anal, Data_ana2, Data_anaI at the output of the conversion core C are aligned at the same active edge of the clock Clk.

[0068] Figure 3 Another embodiment of the apparatus enabling the method according to the application to be implemented is described, in particular an embodiment of the converter DAC having a plurality of conversion cores Cl and C2.

[0069] In the case of a converter having two conversion cores Cl and C2, the converter DAC comprises a synchronization circuit CS, two data decoding circuits Decl and Dec2, and thus two counters Cptl and Cpt2, and two memories Ml and M2. The synchronization circuit CS receives an external synchronization signal SYNC_ext originating from the control unit UC and then generates an internal synchronization signal SYNC_int which is transmitted to the two data decoding circuits Decl and Dec2.

[0070] The decoding circuits Decl and Dec2 are each connected to the same synchronization circuit CS, but are each connected to a memory and to a core (Ml and Cl for the circuit Cptl and M2 and C2 for the circuit Cpt2).

[0071] The synchronization circuit CS can also receive a synchronization signal originating from another converter, if the converter DAC belongs to a plurality of converters, as described in Figure 2

[0072] Each of the data decoding circuits Decl and Dec2 then receives from the control unit UC digital data Data_numl for Decl and digital data Data_num2 for Dec2, and each generates a signal STARTl and START2 respectively, which represents the arrival of a first item of data to be converted on the conversion cores Cl and C2.

[0073] The counter Cptl of the decoding circuit Decl then counts the number of clock cycles between the generation of the signal STARTl and the generation of the signal SYNC_int, and the counter Cpt2 of the decoding circuit Dec2 counts the number of clock cycles between the generation of the signal START2 and the generation of the signal SYNC_int.

[0074] ​The control unit UC thus receives the number of clock strokes counted from the two counters Cptl, Cpt2 and can therefore determine from the cores Cl and C2 of the converter, more generally from all the conversion cores distributed in the converter, which is the slowest conversion core. The slowest core will then be the reference for calculating the delay to be applied to the other conversion cores.

[0075] Next, the memories Ml and M2 are configured to apply the delays Rl and R2, so as to synchronize the arrival of the data to be converted on each core to the slowest core.

[0076] The control unit UC can be produced from programmable logic circuits of the FPGA type. It is designed to control all the converters DACl, DAC2, DACI and all the conversion cores Cl, C2 according to a master / slave communication scheme, by means of a peripheral interface bus such as the SPI (Serial Peripheral Interface) bus, which is a commonly used synchronous serial data bus. The bus SPI enables the exchange of data, in particular as data to be converted, between the control unit UC and the converters DACl, DAC2, DACI and their cores Cl, C2.

[0077] The control unit UC can also comprise one or more programmable logic circuits of the FPGA type. In the case of several circuits, one FPGA circuit can be dedicated to sending digital data to the converters, while a second FPGA circuit can be dedicated to sending the external synchronization signal SYNC ext. It is also possible to have a dedicated FPGA circuit to send digital data, one circuit per converter.

[0078] The memories M present in the converters DAC, DACl, DAC2, DACI can be shift registers whose register length is equal to the difference between the highest number of clock strokes counted from all the conversion cores and the number counted for the core linked to this register.

Claims

1. A method for synchronizing analog data (Data_ana1, Data_ana2, Data_anaI) at the outputs of multiple digital-to-analog converters (DAC, DAC1, DAC2, DCI), the method synchronizing the analog data on the effective edge of a common reference clock (Clk), the multiple digital-to-analog converters including at least one conversion core (C, C1, C2), characterized in that, The method includes the following steps: a) Provide an external synchronization signal (SYNC_ext) issued by the control unit (UC) to at least one of the plurality of digital / analog converters, and provide a clock signal of the common reference clock to the plurality of digital / analog converters; b) Within each of the plurality of digital-to-analog converters, generate internal synchronization signals (SYNC_int, SYNC_int1, SYNC_int2, SYNC_int1) from the external synchronization signal, thereby aligning all the internal synchronization signals on the effective edge of the common reference clock; c) Generating a start signal (START1, START2, START1) through at least one electronic circuit within each of the plurality of digital-to-analog converters, the start signal representing the control unit's commencement of transmitting digital data (Data_num1, Data_num2, Data_num1) on each conversion core of the plurality of digital-to-analog converters, and counting the number of clock runs between the generation of the start signal and the generation of the internal synchronization signal of each conversion core of the plurality of digital-to-analog converters; and d) Apply a delay Ri (R1, R2, RI) to each conversion core i of the plurality of digital-to-analog converters, the delay being equal to the difference between the highest count in step c) and the count of the conversion core i in step c), where i is an integer between 1 and the number of conversion cores of the plurality of digital-to-analog converters.

2. The method for synchronizing analog data (Data_ana1, Data_ana2, Data_anaI) at the outputs of multiple digital-to-analog converters (DAC, DAC1, DAC2, DCI) according to claim 1, wherein, The internal synchronization signal is generated in step b) by resampling the external synchronization signal.

3. The method for synchronizing analog data (Data_ana1, Data_ana2, Data_anaI) at the outputs of multiple digital-to-analog converters (DAC, DAC1, DAC2, DCI) according to claim 1, wherein, The converters of the plurality of digital / analog converters form a serial transmission link for the external synchronization signal, and step a) further includes: - In each of the plurality of digital-to-analog converters, a synchronization circuit (CS, CS1, CS2, CSI) is initialized, the synchronization circuit including at least one polarity parameter defined as the polarity of a reference clock edge, for detecting the signal at the input of the synchronization circuit of the converter, the polarity of the effective edge of the reference clock, or the opposite polarity; and Step b) also includes: - On the reference clock edge, detect the synchronization signal (SYNC_ext, SYNC_int1, SYNC_int2) at the input of the synchronization circuit of each converter, the polarity of which is defined by the polarity parameter value of the synchronization circuit; and - Align the detected signal on the subsequent valid edge so as to provide an internal synchronization signal (SYNC_int1, SYNC_int2, SYNC_int1) aligned on the valid edge of the reference clock at the output of the synchronization circuit of the converter.

4. An apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), the apparatus being used to implement the method according to claim 1, the apparatus comprising: - Multiple digital-to-analog converters (DAC, DAC1, DAC2, DAI), including: -N conversion cores (C, C1, C2); and -N memory locations (M, M1, M2), Each converter includes at least one digital input, at least one analog output, at least one of the N memories, at least one of the N conversion cores, and synchronization circuitry (CS, CS1, CS2, CSI) connected to the digital input. The synchronization circuitry of the digital-to-analog converters is cascaded. Each memory of the digital-to-analog converter is connected to a conversion core of the digital-to-analog converter. The synchronization circuitry of the digital-to-analog converters is configured to generate internal synchronization signals (SYNC_int, SYNC_int1, SYNC_int2, SYNC_int1) and align these generated internal synchronization signals on the effective edge of a common clock, where N is an integer greater than or equal to 1. - A control unit (UC) configured to send signals from the common reference clock (Clk), the external synchronization signal (SYNC_ext), and the digital data (Data_num1, Data_num2, Data_num1) to each converter. The feature is that each converter further includes a data decoding circuit (Dec1, Dec2, Dec), which includes counters (Cpt, Cpt1, Cpt2). For each conversion core included in the converter, the data decoding circuit is placed at the output of the synchronization circuit and the input of the memory, and is configured to generate a start signal (START1, START2, STARTI), which represents the start of sending digital data on the conversion core. Each counter is configured to count the number of clock runs between the generation of the start signal and the generation of the internal synchronization signal of the conversion core. The i-th memory is configured to apply a delay Ri (R1, R2, RI) to the i-th conversion core, where i is an integer between 1 and N.

5. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as described in claim 4, wherein... The control unit includes at least one programmable logic circuit configured to send the external synchronization signal.

6. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as described in claim 4, wherein... The control unit includes at least one programmable logic circuit configured to transmit the digital data.

7. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as described in claim 4, wherein, The control unit is also configured to receive a number of clock runs counted by N counters to determine the delay Ri and provide the N memories with a delay value to be applied to the i-th conversion core.

8. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as described in claim 4, wherein, The N memories are shift registers.

9. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 4, wherein, The plurality of digital-to-analog converters include N converters, each converter including a single conversion core from the N conversion cores.

10. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 5, wherein, The plurality of digital-to-analog converters include N converters, each converter including a single conversion core from the N conversion cores.

11. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 6, wherein, The plurality of digital-to-analog converters include N converters, each converter including a single conversion core from the N conversion cores.

12. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 8, wherein, The plurality of digital-to-analog converters include N converters, each converter including a single conversion core from the N conversion cores.

13. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 10, wherein... The plurality of digital-to-analog converters include N converters, each converter including a single conversion core from the N conversion cores.

14. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as described in claim 13, wherein, The plurality of digital-to-analog converters include N converters, each converter including a single conversion core from the N conversion cores.

15. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as described in claim 5, wherein, The control unit includes at least one programmable logic circuit configured to transmit the digital data.

16. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 6, wherein, The control unit is also configured to receive a number of clock runs counted by N counters to determine the delay Ri and provide the N memories with a delay value to be applied to the i-th conversion core.

17. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 6, wherein, The N memories are shift registers.

18. The apparatus for synchronizing analog data at the outputs of a plurality of digital-to-analog converters on the effective edge of a common reference clock (Clk), as claimed in claim 7, wherein, The N memories are shift registers.

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