Memory and method of programming operation thereof, peripheral circuit and storage system

Abstract

The application provides a memory, a programming operation method thereof, a peripheral circuit, and a storage system. The memory sequentially comprises an array common source, a bottom level, a middle level, a top level, and a bit line connected in series along a preset direction. The programming operation method of the memory comprises: performing precharge of a programming operation, comprising: providing a first voltage to the array common source and the bit line; and providing a second voltage to a programmed-state storage unit in the memory to turn on a channel in the programmed-state storage unit, wherein the programmed-state storage unit is located in at least one of the middle level and the top level; and performing a programming operation on a middle-to-be-programmed storage unit in the middle level.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to methods for programming and operating memory, peripheral circuits, memory, and storage systems. Background Technology

[0002] With the rapid growth in demand for 5G technology and IoT applications, the market demand for memory storage capacity is increasing daily. 3D NAND Flash, as the mainstream memory device, typically increases storage capacity by adding more storage layers. However, in actual memory manufacturing processes, due to the limitations of deep-hole etching technology, multiple etching operations are usually used to increase the number of layers. For example, current mainstream products already use a two-layer stacked architecture, and the number of stacked layers may continue to increase in the future, such as using three or more stacked layers.

[0003] Currently, during the programming of 3D NAND flash memory, a large forward bias voltage is typically applied to the source terminal located at the source side of the channel during the pre-charge phase. This attracts electrons in the channel to migrate towards the source terminal and ultimately be absorbed by it, thereby reducing the channel charge density. However, as the number of stacked layers in 3D NAND flash memory increases, the channel length becomes longer, and the bonding regions between the stacked layers increase. This limits the electric field force experienced by electrons in the channel far from the source terminal, hindering their efficient migration towards the source terminal. Consequently, the channel charge density cannot be effectively reduced during the pre-charge phase, resulting in severe programming interference. Summary of the Invention

[0004] This application provides a method for programming a memory, the memory comprising, in sequence along a preset direction, an array common source, a bottom layer, a middle layer, a top layer, and bit lines connected in series. The method includes: pre-charging for programming operations, comprising: providing a first voltage to the array common source and the bit lines; and providing a second voltage to a programmed memory cell in the memory to turn on the channel in the programmed memory cell, wherein the programmed memory cell is located in at least one of the middle layer and the top layer; and performing a programming operation on the middle memory cell to be programmed in the middle layer.

[0005] In one embodiment, the first voltage is less than the second voltage.

[0006] In one embodiment, the middle layer includes a second bonding region for electrically connecting the middle layer and the top layer, wherein the pre-charging for programming operations further includes: providing the first voltage to the second bonding region; and the programmed memory unit includes: a top programmed memory unit in the top layer and a middle programmed memory unit in the middle layer.

[0007] In one embodiment, the pre-charging for programming operations further includes providing the first voltage to cells in the memory having an initial voltage, wherein the cells having the initial voltage include at least one of a bottom auxiliary cell in the bottom layer and a top auxiliary cell in the top layer.

[0008] In one embodiment, the central unprogrammed memory cell is adjacent to the central programmed memory cell and located on the side of the central programmed memory cell away from the bit line.

[0009] In one embodiment, the pre-charging step for programming operations includes: simultaneously providing the first voltage to the array common source, the bottom auxiliary cell, the second bonding region, the top auxiliary cell, and the bit line, and providing the second voltage to the top programmed memory cell and the middle programmed memory cell.

[0010] In one embodiment, the pre-charging step for programming operations includes: providing a first voltage to the second bonding region, the top auxiliary unit, and the bit line during a first conduction phase, and providing a second voltage to the top programmed memory unit and the middle programmed memory unit; and providing the first voltage to the array common source and the bottom auxiliary unit during a second conduction phase following the first conduction phase.

[0011] In one embodiment, the pre-charging step for programming operations includes: providing a first voltage to the array common source and the bottom auxiliary cell during a first conduction phase; and providing the first voltage to the second bonding region, the top auxiliary cell, and the bit line during a second conduction phase following the first conduction phase, and providing the second voltage to the top programmed memory cell and the middle programmed memory cell.

[0012] In one embodiment, the bottom auxiliary unit includes a bottom select transistor and a bottom redundant memory unit, wherein the bottom redundant memory unit is adjacent to the bottom select transistor and located on the side of the bottom select transistor away from the array common source.

[0013] In one embodiment, the top auxiliary unit includes a top select transistor and a top redundant memory unit, wherein the top redundant memory unit is adjacent to the top select transistor and located on the side of the top select transistor away from the bit line.

[0014] In one embodiment, the top programmed memory cell is adjacent to the top redundant memory cell and located on the side of the top redundant memory cell away from the bit line.

[0015] In one embodiment, the central programmable memory cell includes a plurality of programmable memory cells, and the programming operation of the central programmable memory cell includes: programming the programmable memory cell from the programmable memory cell close to the bit line to the direction away from the bit line, wherein a pre-charging step of the programming operation is performed before programming each programmable memory cell.

[0016] In one embodiment, the central hierarchy includes a plurality of sub-central hierarchies that are connected in series through a central bonding region.

[0017] In one embodiment, the bottom layer includes a first bonding region for electrically connecting the bottom layer and the middle layer, and the memory includes channel structures located in the bottom layer, the middle layer, and the top layer, respectively, wherein the first bonding region, the second bonding region, and the middle bonding region are located at the center of the channel structure, and the channel layers in the channel structure are electrically connected sequentially.

[0018] In one embodiment, the programmable memory cell includes a gate layer, a memory layer, and a channel layer, wherein when programming the programmable memory cell, a programming voltage is provided to the gate layer to allow electrons in the channel layer to enter the memory layer.

[0019] This application also provides a peripheral circuit for a memory. The peripheral circuit is configured to perform the programming operation method described above.

[0020] This application also provides a memory. The memory includes: a first semiconductor structure including a memory block having a plurality of memory strings, each memory string including an array common source, a bottom layer, a middle layer, a top layer, and a bit line sequentially connected in series along a predetermined direction; and peripheral circuitry electrically connected to the first semiconductor structure, the peripheral circuitry being configured to perform the above-described programming operation method.

[0021] This application also provides a storage system, including: at least one of the above-described memory; and a controller for controlling the memory to perform the above-described programming operation method.

[0022] The memory programming operation method and memory provided according to one or more embodiments of this application may have at least one of the following advantages:

[0023] 1) Providing a first voltage to the common source and bit line of the array can cause electrons in the channel to migrate to the common source end and bit line end of the array, respectively, which helps to reduce the charge concentration in the channel;

[0024] 2) Providing a second voltage to the programmed memory cell can turn on the channel in the programmed memory cell, thereby facilitating the migration of electrons in the channel to the common source terminals and bit line terminals of the array, respectively; and

[0025] 3) Setting the programmed memory cell in at least one of the middle level and the top level, and performing programming operations on the middle memory cell to be programmed in the middle level, is beneficial to realize reverse programming (i.e., programming from the memory cell in the top level and gradually programming to the memory cell in the bottom level), which is beneficial to reduce the interference of the conduction voltage of the memory cell in the bottom level, and thus improves the storage characteristics. Attached Figure Description

[0026] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0027] Figure 1A This is a schematic diagram of the structure of a memory according to an exemplary embodiment of this application;

[0028] Figure 1B This is an enlarged view of a storage unit according to an exemplary embodiment of this application;

[0029] Figure 2 This is a flowchart of a method for programming a memory according to an exemplary embodiment of this application;

[0030] Figure 3 This is a schematic diagram of a memory programming operation method according to an exemplary embodiment of this application;

[0031] Figure 4 This is a schematic diagram of a memory programming operation method according to another exemplary embodiment of this application;

[0032] Figure 5 This is a schematic diagram of a memory programming operation method according to another exemplary embodiment of this application;

[0033] Figure 6 This is a schematic block diagram of a memory according to another exemplary embodiment of this application; and

[0034] Figure 7 This is a schematic block diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0035] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first voltage discussed herein may also be referred to as the second voltage, and vice versa.

[0037] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0038] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0039] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0040] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0041] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0042] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0043] Figure 1A This is a schematic diagram of the structure of a memory 1000 according to an exemplary embodiment of this application.

[0044] The memory 1000 may be, for example, a three-dimensional memory. The memory 1000 may sequentially include an array common source (not shown), a bottom layer 100, a middle layer 200, a top layer 300, and bit lines (not shown) along a predetermined direction X. The array common source, bottom layer 100, middle layer 200, top layer 300, and bit lines may be connected in series.

[0045] In an exemplary embodiment of this application, the memory 1000 may include multiple memory strings and multiple word lines. Each memory string includes a bottom level 100, a middle level 200, and a top level 300 connected in series along a predetermined direction X. Each bottom level 100, middle level 200, and top level 300 includes at least one memory cell. Each word line is connected to a memory cell at the same height in each memory string. Each bit line can connect to one memory string, while the array common source can connect to the entire memory block.

[0046] In an exemplary embodiment of this application, the bottom layer 100 may include a bottom auxiliary unit 110, a bottom memory unit 120, and a first bonding region 130. Exemplarily, the bottom auxiliary unit 110 may include a bottom select transistor 111 and a bottom redundant memory unit 112. The bottom redundant memory unit 112 is adjacent to the bottom select transistor 111 and located on the side of the bottom select transistor 111 away from the array common source. Exemplarily, the bottom memory unit 120 may include a gate layer 1, a memory layer 2, and a channel layer 3. Figure 1B Bottom redundant memory cell 112 and bottom memory cell 120 can be connected to word lines at corresponding heights, respectively. Bottom redundant memory cell 112 is a non-data memory cell that does not meet the conditions for storing user data, while bottom memory cell 120 is a data memory cell that meets the conditions for storing user data. Exemplarily, a first bonding region 130 can be used to electrically connect the bottom layer 100 and the middle layer 200. In an exemplary embodiment of this application, the middle layer 200 may include a plurality of memory cells and a second bonding region 230. During the programming of the memory 1000, it is assumed that a portion of the plurality of memory cells in the middle layer 200 has been programmed, thereby dividing the plurality of memory cells into a middle unprogrammed memory cell 210 and a middle programmed memory cell 220. Exemplarily, the middle unprogrammed memory cell 210 may be adjacent to the middle programmed memory cell 220 and located on the side of the middle programmed memory cell 220 away from the bit line. Both the middle programmable memory cell 210 and the middle programmed memory cell 220 may include a gate layer 1, a memory layer 2, and a channel layer 3. The middle programmable memory cell 210 and the middle programmed memory cell 220 may be connected to word lines at corresponding heights. Both the middle programmable memory cell 210 and the middle programmed memory cell 220 may be data memory cells that meet the conditions for storing user data. Exemplarily, the second bonding region 230 may be used to electrically connect the middle layer 200 and the top layer 300.

[0047] In an exemplary embodiment of this application, the top level 300 may include a plurality of memory cells and a top auxiliary unit 320. During the programming of the memory 1000, it is assumed that all the memory cells of the top level 300 have been programmed. Exemplarily, the top programmed memory cell 310 may include a gate layer, a memory layer, and a channel layer. Exemplarily, the top auxiliary unit 320 may include a top select transistor 321 and a top redundant memory cell 322. The top redundant memory cell 322 may be adjacent to the top select transistor 321 and located on the side of the top select transistor 321 away from the bit line. The top programmed memory cell 310 and the top redundant memory cell 322 may be connected to word lines at corresponding heights. The top redundant memory cell 322 is a non-data memory cell that does not meet the conditions for storing user data, while the top programmed memory cell 310 is a data memory cell that meets the conditions for storing user data.

[0048] In an exemplary embodiment of this application, the first bonding region 130 and the second bonding region 230 may contain a large amount of polysilicon. Specifically, by setting a bottom layer 100, a middle layer 200, and a top layer 300, this application can increase the number of memory layers, thereby increasing the memory capacity. Furthermore, considering the limitations of actual processes, to avoid misalignment issues causing channels between adjacent layers to fail to connect, the memory 1000 provided in this application may contain a large amount of polysilicon in the first bonding region 130 and the second bonding region 230. This facilitates the connection of channels between adjacent layers through the polysilicon in the bonding region. For example, the first bonding region 130 can be used to electrically connect the bottom layer 100 and the middle layer 200, and the second bonding region 230 can be used to electrically connect the middle layer 200 and the top layer 300. Through this arrangement, this application can reduce the alignment requirements between different layers. Even if there is a slight deviation between the channels of adjacent layers, the bonding regions used to electrically connect adjacent layers can still effectively achieve the connection of channels between adjacent layers.

[0049] Figure 2 This is a flowchart of a memory programming operation method 2000 according to an exemplary embodiment of this application.

[0050] like Figure 2 As shown, the memory programming operation method 2000 provided in this application may include: S1, pre-charging for programming operation; and S2, programming the central memory cell 210 to be programmed in the central hierarchy 200. Steps S1 and S2 will be described in detail below.

[0051] Step S1

[0052] like Figure 3As shown, the pre-charge for programming operations may include: providing a first voltage V1 to the array common source and bit lines; and providing a second voltage V2 to the programmed memory cells in the memory to turn on the channels in the programmed memory cells. The programmed memory cells are located in at least one of the middle layer 200 and the top layer 300. In this document, providing voltage to the memory cells and auxiliary cells means providing voltage to the gates of the memory cells and auxiliary cells via word lines.

[0053] For example, a programmed memory cell may include a top programmed memory cell 310 and a middle programmed memory cell 220. Providing a first voltage V1 to the bit line and a second voltage V2 to the top programmed memory cell 310 and the middle programmed memory cell 220 can cause electrons in the memory channel to migrate towards the bit line end, thereby reducing the electron concentration in the channel layer between the middle programmed memory cell 210 and the bit line and clearing residual electrons in the channel layer between the middle programmed memory cell 210 and the bit line.

[0054] For example, providing a first voltage V1 to the array common source can cause electrons in the memory channel to migrate to the array common source end, which can reduce the electron concentration in the channel layer between the middle programmable memory cell 210 and the array common source, and clear residual electrons in the channel layer between the middle programmable memory cell 210 and the array common source.

[0055] For example, the first voltage V1 may be less than the second voltage V2. Both the first voltage V1 and the second voltage V2 can be adjustable voltages; for example, the first voltage V1 can be 1-3V, and the second voltage V2 can be 4-6V. Providing the first voltage V1 to the array common source and the bit line allows electrons in the channel layer of the memory to migrate to the array common source terminal and the bit line terminal, respectively. Providing the second voltage V2 to the programmed memory cell allows the channel in the programmed memory cell to be turned on, thereby preventing the migration of electrons in the channel layer of the memory to the array common source terminal and the bit line terminal from being hindered.

[0056] In an exemplary embodiment of this application, a reverse programming method can be used, that is, programming starts from the memory cells in the top level 300 along the Y direction and gradually programs towards the memory cells in the bottom level 100. Figure 3 Specifically, when programming the memory cells to be programmed in the top layer 300 and the bottom layer 100, a single-sided pre-charge method can be used, that is, providing a first voltage V1 to the array common source to clear the electrons remaining in the channel layer of the memory. When programming the middle memory cell 210 to be programmed in the middle layer 200, a double-sided pre-charge method can be used, that is, providing a first voltage V1 to the bit line and the array common source to clear the electrons remaining in the channel layer of the memory.

[0057] For example, when the middle layer 200 includes a second bonding region 230, the pre-charging for programming operations may further include providing a first voltage V1 to the second bonding region 230. In the actual fabrication process of forming the second bonding region 230, in order to reduce the alignment requirements between adjacent layers, a larger amount of polysilicon can be deposited at the second bonding region 230 to facilitate channel interconnection between adjacent layers. However, when programming memory cells near the second bonding region 230, the presence of a large amount of polysilicon at the second bonding region 230 may cause a large number of electrons to accumulate at the second bonding region 230, which may cause severe programming interference to memory cells near the second bonding region 230. Therefore, during the pre-charging stage of programming operations, by providing the first voltage V1 to the second bonding region 230, the second bonding region 230 can be put into a conductive state, causing electrons at that location to migrate towards the bit line direction, thereby reducing the electron concentration at that location.

[0058] In an exemplary embodiment of this application, the pre-charging process for programming operations may further include providing a first voltage V1 to cells in the memory that have an initial voltage. Exemplarily, the cells with the initial voltage may include at least one of the bottom auxiliary cell 110 in the bottom layer 100 and the top auxiliary cell 320 in the top layer 300. During factory setup, the memory requires the application of a certain voltage value to the bottom auxiliary cell 110 and the top auxiliary cell 320. Therefore, during the pre-charging phase of the programming operation, to enable electrons in the channel to migrate to the bit line terminals and the array common source terminals, respectively, the first voltage V1 may be applied to the bottom auxiliary cell 110 and the top auxiliary cell 320, so that the channel layers in the bottom auxiliary cell 110 and the top auxiliary cell 320 are in a conductive state.

[0059] In an exemplary embodiment of this application, during the pre-charge phase of programming operations, a first voltage V1 can be simultaneously provided to the array common source, bottom auxiliary unit 110, second bonding region 230, top auxiliary unit 320, and bit line, and a second voltage V2 can be provided to the top programmed memory unit 310 and the middle programmed memory unit 220. Specifically, as Figure 3As shown, during the pre-charge phase of programming the middle programmable memory cell 210, a first voltage V1 can be provided to the array common source, the bottom select transistor 111, and the bottom redundant memory cell 112 to allow electrons in the channel layer between the middle programmable memory cell 210 and the array common source 100 to migrate to the array common source terminal. Simultaneously, the first voltage V1 can be provided to the second bonding region 230, the top redundant memory cell 322, the top select transistor 321, and the bit line, and a second voltage V2 can be provided to the top programmed memory cell 310 and the middle programmed memory cell 220 to allow electrons in the channel layer between the middle programmable memory cell 210 and the bit line to migrate to the bit line terminal.

[0060] In an exemplary embodiment of this application, such as Figure 4 As shown, during the pre-charge phase of programming operations, a first voltage V1 can be provided to the second bonding region 230, the top auxiliary cell 320, and the bit line in the first conduction phase t1, and a second voltage V2 can be provided to the top programmed memory cell 310 and the middle programmed memory cell 220; and in the second conduction phase t2 after the first conduction phase t1, the first voltage V1 can be provided to the array common source and the bottom auxiliary cell 110. Specifically, as Figure 4 As shown, during the pre-charge phase of programming the middle programmable memory cell 210, a first voltage V1 can be provided to the array common source, the bottom select transistor 111, and the bottom redundant memory cell 112 in the first conduction phase t1, so that electrons in the channel layer between the middle programmable memory cell 210 and the array common source migrate to the array common source terminal. Then, in the second conduction phase t2, the first voltage V1 can be provided to the second bonding region 230, the top redundant memory cell 322, the top select transistor 321, and the bit line, and a second voltage V2 can be provided to the top programmed memory cell 310 and the middle programmed memory cell 220, so that electrons in the channel layer between the middle programmable memory cell 210 and the bit line migrate to the bit line terminal. Exemplarily, the first conduction phase t1 and the second conduction phase t2 can be spaced 0-10 microseconds apart.

[0061] In an exemplary embodiment of this application, such as Figure 5 As shown, during the pre-charge phase of programming operations, a first voltage V1 is provided to the array common source and bottom auxiliary cell 110 in the first conduction phase t1; and in the second conduction phase t2 after the first conduction phase t1, the first voltage V1 is provided to the second bonding region 230, the top auxiliary cell 320, and the bit line, and a second voltage V2 is provided to the top programmed memory cell 310 and the middle programmed memory cell 220. Specifically, as Figure 5As shown, during the pre-charge phase of programming the middle programmable memory cell 210, a first voltage V1 can be provided to the array common source, the bottom select transistor 111, and the bottom redundant memory cell 112 in the first conduction phase t1, so that electrons in the channel layer between the middle programmable memory cell 210 and the array common source migrate to the array common source terminal. Then, in the second conduction phase t2, the first voltage V1 can be provided to the second bonding region 230, the top redundant memory cell 322, the top select transistor 321, and the bit line, and a second voltage V2 can be provided to the top programmed memory cell 310 and the middle programmed memory cell 220, so that electrons in the channel layer between the middle programmable memory cell 210 and the bit line migrate to the bit line terminal. Exemplarily, the first conduction phase t1 and the second conduction phase t2 can be spaced 0-10 microseconds apart.

[0062] In an exemplary embodiment of this application, the central programmable memory cell 210 may include a plurality of programmable memory cells. Programming the central programmable memory cell 210 may include programming the programmable memory cell from the memory cell closest to the bit line toward the memory cell furthest from the bit line (i.e., along the Y direction). A pre-charge step may be performed before programming each programmable memory cell. Exemplarily, the central hierarchy 200 may include a plurality of sub-central hierarchies connected in series via a central bonding region (not shown). Each of the plurality of sub-central hierarchies may have a plurality of programmable memory cells.

[0063] In an exemplary embodiment of this application, such as Figure 1A As shown, the memory 1000 may include a channel structure 400 located in a bottom layer 100, a middle layer 200, and a top layer 300, respectively. A first bonding region 130, a second bonding region 230, and a middle bonding region (not shown) may be located at the center of the channel structure 400, such that the channel layers in the channel structure 400 are electrically connected in sequence.

[0064] Step S2

[0065] The middle programmable memory cell 210 in the middle layer 200 is programmed. Specifically, when programming the middle programmable memory cell 210, a programming voltage is provided to the gate layer 1 of the middle programmable memory cell 210 to make its storage layer 2 have the required number of electrons.

[0066] For example, after the pre-charge phase of the above programming operation ends, the programming phase of the programming operation can be entered. During the programming phase of this operation, a programming voltage Vpgm can be provided to the gate layer of the currently programmed intermediate memory cell 210 to enable data writing. After programming the currently programmed intermediate memory cell 210 is completed, before programming the next memory cell, step S1 can be re-executed to remove electrons generated in the channel due to the previous programming step.

[0067] This application also provides a memory 3000. Figure 6 This is a schematic block diagram of a memory 3000 according to another exemplary embodiment of this application. Figure 6 As shown, the memory 3000 may include a first semiconductor structure 3100 and peripheral circuitry 3200. The first semiconductor structure 3100 may include at least one memory block 3110 having a plurality of memory strings 3111. Each memory string 3111 includes a bottom layer, a middle layer, and a top layer sequentially connected in series along a predetermined direction. The peripheral circuitry 3200 may be electrically connected to the first semiconductor structure 3100. The peripheral circuitry 3200 may be configured to perform the programming operation method 2000 described above.

[0068] Figure 7 This is a schematic block diagram of a storage system 4000 according to an embodiment of this application. Figure 7 As shown, the storage system 4000 may include at least one memory 4100 and a controller 4200.

[0069] The memory 4100 may be the same as the memory 3000 described in any of the embodiments above, and will not be described again in this application.

[0070] The controller 4200 can control the memory 4100 via channel CH, and the memory 4100 can perform operations based on the control of the controller 4200 in response to requests from the host 5000. The memory 4100 can receive commands CMD and addresses ADDR from the controller 4200 via channel CH and access regions selected from the memory cell array in response to those addresses. In other words, the memory 4100 can perform internal operations corresponding to commands on regions selected by addresses. More specifically, the controller 4200 sends commands and addresses ADDR via channel CH to execute the programming operation method 2000 described in any of the embodiments above, causing the memory 4100 to execute the programming operation method 2000.

[0071] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for programming a memory, wherein the memory sequentially comprises, along a predetermined direction, an array of common source terminals, a bottom layer, a middle layer, a top layer, and bit lines connected in series, the method comprising: Pre-charging for programming operations includes: A first voltage is provided to the array common source and the bit line; and A second voltage is provided to a programmed memory cell in the memory to turn on a channel in the programmed memory cell, wherein the programmed memory cell is located in at least one of the middle level and the top level; and Programming operations are performed on the middle unprogrammed memory cell in the middle hierarchy, wherein the middle unprogrammed memory cell is located on the side of the already programmed memory cell away from the bit line.

2. The programming operation method according to claim 1, characterized in that, The first voltage is less than the second voltage.

3. The programming operation method according to claim 2, characterized in that, The middle layer includes a second bonding region for electrically connecting the middle layer and the top layer, wherein the pre-charging for programming operations further includes: providing the first voltage to the second bonding region; and The programmed storage unit includes: a top programmed storage unit in the top level and a middle programmed storage unit in the middle level.

4. The programming operation method according to claim 3, characterized in that, Pre-charging for programming operations also includes: The first voltage is provided to cells in the memory that have an initial voltage, wherein the cells having an initial voltage include at least one of the bottom auxiliary cells in the bottom layer and the top auxiliary cells in the top layer.

5. The programming operation method according to claim 3, characterized in that, The central unprogrammed storage unit is adjacent to the central programmed storage unit.

6. The programming operation method according to claim 4, characterized in that, The pre-charging steps for performing programming operations include: Simultaneously, the first voltage is provided to the array common source, the bottom auxiliary unit, the second bonding region, the top auxiliary unit, and the bit line, and the second voltage is provided to the top programmed memory unit and the middle programmed memory unit.

7. The programming operation method according to claim 4, characterized in that, The pre-charging steps for performing programming operations include: During the first conduction phase, the first voltage is provided to the second bonding region, the top auxiliary unit, and the bit line, and the second voltage is provided to the top programmed memory unit and the middle programmed memory unit; and In the second conduction phase following the first conduction phase, the first voltage is provided to the array common source and the bottom auxiliary unit.

8. The programming operation method according to claim 4, characterized in that, The pre-charging steps for performing programming operations include: During the first conduction phase, the first voltage is provided to the array common source and the bottom auxiliary unit; and In the second conduction phase following the first conduction phase, the first voltage is provided to the second bonding region, the top auxiliary unit, and the bit line, and the second voltage is provided to the top programmed memory unit and the middle programmed memory unit.

9. The programming operation method according to any one of claims 4-8, characterized in that, The bottom auxiliary unit includes a bottom select transistor and a bottom redundant memory unit, wherein the bottom redundant memory unit is adjacent to the bottom select transistor and located on the side of the bottom select transistor away from the array common source.

10. The programming operation method according to any one of claims 4-8, characterized in that, The top auxiliary unit includes a top select transistor and a top redundant memory unit, wherein the top redundant memory unit is adjacent to the top select transistor and located on the side of the top select transistor away from the bit line.

11. The programming operation method according to claim 10, characterized in that, The top programmed storage cell is adjacent to the top redundant storage cell and is located on the side of the top redundant storage cell away from the bit line.

12. The programming operation method according to any one of claims 4-8, characterized in that, The central programmable storage unit includes multiple programmable storage units, and the programming operation of the central programmable storage unit includes: The programmable memory cells are programmed from the memory cells to be programmed that are close to the bit line toward the memory cells to be programmed, wherein a pre-charge step is performed before programming each memory cell is programmed.

13. The programming operation method according to claim 12, characterized in that, The central hierarchy includes multiple sub-central hierarchies that are connected in series through a central connecting region.

14. The programming operation method according to claim 13, characterized in that, The bottom layer includes a first bonding region for electrically connecting the bottom layer and the middle layer, and The memory includes channel structures located in the bottom layer, the middle layer, and the top layer, respectively, with the first bonding region, the second bonding region, and the middle bonding region located at the center of the channel structure, such that the channel layers in the channel structure are electrically connected sequentially.

15. The programming operation method according to claim 14, characterized in that, The programmable memory cell includes a gate layer, a memory layer, and a channel layer, wherein, When programming the memory cell to be programmed, a programming voltage is provided to the gate layer to allow electrons in the channel layer to enter the memory layer.

16. A peripheral circuit for a memory, characterized in that, The peripheral circuit is configured to perform the programming operation method as described in any one of claims 1 to 15.

17. A memory, characterized in that, The memory includes: A first semiconductor structure includes a memory block having multiple memory strings, each memory string including a bottom layer, a middle layer, and a top layer sequentially connected in series along a predetermined direction; and An external circuit, electrically connected to the first semiconductor structure, is configured to perform the programming operation method according to any one of claims 1 to 15.

18. A storage system, characterized in that, include: At least one memory as described in claim 17; as well as A controller for controlling the memory to perform the programming operation method as described in any one of claims 1 to 15.

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