Method for memory error correction, memory controller, and computer system

Abstract

The present disclosure provides a method for memory error correction, a memory controller and a computer system. The method for memory error correction comprises: determining whether a first memory particle of a memory has a fault; in the case that the first memory particle has the fault, correcting error data in stored data of the first memory particle using a first error correction algorithm to obtain corrected stored data of the first memory particle; and storing the corrected stored data into a second memory particle of the memory using a second error correction algorithm. The method for memory error correction improves the fault tolerance of the memory.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of memory, and more specifically, to a method for memory error correction, a memory controller, and a computer system. Background Technology

[0002] Memory, such as Double Data Rate (DDR) memory, is inevitably subject to interference from environmental factors such as electromagnetic fields during operation, which can lead to errors. For example, for users with high stability requirements, memory errors can cause fatal problems. DDR memory must have advanced reliability, availability, and maintainability (RAS) features to extend the uptime of the entire system in the event of memory errors. Therefore, improving memory fault tolerance is particularly important; otherwise, the system may crash or shut down due to memory errors. Summary of the Invention

[0003] At least one embodiment of this disclosure discloses a method, memory controller, and computer system for memory error correction, which are used to improve the fault tolerance of memory.

[0004] The first aspect of this disclosure provides a method for memory error correction, comprising: determining whether a first memory chip of the memory is faulty; if the first memory chip is faulty, using a first error correction algorithm to correct erroneous data in the stored data of the first memory chip to obtain corrected stored data of the first memory chip; and using a second error correction algorithm to store the corrected stored data in a second memory chip of the memory.

[0005] For example, according to the method provided in the first aspect of this disclosure, storing the corrected storage data into a second memory particle of the memory using the second error correction algorithm further includes: replacing the first error correction algorithm with the second error correction algorithm and generating an error correction code for the second error correction algorithm; storing the error correction code in a third memory particle of the memory; and storing the corrected storage data into the second memory particle.

[0006] For example, according to the method provided in the first aspect of this disclosure, determining whether a first memory chip is faulty includes: determining the number of times a correctable error occurs consecutively in the first memory chip; determining whether the number is greater than or equal to a correctable error threshold; and determining that the first memory chip is faulty in response to the number being greater than or equal to the correctable error threshold.

[0007] For example, according to the method provided in the first aspect of this disclosure, determining the number of times a correctable error occurs consecutively in a first memory chip includes: determining whether a correctable error occurs in a column to which the first memory chip belongs; in response to a correctable error occurring in a column, determining whether correctable errors occur consecutively in the first memory chip; in response to correctable errors occurring consecutively in the first memory chip, counting the number of times correctable errors occur consecutively in the first memory chip; and in response to correctable errors not occurring consecutively in the first memory chip, resetting the count to zero.

[0008] For example, the method provided by the first aspect of this disclosure further includes: receiving write data; and using a second error correction algorithm to write data originally intended to be written to the first memory chip into the second memory chip.

[0009] For example, the method provided by the first aspect of this disclosure further includes: determining whether the read data was written before the fault; and verifying the read data using a first error correction algorithm in response to the fact that the read data was written before the fault.

[0010] For example, the method provided by the first aspect of this disclosure further includes: using a second error correction algorithm to store the verified read data into a second memory chip.

[0011] For example, the method provided according to the first aspect of this disclosure further includes: in response to the read data being written after a fault, verifying the read data using a second error correction algorithm.

[0012] For example, according to the method provided in the first aspect of this disclosure, the first error correction algorithm is the RS algorithm, and the second error correction algorithm is the Hamming code algorithm.

[0013] A second aspect of this disclosure provides a memory controller for a memory, the memory including a first memory chip and a second memory chip. The memory controller includes: a fault determination unit configured to: determine whether a fault exists in the first memory chip; an error correction control unit configured to: in the event that a fault exists in the first memory chip, use a first error correction algorithm to correct erroneous data in the stored data of the first memory chip to obtain corrected stored data of the first memory chip; and use a second error correction algorithm to store the corrected stored data in the second memory chip of the memory.

[0014] For example, according to the memory controller provided in the second aspect of this disclosure, the memory further includes a third memory chip, and the error correction control unit is further configured to: replace the first error correction algorithm with a second error correction algorithm and generate an error correction code of the second error correction algorithm; store the error correction code in the third memory chip; and store the corrected storage data in the second memory chip.

[0015] For example, according to the memory controller provided in the second aspect of this disclosure, the fault determination unit includes: an error count determination unit configured to: determine the number of times a correctable error occurs consecutively in the first memory chip; an error count determination unit configured to: determine whether the count is greater than or equal to a correctable error threshold; and determine that the first memory chip is faulty in response to the count being greater than or equal to the correctable error threshold.

[0016] For example, according to the memory controller provided in the second aspect of this disclosure, the error count determination unit includes: a column error count determination unit configured to: determine whether a correctable error has occurred in the column to which the first memory chip belongs; in response to the occurrence of a correctable error in the column, determine whether the correctable error occurs consecutively in the first memory chip; in response to the consecutive occurrence of correctable errors in the first memory chip, count the number of times the correctable error occurs consecutively in the first memory chip; and in response to the absence of consecutive occurrence of correctable errors in the first memory chip, reset the count to zero.

[0017] For example, according to the memory controller provided in the second aspect of this disclosure, the error correction control unit is further configured to: receive write data; and use a second error correction algorithm to write data originally intended to be written to the first memory chip to the second memory chip.

[0018] For example, according to the memory controller provided in the second aspect of this disclosure, the error correction control unit is further configured to: determine whether read data was written before the fault occurred; and, in response to the read data being written before the fault occurred, verify the read data using a first error correction algorithm.

[0019] For example, according to the memory controller provided in the second aspect of this disclosure, the error correction control unit is further configured to: use a second error correction algorithm to store the verified read data into a second memory chip.

[0020] For example, according to the memory controller provided in the second aspect of this disclosure, the error correction control unit is further configured to: in response to read data being written after a fault, verify the read data using a second error correction algorithm.

[0021] For example, according to the memory controller provided in the second aspect of this disclosure, the first error correction algorithm is the RS algorithm and the second error correction algorithm is the Hamming code algorithm.

[0022] A third aspect of this disclosure provides a computer system comprising: a memory and a memory controller according to at least one embodiment of this disclosure.

[0023] At least one embodiment of this disclosure uses a method that combines a first error correction algorithm and a second error correction algorithm. After determining that a certain memory chip in the memory has failed, there is an algorithm switching behavior, which realizes the combination of the error correction capabilities of the two error correction algorithms, improves the error correction capability of the memory, and improves the fault tolerance capability of the memory. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Clearly, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0025] Figure 1 A flowchart of a method for memory error correction according to at least one embodiment of the present disclosure is shown.

[0026] Figure 2 A schematic diagram of a memory controller according to at least one embodiment of the present disclosure is shown.

[0027] Figure 3 A schematic diagram of the architecture in an exemplary application scenario according to at least one embodiment of the present disclosure is shown.

[0028] Figure 4 At least one embodiment according to the present disclosure is shown. Figure 3 A schematic diagram of the architecture for reading data in an exemplary application scenario.

[0029] Figure 5 At least one embodiment according to the present disclosure is shown. Figure 3 The diagram illustrates the architecture for writing data in an exemplary application scenario.

[0030] Figure 6 A schematic diagram of a computer system according to at least one embodiment of the present disclosure is shown.

[0031] Figure 7 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0032] Figure 8 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown.

[0033] Figure 9 A schematic diagram of a non-transiently readable storage medium according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0034] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0035] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0037] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0038] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0039] For ease of understanding, the relevant terms involved in at least one embodiment of this disclosure will first be explained:

[0040] Correctable Error (CE) refers to errors that hardware (chips) can correct based on their own ECC algorithm. Due to differences in memory controller design, the ability to correct CE errors may vary. For example, in a mainstream x86 server memory controller (supporting ECC-enabled memory modules), any error within a 4-bit data width (x4 width / bit width) memory chip is correctable during a single read operation. If a memory rank consists of 8-bit data width (x8 width / bit width) memory chips, its correction capability remains consistent with that of x4-bit memory chips. In an x8-bit memory chip containing 8 bits of data (DQ0-7), only DQ0-3 or DQ4-7 can be corrected.

[0041] Uncorrectable Error (UCE) refers to errors that hardware (chips) cannot correct based on their own ECC algorithm. For example, in a read operation, if the erroneous data bits are distributed across memory chips of different x4 widths, resulting in an error spanning multiple memory chips, this is considered an uncorrectable error under current memory control designs. Another example is a memory module composed of x8 width memory chips. Its correction capability remains consistent with x4 width memory chips and their positions. Within an x8 width memory chip, if the error location is, for example, DQ2-5, although it is x4 width, its position does not correspond to the x4 width. Error location DQ2-3 corresponds to one x4 bit width, while error location DQ4-5 corresponds to another x4 bit width. In other words, when the error location of a memory chip spans different x4 bit widths, it cannot be corrected. For example, if a memory group consists of memory chips with an X8 width, its correction capability remains consistent with that of memory chips with an X4 width and their positions. In an X8 memory chip, such as DQ0-4, if the faulty bit width (in this case, an X5 bit width) exceeds the correctable bit width (X4), it cannot be corrected.

[0042] At least one embodiment of this disclosure provides a method, memory controller, and computer system for memory error correction, which improves the fault tolerance of memory.

[0043] The following describes in detail, with reference to the accompanying drawings, the method for memory error correction, the memory controller, and the computer system according to embodiments of the present disclosure.

[0044] First, the following describes a method for memory error correction according to embodiments of the present disclosure. This method for memory error correction can be applied to a memory controller, computer system, electronic device, other suitable software or hardware, or a combination of hardware and software for a marked memory, as further described below.

[0045] Figure 1 A flowchart of a method for memory error correction according to at least one embodiment of the present disclosure is shown.

[0046] The method for memory error correction may include steps S102 to S106.

[0047] In step S102, it is determined whether the first memory chip of the memory is faulty.

[0048] The memory can be represented, for example, as a memory module, and may include one or more memory chips. Object data can be read from the memory via read commands. In ECC-enabled memory architectures, object data can be represented as data bits plus checksum information; such object data can also be referred to as an ECC word. The object data can be decoded and error-corrected (if necessary) during a checksum operation to obtain data or instructions for performing calculations to achieve a predetermined function. For example, an ECC algorithm (such as the Reed-Solomon (RS) algorithm) can be used to check the object data to determine whether the object data contains errors, or if errors are included, whether the errors are correctable or uncorrectable. The checksum result can include, for example, information related to correctable errors, such as the location of the correctable errors. The inventors of this disclosure have found that correctable errors can effectively characterize whether a memory chip is faulty; for example, a memory chip having a certain threshold of correctable errors can indicate that the memory chip is faulty. However, the embodiments of this disclosure are not limited to this.

[0049] In step S104, if the first memory chip is faulty, the first error correction algorithm is used to correct the erroneous data in the stored data of the first memory chip, so as to obtain the corrected stored data of the first memory chip.

[0050] If a memory chip is determined to be faulty, the data from the faulty memory chip is read, and errors are corrected using an error correction algorithm to obtain the corrected stored data for that faulty memory chip. This corrected data is considered correct. For example, ECC-enabled memory modules include ECC memory chips, which store error correction codes. When an error exists in an ECC word read from memory, the error correction code can be used to correct the ECC word. In this way, the correction of correctable errors (such as errors in a single memory chip) is achieved using a first error correction algorithm.

[0051] In step S106, the corrected storage data is stored in the second memory chip of the memory using the second error correction algorithm.

[0052] Generally, if a memory chip is found to be faulty, the memory module needs to be replaced to prevent the risk of system crashes or shutdowns caused by correctable errors turning into uncorrectable errors. In this embodiment, after obtaining the corrected storage data from the first memory chip, a new error correction algorithm (second error correction algorithm) can be used to store the corrected storage data in the second memory chip of the memory, thus realizing the operation of new error correction algorithm + memory chip replacement.

[0053] As described above, the method for memory error correction disclosed in at least one embodiment of this disclosure involves correcting the data stored in the faulty memory chip using a first error correction algorithm to obtain the corrected storage data of the faulty memory chip, and then using a second algorithm to store the corrected storage data in another memory chip, thereby combining the error correction capabilities of the two error correction algorithms and improving the fault tolerance capability of the memory.

[0054] In addition, compared to replacing the memory module when a faulty memory chip is detected, the second algorithm provides additional corrective capabilities for the data stored in the memory. Therefore, even if errors occur during subsequent use of the memory, the second algorithm can be used to correct them, thus extending the lifespan of the memory.

[0055] Other aspects of the method for memory error correction according to at least one embodiment of the present disclosure are described in detail below.

[0056] In some embodiments, storing the corrected storage data in a second memory cell of the memory using the second error correction algorithm further includes: replacing the first error correction algorithm with the second error correction algorithm and generating an error correction code for the second error correction algorithm; storing the error correction code in a third memory cell of the memory; and storing the corrected storage data in the second memory cell. The error correction code can be used for encoding, decoding, and error correction of data.

[0057] In this way, the error correction code of the second error correction algorithm can be stored in an additional memory granule, so as to facilitate efficient decoding and error correction when the data stored in the second memory granule is read out later.

[0058] In some embodiments, the second and third memory chips may be ECC memory chips. In some embodiments, at least one of the second and third memory chips may be an ECC memory chip used for the first error correction algorithm. In this way, the number of ECC memory chips can be reduced.

[0059] In some embodiments, determining whether a first memory chip is faulty includes: determining the number of times a correctable error occurs consecutively in the first memory chip; determining whether the number is greater than or equal to a correctable error threshold; and determining that the first memory chip is faulty in response to the number being greater than or equal to the correctable error threshold.

[0060] The inventors of this disclosure realized that memory errors accumulate gradually, and that judging whether a memory chip has consecutive correctable errors and the number of such correctable errors can effectively characterize whether the memory chip has failed.

[0061] In some embodiments, determining the number of times a correctable error occurs consecutively in the first memory chip includes: determining whether a correctable error occurs in the column to which the first memory chip belongs; in response to a correctable error occurring in the column, determining whether correctable errors occur consecutively in the first memory chip; in response to correctable errors occurring consecutively in the first memory chip, counting the number of times correctable errors occur consecutively in the first memory chip; and in response to correctable errors not occurring consecutively in the first memory chip, resetting the count to zero.

[0062] In this way, the number of times a correctable error occurs consecutively in the same position can be determined on a column-by-column basis. That is, the memory chip failure can be determined on a column-by-column basis, which reduces the computational overhead compared to determining whether the memory chip failure is determined on a chip-by-chip basis.

[0063] In some embodiments, the method for memory error correction in at least one embodiment of the present disclosure further includes: receiving write data; and using a second error correction algorithm to write data originally intended to be written to a first memory chip into a second memory chip.

[0064] During the process of writing data to the memory, a portion of the data written to the first memory chip (i.e., the faulty memory chip) is redirected to the second memory chip and stored thereusing a second error correction algorithm. For example, error correction codes can be generated for the written data and stored, for instance, in a third memory chip. In this way, erroneous data is prevented from being written to the faulty memory chip, ensuring reliable storage of the written data, and the second error correction algorithm provides additional error correction capability for the written data.

[0065] In some embodiments, the method for memory error correction in at least one embodiment of this disclosure further includes: determining whether read data was written before the fault occurred; and verifying the read data using a first error correction algorithm in response to the read data being written before the fault occurred.

[0066] After determining that the first memory chip has failed, it can be determined whether the data read from the memory was written before the failure. If the data was written before the failure, i.e., written using the first error correction algorithm, it can be verified using the first error correction algorithm, i.e., the read data is decoded and corrected (if necessary). In this way, data written using the first error correction algorithm can also be read using the first error correction algorithm to obtain the correct read data.

[0067] In some embodiments, the method for memory error correction in at least one embodiment of this disclosure further includes using a second error correction algorithm to store the verified read data into a second memory chip.

[0068] In the above embodiment, after obtaining the correct read data, since it is determined that the memory chip has failed, a new error correction algorithm and memory chip replacement operation are required. Therefore, the second error correction algorithm is used to store the verified read data in the second memory chip to ensure the correctness of the stored data. In subsequent reading processes, if the data is incorrect, the second error correction algorithm can be used to correct it, ensuring reliable data storage and extending the lifespan of the memory.

[0069] In some embodiments, the method for memory error correction according to at least one embodiment of the present disclosure further includes: verifying the read data using a second error correction algorithm in response to the read data being written after a fault.

[0070] If the read data was written after the fault, since the aforementioned new error correction algorithm and memory chip replacement operation are required after the fault, a second error correction algorithm can be used for verification. In this way, data written with the second error correction algorithm can also be read using the same second error correction algorithm to obtain correct read data.

[0071] In some embodiments, the first error correction algorithm is the RS algorithm, and the second error correction algorithm is the Hamming code algorithm.

[0072] The RS algorithm can achieve Single Device Data Correction (SDDC), while the Hamming code algorithm can achieve one-bit data correction. Therefore, combining the RS and Hamming code algorithms can achieve one-bit data correction per memory chip, i.e., SDDC + 1-bit error correction capability. In some cases, memory modules can be configured with two ECC memory chips. Before the operation of replacing the memory chip with a new error correction algorithm, these two ECC memory chips can be used to store the error correction code of the RS algorithm, used for encoding, decoding, and error correction of data based on the RS algorithm. After the operation of replacing the memory chip with a new error correction algorithm, one of the two ECC memory chips can be used to store the corrected data of the faulty memory chip, and the other ECC memory chip can be used to store the error correction code of another Hamming code algorithm, used for encoding, decoding, and error correction of correct data based on the Hamming code algorithm, achieving additional error correction capability.

[0073] To enable those skilled in the art to better understand and implement the embodiments of this disclosure, the following describes the implementation of the above-mentioned embodiments. Figure 1 The method for memory error correction and the memory controller for additional aspects are described in accordance with the accompanying drawings.

[0074] Corresponding to the method for memory error correction provided in at least one embodiment of this disclosure, this disclosure also provides a memory controller.

[0075] Figure 2 A schematic diagram of a memory controller according to at least one embodiment of the present disclosure is shown. See also Figure 2 The memory controller shown can be used to control access to memory, which may include one or more memory chips, such as a first memory chip and a second memory chip.

[0076] Reference Figure 2 The memory controller 200 of the embodiments of this disclosure includes a fault determination unit 210 and an error correction control unit 220.

[0077] The fault determination unit 210 is configured to determine whether the first memory chip is faulty.

[0078] The error correction control unit 220 is configured to, in the event of a fault in the first memory chip, use a first error correction algorithm to correct the erroneous data in the stored data of the first memory chip to obtain the corrected stored data of the first memory chip; and use a second error correction algorithm to store the corrected stored data in the second memory chip of the memory.

[0079] As described above, the memory controller disclosed in at least one embodiment of this disclosure is characterized by correcting the data stored in the faulty memory chip using a first error correction algorithm to obtain the corrected storage data of the faulty memory chip, and then using a second algorithm to store the corrected storage data in another memory chip, thereby combining the error correction capabilities of the two error correction algorithms and improving the fault tolerance capability of the memory.

[0080] In addition, compared to replacing the memory module when a faulty memory chip is detected, the second algorithm provides additional corrective capabilities for the data stored in the memory. Therefore, even if errors occur during subsequent use of the memory, the second algorithm can be used to correct them, thus extending the lifespan of the memory.

[0081] Other aspects of the memory controller of at least one embodiment of the present disclosure are described in detail below.

[0082] In some embodiments, the memory disclosed in at least one embodiment of this disclosure further includes a third memory particle, and the error correction control unit is further configured to: replace the first error correction algorithm with a second error correction algorithm and generate an error correction code of the second error correction algorithm; store the error correction code in the third memory particle; and store the corrected storage data in the second memory particle.

[0083] In some embodiments, the fault determination unit includes: an error count determination unit configured to: determine the number of times a correctable error occurs consecutively in the first memory chip; an error count determination unit configured to: determine whether the number is greater than or equal to a correctable error threshold; and determine that the first memory chip has a fault in response to the number being greater than or equal to the correctable error threshold.

[0084] In some embodiments, the error count determination unit includes: a column error count determination unit, configured to: determine whether a correctable error has occurred in the column to which the first memory chip belongs; in response to the occurrence of a correctable error in the column, determine whether the correctable error occurs consecutively in the first memory chip; in response to the consecutive occurrence of correctable errors in the first memory chip, count the number of times the correctable error occurs consecutively in the first memory chip; and in response to the absence of consecutive occurrence of correctable errors in the first memory chip, reset the count to zero.

[0085] In some embodiments, the error correction control unit is further configured to: receive write data; and use a second error correction algorithm to write the data originally intended to be written to the first memory chip to the second memory chip.

[0086] In some embodiments, the error correction control unit is further configured to: determine whether the read data was written before the fault occurred; and, in response to the read data being written before the fault occurred, verify the read data using a first error correction algorithm.

[0087] In some embodiments, the error correction control unit is further configured to: use a second error correction algorithm to store the verified read data into a second memory chip.

[0088] In some embodiments, the error correction control unit is further configured to: in response to read data being written after a fault, verify the read data using a second error correction algorithm.

[0089] In some embodiments, the first error correction algorithm is the RS algorithm, and the second error correction algorithm is the Hamming code algorithm.

[0090] The above is only based on Figure 2 A portion of a memory controller 200 according to at least one embodiment of the present disclosure has been described, and the remaining portions of the memory controller 200 may be incorporated into the present disclosure. Figure 1 Various aspects of the described method for memory error correction are referenced and incorporated herein by reference. Figure 1 The effects of various aspects of the described method for memory error correction can also be mapped to the memory controller 200 of this disclosure, and will not be repeated here. Furthermore, known parts of the related technology of the memory controller 200 are omitted to avoid obscuring this disclosure.

[0091] The following is through Figures 3 to 5 This describes example application scenarios where the memory error correction method or memory controller provided according to at least one embodiment of the present disclosure can be utilized. It is understood that... Figures 3 to 5 The scenarios shown are merely illustrative and do not exhaustively list all aspects of the methods or memory controllers used for storing error correction, and are combined with... Figures 3 to 5 The description of various aspects and combinations Figure 1 and Figure 2 The various aspects described may be referenced in relation to each other without exceeding the scope of this disclosure.

[0092] Figure 3 A schematic diagram of architecture 300 in an exemplary application scenario according to at least one embodiment of the present disclosure is shown.

[0093] exist Figure 3 In the exemplary application scenario shown in architecture 300, some or all of the memory error correction methods described above can be applied.

[0094] See Figure 3 Architecture 300 may include a data path module 310, a DDR control module 320, and a memory module 330.

[0095] The data path module 310 can be the initiator of read / write data commands. For example, the data path module 310 can initiate read / write data commands via a data path (such as...). Figure 3(As indicated by the arrow in the image) Initiate an access request (e.g., a read or write request) to memory module 330 to read or write data from memory module 330.

[0096] The data path module 310 may include a data scrubbing module 312. The data scrubbing module 312 can periodically read data from the memory module 330 in the background, detect and correct errors in the data read from the memory module 330 in advance to avoid error accumulation, and write the correct data back.

[0097] The DDR control module 320 (e.g., corresponding to the memory controller 20 mentioned above) can control the data path module 310's access to the memory module 330. For example, the DDR control module 320 can parse access requests from the data path module 310, obtain the address corresponding to the access request, and access that address.

[0098] The DDR control module 320 may include a Reed-Solomon code / Hamming (RS / Hamming) ECC error correction module 302 and a multiplexing module 304. The Reed-Solomon code / Hamming ECC error correction module 302 may include ECC error correction modules encoded using the RS algorithm or Hamming code, respectively.

[0099] See Figure 3 The exemplary memory module 330 includes 10 memory chips 331-340. Memory chips 331-338 can be data memory chips, used to store data bits. Memory chips 339-340 can be ECC check memory chips. In this example, one of the ECC check memory chips 339-340 is called a spare memory chip, for example... Figure 3 The spare memory chip 339 shown (e.g., the second memory chip mentioned above) is used to replace the faulty data memory chip (e.g. Figure 3 The memory chip shown in dark gray is 335, while another memory chip is called the parity memory chip, for example... Figure 3 The verification memory chip 340 shown (e.g., the third memory chip mentioned above) is used to store Hamming code values.

[0100] In this application scenario, the RS algorithm corresponds to the first error correction algorithm mentioned above, and the Hamming code algorithm corresponds to the second error correction algorithm. The RS algorithm can implement SDDC, while the Hamming code algorithm can correct one bit of data. Therefore, combining the RS algorithm and the Hamming code algorithm can achieve one bit of data correction per memory granule, i.e., SDDC+1 bit error correction capability. To achieve SDDC+1 bit error correction capability, the following SDDC+1 replacement process is required.

[0101] The SDDC+1 replacement process is described below. Specific circumstances triggering the SDDC+1 replacement process will be explained in conjunction with the following text. Figure 4 and Figure 5 The embodiments are described in detail below.

[0102] When the SDDC+1 replacement process begins, the data scrubbing module 312, located upstream of the data path, initiates a data transfer process. During this process, the data scrubbing module 312 performs read and write operations on all data stored in the memory module 330, copying all data from the faulty memory chip to the spare memory chip 339.

[0103] The following describes the data read and write-back operations in the data transfer process.

[0104] During the data read operation, the data read path remains unchanged, meaning the data path for reading data from the memory module remains constant. After data is read from memory module 330, the CE error of a single chip can be corrected in the Reed-Solomon Code / Hamming ECC error correction module 302 using the initial RS ECC algorithm (also known as the RS algorithm), for example, correcting the CE error of memory chip 335, and recovering all the original data for that memory chip (corresponding to the corrected stored data mentioned above). Here, all the original data includes the data in memory chip 335 that did not contain errors, as well as the corrected data.

[0105] In the data write-back operation, the Hamming ECC algorithm (also known as the Hamming code algorithm) in the Reed-Solomon Code / Hamming ECC error correction module 302 is used to store all the original data of memory chip 335 into spare memory chip 339. For example, the original RS ECC algorithm in the Reed-Solomon Code / Hamming ECC error correction module 302 is replaced with the Hamming ECC algorithm to generate the corresponding ECC check bits (e.g., corresponding to the error correction code mentioned above). For example, the Hamming ECC algorithm can be applied to all the original data of memory chip 335, or data including all the original data of memory chip 335 and all the data in memory chips 331-334 and 336-338, to generate the corresponding ECC check bits. In this example, the ECC check bits can be stored in the check memory chip 340. In addition, while generating the corresponding ECC check bits, the data that was originally to be written to memory chip 335 is imported into spare memory chip 339 through the multiplexing module 304 on the data path.

[0106] In this application scenario, before the SDDC+1 replacement process described above, ECC check memory chips 339-340 can be used to store check bits for the RS algorithm. After the SDDC+1 replacement process described above, ECC check memory chip 339 can store all the original data of the faulty memory chip (i.e., spare memory chip 339), while ECC check memory chip 340 can store the check bits for the Hamming code algorithm (check memory chip 340).

[0107] In this way, in the above SDDC+1 replacement process, all the data in the faulty memory chip is transferred to the spare memory chip after being corrected by the original RS ECC algorithm. It can also be encoded and stored, and even further corrected by the Hamming ECC algorithm, thus realizing the error correction capability of SDDC+1 bits.

[0108] After the SDDC+1 replacement process is completed, both data writing and reading will point to the spare memory chip.

[0109] Understandably, during the data transfer process, it is necessary to pause external services of the memory module, such as the actual application's read and write operations on the memory module.

[0110] The following is combined with Figure 4 and Figure 5 An exemplary architecture for reading and writing operations on memory modules is described.

[0111] Figure 4 At least one embodiment according to the present disclosure is shown. Figure 3 A schematic diagram of the architecture for reading data in an exemplary application scenario.

[0112] See Figure 4 The CE error threshold 402 can be set, for example, through the Basic Input / Output System (BIOS) or other software or hardware methods. The CE error threshold 402 can be a threshold representing the number of times a correctable error occurs consecutively at the same location, indicating the number of times a correctable error can occur at the same location, specifically for memory ( Figure 4 The upper limit for correctable errors (CE errors) occurring consecutively at the same location (as shown in the DDR memory). In this document, correctable errors occurring at the same location are also referred to as fixed CE errors. The location here can include memory chips within the DDR memory, or bit locations within memory chips (i.e., CE errors occurring on a specific DQ).

[0113] The inventors of this disclosure recognized that, in practice, when the number of times a correctable error occurs consecutively at the same position reaches the CE error threshold, it can be considered that the memory chip in the current DDR memory, or even the bit position within the memory chip, has failed, and there is a high probability that it will transition from a correctable error to a UCE error. Of course, other CE error thresholds can also be used to indicate a failure in the memory chip of the DDR memory. For example, the CE error threshold could be a threshold for the total number of correctable errors occurring in the DDR memory, representing the upper limit of the total number of correctable errors occurring for the DDR memory, or the upper limit of the total number of correctable errors occurring within a certain period. As another example, the CE error threshold could be a threshold for the number of consecutive occurrences of correctable errors in the memory, representing the upper limit of the number of consecutive occurrences of correctable errors for the DDR memory. Therefore, when a memory chip failure is determined based on the CE error threshold, triggering the aforementioned SDDC+1 replacement process to achieve SDDC+1 bit error correction capability will reduce the likelihood of UCE errors and system crashes, and extend the lifespan of the DDR memory.

[0114] Alternatively, the SDDC+1 replacement process can be triggered by setting the parameter SDDC_PLUS_en to 404. For example, SDDC_PLUS_en of 1 indicates that the SDDC+1 replacement process is enabled, while SDDC_PLUS_en of 0 indicates that the SDDC+1 replacement process is disabled. The parameter SDDC_PLUS_en provides an additional way to trigger the SDDC+1 replacement process, increasing the flexibility of the system in triggering the SDDC+1 replacement process.

[0115] The following describes the SDDC+1 replacement process triggered based on the CE error threshold.

[0116] The DDR memory 406 can store data and can be accessed based on access requests. In this example, the DDR memory is considered to be DDR5 memory, which has a data width of 32+8 bits (8 x4 data memory chips with a width of 4 bits + 2 x4 ECC check memory chips) and uses the RS algorithm (RS(64,80)) to implement SDDC.

[0117] It is understandable that DDR memory 406 will generally not reach the CE error threshold in the early stages of use (e.g., reading and writing). CE errors are accumulated during use.

[0118] After data is read from DDR memory 406, the CE error threshold determination module 408 can determine whether the CE error has reached the CE error threshold. If it has not reached the threshold ("No" branch), and if the read data does not contain errors, the read data can be decoded via SDDC algorithm module 409 (where an algorithm such as RS can be executed) and the decoded data can be directly output. If the read data contains CE errors, the SDDC algorithm can be used directly to correct the CE errors, and the corrected data can be output. If the read data contains CE errors, the location where the CE error currently occurs is stored (as shown in module 410 in the figure). For example, this location can indicate which memory chip the CE error occurred in (e.g., ...). Figure 3 The location of the CE error can be either the Device or the bit at which the CE error occurred (as shown in the Sym). In some embodiments, the location of the current CE error can be stored in memory or a register. In some embodiments, the location of the current CE error can be stored in a Machine Verification Architecture (MCA) module (also known as an error handling mechanism module).

[0119] When a CE error occurs, the CE error statistics module 411 can collect relevant information about the CE error to generate statistical data. This statistical data corresponds to a CE error threshold, allowing for comparison with the corresponding CE error threshold in comparator 412. In this example, the CE error threshold is the threshold for the number of times a correctable error occurs consecutively in the same position, and the statistical data is the number of times a correctable error occurs consecutively in the same position. In some cases, the CE error threshold can be the threshold for the total number of times a correctable error occurs in the same position, and the statistical data can also be the total number of times a correctable error occurs in the same position.

[0120] The CE error statistics module 411 may include CE_Err_Num_R1 to CE_Err_Num_R4, which are CE counters corresponding to each group. When a CE error occurs consecutively on the same memory chip, the count value of the CE counter can be accumulated (e.g., incremented by 1). When it occurs on a different memory chip, the count value of the CE counter corresponding to the group of the previous memory chip is cleared to zero, and the count value of the CE counter corresponding to the group of the new memory chip is counted as 1. In this way, the number of times a correctable error occurs consecutively at the same location can be determined on a group basis.

[0121] After obtaining the statistics, the statistics and the CE error threshold can be compared in comparator 412. Figure 4Four comparators—Comparator_Rank1 to Comparator_Rank4—are shown, used to compare the current CE_Err_Num_R1 to CE_Err_Num_R4 with the CE error threshold 402, respectively. The comparison results can be sent to the CE error threshold judgment module 408. In the CE error threshold judgment module 408, if it is determined that the number of correctable errors occurring consecutively on the same memory chip within a certain group is greater than or equal to the CE threshold, it means that the number of errors occurring on that memory chip in this group has reached the CE error threshold, and the memory chip in the current memory module (DIMM) (for example, DDR memory 406 can be represented as a memory module) is considered to be faulty.

[0122] If it is determined that the number of correctable errors in a certain group that occur consecutively in the same memory chip is greater than or equal to the CE threshold, the SDDC+1 replacement process 414 can be triggered after the current group corresponding to the memory chip is marked as faulty in the SDDC+1 module 414 (for example, so that the software can query and use it).

[0123] In this example, the memory divides the DDR memory 406 into four groups, using four error counters (CE) and corresponding four comparators to determine if a memory chip in the memory module is faulty. However, the DDR memory can be divided into other numbers of groups, such as one group, two groups, etc., or the faulty memory chip can be determined without using groups as the unit.

[0124] In some cases, when the data read is data written after an SDDC+1 replacement process, it will be retrieved from spare memory chips (e.g., Figure 3 Data is retrieved from the spare memory chip 339 and read using a new algorithm (e.g., the Hamming ECC algorithm). If the data to be read is data written before the aforementioned fault (without the aforementioned SDDC+1 replacement process), since the data to be read was written into the DDR memory without undergoing the aforementioned SDDC+1 replacement process, the previous SDDC algorithm (RS algorithm) can be used for corrective readback, thereby allowing the correct data to be read back.

[0125] Therefore, continue to refer to Figure 4When the CE error threshold judgment module determines that the current group is faulty, the fault handling module 416 can determine whether it is necessary to read data written before the fault. For example, the errflow_rd_en bit can be used to indicate whether the data to be read was written before the fault. errflow_rd_en can be set to 1 to indicate that the data to be read was written before the fault, and errflow_rd_en can be set to 0 to indicate that the data to be read was written after the fault.

[0126] After the correct data is read back, because one of the memory chips has failed, the correct data can be written again using a new algorithm and a spare memory chip.

[0127] In combination Figure 4 In the described data readout architecture, the presence of a faulty memory chip in the DDR memory can be indicated by comparing the CE error information included in the data read from the DDR memory with the CE error threshold. In the event of a fault, the SDDC+1 replacement process is triggered, thus achieving the error correction capability of SDDC+1 bits.

[0128] Figure 5 At least one embodiment according to the present disclosure is shown. Figure 3 The diagram illustrates the architecture for writing data in an exemplary application scenario.

[0129] Figure 5 Zhongyu Figure 4 In the accompanying drawings, the same reference numerals indicate the same or similar content, which will not be repeated here.

[0130] Reference Figure 5 In the CE error threshold judgment module 408, if it is determined that the number of correctable errors occurring consecutively on the same memory chip within a certain group is greater than or equal to the CE threshold ("it's a branch"), it means that the number of errors occurring on that memory chip in this group has reached the CE error threshold, and the memory chip in the current memory module is considered faulty. In this case, in the SDDC+1 module, after marking the current group corresponding to the memory chip as faulty (for example, allowing software to query and use it), the SDDC+1 replacement process 414 can be triggered. Subsequently, during the data writing process, the memory chip that was originally intended to be written to (for example, the memory chip that has the error) is replaced. Figure 3 Data from memory chip 335 in the memory chip is written to a spare memory chip (e.g., memory chip 335). Figure 3 In memory chip 339, the error correction algorithm is switched from RS error correction algorithm to Hamming error correction algorithm, and the check value is written to the check memory chip (e.g., using Hamming code encoding). Figure 3 In the memory chips (340).

[0131] Returning to the CE error threshold judgment module 408, if it is determined that the number of times a correctable error occurs consecutively on the same memory chip within a certain group is less than the CE error threshold ("No" branch), it means that the number of errors occurring on that memory chip in this group has not reached the CE error threshold, and the current memory module is considered to be in good condition and can continue to be used. In this case, the previous SDDC algorithm (such as the RS algorithm) can continue to be used in the SDDC algorithm module 409 to write data to the DDR memory.

[0132] In combination Figure 5 In the described data writing architecture, the presence of a faulty memory chip in the DDR memory can be indicated by comparing the CE error information included in the data read from the DDR memory with the CE error threshold. In the event of a fault, the SDDC+1 replacement process is triggered, thus achieving the error correction capability of SDDC+1 bits.

[0133] Although the above refers to Figure 4 and Figure 5 The described exemplary architecture combines the error correction capabilities of the RS algorithm and the Hamming code algorithm, providing an error correction capability of one memory chip plus 1 bit, thus improving the error correction capability and fault tolerance of DDR memory. Specifically, for groups of memory chips that have already reported errors, data can be recovered, preventing data loss. This exemplary architecture supports the scenario where four groups of x4 memory chips can independently correct and tolerate errors.

[0134] The exemplary architecture based on the above SDDC+1 replacement process can reduce the possibility of UCE errors and crashes, and can extend the lifespan of memory modules.

[0135] Although the above refers to Figure 4 and Figure 5 The modules described, excluding the DDR memory, may correspond to those described in this disclosure. Figure 2 The memory controller 200 described and the reference Figure 3 The DDR controller module 320 is described, and modules 408-412 may be included in the fault determination unit 210 and module 414 may be included in the fault correction unit 220. However, it is understood that the above modules may be combined or separated without departing from the scope of this disclosure.

[0136] Figure 6 A schematic diagram of a computer system according to at least one embodiment of the present disclosure is shown. The computer system 600 may include the memory 610 as described above, and (for example, may include reference) Figure 1 The memory described, see reference Figure 3 The memory module 330 described and referenced Figure 4 The DDR memory 406 shown above) and memory controller 620 (e.g., may include the above-referenced) Figure 2 The memory controller described or referenced Figure 3 The DDR control module 320 is described. In specific application scenarios, refer to... Figure 6 The described computer system 600 may include references Figure 4 and Figure 5 The architecture described, either partially or entirely.

[0137] It is understood that only the main components of computer system 600 are shown here, and computer system 600 may also include other components.

[0138] As described above, corresponding to the memory error correction method and memory controller disclosed according to at least one embodiment of the present disclosure, the computer system disclosed in at least one embodiment of the present disclosure is characterized by correcting the data stored in the faulty memory chip using a first error correction algorithm to obtain the corrected storage data of the faulty memory chip, and then using a second algorithm to store the corrected storage data in another memory chip, thereby combining the error correction capabilities of the two error correction algorithms and improving the fault tolerance capability of the memory.

[0139] In addition, compared to replacing the memory module when a faulty memory chip is detected, the second algorithm provides additional corrective capabilities for the data stored in the memory. Therefore, even if errors occur during subsequent use of the memory, the second algorithm can be used to correct them, thus extending the lifespan of the memory.

[0140] Figure 7 A schematic diagram of an electronic device 700 according to at least one embodiment of the present disclosure is shown. Figure 7 As shown, the electronic device 700 includes a processor 710 and a memory 720.

[0141] The memory 720 includes one or more computer program modules 721. The one or more computer program modules 721 are stored in the memory 720 and configured to be executed by the processor 710. The one or more computer program modules 721 include instructions for performing the memory error correction method provided in at least one embodiment of the present disclosure. When executed by the processor 710, these instructions can perform one or more steps of the memory error correction method and its additional aspects provided in at least one embodiment of the present disclosure. The memory 720 and the processor 710 can be interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0142] For example, processor 710 can be a central processing unit (CPU), a digital signal processor (DSP), or other processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86 or ARM architecture, RISC-V architecture, etc. Processor 710 can be a general-purpose processor or a special-purpose processor, which can control other components in electronic device 700 to perform desired functions.

[0143] For example, memory 720 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 721 may be stored on the computer-readable storage medium, and processor 710 may run one or more computer program modules 721 to implement various functions of electronic device 700. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium. Electronic device 700 may be, for example, a system-on-a-chip (SOC) or a computer, television, monitor, etc., including the SOC. The specific functions and technical effects of electronic device 700 can be referred to the description above regarding the methods for memory error correction and their additional aspects, and will not be repeated here.

[0144] Figure 8 A schematic diagram of another electronic device 800 according to at least one embodiment of the present disclosure is shown. This electronic device 800 is, for example, adapted to implement the method for memory error correction and its additional aspects provided by at least one embodiment of the present disclosure. It should be noted that... Figure 8 The illustrated electronic device 800 is merely an example and does not impose any limitation on the functionality and scope of use of at least one embodiment of this disclosure.

[0145] like Figure 8As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 810, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 into a random access memory (RAM) 830. The RAM 830 may also store various programs and data required for the operation of the electronic device 800. The processing device 810, ROM 820, and RAM 830 are interconnected via a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0146] Typically, the following devices can be connected to I / O interface 850: input devices 860 such as touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 870 such as liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 880 such as magnetic tapes, hard disks, etc.; and communication devices 890. Communication device 890 allows electronic device 800 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although... Figure 8 An electronic device 800 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 800 may alternatively implement or have more or fewer devices.

[0147] For example, the memory error correction method and its additional aspects provided in at least one embodiment of this disclosure can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the aforementioned memory error correction method and its additional aspects. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 890, or installed from a storage device 880, or installed from a ROM 820. When the computer program is executed by a processing device 810, the memory error correction method and its additional aspects provided in at least one embodiment of this disclosure can be performed.

[0148] At least one embodiment of this disclosure also provides a non-transiently readable storage medium. Figure 9 A schematic diagram of a non-transitory readable storage medium 900 according to at least one embodiment of the present disclosure is shown. Figure 9 As shown, a non-transiently readable storage medium 900 stores computer instructions 910, which, when executed by a processor, perform one or more steps of the memory error correction method and its additional aspects as described above.

[0149] For example, the non-transiently readable storage medium 900 can be any combination of one or more computer-readable storage media. For instance, one computer-readable storage medium contains computer-readable program code for determining whether a first memory chip of the memory is faulty, another computer-readable storage medium contains computer-readable program code for correcting erroneous data in the stored data of the first memory chip using a first error correction algorithm in the event of a fault in the first memory chip, thereby obtaining corrected stored data of the first memory chip, and yet another computer-readable storage medium contains computer-readable program code for storing the corrected stored data into a second memory chip of the memory using a second error correction algorithm.

[0150] Of course, the various program codes described above can also be stored in the same computer-readable medium, and the embodiments of this disclosure do not limit this.

[0151] For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium, performing, for example, the memory error correction method and its additional aspects provided in any embodiment of this disclosure.

[0152] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard disk for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media.

[0153] It is understood that the block diagrams herein may represent conceptual diagrams of illustrative circuit systems or other functional units embodying the principles of the described embodiments. Similarly, it is understood that any flowchart, etc., represents various processes that may be substantially represented in a computer-readable storage medium and executed by a computer or processor, whether or not such a computer or processor is explicitly shown. The functionality of the various elements comprising the functional blocks may be provided using hardware, such as circuit hardware and / or hardware capable of executing software in the form of coded instructions stored on the aforementioned computer-readable storage medium. Therefore, such functionality and the illustrated functional blocks will be understood as hardware-implemented and / or computer-implemented, and thus machine-implemented. In terms of hardware implementation, functional blocks may include or encompass, but are not limited to, digital signal processor (DSP) hardware, reduced instruction set processors, hardware (e.g., digital or analog) circuit systems, including but not limited to application-specific integrated circuits (ASICs) and / or field-programmable gate arrays (FPGAs), and (where appropriate) state machines capable of performing these functions.

[0154] In terms of computer implementation, a computer is generally understood to include one or more processors or one or more controllers. When provided by a computer, processor, or controller, functionality may be provided by a single dedicated computer, processor, or controller, a single shared computer, processor, or controller, or multiple separate computers, processors, or controllers, some of which may be shared or distributed.

[0155] The various embodiments in this disclosure are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0156] In the several embodiments provided in this disclosure, it should be understood that each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks / operations may occur in a different order than those indicated in the figures. For example, two consecutive blocks / operations may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block / operation in the block diagrams and / or flowcharts, and combinations of blocks / operations in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0157] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0158] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art.

Claims

1. A method for memory error correction, comprising: determining whether a first memory die of a memory has a fault; in a case where the first memory die has the fault, correcting erroneous data in stored data of the first memory die using a first error correction algorithm to obtain corrected stored data of the first memory die; and storing the corrected stored data into a second memory die of the memory using a second error correction algorithm, wherein the second memory die is a check memory die of the memory, all check memory dies of the memory are used for the first error correction algorithm, and remaining check memory dies of the memory except the second memory die are used for the second error correction algorithm. Storing the corrected stored data into the second memory die using the second error correction algorithm further comprises:

2. The method of claim 1, wherein, replacing the first error correction algorithm with the second error correction algorithm, and generating error correction encoding of the second error correction algorithm; storing the error correction encoding in a third memory die of the memory; and storing the corrected stored data into the second memory die. Determining whether the first memory die has the fault comprises:

3. The method of claim 1, wherein, determining a number of times that a correctable error continuously occurs in the first memory die; determining whether the number is greater than or equal to a correctable error threshold; and in response to the number being greater than or equal to the correctable error threshold, determining that the first memory die has the fault. Determining the number of times that the correctable error continuously occurs in the first memory die comprises:

4. The method of claim 3, wherein, determining whether a column to which the first memory die belongs has the correctable error; in response to the column having the correctable error, determining whether the correctable error continuously occurs in the first memory die; in response to the correctable error continuously occurring in the first memory die, counting the number of times that the correctable error continuously occurs in the first memory die; and in response to the correctable error not continuously occurring in the first memory die, zeroing the count.

5. The method of claim 1, further comprising: receiving write data; storing data of the write data that is originally intended to be written into the first memory die into the second memory die using the second error correction algorithm.

6. The method of claim 1, further comprising: determining whether readout data is written before the fault; in response to the readout data being written before the fault, checking the readout data using the first error correction algorithm.

7. The method of claim 6, further comprising: storing the checked readout data into the second memory die using the second error correction algorithm.

8. The method of claim 6, further comprising: in response to the readout data being written after the fault, checking the readout data using the second error correction algorithm. The first error correction algorithm is an RS algorithm, and the second error correction algorithm is a Hamming code algorithm.

9. The method of any one of claims 1-8, wherein, 10. A memory controller for a memory, the memory comprising a first memory die and a second memory die, the memory controller comprising: ​ a fault determination unit configured to determine whether the first memory grain has a fault; and an error correction control unit configured to: in a case where the first memory grain has a fault, correct error data in stored data of the first memory grain using a first error correction algorithm to obtain corrected stored data of the first memory grain, and store the corrected stored data into a second memory grain of the memory using a second error correction algorithm, wherein the second memory grain is a check memory grain of the memory, all check memory grains of the memory are used for the first error correction algorithm, and remaining check memory grains of the memory except the second memory grain are used for the second error correction algorithm.

11. The memory controller of claim 10, wherein, the memory further comprises a third memory grain, and the error correction control unit is further configured to: replace the first error correction algorithm with the second error correction algorithm, and generate error correction coding of the second error correction algorithm, and store the error correction coding in the third memory grain; and store the corrected stored data into the second memory grain.

12. The memory controller of claim 10, wherein, the fault determination unit comprises: an error number determination unit configured to determine a number of times that a correctable error continuously occurs in the first memory grain; an error number determination unit configured to: determine whether the number is greater than or equal to a correctable error threshold, and in response to the number being greater than or equal to the correctable error threshold, determine that the first memory grain has a fault.

13. The memory controller of claim 12, wherein, the error number determination unit comprises: a column error number determination unit configured to: determine whether a column to which the first memory grain belongs has the correctable error; in response to the column having the correctable error, determine whether the correctable error continuously occurs in the first memory grain; in response to the correctable error continuously occurring in the first memory grain, count the number of times that the correctable error continuously occurs in the first memory grain; and in response to the correctable error not continuously occurring in the first memory grain, reset the count to zero.

14. The memory controller of claim 10, the error correction control unit is further configured to: receive write data; and write data originally intended to be written into the first memory grain in the write data into the second memory grain using the second error correction algorithm.

15. The memory controller of claim 10, the error correction control unit is further configured to: determine whether readout data is written before the fault; in response to the readout data being written before the fault, check the readout data using the first error correction algorithm.

16. The memory controller of claim 15, the error correction control unit is further configured to: store the checked readout data into the second memory grain using the second error correction algorithm.

17. The memory controller of claim 15, the error correction control unit is further configured to: in response to the readout data being written after the fault, check the readout data using the second error correction algorithm.

18. The memory controller of any one of claims 10-17, wherein, The first error correction algorithm is an RS algorithm and the second error correction algorithm is a Hamming code algorithm.

19. A computer system comprising: The memory controller of any of claims 10-18; and The memory.

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