A low-voltage high-efficiency gallium nitride power device and a manufacturing method thereof

Abstract

The application discloses a kind of low-voltage high-efficiency gallium nitride power devices and its manufacturing method, method includes: obtaining epitaxial wafer;Epitaxial wafer is electrically isolated;Cap layer is lithographed on source, drain electrode area, and ohmic metal is formed in source electrode, drain electrode by using secondary epitaxy technology and patterned etching technology in source, drain electrode area growth;Passivation layer is grown on source electrode, drain electrode and cap layer;Recess area is lithographed on passivation layer, and passivation layer in recess area is etched until recess is formed by reaching preset position;Gate dielectric layer is grown in recess;Gate electrode area is lithographed on passivation layer and above recess, and T-shaped gate electrode is formed by growing gate metal on passivation layer in gate electrode area and gate dielectric layer in recess;Passivation layer on source electrode, drain electrode is etched until source electrode, drain electrode, respectively, and interconnection electrode is grown on source electrode, drain electrode and T-shaped gate electrode.The application reduces the power consumption of device, improves the power characteristics of device.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a low-voltage, high-efficiency gallium nitride power device and its fabrication method. Background Technology

[0002] With the advancement of science and technology and social development, first- and second-generation semiconductor materials can no longer meet the demands of higher-frequency and higher-power electronic devices. Due to its wide bandgap, high electron saturation velocity, high breakdown field strength, high thermal conductivity, and high electron mobility, GaN-based devices have wide applications in high-temperature, high-frequency, and microwave power devices. These devices have become a key focus of research.

[0003] Based on their threshold voltage, GaN-based high electron mobility transistors (HEMTs) can be divided into two categories: One is the traditional depletion-mode GaN-based HEMT, which remains on even without a gate bias and requires a negative gate voltage (Vth < 0) to turn off. Therefore, conventional GaN-based HEMTs are depletion-mode, also known as normally-on. The other is the enhancement-mode GaN-based HEMT, which is the opposite of depletion-mode devices. These devices have a positive turn-on voltage (Vth > 0), simplifying RF / microwave circuits and preventing power electronic device failures. More importantly, when combined with depletion-mode devices, they can form direct-coupled field-effect transistor (DCFL) digital circuits, greatly expanding the application range of GaN-based HEMTs. Currently, low-voltage, high-efficiency gallium nitride (GaN) power devices are widely used in the RF field and as low-voltage, high-efficiency power switching devices. Currently, the most common low-voltage, high-efficiency gallium nitride (GaN) RF power devices are those based on grooved gate structures. These devices feature low leakage current, high saturation current, and gate length that can be controlled through etching processes to ensure device stability. Ohmic annealing is commonly used in the fabrication of the ohmic contacts for the source and drain electrodes.

[0004] However, contact resistance is a very important parameter for RF power devices with grooved gate structures. Currently, conventional ohmic annealing technology requires constant adjustment of annealing temperature and time for different barrier materials and cap thicknesses, making contact resistance difficult to control. This results in poor operating stability and short lifespan of the power devices. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a low-voltage, high-efficiency gallium nitride power device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a method for fabricating a low-voltage, high-efficiency gallium nitride power device, comprising:

[0007] Obtain an epitaxial substrate; wherein, from bottom to top, the epitaxial substrate comprises a substrate layer, a nucleation layer, a buffer layer, an insertion layer, a barrier layer, and a cap layer;

[0008] Electrical isolation of the active region is formed on the epitaxial substrate;

[0009] The source electrode region and the drain electrode region are photolithographically etched on the cap layer. Ohmic metal is grown in the source electrode region and the drain electrode region to form the source electrode and the drain electrode, respectively, using secondary epitaxial technology and patterning etching technology.

[0010] A passivation layer is grown on the source electrode, the drain electrode, and the cap layer;

[0011] A groove region is photolithographically formed on the passivation layer, and the passivation layer within the groove region is etched until a groove is formed at a predetermined position;

[0012] A gate dielectric layer is grown within the groove;

[0013] A gate electrode region is photolithographically formed on the passivation layer and above the groove, and a gate metal is grown on the passivation layer within the gate electrode region and on the gate dielectric layer within the groove to form a T-shaped gate electrode;

[0014] The passivation layers on the source electrode and the drain electrode are etched down to the source electrode and the drain electrode, and interconnect electrodes are grown on the source electrode, the drain electrode and the T-type gate electrode, respectively.

[0015] In one embodiment of the present invention, the electrical isolation of forming an active region on the epitaxial substrate includes:

[0016] An electrically isolated region is photolithographically formed on the cap layer;

[0017] The cap layer, the barrier layer, the insertion layer, and a portion of the buffer layer of the electrically isolated region are sequentially etched using an ICP etching process to form electrical isolation of the active region; wherein the etching depth is 140nm to 150nm.

[0018] In one embodiment of the present invention, the electrical isolation of forming an active region on the epitaxial substrate includes:

[0019] An electrically isolated region is photolithographically formed on the cap layer;

[0020] N ions are sequentially implanted into the cap layer, the barrier layer, the insertion layer, and up to a portion of the buffer layer of the electrically isolated region using an ion implantation process to form an electrically isolated active region; wherein the implantation depth is 110 nm to 120 nm.

[0021] In one embodiment of the present invention, the step of growing ohmic metal in the source electrode region and the drain electrode region to form the source electrode and drain electrode using secondary epitaxial technology and patterned etching technology, respectively, includes:

[0022] A mask layer is grown on the cap layer;

[0023] The source electrode region and the drain electrode region are photolithographically etched on the mask layer;

[0024] Etch the mask layer within the source electrode region and the drain electrode region until a portion of the buffer layer is reached;

[0025] An N+GaN epitaxial layer is grown on the buffer layer and the mask layer;

[0026] The mask layer and the N+GaN epitaxial layer on the cap layer are removed by wet etching.

[0027] An ohmic patterned region is photolithographically etched on the N+GaN epitaxial layer;

[0028] Etching a portion of the N+GaN epitaxial layer within the ohmic patterned region forms an array of ohmic contact trenches;

[0029] Ohmic metal is deposited on the N+GaN epitaxial layer and in each ohmic contact trench in the ohmic contact trench array to form the source electrode and the drain electrode.

[0030] In one embodiment of the present invention, etching the passivation layer in the groove region until a preset position is formed to form a groove includes:

[0031] Using the first etching process conditions, the passivation layer in the groove area is etched up to the upper surface of the barrier layer;

[0032] Using the second etching process conditions, a portion of the barrier layer within the groove region is further etched; wherein the etching depth within the barrier layer is the first etching depth, and the first etching depth is at most 1 / 2 of the thickness of the barrier layer;

[0033] Using a third etching process, a portion of the barrier layer within the groove region is etched to form the groove; wherein the etching depth within the barrier layer is a second etching depth, and the second etching depth is 1 / 4 of the first etching depth.

[0034] In one embodiment of the present invention, etching the passivation layer in the groove region until a preset position is formed to form a groove includes:

[0035] Using the fourth etching process conditions, the passivation layer in the groove area is etched up to the upper surface of the barrier layer;

[0036] Using the fifth etching process conditions, the barrier layer in the groove area is etched until the groove is formed on the upper surface of the buffer layer.

[0037] In one embodiment of the present invention, the step of growing a gate dielectric layer in the groove includes:

[0038] Using a plasma-enhanced atomic layer deposition (PEALD) apparatus, a gate dielectric layer with a thickness of 2 nm to 7 nm is formed in situ within the groove by thermal oxidation at a temperature of 250 °C to 300 °C.

[0039] In one embodiment of the present invention, the step of growing a gate dielectric layer in the groove includes:

[0040] Using an atomic layer deposition apparatus, a gate dielectric layer with a thickness of 1 nm to 10 nm is grown in the groove at a temperature of 250 °C to 300 °C.

[0041] Secondly, embodiments of the present invention provide a low-voltage, high-efficiency gallium nitride power device, comprising:

[0042] Epitaxial substrate; wherein, from bottom to top, the epitaxial substrate comprises a substrate layer, a nucleation layer, a buffer layer, an insertion layer, a barrier layer, and a cap layer;

[0043] The source electrode and the drain electrode are located at both ends of the buffer layer that penetrates the cap layer, the barrier layer and the insertion layer; wherein, an N+GaN epitaxial layer is respectively disposed between the source electrode and the drain electrode and the buffer layer, and an ohmic contact trench array is disposed in the N+GaN epitaxial layer, and each ohmic contact trench in the ohmic contact trench array is filled with ohmic metal.

[0044] A passivation layer is located on the source electrode, the drain electrode, and the cap layer;

[0045] The T-shaped gate electrode includes a first part and a second part flush with the first part; the first part is located in the barrier layer that penetrates the middle position of the passivation layer and the cap layer; the second part is located on both sides of the first part and embedded in the passivation layer; wherein, a gate dielectric layer is further disposed between the first part and the barrier layer;

[0046] Interconnect electrodes are located on the source electrode and the drain electrode, which penetrate the passivation layer, and on the T-type gate electrode.

[0047] Thirdly, embodiments of the present invention provide a low-voltage, high-efficiency gallium nitride power device, comprising:

[0048] Epitaxial substrate; wherein, from bottom to top, the epitaxial substrate comprises a substrate layer, a nucleation layer, a buffer layer, an insertion layer, a barrier layer, and a cap layer;

[0049] The source electrode and the drain electrode are located at both ends of the buffer layer that penetrates the cap layer, the barrier layer and the insertion layer; wherein, an N+GaN epitaxial layer is respectively disposed between the source electrode and the drain electrode and the buffer layer, and an ohmic contact trench array is disposed in the N+GaN epitaxial layer, and each ohmic contact trench in the ohmic contact trench array is filled with ohmic metal.

[0050] A passivation layer is located on the source electrode, the drain electrode, and the cap layer;

[0051] The T-shaped gate electrode includes a first part and a second part flush with the first part. The first part is located on the buffer layer that penetrates the passivation layer, the cap layer, the barrier layer and the insertion layer. The second part is located on both sides of the first part and embedded in the passivation layer. A gate dielectric layer is also disposed between the first part and the buffer layer.

[0052] Interconnect electrodes are located on the source electrode and the drain electrode, which penetrate the passivation layer, and on the T-type gate electrode.

[0053] The beneficial effects of this invention are:

[0054] The method for fabricating low-voltage, high-efficiency gallium nitride power devices proposed in this invention employs a secondary epitaxial layer to generate an epitaxial layer during the fabrication of ohmic contacts. This epitaxial layer forms an ohmic contact with an ohmic metal. Simultaneously, combined with ohmic patterning etching, the contact area of ​​the ohmic metal is increased, thereby reducing the ohmic contact resistance, lowering parasitic capacitance, reducing device power consumption, and improving device frequency characteristics.

[0055] The reliability of existing gallium nitride power devices can be improved by the fabrication method of this invention, which is of great significance for the fabrication of various low-voltage, high-efficiency gallium nitride power devices and has broad prospects for low-voltage, high-efficiency applications.

[0056] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of a method for fabricating a low-voltage, high-efficiency gallium nitride power device according to an embodiment of the present invention;

[0058] Figures 2(a) to 2(o)This is a schematic diagram of the structure corresponding to the fabrication process of the low-voltage, high-efficiency gallium nitride power device provided in the embodiments of the present invention;

[0059] Figure 3 This is a schematic diagram of the structure corresponding to the electrical isolation achieved by ion implantation process provided in the embodiments of the present invention;

[0060] Figure 4 This is a schematic diagram of another groove etching structure provided in an embodiment of the present invention;

[0061] Figure 5 This is a schematic diagram of the structure of a low-voltage, high-efficiency gallium nitride power device provided in an embodiment of the present invention;

[0062] Figure 6 This is a schematic diagram of another low-voltage, high-efficiency gallium nitride power device provided in an embodiment of the present invention.

[0063] Explanation of reference numerals in the attached figures:

[0064] 1-Substrate layer; 2-Nucleation layer; 3-Buffer layer; 4-Insertion layer; 5-Barrier layer; 6-Cap layer; 7-Source electrode; 8-Drain electrode; 9-N+GaN epitaxial layer; 10-Passivation layer; 11-Gate dielectric layer; 12-T-type gate electrode; 13-Interconnect electrode; 14-Mask layer. Detailed Implementation

[0065] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0066] Example 1

[0067] To reduce power consumption and improve power characteristics, this invention provides a low-voltage, high-efficiency gallium nitride power device and its fabrication method.

[0068] Firstly, please see Figure 1 This invention provides a method for fabricating a low-voltage, high-efficiency gallium nitride power device, comprising the following steps:

[0069] S10. Obtain an epitaxial substrate; wherein, the epitaxial substrate includes, from bottom to top, a substrate layer 1, a nucleation layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5, and a cap layer 6.

[0070] Specifically, referring to Figure 2(a), the epitaxial substrate selected in this embodiment of the invention includes, from bottom to top, a substrate layer 1, a nucleation layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5, and a cap layer 6. This epitaxial substrate can be an existing integrated epitaxial substrate, or it can be fabricated using a metal-organic chemical vapor deposition (MOCVD) process to sequentially grow the nucleation layer 2, buffer layer 3, insertion layer 4, barrier layer 5, and cap layer 6 on the substrate layer 1.

[0071] Preferably, the substrate layer 1 comprises sapphire, SiC, or Si with a thickness of 400 μm to 500 μm; the nucleation layer 2 comprises AlN with a thickness of 160 nm to 180 nm; the buffer layer 3 comprises GaN with a thickness of 1.3 μm to 2 μm; the insertion layer 4 comprises AlN with a thickness of 0 to 1 nm; the barrier layer 5 comprises AlGaN, AlN, InAlN, ScAlN, or InAlGaN with a thickness of 3 nm to 20 nm; and the cap layer 6 comprises GaN with a thickness of 2 nm to 6 nm.

[0072] S20. Electrical isolation of the active region is formed on the epitaxial substrate.

[0073] Specifically, referring to Figure 2(b), this embodiment of the invention provides an optional solution for forming an active region with electrical isolation on an epitaxial substrate, including:

[0074] S201, Photolithography is performed on the cap layer 6 to create an electrical isolation region.

[0075] Specifically, first, the sample is baked on a hot plate at 200°C for 5 minutes; then, photoresist is applied and spun at a speed of 3500 rpm, and the sample is baked on a hot plate at 90°C for 1 minute; next, the sample is placed in a lithography machine to expose the photoresist in the electrically isolated area; finally, the exposed sample is placed in a developing solution to remove the photoresist in the electrically isolated area, and then rinsed with ultrapure water and dried with nitrogen.

[0076] S202. Using ICP etching process, the cap layer 6, barrier layer 5, insertion layer 4 and up to part of the buffer layer 3 of the electrically isolated region are etched sequentially to form the electrical isolation of the active region; wherein the etching depth is 140nm to 150nm.

[0077] Specifically, firstly, the cap layer 6, barrier layer 5, insertion layer 4, and part of the buffer layer 3 of the electrically isolated region are sequentially etched using inductively coupled plasma (ICP) technology to achieve mesa isolation of the active region, with a total etching depth of 140 nm to 150 nm. Then, the sample is sequentially cleaned in acetone solution, stripping solution, acetone solution, and ethanol solution to remove the photoresist outside the electrically isolated region. Finally, the sample is rinsed with ultrapure water and dried with nitrogen gas.

[0078] Please see Figure 3 The present invention provides another optional solution, which involves forming an active region with electrical isolation on an epitaxial substrate, including:

[0079] S20-1, Photolithography is performed on the cap layer 6 to create an electrical isolation region.

[0080] Specifically, the sample is first baked on a hot plate at 200°C for 5 minutes; then the photoresist is coated and spun to a thickness of 2 μm, and the sample is baked on a hot plate at 90°C for 1 minute; next, the sample is placed in a lithography machine to expose the photoresist in the electrically isolated area; finally, the exposed sample is placed in a developing solution to remove the photoresist in the electrically isolated area, and then rinsed with ultrapure water and dried with nitrogen.

[0081] S20-2. Using an ion implantation process, N ions are sequentially implanted into the cap layer 6, barrier layer 5, insertion layer 4, and up to part of the buffer layer 3 of the electrically isolated region to form an electrically isolated active region; wherein the implantation depth is 110nm to 120nm.

[0082] Specifically, firstly, N ions are sequentially implanted into the cap layer 6, barrier layer 5, insertion layer 4, and part of the buffer layer 3 of the electrically isolated region using an ion implantation process to achieve electrical isolation of the active region, with a total implantation depth of 110 nm to 120 nm. Then, the sample is sequentially cleaned in acetone solution, stripping solution, acetone solution, and ethanol solution to remove the photoresist outside the electrically isolated region. Finally, the sample is rinsed with ultrapure water and dried with nitrogen gas.

[0083] S30. Photolithography is performed on the cap layer 6 to form the source electrode region and the drain electrode region. Ohmic metal is grown in the source electrode region and the drain electrode region to form the source electrode 7 and the drain electrode 8, respectively, using secondary epitaxial technology and patterned etching technology.

[0084] Specifically, embodiments of the present invention provide an optional solution, including:

[0085] S301. A mask layer 14 is grown on the cap layer 6.

[0086] Specifically, please refer to Figure 2(c). The sample is placed in a plasma-enhanced chemical vapor deposition (PECVD) apparatus to grow mask layer 14. The growth process conditions are as follows: O2 and SiH4 are used as reaction gases, the substrate temperature is 250°C, the reaction chamber pressure is 600 mTorr, and the RF power is 44 W.

[0087] Preferably, the mask layer 14 comprises SiO2 with a thickness of 150 nm to 200 nm.

[0088] S302, Photolithography is performed on the mask layer 14 to create the source electrode region and the drain electrode region.

[0089] Specifically, firstly, the sample is baked on a hot plate at 200°C for 5 minutes; then, a release agent is coated and spun onto the mask layer 14, with a spun-off thickness of 0.35 μm, and the sample is baked on a hot plate at 200°C for 5 minutes; next, photoresist is coated and spun onto the release agent, with a spun-off thickness of 0.77 μm, and the sample is baked on a hot plate at 90°C for 1 minute; after that, the sample with the coating and spun-off completed is placed in a lithography machine to expose the photoresist in the source electrode region and the drain electrode region; finally, the exposed sample is placed in a developing solution to remove the photoresist and release agent in the source electrode region and the drain electrode region, and then rinsed with ultrapure water and dried with nitrogen.

[0090] S303, within the mask layer 14 and up to part of the buffer layer 3 in the etching source electrode region and drain electrode region.

[0091] Specifically, please refer to Figure 2(d). First, the sample with the photolithographic pattern of the active electrode 7 and the drain electrode 8 is placed in an ICP etching machine for etching. Under one etching condition: the reaction gases are CF4 and O2, the reaction chamber pressure is 10 mTorr, and the radio frequency power of the upper electrode and the lower electrode is 100 W and 10 W, respectively, to etch the mask layer 14, the cap layer 6, and up to the upper surface of the barrier layer 5. Then, under another etching condition: the reaction gases are Cl2 and BCl3, the reaction chamber pressure is 5 mTorr, and the radio frequency power of the upper electrode and the lower electrode is 150 W and 50 W, respectively, to etch into part of the buffer layer 3. The etching depth in the buffer layer 3 is 10 nm to 20 nm. Next, the photoresist on the surface of the etched sample is cleaned.

[0092] S304. An N+GaN epitaxial layer 9 is grown on the buffer layer 3 and the mask layer 14.

[0093] Specifically, please refer to Figure 2(e). The sample is placed in the MOCVD equipment, and an N+GaN epitaxial layer 9 is grown on the buffer layer 3 and the mask layer 14 using the MOCVD process, that is, secondary epitaxy. Specifically, an N+GaN epitaxial layer 9 with a thickness of 100nm to 200nm is grown on the buffer layer 3 and the mask layer 14.

[0094] S305, wet etching is used to remove the mask layer 14 and the N+GaN epitaxial layer 9 on the cap layer 6.

[0095] Specifically, as shown in Figure 2(f), the sample is immersed in a buffered oxide etching (BOE) solution for wet etching, which etches away the mask layer 14 on the cap layer 6. Simultaneously, the N+GaN epitaxial layer 9 covering the mask layer 14 is detached along with the mask layer 14. The etching process conditions are as follows: the BOE solution is a mixture of 49% HF aqueous solution and 40% NH4F aqueous solution in a volume ratio of 1:6, and the etching time is 3 minutes.

[0096] S306. An ohmic patterned region is photolithographically formed on the N+GaN epitaxial layer 9.

[0097] Specifically, the source electrode region and drain electrode region are etched using S302 photolithography to etch an ohmic patterned region on the N+GaN epitaxial layer 9.

[0098] S307, a portion of the N+GaN epitaxial layer 9 within the ohmic patterned area is etched to form an ohmic contact trench array.

[0099] Specifically, referring to Figure 2(g), a portion of the N+GaN epitaxial layer 9 within the ohmic patterned area is removed using an ICP etching process. The etching conditions are as follows: the reaction gases are CF4 and O2, the reaction chamber pressure is 10 mTorr, and the RF power of the upper and lower electrodes is 100 W and 10 W, respectively. The etched portion forms an ohmic contact trench array within the N+GaN epitaxial layer 9, with an etching depth of 50 nm to 80 nm. The ohmic contact trench array comprises several ohmic contact trenches, and the surface shape of each ohmic contact trench can be circular, rectangular, etc., with no specific shape limitation.

[0100] S308. Deposit ohmic metal in each ohmic contact trench of the N+GaN epitaxial layer 9 and the ohmic contact trench array to form source electrode 7 and drain electrode 8.

[0101] Specifically, referring to Figure 2(h), firstly, the sample with the photolithographic pattern of the active electrode 7 and the drain electrode 8 is placed in a plasma resist stripper for bottom film treatment, which takes 5 minutes; then, the sample is placed in an electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6Following the torsion process, ohmic metal is evaporated in the N+GaN epitaxial layer 9 in the source and drain electrode regions, in each ohmic contact trench in the ohmic contact trench array, and on the photoresist outside the source and drain electrode regions. This ohmic metal is a metal stack structure consisting of four metal layers, Ti, Al, Ni, and Au, arranged sequentially from bottom to top. Next, the sample after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist, and release adhesive outside the source and drain electrode regions. Finally, the sample is rinsed with ultrapure water and dried with nitrogen.

[0102] In embodiment S30 of this invention, when a secondary epitaxial growth method is used, the requirements for the selection of the mask layer 14, the growth process of the N+GaN epitaxial layer 9, and the selection of the ohmic metal evaporated on the N+GaN epitaxial layer 9 are extremely stringent. During the fabrication process, due to the need for selective growth, a mask layer 14 must be added. The mask layer 14 must be a mask material that is invariably stable at high temperatures and easily peeled off to ensure the growth quality of the N+GaN epitaxial layer 9. If the N+GaN epitaxial layer 9 is grown too thick or too thin, it will severely affect the quality of the source electrode 7 and the drain electrode 8. In this embodiment, the preferred growth thickness of the N+GaN epitaxial layer 9 is 100nm to 200nm. Simultaneously, after growth, a suitable proportion of BOE solution is used for surface etching of the N+GaN epitaxial layer 9 to improve its growth quality. Furthermore, when growing the ohmic metal on the N+GaN epitaxial layer 9, the metal selection is also important; the ohmic metal must include Ni metal with good adhesion and Au, which has better conductivity on top.

[0103] S40. A passivation layer 10 is grown on the source electrode 7, the drain electrode 8 and the cap layer 6.

[0104] Specifically, this embodiment of the invention provides an optional solution, in which a passivation layer 10 is grown on the source electrode 7, the drain electrode 8, and the cap layer 6, including:

[0105] S401. Clean the surface of the sample after the growth of the active electrode 7 and the drain electrode 8 is completed.

[0106] Specifically, first, the sample after the growth of the active electrode 7 and the drain electrode 8 is placed in an acetone solution and ultrasonically cleaned for 3 minutes with an ultrasonic intensity of 3.0; then, the sample is placed in a stripping solution at a temperature of 60°C and heated in a water bath for 5 minutes; next, the sample is placed in an acetone solution and an ethanol solution in sequence and ultrasonically cleaned for 3 minutes with an ultrasonic intensity of 3.0; finally, the sample is rinsed with ultrapure water and dried with nitrogen gas.

[0107] S402, A passivation layer 10 is grown on the source electrode 7, the drain electrode 8 and the cap layer 6.

[0108] Specifically, please refer to Figure 2(i). The sample is placed in the PECVD equipment, and a passivation layer 10 is grown on the source electrode 7, the drain electrode 8 and the cap layer 6 of the active region using the PECVD process. The growth process conditions are as follows: NH3 and SiH4 are used as reaction gases, the substrate temperature is 250°C, the reaction chamber pressure is 600 mTorr, and the RF power is 22 W.

[0109] Preferably, the passivation layer 10 comprises SiN with a thickness of 100 nm to 120 nm.

[0110] S50. A groove area is photolithographically formed on the passivation layer 10, and the passivation layer 10 in the groove area is etched until a groove is formed at a preset position.

[0111] Specifically, this embodiment of the invention provides an optional solution, in which a groove region is photolithographically formed on the passivation layer 10, and the passivation layer 10 within the groove region is etched until a preset position is formed to form a groove, including:

[0112] S501. A groove area is photolithographically formed on the passivation layer 10.

[0113] Specifically, first, the sample is baked on a hot plate at 200°C for 5 minutes; then, photoresist is applied and spun at a speed of 3500 rpm, and the sample is baked on a hot plate at 90°C for 1 minute; next, the sample is placed in a lithography machine to expose the photoresist in the groove area; finally, the exposed sample is placed in a developer to remove the photoresist in the groove area, and then rinsed with ultrapure water and dried with nitrogen.

[0114] S502. Using the first etching process conditions, etch the passivation layer 10 in the groove area up to the upper surface of the barrier layer 5.

[0115] Specifically, please refer to Figure 2(j). The sample is placed in an ICP etching machine, and the passivation layer 10 and cap layer 6 in the groove area are removed by ICP etching process. The first etching process is used for etching, and the etching conditions are as follows: the reaction gas is CF4 and O2, the reaction chamber pressure is 10mTorr, and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W, respectively. The etching is carried out until the upper surface of the barrier layer 5 is reached.

[0116] S503. Using the second etching process conditions, continue etching a portion of the barrier layer 5 within the groove area; wherein, the etching depth within the barrier layer 5 is the first etching depth.

[0117] Specifically, please refer to Figure 2(k). By changing the etching conditions, a second etching process condition is adopted in the ICP etching machine to achieve rapid etching and continue etching the barrier layer 5 in the groove area. The specific rapid etching conditions are: the reaction gases are Cl2 and BCl3, the reaction chamber pressure is 5 mTorr, the RF power of the upper electrode and the lower electrode is 300W and 75W respectively, and the etching depth is the first etching depth. Specifically, the first etching depth is at most 1 / 2 of the thickness of the barrier layer 5. For example, when the thickness of the barrier layer 5 is 20nm, the first etching depth can be 8nm, corresponding to a remaining thickness of 12nm for the barrier layer 5 in the groove area.

[0118] S504. Using the third etching process conditions, continue etching a portion of the barrier layer 5 within the groove area to form a groove; wherein, the etching depth within the barrier layer 5 is the second etching depth, and the second etching depth is 1 / 4 of the first etching depth.

[0119] Specifically, please refer to Figure 2(l). The etching conditions are changed again. The third etching process conditions are used in the ICP etching machine to achieve low-loss recovery. The barrier layer 5 in the groove area is etched to form a groove. The specific low-damage repair conditions are: the reaction gas is O2 and BCl3, the reaction chamber pressure is 20mTorr, the RF power of the upper electrode and the lower electrode is 50W and 15W respectively, and the etching depth is the second etching depth. The second etching depth is 1 / 4 of the first etching depth. For example, when the second etching depth is 8nm, the second etching depth can be 2nm, and the remaining thickness of the barrier layer 5 in the groove area is 10nm.

[0120] This invention provides another optional solution, wherein the passivation layer within the groove region is etched in S50 until a preset position is formed to form a groove, including:

[0121] S50-1. Using the fourth etching process conditions, etch the passivation layer in the groove area up to the upper surface of the barrier layer 5.

[0122] Specifically, in this embodiment of the invention, the same first etching process conditions as S502 are selected as the fourth etching process conditions. In the ICP etching machine, the passivation layer 10 in the groove area is etched up to the upper surface of the barrier layer 5 to form the structure shown in FIG2(j).

[0123] S50-2. Using the fifth etching process conditions, continue etching the barrier layer 5 in the groove area until the upper surface of the buffer layer 3 forms a groove.

[0124] Specifically, please see Figure 3 The etching process conditions are changed. In this embodiment of the invention, the same third etching process conditions as S504 are used as the fifth etching process conditions. The barrier layer 5 in the groove area is etched in the ICP etching machine until the upper surface of the buffer layer 3 forms a groove.

[0125] Figure 2(m)~Figure 2(o) This is a schematic diagram of the fabrication structure based on the process shown in Figure 2(l). This only illustrates the structure fabricated using the process shown in Figure 2(l). The subsequent fabrication process for forming the grooves through etching S50-1 and S50-2 is similar. The following section will focus on... Figure 2(m)~Figure 2(o) The subsequent process flow is based on Figure 2(l).

[0126] S60. Grow a gate dielectric layer 11 in the groove.

[0127] Specifically, referring to Figure 2(i), this embodiment of the invention provides an optional solution: using a plasma-enhanced atomic layer deposition (PEALD) apparatus, a thermal oxidation process is employed at a temperature of 250°C to 300°C to form a gate dielectric layer with a thickness of 1 nm to 10 nm in situ within the trench, specifically including:

[0128] S601. Clean the surface of the sample after the groove etching is completed.

[0129] Specifically, first, the sample with the groove etched is placed in an acetone solution and ultrasonically cleaned for 3 minutes at an ultrasonic intensity of 3.0; then, the sample is placed in a stripping solution at 60°C and heated in a water bath for 5 minutes; next, the sample is placed in an acetone solution and an ethanol solution in sequence and ultrasonically cleaned for 3 minutes at an ultrasonic intensity of 3.0; finally, the sample is rinsed with ultrapure water and dried with nitrogen.

[0130] S602. Perform in-situ pretreatment on the surfaces of the barrier layer 5 in the groove region and the passivation layer 10 outside the groove region.

[0131] Specifically, the sample with the cleaned surface is placed in a Plasma Enhanced Atomic Layer Deposition (PEALD) device to perform in-situ pretreatment on the surface of the barrier layer 5 in the groove region and the passivation layer 10 outside the groove region. The process conditions are as follows: the reaction gas is a mixture of NH3 and N2, the substrate temperature is 300℃, the RF power is set to 200W, and the processing time is 5min.

[0132] S603. An AlN dielectric insertion layer is grown on the surface of the barrier layer 5 in the groove region.

[0133] Specifically, an AlN dielectric insertion layer of 1 nm to 2 nm was grown on the surface of the barrier layer 5 in the groove region using the PEALD process. The growth process conditions were as follows: NH3 and TMA were used as reaction precursor sources, the substrate temperature was 250℃ to 300℃, the RF power was set to 50W, and the reaction chamber pressure was 0.3 Torr.

[0134] S604. The AlN dielectric insertion layer in the groove region and the passivation layer 10 outside the groove region are subjected to oxidation treatment.

[0135] Specifically, the AlN dielectric insertion layer in the groove region and the passivation layer 10 outside the groove region are oxidized using the PEALD process. The process conditions are as follows: the reaction gas is O2, the substrate temperature is 250℃~300℃, the RF power is set to 200W, and the processing time is 20min.

[0136] S605. In-situ oxidation is performed on the AlN dielectric insertion layer in the groove region and the passivation layer 10 outside the groove region to form the gate dielectric layer 11 using a thermal oxidation process.

[0137] Specifically, on the AlN dielectric insertion layer in the groove region and the passivation layer 10 outside the groove region, a high-k Al2O3 dielectric layer with a thickness of 2nm to 5nm is formed in situ by thermal oxidation using a PEALD device on the AlN dielectric insertion layer. The gate dielectric layer 11 is formed by the AlN dielectric insertion layer and the high-k Al2O3 dielectric layer. On the passivation layer 10, a SiO2 passivation layer 10 is formed in situ by oxidation. The growth process conditions are as follows: O2 and TMA are used as reaction precursor sources, the substrate temperature is 250℃ to 300℃, the RF power is set to 100W, and the reaction chamber pressure is 0.3 Torr.

[0138] This invention provides another optional solution, where S60 grows a gate dielectric layer 11 within the groove, including: using an atomic layer deposition (ALD) device to grow a gate dielectric layer with a thickness of 2nm to 7nm within the groove at a temperature of 250°C to 300°C, specifically:

[0139] S60-1. Clean the surface of the sample after the groove etching is completed.

[0140] S60-2. Perform in-situ pretreatment on the surfaces of the barrier layer 5 in the groove region and the passivation layer 10 outside the groove region.

[0141] S60-3, An AlN dielectric insertion layer is grown on the surface of the barrier layer 5 in the groove region.

[0142] S60-4. Growth of HfO2 high-k dielectric layer on AlN dielectric insertion layer.

[0143] The processing of S60-1 to S60-3 is the same as that of S601 to S603, so it will not be repeated here. The difference is that S60-4 uses ALD process to grow a HfO2 high-k dielectric layer with a thickness of 1nm to 5nm on the AlN dielectric insertion layer. The growth process conditions are: the reaction precursor source is O3 and TEMAH, the substrate temperature is 300℃, and the reaction chamber pressure is 0.3 Torr.

[0144] S70. A gate electrode region is photolithographically formed on the passivation layer 10 and above the groove. A gate metal is grown on the gate dielectric layer 11 in the gate electrode region and on the gate dielectric layer 11 in the groove to form a T-shaped gate electrode 12.

[0145] Specifically, referring to Figure 2(n), a gate electrode region is photolithographically formed on the passivation layer 10 and above the groove. A gate metal is grown on the passivation layer 10 within the gate electrode region and on the gate dielectric layer 11 within the groove to form a T-shaped gate electrode 12, including:

[0146] S701. The gate electrode region is photolithographically formed on the passivation layer 10 and above the groove.

[0147] Specifically, firstly, the sample with the completed gate dielectric layer 11 is baked on a hot plate at 200°C for 5 minutes; then, a stripping agent is applied and spun onto the passivation layer 10 and above the groove, with a spun-off thickness of 0.35 μm, and the sample is baked on a hot plate at 200°C for 5 minutes; next, photoresist is applied and spun onto the stripping agent, with a spun-off thickness of 0.77 μm, and the sample is baked on a hot plate at 90°C for 1 minute; after that, the sample with the completed stripping and spun-off is placed in a photolithography machine to expose the photoresist in the gate electrode area; finally, the exposed sample is placed in a developing solution to remove the photoresist and stripping agent in the gate electrode area, and then rinsed with ultrapure water and dried with nitrogen.

[0148] S702, A T-shaped gate electrode 12 is formed by growing gate metal on the passivation layer 10 in the gate electrode region and on the gate dielectric layer 11 in the groove.

[0149] Specifically, firstly, the sample with the photolithographic pattern of the T-shaped gate electrode 12 is placed in a plasma resist remover for bottom film treatment, which takes 5 minutes; then, the sample is placed in an electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6 After Torr, gate metal is evaporated in the passivation layer 10 and the groove in the gate electrode region, as well as on the photoresist outside the gate electrode region. The gate metal is a metal stack structure composed of two layers of metal, Ni and Au, arranged sequentially from bottom to top. Then, the sample after the gate metal evaporation is completed is stripped to remove the gate metal, photoresist and stripping adhesive outside the gate electrode region. Finally, the sample is rinsed with ultrapure water and dried with nitrogen.

[0150] S80, etch the passivation layer 10 on the source electrode 7 and the drain electrode 8 until the source electrode 7 and the drain electrode 8, and grow interconnect electrodes 13 on the source electrode 7, the drain electrode 8 and the T-type gate electrode 12 respectively.

[0151] Specifically, referring to Figure 2(o), the passivation layer 10 on the source electrode 7 and drain electrode 8 is etched down to the source electrode 7 and drain electrode 8, and interconnect electrodes 13 are grown on the source electrode 7, drain electrode 8 and T-type gate electrode 12, respectively, including:

[0152] S801, Photolithographically etch metal interconnect regions on passivation layer 10.

[0153] Specifically, the sample with the completed T-gate electrode 12 growth is baked on a hot plate at 200°C for 5 minutes; the release agent is coated and spin-spinned onto the passivation layer 10 on the source electrode 7 and drain electrode 8 and onto the T-gate electrode 12, with a spin-spinning thickness of 0.35 μm, and the sample is baked on a hot plate at 200°C for 5 minutes; the photoresist is coated and spin-spinned onto the release agent, with a spin-spinning thickness of 0.77 μm, and the sample is baked on a hot plate at 90°C for 1 minute; the sample with the completed coating and spin-spinning is placed in a photolithography machine to expose the photoresist in the metal interconnect area, and then the exposed sample is placed in a developing solution to remove the photoresist and release agent in the metal interconnect area, and then rinsed with ultrapure water and dried with nitrogen.

[0154] S802, Etch the passivation layer 10 in the metal interconnect region up to the source electrode 7 and the drain electrode 8.

[0155] Specifically, the passivation layer 10 in the metal interconnect region is removed using an ICP etching process. The etching conditions are as follows: the reaction gases are CF4 and O2, the reaction chamber pressure is 10 mTorr, the RF power of the upper electrode and the lower electrode is 100 W and 10 W respectively, and the etching depth is 100 nm to 120 nm, that is, etching up to the upper surface of the source electrode 7 and the drain electrode 8.

[0156] S803. Interconnect metal is evaporated on the source electrode 7, drain electrode 8 and T-type gate electrode 12 in the metal interconnect region to form interconnect electrode 13.

[0157] Specifically, the sample with the metal interconnect region is placed in a plasma stripper for bottom film treatment for 5 minutes; the sample is then placed in an electron beam evaporation stage until the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 2 × 10⁻⁶. -6After the Torr process, interconnect metal is evaporated on the source electrode 7, drain electrode 8, and T-type gate electrode 12 within the metal interconnect region, as well as on the photoresist outside the metal interconnect region, to form interconnect electrode 13. This interconnect electrode 13 is a metal stack structure consisting of two layers, Ti and Au, arranged sequentially from bottom to top. The sample after the interconnect metal evaporation is completed is stripped to remove the interconnect metal, photoresist, and release adhesive outside the metal interconnect region. The sample is then rinsed with ultrapure water and dried with nitrogen to complete the device fabrication.

[0158] In summary, the method for fabricating low-voltage, high-efficiency gallium nitride power devices proposed in this embodiment of the invention employs a secondary epitaxial layer to generate an epitaxial layer during the fabrication of ohmic contacts. This epitaxial layer forms an ohmic contact with an ohmic metal. Simultaneously, combined with ohmic patterning etching, the ohmic metal contact area is increased, thereby reducing the ohmic contact resistance, lowering parasitic capacitance, reducing device power consumption, and improving device frequency characteristics.

[0159] During the groove etching process, the groove is processed by using rapid etching followed by low-damage repair, which reduces fixed charge and etching damage, and improves the scattering effect of interface charge and impurities on channel electrons in the groove, thereby improving the reliability of the device.

[0160] In this embodiment of the invention, the gate dielectric layer 11 adopts a stacked structure composed of an AlN dielectric insertion layer and a high-k dielectric layer. The AlN dielectric insertion layer improves the interface quality between the gate dielectric layer 11 and the cap layer 6, while the high-k dielectric layer improves the off-state leakage current and gate control capability of the insulated-gate high electron mobility transistor. The high-k dielectric layer includes an Al2O3 high-k dielectric layer or an HfO2 high-k dielectric layer.

[0161] During the growth of the gate dielectric layer 11, an in-situ oxidation process is used to oxidize the gate dielectric layer 11. This process ensures that the height of the strongly polarized nitride barrier is not reduced, oxidizing a portion of the barrier layer 5 into the gate dielectric layer 11. This avoids the interface damage caused by etching during the traditional ALD process for growing the gate dielectric layer 11, reducing the sheet resistance of the device. The gate dielectric layer 11 improves the off-state leakage current, thereby enhancing the device's power characteristics. During the thermal oxidation process, a plasma-enhanced atomic layer deposition (PEALD) system is used for remote plasma oxidation, increasing the oxidation rate while reducing damage to the barrier layer 5 surface. Furthermore, the oxidation process requires a relatively low temperature (around 250℃ to 300℃), effectively avoiding damage to the material caused by high temperatures, improving gate off-state leakage current, increasing the device's breakdown voltage, and simultaneously increasing the threshold voltage, thus achieving the goal of fabricating an enhancement-mode device.

[0162] Finally, the fabrication method of this invention can improve the reliability of existing gallium nitride power devices by addressing various reliability issues. This method is of great significance for the fabrication of various low-voltage, high-efficiency gallium nitride power devices and has broad prospects for low-voltage, high-efficiency applications.

[0163] Secondly, please see Figure 5 This invention provides a low-voltage, high-efficiency gallium nitride power device, comprising:

[0164] Epitaxial substrate; wherein, from bottom to top, the epitaxial substrate includes a substrate layer 1, a nucleation layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5, and a cap layer 6;

[0165] Source electrode 7 and drain electrode 8 are located at both ends of buffer layer 3 that penetrates cap layer 6, barrier layer 5 and insertion layer; wherein, N+GaN epitaxial layer 9 is respectively disposed between source electrode 7 and drain electrode 8 and buffer layer 3, and ohmic contact trench array is disposed in N+GaN epitaxial layer 9, and each ohmic contact trench in ohmic contact trench array is filled with ohmic metal.

[0166] Passivation layer 10 is located on source electrode 7, drain electrode 8 and cap layer 6;

[0167] The T-shaped gate electrode 12 includes a first part and a second part flush with the first part; the first part is located in the barrier layer 5 that penetrates the middle position of the passivation layer 10 and the cap layer 6; the second part is located on both sides of the first part and embedded in the passivation layer 10; wherein, a gate dielectric layer 11 is also disposed between the first part and the barrier layer 5.

[0168] Interconnect electrode 13 is located on the source electrode 7 and drain electrode 8 that penetrate the passivation layer, and on the T-type gate electrode 12.

[0169] The low-voltage, high-efficiency gallium nitride power device is fabricated using the aforementioned method for fabricating low-voltage, high-efficiency gallium nitride power devices.

[0170] Thirdly, please see Figure 6 This invention provides a low-voltage, high-efficiency gallium nitride power device, comprising:

[0171] Epitaxial substrate; wherein, from bottom to top, the epitaxial substrate includes a substrate layer 1, a nucleation layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5, and a cap layer 6;

[0172] Source electrode 7 and drain electrode 8 are located at both ends of buffer layer 3 that penetrates cap layer 6, barrier layer 5 and insertion layer 4; wherein, N+GaN epitaxial layer 9 is respectively disposed between source electrode 7 and drain electrode 8 and buffer layer 3, and ohmic contact trench array is disposed in N+GaN epitaxial layer 9, and each ohmic contact trench in ohmic contact trench array is filled with ohmic metal.

[0173] Passivation layer 10 is located on source electrode 7, drain electrode 8 and cap layer 6;

[0174] The T-shaped gate electrode 12 includes a first part and a second part flush with the first part. The first part is located on the buffer layer 3 that penetrates the passivation layer 10, the cap layer 6, the barrier layer 5 and the insertion layer 4. The second part is located on both sides of the first part and embedded in the passivation layer 10. A gate dielectric layer 11 is also disposed between the first part and the buffer layer 3.

[0175] Interconnect electrode 13 is located on the source electrode 7 and drain electrode 8 that penetrate the passivation layer 10, and on the T-type gate electrode 12.

[0176] The low-voltage, high-efficiency gallium nitride (GaN) power device is fabricated using the aforementioned method. The biggest difference between this and the low-voltage, high-efficiency GaN power device provided in the second aspect is that the pre-defined location for the groove etching in the second aspect is within the barrier layer 5, while the pre-defined location for the groove etching in the third aspect is on the upper surface of the buffer layer 3.

[0177] The low-voltage, high-efficiency gallium nitride power device proposed in the first and second aspects of the present invention uses an N+GaN epitaxial layer 9 to form an ohmic contact with an ohmic metal in the ohmic contact region. At the same time, it combines ohmic patterning etching to form an ohmic contact trench array, which increases the ohmic metal contact area, thereby reducing the ohmic contact resistance, reducing parasitic capacitance, reducing device power consumption, and improving device frequency characteristics.

[0178] During the groove etching process, the groove is processed by using rapid etching followed by low-damage repair, which reduces fixed charge and etching damage, and improves the scattering effect of interface charge and impurities on channel electrons in the groove, thereby improving the reliability of the device.

[0179] In this embodiment of the invention, the gate dielectric layer 11 adopts a stacked structure composed of an AlN dielectric insertion layer and a high-k dielectric layer. The AlN dielectric insertion layer improves the interface quality between the gate dielectric layer 11 and the cap layer 6, while the high-k dielectric layer improves the off-state leakage current and gate control capability of the insulated-gate high electron mobility transistor. The high-k dielectric layer includes an Al2O3 high-k dielectric layer or an HfO2 high-k dielectric layer.

[0180] During the growth of the gate dielectric layer 11, an in-situ oxidation process is used to oxidize the gate dielectric layer 11. This process ensures that the height of the strongly polarized nitride barrier is not reduced, oxidizing a portion of the barrier layer 5 into the gate dielectric layer 11. This avoids the interface damage caused by etching during the traditional ALD process for growing the gate dielectric layer 11, reducing the sheet resistance of the device. The gate dielectric layer 11 improves the off-state leakage current, thereby enhancing the device's power characteristics. During the thermal oxidation process, a plasma-enhanced atomic layer deposition (PEALD) system is used for remote plasma oxidation, increasing the oxidation rate while reducing damage to the barrier layer 5 surface. Furthermore, the oxidation process requires a relatively low temperature (around 250℃ to 300℃), effectively avoiding damage to the material caused by high temperatures, improving gate off-state leakage current, increasing the device's breakdown voltage, and simultaneously increasing the threshold voltage, thus achieving the goal of fabricating an enhancement-mode device.

[0181] Finally, the fabrication method of this invention can improve the reliability of existing gallium nitride power devices by addressing various reliability issues. This method is of great significance for the fabrication of various low-voltage, high-efficiency gallium nitride power devices and has broad prospects for low-voltage, high-efficiency applications.

[0182] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0183] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0184] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0185] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a low-voltage, high-efficiency gallium nitride power device, characterized in that, include: Obtain an epitaxial substrate; wherein, the epitaxial substrate comprises, from bottom to top, a substrate layer, a nucleation layer, a buffer layer, an insertion layer, a barrier layer and a cap layer; the barrier layer is a strongly polarized nitride of AlGaN or AlN or InAlN or ScAlN or InAlGaN with a thickness of 3nm~20nm; Electrical isolation of the active region is formed on the epitaxial substrate; Source electrode regions and drain electrode regions are photolithographically etched on the cap layer. Ohmic metals are then grown in the source electrode regions and drain electrode regions respectively using secondary epitaxial growth and patterned etching techniques to form source and drain electrodes. The step of growing ohmic metals in the source electrode regions and drain electrode regions using secondary epitaxial growth and patterned etching techniques includes: growing a mask layer on the cap layer; photolithographically etching the source electrode regions and drain electrode regions on the mask layer; and etching the mask layer in the source electrode regions and drain electrode regions until a portion is reached. Within the buffer layer; an N+GaN epitaxial layer with a thickness of 100nm~200nm is grown on the buffer layer and the mask layer; the mask layer and the N+GaN epitaxial layer on the cap layer are removed by wet etching; an ohmic patterned region is photolithographically formed on the N+GaN epitaxial layer; a portion of the N+GaN epitaxial layer within the ohmic patterned region is etched to form an ohmic contact trench array; ohmic metal is deposited on the N+GaN epitaxial layer and in each ohmic contact trench in the ohmic contact trench array to form the source electrode and the drain electrode; A passivation layer is grown on the source electrode, the drain electrode, and the cap layer; A groove region is photolithographically formed on the passivation layer, and the passivation layer within the groove region is etched until a groove is formed at a preset position. During the groove etching process, the etching conditions are changed to achieve rapid etching followed by low-damage repair. The low-damage repair conditions in the ICP etching machine are: the reaction gases are O2 and BCl3, the reaction chamber pressure is 20 mTorr, the RF power of the upper electrode and the lower electrode is 50 W and 15 W respectively, the etching depth is the second etching depth, the second etching depth is 1 / 4 of the first etching depth, and the first etching depth is at most 1 / 2 of the barrier layer thickness. Using a plasma-enhanced atomic layer deposition (PAL) apparatus, a gate dielectric layer with a thickness of 2 nm to 7 nm is formed in situ within the groove using a thermal oxidation process at a temperature of 250°C to 300°C. The process includes: in-situ pretreatment of the barrier layer in the groove region and the passivation layer outside the groove region at a temperature of 300°C; growth of an AlN dielectric insertion layer on the surface of the barrier layer in the groove region at a temperature of 250°C to 300°C; oxidation treatment of the AlN dielectric insertion layer in the groove region and the passivation layer outside the groove region at a temperature of 250°C to 300°C; and in-situ oxidation of the AlN dielectric insertion layer in the groove region and the passivation layer outside the groove region using a thermal oxidation process at a temperature of 250°C to 300°C to form a gate dielectric layer with a thickness of 2 nm to 7 nm. The gate dielectric layer is composed of both an AlN dielectric insertion layer and an Al₂O₃ high-k dielectric layer. A gate electrode region is photolithographically formed on the passivation layer and above the groove, and a gate metal is grown on the passivation layer within the gate electrode region and on the gate dielectric layer within the groove to form a T-shaped gate electrode; The passivation layers on the source electrode and the drain electrode are etched down to the source electrode and the drain electrode, and interconnect electrodes are grown on the source electrode, the drain electrode and the T-type gate electrode, respectively.

2. The method for fabricating a low-voltage, high-efficiency gallium nitride power device according to claim 1, characterized in that, The electrical isolation of the active region formed on the epitaxial substrate includes: An electrically isolated region is photolithographically formed on the cap layer; The cap layer, the barrier layer, the insertion layer, and a portion of the buffer layer of the electrically isolated region are sequentially etched using an ICP etching process to form the electrical isolation of the active region; wherein the etching depth is 140nm~150nm.

3. The method for fabricating a low-voltage, high-efficiency gallium nitride power device according to claim 1, characterized in that, The electrical isolation of the active region formed on the epitaxial substrate includes: An electrically isolated region is photolithographically formed on the cap layer; N ions are sequentially implanted into the cap layer, the barrier layer, the insertion layer, and up to a portion of the buffer layer of the electrically isolated region using an ion implantation process to form an electrically isolated active region; wherein the implantation depth is 110 nm to 120 nm.

4. The method for fabricating a low-voltage, high-efficiency gallium nitride power device according to claim 1, characterized in that, The etching of the passivation layer within the groove region until a preset position is formed to create the groove includes: Using the first etching process conditions, the passivation layer in the groove area is etched up to the upper surface of the barrier layer; Using the second etching process conditions, a portion of the barrier layer within the groove region is further etched; wherein the etching depth within the barrier layer is the first etching depth, and the first etching depth is at most 1 / 2 of the thickness of the barrier layer; Using a third etching process, a portion of the barrier layer within the groove region is etched to form the groove; wherein the etching depth within the barrier layer is a second etching depth, and the second etching depth is 1 / 4 of the first etching depth.

5. The method for fabricating a low-voltage, high-efficiency gallium nitride power device according to claim 1, characterized in that, The etching of the passivation layer within the groove region until a preset position is formed to create the groove includes: Using the fourth etching process conditions, the passivation layer in the groove area is etched up to the upper surface of the barrier layer; Using the fifth etching process conditions, the barrier layer in the groove area is etched until the groove is formed on the upper surface of the buffer layer.

6. A low-voltage, high-efficiency gallium nitride power device, characterized in that, The low-voltage, high-efficiency gallium nitride power device is fabricated according to the method of fabrication of any one of claims 1 to 5, and the corresponding low-voltage, high-efficiency gallium nitride power device includes: Epitaxial substrate; wherein, from bottom to top, the epitaxial substrate comprises a substrate layer, a nucleation layer, a buffer layer, an insertion layer, a barrier layer, and a cap layer; The source electrode and the drain electrode are located at both ends of the buffer layer that penetrates the cap layer, the barrier layer and the insertion layer; wherein, an N+GaN epitaxial layer is respectively disposed between the source electrode and the drain electrode and the buffer layer, and an ohmic contact trench array is disposed in the N+GaN epitaxial layer, and each ohmic contact trench in the ohmic contact trench array is filled with ohmic metal. A passivation layer is located on the source electrode, the drain electrode, and the cap layer; The T-shaped gate electrode includes a first part and a second part flush with the first part; the first part is located in the barrier layer that penetrates the middle position of the passivation layer and the cap layer; the second part is located on both sides of the first part and embedded in the passivation layer; wherein, a gate dielectric layer is further disposed between the first part and the barrier layer; Interconnect electrodes are located on the source electrode and the drain electrode, which penetrate the passivation layer, and on the T-type gate electrode.

7. A low-voltage, high-efficiency gallium nitride power device, characterized in that, The low-voltage, high-efficiency gallium nitride power device is fabricated according to the method of fabrication of any one of claims 1 to 5, and the corresponding low-voltage, high-efficiency gallium nitride power device includes: Epitaxial substrate; wherein, from bottom to top, the epitaxial substrate comprises a substrate layer, a nucleation layer, a buffer layer, an insertion layer, a barrier layer, and a cap layer; The source electrode and the drain electrode are located at both ends of the buffer layer that penetrates the cap layer, the barrier layer and the insertion layer; wherein, an N+GaN epitaxial layer is respectively disposed between the source electrode and the drain electrode and the buffer layer, and an ohmic contact trench array is disposed in the N+GaN epitaxial layer, and each ohmic contact trench in the ohmic contact trench array is filled with ohmic metal. A passivation layer is located on the source electrode, the drain electrode, and the cap layer; The T-shaped gate electrode includes a first part and a second part flush with the first part. The first part is located on the buffer layer that penetrates the passivation layer, the cap layer, the barrier layer and the insertion layer. The second part is located on both sides of the first part and embedded in the passivation layer. A gate dielectric layer is also disposed between the first part and the buffer layer. Interconnect electrodes are located on the source electrode and the drain electrode, which penetrate the passivation layer, and on the T-type gate electrode.

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