Semiconductor packaging structure and preparation method

Abstract

The present invention provides a semiconductor packaging structure and preparation method. The semiconductor packaging structure includes: a second redistribution structure; a first functional chip and a pressure supply chip, the pressure supply chip being flip-chip mounted on the second redistribution structure, and the first functional chip being mounted upright on the side of the pressure supply chip facing away from the second redistribution structure; a first plastic encapsulation layer located on one side of the second redistribution structure and covering the first functional chip and the pressure supply chip; a first conductive connector located on the side of the first functional chip and the pressure supply chip; a first redistribution structure located on the side of the first plastic encapsulation layer facing away from the second redistribution structure, the first redistribution structure being electrically connected to the front of the first functional chip, the first conductive connector being electrically connected to the first redistribution structure and the second redistribution structure; and a second functional chip flip-chip mounted on the side of the first redistribution structure facing away from the second redistribution structure and electrically connected to the first redistribution structure. The semiconductor packaging structure of the present invention has high integration density and large transmission bandwidth.

Description

Technical Field

[0001] The present invention relates to the technical field, and in particular to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] In data centers and high-performance computing applications, communication data rates are evolving toward ultra-high throughput and high-quality transmission. Consequently, optoelectronic conversion has evolved from pluggable modules at the edge to co-packaged optoelectronics (CPO) technology, integrating the CPO with ASICs such as switches, FPGAs, and CPUs on a single package substrate. To increase integration density, CPOs are shrinking in size, making the development of a compact CPO package crucial. Furthermore, to reduce CPO size, the industry advocates placing the CPO's power supply microcontroller (PMIC) on the same package substrate as the switch. However, this increases the power supply path, increasing the parasitic inductance and resistance of the link and impacting the supply voltage. Therefore, integrating the PMIC into the CPO offers promising applications.

[0003] Existing technologies typically package the electronic chip (EIC) and optical chip (PIC) together via a substrate to form an MCM. For example, Intel's LGA-based CPO integrates a PMIC chip, but this CPO utilizes a double-sided planar integration approach. While this CPO module is simple to assemble, it is large and has low integration density. Acacia's coherent optical module stacks the EIC and PIC, interconnecting the EIC and digital signal processing chip (DSP) via bonding wires and a short interconnect. This structure reduces size compared to a multi-chip module (MCM) package, but the interconnection path between the EIC and DSP is long, limiting transmission bandwidth. Furthermore, the module lacks a PMIC and requires voltage supply from a power chip on the package substrate. This long supply path results in high voltage drop and power supply noise. Luxtera uses a monolithic integration approach to integrate the PIC and EIC, but this approach has a long development cycle and the PIC and EIC operate at different process nodes, making it difficult to leverage their respective strengths if integrated on a monolithic basis. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defect that the existing packaging structure cannot take into account both high integration density and large transmission bandwidth, and further provide a semiconductor packaging structure and a preparation method.

[0005] The present invention provides a semiconductor packaging structure, comprising: a second rewiring structure; a first functional chip and a pressure supply chip located on one side of the second rewiring structure, the pressure supply chip being flipped on one side of the second rewiring structure, and the first functional chip being mounted on the side of the pressure supply chip away from the second rewiring structure; a first plastic encapsulation layer located on one side of the second rewiring structure and covering the side walls of the first functional chip and the side walls of the pressure supply chip; a first conductive connector located on the side of the first functional chip and the pressure supply chip and penetrating the first plastic encapsulation layer; a first rewiring structure located on the side of the first plastic encapsulation layer away from the second rewiring structure, the first rewiring structure being electrically connected to the front of the first functional chip, and the first conductive connector being electrically connected to the first rewiring structure and the second rewiring structure; a second functional chip being flipped on the side of the first rewiring structure away from the second rewiring structure and electrically connected to the first rewiring structure.

[0006] Optionally, the first functional chip is an electrical chip, and the second functional chip is an optical chip; the second functional chip includes a second optical coupling structure, and a side portion of the second functional chip exposes the second optical coupling structure.

[0007] Optionally, the semiconductor packaging structure further includes: an optical fiber, wherein a cross section of one end of the optical fiber faces the side of the second functional chip and is arranged opposite to the second optical coupling structure.

[0008] Optionally, the first functional chip is an optical chip, and the second functional chip is an electrical chip; the first functional chip includes a first optical coupling structure, and the front of the first functional chip exposes the first optical coupling structure; the projection of the second functional chip on the first rewiring structure and the projection of the first functional chip on the first rewiring structure are staggered; the first rewiring structure has an optical channel that runs through the first rewiring structure, and the optical channel is located above the first optical coupling structure and on the outside of the second functional chip.

[0009] Optionally, the semiconductor packaging structure further includes: an optical fiber, one end of which is arranged in the optical channel and opposite to the first optical coupling structure.

[0010] Optionally, it further includes: a digital signal processing chip located on a side of the first rewiring structure away from the second rewiring structure, with the front of the digital signal processing chip facing the first rewiring structure and electrically connected to the first rewiring structure.

[0011] Optionally, it also includes: a first heat conduction layer located on the back side of the digital signal processing chip; a second heat conduction layer located on the back side of the second function chip; and a heat sink spanning the digital signal processing chip and the second function chip, the heat sink being in contact with the first heat conduction layer and the second heat conduction layer.

[0012] Optionally, the material of the first heat-conducting layer includes thermal grease or thermal silica gel; the material of the second heat-conducting layer includes thermal grease or thermal silica gel.

[0013] Optionally, the radiator includes a serrated fin radiator, a water-cooled radiator or a heat pipe radiator.

[0014] Optionally, the method further includes: a solder ball, wherein the solder ball is located on a side of the second redistribution structure away from the first redistribution structure and is electrically connected to the second redistribution structure.

[0015] Optionally, it also includes: the first sub-packaging unit to the Nth sub-packaging unit located on the side of the second rewiring structure away from the first rewiring structure, where N is an integer greater than or equal to 1; the kth sub-packaging unit includes: the k+2th rewiring structure; the kth functional chip unit located between the k+2th rewiring structure and the second rewiring structure; the k+1th plastic packaging layer located between the k+2th rewiring structure and the second rewiring structure and covering the kth functional chip unit; the k+1th conductive connector located on the side of the kth functional chip unit and penetrating the k+1th plastic packaging layer, the k+1th conductive connector being electrically connected to the k+2th rewiring structure; k is an integer greater than or equal to 1 and less than or equal to N.

[0016] Optionally, when N is greater than or equal to 2, the first sub-package unit to the Nth sub-package unit are stacked vertically; the j+1th sub-package unit is located on the side of the jth sub-package unit away from the second rewiring structure; j is an integer greater than or equal to 1 and less than or equal to N-1; the kth functional chip unit is located between the k+2th rewiring structure and the k+1th rewiring structure; the k+1th plastic encapsulation layer is located between the k+2th rewiring structure and the k+1th rewiring structure; and the k+1th conductive connector is also electrically connected to the k+1th rewiring structure.

[0017] Optionally, the kth functional chip unit includes one or a combination of the kth additional electrical chip and the kth additional voltage supply chip.

[0018] Optionally, the method further includes: a solder ball, wherein the solder ball is located on a side of the (N+2)th redistribution structure away from the second redistribution structure and is electrically connected to the (N+2)th redistribution structure.

[0019] The present invention provides a method for preparing a semiconductor packaging structure, comprising: forming a second rewiring structure; forming a first conductive connector on one side of the second rewiring structure and electrically connecting it to the second rewiring structure; providing a first functional chip and a pressure supply chip, flipping the pressure supply chip on one side of the second rewiring structure, and mounting the first functional chip upright on the side of the pressure supply chip away from the second rewiring structure, the first conductive connector being located on the side of the first functional chip and the pressure supply chip; forming a first plastic encapsulation layer on one side of the second rewiring structure, the first plastic encapsulation layer covering the first conductive connector, the side wall of the first functional chip and the side wall of the pressure supply chip; forming a first rewiring structure on the side of the first plastic encapsulation layer away from the second rewiring structure, the first rewiring structure being electrically connected to the front of the first functional chip, and the first conductive connector being electrically connected to the first rewiring structure; providing a second functional chip, flipping the second functional chip on the side of the first rewiring structure away from the second rewiring structure and electrically connecting it to the first rewiring structure.

[0020] Optionally, it also includes: providing a digital signal processing chip; flipping the digital signal processing chip on the side of the first rewiring structure away from the second rewiring structure, with the front of the digital signal processing chip facing the first rewiring structure and electrically connected to the first rewiring structure.

[0021] Optionally, the method further includes: setting a first heat conduction layer on the back side of the digital signal processing chip; setting a second heat conduction layer on the back side of the second function chip; providing a heat sink, setting the heat sink across the digital signal processing chip and the second function chip, and the heat sink is in contact with the first heat conduction layer and the second heat conduction layer.

[0022] Optionally, the material of the first heat-conducting layer includes thermal grease or thermal silica gel; the material of the second heat-conducting layer includes thermal grease or thermal silica gel.

[0023] Optionally, the radiator includes a serrated fin radiator, a water-cooled radiator or a heat pipe radiator.

[0024] Optionally, a solder ball is provided and soldered to a side of the second redistribution structure facing away from the first redistribution structure, and the solder ball is electrically connected to the second redistribution structure.

[0025] Optionally, the first functional chip is an electrical chip, and the second functional chip is an optical chip; the second functional chip includes a second optical coupling structure, and a side portion of the second functional chip is exposed to the second optical coupling structure.

[0026] Optionally, the method for preparing the semiconductor packaging structure further includes: providing an optical fiber, arranging one end section of the optical fiber toward the side of the second functional chip, and arranging the optical fiber relative to the second optical coupling structure of the second functional chip.

[0027] Optionally, the first functional chip is an optical chip, and the second functional chip is an electrical chip; the first functional chip includes a first optical coupling structure, and the front side of the first functional chip is exposed to the first optical coupling structure; the projection of the second functional chip on the first rewiring structure and the projection of the first functional chip on the first rewiring structure are staggered; the preparation method of the semiconductor packaging structure also includes: forming an optical channel that penetrates the first rewiring structure in the first rewiring structure, and the optical channel is located above the first optical coupling structure and on the outside of the second functional chip; providing an optical fiber, and setting one end of the optical fiber in the optical channel and opposite to the first optical coupling structure.

[0028] Optionally, it also includes: forming a first sub-package unit to an Nth sub-package unit, the first sub-package unit to the Nth sub-package unit are located on the side of the second rewiring structure away from the first rewiring structure, and N is an integer greater than or equal to 1; the step of forming the kth sub-package unit includes: forming a k+2th rewiring structure; forming a k+1th conductive connector, the k+1th conductive connector is located on one side of the k+2 rewiring structure and is electrically connected to the k+2 rewiring structure; forming a kth functional chip unit, the kth functional chip unit is located between the k+2 rewiring structure and the second rewiring structure, and the k+1th conductive connector is located on the side of the kth functional chip unit; forming a k+1th plastic encapsulation layer, the k+1th plastic encapsulation layer is located between the k+2 rewiring structure and the second rewiring structure and covers the kth functional chip unit and the k+1th conductive connector; k is an integer greater than or equal to 1 and less than or equal to N.

[0029] Optionally, when N is greater than or equal to 2, the first sub-package unit to the Nth sub-package unit are stacked vertically; the j+1th sub-package unit is located on the side of the jth sub-package unit away from the second rewiring structure; j is an integer greater than or equal to 1 and less than or equal to N-1; in the step of forming the k+1th conductive connector, the k+1th conductive connector is also electrically connected to the k+1th rewiring structure; in the step of forming the kth functional chip unit, the kth functional chip unit is located between the k+2th rewiring structure and the k+1th rewiring structure; in the step of forming the k+1th plastic encapsulation layer, the k+1th plastic encapsulation layer is located between the k+2th rewiring structure and the k+1th rewiring structure.

[0030] Optionally, the kth functional chip unit includes one or a combination of the kth additional electrical chip and the kth additional voltage supply chip.

[0031] Optionally, the method further includes: providing a solder ball, soldering the solder ball to a side of the (N+2)th redistribution structure away from the second redistribution structure, wherein the solder ball is electrically connected to the (N+2)th redistribution structure.

[0032] The technical solution of the present invention has the following advantages:

[0033] The semiconductor package structure of the present invention reduces the size of the semiconductor package and improves integration density by packaging the first function chip and the pressure supply chip back-to-back between the first and second rewiring structures. Furthermore, the back-to-back connection of the pressure supply chip to the first function chip reduces parasitic inductance and resistance in the pressure supply path, thereby reducing voltage drop and noise. Furthermore, the first and second function chips are electrically connected via the first rewiring structure, reducing the interconnect length between the first and second function chips and improving transmission bandwidth.

[0034] The device further includes a digital signal processing chip located on a side of the first rewiring structure facing away from the second rewiring structure, with the front of the digital signal processing chip facing the first rewiring structure and electrically connected to the first rewiring structure. The digital signal processing chip is electrically connected to the first function chip or the second function chip via the first rewiring structure, thereby reducing the interconnection length between the digital signal processing chip and the first function chip or the second function chip and improving the transmission bandwidth.

[0035] Furthermore, the present invention further comprises: a first heat-conducting layer located on the back side of the digital signal processing chip; a second heat-conducting layer located on the back side of the second functional chip; and a heat sink spanning the digital signal processing chip and the second functional chip, the heat sink being in contact with the first heat-conducting layer and the second heat-conducting layer. In the semiconductor package structure of the present invention, the digital signal processing chip is exposed outside the sub-package unit, and a heat sink is disposed above it, thereby improving heat dissipation. The heat sink spans the digital signal processing chip and the second functional chip, creating a larger heat dissipation area and further enhancing heat dissipation.

[0036] Furthermore, the kth functional chip unit includes one or a combination of a kth additional electrical chip and a kth additional voltage supply chip. Two kth additional electrical chips are packaged back-to-back in the kth sub-package unit, or a kth additional electrical chip and a kth additional voltage supply chip are packaged back-to-back in the kth sub-package unit. Compared to a three-dimensional packaging structure in which a single chip is embedded and then stacked via fan-out, the number of interfaces between the redistribution structure and the sub-package units is reduced by approximately half, effectively preventing warping caused by thermal stress.

[0037] The method for preparing the semiconductor packaging structure of the present invention reduces the size of the semiconductor packaging structure and improves the integration density and transmission bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a semiconductor package structure according to another embodiment of the present invention;

[0041] Figure 3 A schematic diagram of a semiconductor packaging structure of several sub-packaging units of the present invention;

[0042] Figure 4 A schematic diagram of a conventional semiconductor packaging structure based on a plurality of sub-packaging units of a single chip package;

[0043] Figure 5 Schematic diagram of the process of preparing a semiconductor packaging structure of the present invention;

[0044] Figures 6 to 16 It is a structural schematic diagram of the semiconductor packaging structure of the present invention during the preparation process. DETAILED DESCRIPTION

[0045] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0046] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0047] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0048] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0049] Example 1

[0050] This embodiment provides a semiconductor packaging structure, such as Figure 1 As shown, including:

[0051] a second rewiring structure 12; a first functional chip 21 and a pressure supply chip 23 located on one side of the second rewiring structure 12, the pressure supply chip 23 being flipped on one side of the second rewiring structure 12, and the first functional chip 21 being mounted on the side of the pressure supply chip 23 away from the second rewiring structure 12; a first plastic encapsulation layer 31 located on one side of the second rewiring structure 12 and covering the side walls of the first functional chip 21 and the side walls of the pressure supply chip 23; a first conductive connector 41 located on the side of the first functional chip 21 and the pressure supply chip 23 and passing through the first plastic encapsulation layer 31; a first rewiring structure 11 located on the side of the first plastic encapsulation layer 31 away from the second rewiring structure 12, the first rewiring structure 11 being electrically connected to the front of the first functional chip 21, and the first conductive connector 41 being electrically connected to the first rewiring structure 11 and the second rewiring structure 12; a second functional chip 22 being flipped on the side of the first rewiring structure 11 away from the second rewiring structure 12 and electrically connected to the first rewiring structure 11.

[0052] The semiconductor package structure of this embodiment reduces the size of the semiconductor package and improves integration density by packaging the first function chip 21 and the pressure supply chip 23 back-to-back between the first rewiring structure 11 and the second rewiring structure 12. Furthermore, the back-to-back connection of the pressure supply chip 23 to the first function chip 21 reduces the parasitic inductance and resistance in the pressure supply path, thereby reducing voltage drop and noise. Furthermore, the first function chip 21 and the second function chip 22 are electrically connected via the first rewiring structure 11, reducing the interconnect length between them and improving transmission bandwidth.

[0053] In one embodiment, Figure 1 As shown, the first function chip 21 is an electrical chip, and the second function chip 22 is an optical chip. The second function chip 22 includes a second optical coupling structure 221, and the second optical coupling structure 221 is exposed on the side of the second function chip 22. Specifically, the semiconductor package structure further includes an optical fiber 5, with one end of the optical fiber 5 facing the side of the second function chip 22 and arranged opposite the second optical coupling structure 221.

[0054] In one embodiment, Figure 2 As shown, the first function chip 21 is an optical chip, and the second function chip 22 is an electrical chip. The first function chip 21 includes a first optical coupling structure 211, with the first optical coupling structure 211 exposed on the front of the first function chip 21. The projection of the second function chip 22 on the first rewiring structure 11 and the projection of the first function chip 21 on the first rewiring structure 11 are offset. The first rewiring structure 11 includes an optical channel 110 that runs through the first rewiring structure 11. The optical channel 110 is located above the first optical coupling structure 211 and outside the second function chip 22. Specifically, the semiconductor package structure further includes an optical fiber 5, one end of which is disposed in the optical channel 110 and opposite to the first optical coupling structure 211.

[0055] This embodiment further includes: a digital signal processing chip 24, which is located on a side of the first rewiring structure 11 facing away from the second rewiring structure 12, with the front of the digital signal processing chip 24 facing the first rewiring structure 11 and electrically connected to the first rewiring structure 11. The digital signal processing chip 24 is electrically connected to the first function chip 21 or the second function chip 22 via the first rewiring structure 11, thereby reducing the interconnection length between the digital signal processing chip 24 and the first function chip 21 or the second function chip 22 and improving the transmission bandwidth.

[0056] This embodiment further includes: a first heat-conducting layer 61 located on the back side of the digital signal processing chip 24; a second heat-conducting layer 62 located on the back side of the second functional chip 22; and a heat sink 7 spanning the digital signal processing chip 24 and the second functional chip 22, the heat sink 7 being in contact with the first heat-conducting layer 61 and the second heat-conducting layer 62. In the semiconductor packaging structure of the present invention, the digital signal processing chip 24 is exposed outside the sub-package unit, and a heat sink 7 is disposed above it, thereby improving the heat dissipation effect. The heat sink spans the digital signal processing chip and the second functional chip, thereby forming a larger heat dissipation area and further improving the heat dissipation effect. Specifically, the material of the first heat-conducting layer 61 includes thermal grease or thermal silica gel; the material of the second heat-conducting layer 62 includes thermal grease or thermal silica gel. Specifically, the heat sink 7 includes a serrated fin heat sink, a water-cooled heat sink, or a heat pipe heat sink.

[0057] In one embodiment, the device further includes: a solder ball 8 , which is located on a side of the second redistribution structure 12 away from the first redistribution structure 11 and is electrically connected to the second redistribution structure 12 .

[0058] In one embodiment, it also includes: a first sub-packaging unit to an Nth sub-packaging unit located on the side of the second rewiring structure 12 away from the first rewiring structure 11, where N is an integer greater than or equal to 1; the kth sub-packaging unit includes: a k+2th rewiring structure; a kth functional chip unit located between the k+2th rewiring structure and the second rewiring structure 12; a k+1th plastic encapsulation layer located between the k+2th rewiring structure and the second rewiring structure 12 and covering the kth functional chip unit; a k+1th conductive connector located on the side of the kth functional chip unit and penetrating the k+1th plastic encapsulation layer, the k+1th conductive connector being electrically connected to the k+2th rewiring structure; k is an integer greater than or equal to 1 and less than or equal to N.

[0059] In one embodiment, when N is greater than or equal to 2, the first sub-package unit to the Nth sub-package unit are stacked vertically; the j+1th sub-package unit is located on the side of the jth sub-package unit away from the second rewiring structure 12; j is an integer greater than or equal to 1 and less than or equal to N-1; the kth functional chip unit is located between the k+2th rewiring structure and the k+1th rewiring structure; the k+1th plastic encapsulation layer is located between the k+2th rewiring structure and the k+1th rewiring structure; and the k+1th conductive connector is also electrically connected to the k+1th rewiring structure.

[0060] In one embodiment, the kth functional chip unit includes one or a combination of the kth additional electrical chip and the kth additional voltage supply chip. In a specific embodiment, when N is equal to 2, as Figure 3As shown, the semiconductor package structure further includes a first sub-package unit N1 and a second sub-package unit N2. Two additional electronic chips are packaged back-to-back in the first sub-package unit N1, or one additional electronic chip and one additional voltage supply chip are packaged; two additional electronic chips are packaged back-to-back in the second sub-package unit N2, or one additional electronic chip and one additional voltage supply chip are packaged. In a specific embodiment, when N is equal to 4, as shown in FIG. Figure 4 As shown, the semiconductor package structure further includes a first sub-package unit N1, a second sub-package unit N2, a third sub-package unit N3, and a fourth sub-package unit N4. An additional electrical chip or an additional voltage supply chip is packaged in each of the first sub-package unit N1, the second sub-package unit N2, the third sub-package unit N3, and the fourth sub-package unit N4. Figure 3 The structure of packaging two chips back to back in a sub-package unit is compared with Figure 4 In the structure of the single-chip package, the number of redistribution structures and sub-package unit interfaces is reduced by about half, effectively avoiding warping caused by thermal stress.

[0061] In one embodiment, the system further includes: a solder ball 8 , which is located on a side of the (N+2)th redistribution structure away from the second redistribution structure 12 and is electrically connected to the (N+2)th redistribution structure.

[0062] Example 2

[0063] This embodiment provides a method for preparing a semiconductor packaging structure, the flow chart is as follows Figure 5 As shown, the following steps are included:

[0064] Step S1: forming a second redistribution structure 12;

[0065] Step S2: forming a first conductive connecting member 41 on one side of the second redistribution structure 12 and electrically connecting the first conductive connecting member 41 to the second redistribution structure 12;

[0066] Step S3: providing a first function chip 21 and a pressure supply chip 23, flip-mounting the pressure supply chip 23 on one side of the second redistribution structure 12, and mounting the first function chip upright on the side of the pressure supply chip facing away from the second redistribution structure, with the first conductive connector 41 located on the sides of the first function chip 21 and the pressure supply chip 23;

[0067] Step S4: forming a first plastic encapsulation layer 31 on one side of the second redistribution structure 12 , wherein the first plastic encapsulation layer 31 covers the first conductive connector 41 , the sidewall of the first functional chip 21 , and the sidewall of the voltage supply chip 23 ;

[0068] Step S5: forming a first redistribution structure 11 on the side of the first plastic encapsulation layer 31 away from the second redistribution structure 12, wherein the first redistribution structure 11 is electrically connected to the front surface of the first functional chip 21, and the first conductive connector 41 is electrically connected to the first redistribution structure 11;

[0069] Step S6 : providing a second function chip 22 , flip-chipping the second function chip 22 on a side of the first re-distribution structure 11 away from the second re-distribution structure 12 and electrically connecting the second function chip 22 to the first re-distribution structure 11 .

[0070] The following combination Figures 6 to 16 Provide a detailed introduction.

[0071] refer to Figure 6 , prepare temporary bonding carrier 9.

[0072] refer to Figure 7 , forming a second redistribution structure 12 on the temporary bonding carrier 9. The process of forming the second redistribution structure 12 includes an electroplating process and a photolithography process.

[0073] refer to Figure 8 A first conductive connecting member 41 is formed on one side of the second redistribution structure 12 by an electroplating process and is electrically connected to the second redistribution structure 12 .

[0074] refer to Figure 9 The pressure supply chip 23 is flip-chip mounted on the second rewiring structure 12 by high-precision flip-chip on the side of the second rewiring structure 12 facing away from the temporary bonding carrier 9, and the first functional chip 21 is mounted upright on the side of the pressure supply chip 23 facing away from the second rewiring structure 12, and the first conductive connecting member 41 is located on the side of the first functional chip 21 and the pressure supply chip 23.

[0075] refer to Figure 10 A first plastic encapsulation layer 31 is formed on one side of the second redistribution structure 12. The first plastic encapsulation layer 31 covers the first conductive connector 41, the sidewalls of the first functional chip 21, and the sidewalls of the voltage supply chip 23. After forming the first plastic encapsulation layer 31, the first plastic encapsulation layer 31 is thinned to the corresponding position.

[0076] refer to Figure 11 A first redistribution structure 11 is formed on the side of the first plastic encapsulation layer 31 facing away from the second redistribution structure 12. The first redistribution structure 11 is electrically connected to the front surface of the first functional chip 21, and the first conductive connector 41 is electrically connected to the first redistribution structure 11. The process of forming the first redistribution structure 11 includes electroplating and photolithography.

[0077] refer to Figure 12, providing a second function chip 22, flip-mounting the second function chip 22 on a side of the first rewiring structure 11 facing away from the second rewiring structure 12 and electrically connecting the first rewiring structure 11. In one embodiment, the present invention further comprises: providing a digital signal processing chip 24; flip-mounting the digital signal processing chip 24 on a side of the first rewiring structure 11 facing away from the second rewiring structure 12, with the front side of the digital signal processing chip 24 facing the first rewiring structure 11 and electrically connecting the first rewiring structure 11.

[0078] refer to Figure 13 , remove the temporary bonding carrier 9.

[0079] refer to Figure 14 , provide a solder ball 8, and solder the solder ball 8 to the side of the second redistribution structure 12 away from the first redistribution structure 11, so that the solder ball 8 is electrically connected to the second redistribution structure 12.

[0080] refer to Figure 15 In one embodiment, the system further includes: disposing a first heat-conducting layer 61 on the back side of the digital signal processing chip 24; disposing a second heat-conducting layer 62 on the back side of the second function chip 22; and providing a heat sink 7, which is disposed across the digital signal processing chip 24 and the second function chip 22, and is in contact with the first heat-conducting layer 61 and the second heat-conducting layer 62. Specifically, the material of the first heat-conducting layer 61 includes thermal grease or thermal silica gel; the material of the second heat-conducting layer 62 includes thermal grease or thermal silica gel. Specifically, the heat sink 7 includes a serrated fin heat sink, a water-cooled heat sink, or a heat pipe heat sink.

[0081] refer to Figure 16 In one embodiment, the first functional chip 21 is an electrical chip, and the second functional chip 22 is an optical chip. The second functional chip 22 includes a second optical coupling structure 221, and the side of the second functional chip 22 is exposed to the second optical coupling structure 221. Specifically, the method for preparing the semiconductor package structure further includes providing an optical fiber 5, positioning one end of the optical fiber 5 toward the side of the second functional chip 22, and positioning the optical fiber 5 opposite the second optical coupling structure 221 of the second functional chip 22 to complete the coupling of the optical fiber 5.

[0082] In other embodiments, the first function chip 21 is an optical chip, and the second function chip 22 is an electrical chip; the first function chip 21 includes a first optical coupling structure 211, with the front surface of the first function chip 21 exposing the first optical coupling structure 211; the projection of the second function chip 22 on the first rewiring structure 11 and the projection of the first function chip 21 on the first rewiring structure 11 are offset; the method for manufacturing the semiconductor package structure further includes: forming an optical channel 110 in the first rewiring structure 11 that penetrates the first rewiring structure 11, the optical channel 110 being located above the first optical coupling structure 211 and outside the second function chip 22. Specifically, the method for manufacturing the semiconductor package structure further includes: providing an optical fiber 5, and disposing one end of the optical fiber 5 in the optical channel 110 and opposite the first optical coupling structure 211.

[0083] refer to Figure 3 In one embodiment, it also includes: forming a k+1th conductive connector, the k+1th conductive connector is located on one side of the k+2th rewiring structure and is electrically connected to the k+2th rewiring structure; forming a kth functional chip unit, the kth functional chip unit is located between the k+2th rewiring structure and the second rewiring structure 12, and the k+1th conductive connector is located on the side of the kth functional chip unit; forming a k+1th plastic encapsulation layer, the k+1th plastic encapsulation layer is located between the k+2th rewiring structure and the second rewiring structure 12 and covers the kth functional chip unit and the k+1th conductive connector; k is an integer greater than or equal to 1 and less than or equal to N. Figure 3 The first sub-package unit N1 and the second sub-package unit N2 are shown. The first sub-package unit N1 includes a third rewiring structure, a first functional chip unit, a second plastic packaging layer and a second conductive connector. The second sub-package unit N2 includes a fourth rewiring structure, a second functional chip unit, a third plastic packaging layer and a third conductive connector.

[0084] In one embodiment, when N is greater than or equal to 2, the first sub-package unit to the Nth sub-package unit are stacked vertically; the j+1th sub-package unit is located on the side of the jth sub-package unit away from the second rewiring structure 12; j is an integer greater than or equal to 1 and less than or equal to N-1; in the step of forming the k+1th conductive connector, the k+1th conductive connector is also electrically connected to the k+1th rewiring structure; in the step of forming the kth functional chip unit, the kth functional chip unit is located between the k+2th rewiring structure and the k+1th rewiring structure; in the step of forming the k+1th plastic encapsulation layer, the k+1th plastic encapsulation layer is located between the k+2th rewiring structure and the k+1th rewiring structure. Figure 3 The kth function chip in the system is a back-to-back combination of two chips. Figure 4In a specific embodiment, the kth functional chip is a single chip. In a specific embodiment, the Nth sub-package unit is formed first, and then the N-1th sub-package unit to the first sub-package unit are formed in sequence on one side of the Nth sub-package unit.

[0085] In one embodiment, the method further includes: providing a solder ball 8, and soldering the solder ball 8 to a side of the (N+2)th redistribution structure away from the second redistribution structure 12, wherein the solder ball 8 is electrically connected to the (N+2)th redistribution structure.

[0086] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: Secondary wiring structure; A first function chip and a pressure supply chip located on one side of the second rewiring structure, wherein the pressure supply chip is flip-chip mounted on one side of the second rewiring structure, and the first function chip is mounted on the side of the pressure supply chip away from the second rewiring structure; a first plastic packaging layer located on one side of the second redistribution structure and covering a side wall of the first functional chip and a side wall of the pressure supply chip; a first conductive connector located on the sides of the first function chip and the pressure supply chip and penetrating the first plastic packaging layer; a first redistribution structure located on a side of the first plastic encapsulation layer facing away from the second redistribution structure, the first redistribution structure being electrically connected to the front surface of the first functional chip, and the first conductive connector being electrically connected to the first redistribution structure and the second redistribution structure; A second functional chip is flip-chip mounted on a side of the first redistribution structure away from the second redistribution structure and electrically connected to the first redistribution structure.

2. The semiconductor package structure according to claim 1, wherein: The first function chip is an electrical chip, and the second function chip is an optical chip; the second function chip includes a second optical coupling structure, and a side portion of the second function chip exposes the second optical coupling structure; The semiconductor packaging structure further includes an optical fiber, wherein a cross section of one end of the optical fiber faces the side of the second functional chip and is arranged opposite to the second optical coupling structure.

3. The semiconductor package structure according to claim 1, wherein: The first function chip is an optical chip, and the second function chip is an electrical chip; the first function chip includes a first optical coupling structure, and the first optical coupling structure is exposed on the front of the first function chip; the projection of the second function chip on the first rewiring structure and the projection of the first function chip on the first rewiring structure are staggered; The first rewiring structure has an optical channel running through the first rewiring structure, and the optical channel is located above the first optical coupling structure and outside the second functional chip; The semiconductor packaging structure further includes an optical fiber, one end of which is disposed in the optical channel and opposite to the first optical coupling structure.

4. The semiconductor package structure according to claim 1, wherein: Also includes: The digital signal processing chip is located on a side of the first rewiring structure away from the second rewiring structure, and the front side of the digital signal processing chip faces the first rewiring structure and is electrically connected to the first rewiring structure.

5. The semiconductor package structure according to claim 4, wherein: Also includes: a first heat conducting layer located on the back side of the digital signal processing chip; a second heat conducting layer located on the back side of the second function chip; a heat sink spanning the digital signal processing chip and the second function chip, the heat sink being in contact with the first heat conducting layer and the second heat conducting layer; The material of the first heat-conducting layer includes thermal grease or thermal silica gel; the material of the second heat-conducting layer includes thermal grease or thermal silica gel; The radiator includes a serrated fin radiator, a water-cooled radiator or a heat pipe radiator.

6. The semiconductor package structure according to claim 1, wherein: Also includes: A solder ball is located on a side of the second redistribution structure away from the first redistribution structure and is electrically connected to the second redistribution structure.

7. The semiconductor package structure according to claim 1, wherein: Also includes: the first sub-package unit to the Nth sub-package unit located on a side of the second redistribution structure away from the first redistribution structure, where N is an integer greater than or equal to 1; The kth sub-packaging unit includes: a k+2th rewiring structure; a kth functional chip unit located between the k+2th rewiring structure and the second rewiring structure; a k+1th plastic encapsulation layer located between the k+2th rewiring structure and the second rewiring structure and covering the kth functional chip unit; a k+1th conductive connector located on the side of the kth functional chip unit and penetrating the k+1th plastic encapsulation layer, the k+1th conductive connector being electrically connected to the k+2th rewiring structure; k is an integer greater than or equal to 1 and less than or equal to N.

8. The semiconductor package structure according to claim 7, wherein: When N is greater than or equal to 2, the first sub-package unit to the Nth sub-package unit are vertically stacked; the j+1th sub-package unit is located on a side of the jth sub-package unit away from the second redistribution structure; j is an integer greater than or equal to 1 and less than or equal to N-1; The kth functional chip unit is located between the k+2th rewiring structure and the k+1th rewiring structure; the k+1th plastic encapsulation layer is located between the k+2th rewiring structure and the k+1th rewiring structure; and the k+1th conductive connector is also electrically connected to the k+1th rewiring structure. The kth functional chip unit includes one or a combination of the kth additional electrical chip and the kth additional voltage supply chip; The system further includes: a solder ball, wherein the solder ball is located on a side of the (N+2)th redistribution structure away from the second redistribution structure and is electrically connected to the (N+2)th redistribution structure.

9. A method for preparing a semiconductor packaging structure, characterized in that: include: forming a second redistribution structure; forming a first conductive connecting member on one side of the second redistribution structure and electrically connected to the second redistribution structure; Providing a first function chip and a pressure supply chip, flip-mounting the pressure supply chip on one side of the second redistribution structure, and mounting the first function chip on the side of the pressure supply chip facing away from the second redistribution structure, with the first conductive connector being located on the sides of the first function chip and the pressure supply chip; forming a first plastic encapsulation layer on one side of the second redistribution structure, wherein the first plastic encapsulation layer covers the first conductive connector, the side wall of the first functional chip, and the side wall of the voltage supply chip; forming a first redistribution structure on a side of the first plastic encapsulation layer away from the second redistribution structure, the first redistribution structure being electrically connected to the front surface of the first functional chip, and the first conductive connector being electrically connected to the first redistribution structure; A second function chip is provided. The second function chip is flip-chip mounted on a side of the first redistribution structure away from the second redistribution structure and is electrically connected to the first redistribution structure.

10. The method for preparing a semiconductor package structure according to claim 9, wherein: Also includes: Provide digital signal processing chips; The digital signal processing chip is flipped onto a side of the first rewiring structure away from the second rewiring structure, with the front side of the digital signal processing chip facing the first rewiring structure and electrically connected to the first rewiring structure.

11. The method for preparing a semiconductor package structure according to claim 10, wherein: Also includes: A first heat conducting layer is provided on the back of the digital signal processing chip; a second heat conducting layer is provided on the back of the second function chip; Providing a heat sink, and placing the heat sink across the digital signal processing chip and the second function chip, wherein the heat sink is in contact with the first heat conduction layer and the second heat conduction layer; The material of the first heat-conducting layer includes thermal grease or thermal silica gel; the material of the second heat-conducting layer includes thermal grease or thermal silica gel; The radiator includes a serrated fin radiator, a water-cooled radiator or a heat pipe radiator.

12. The method for preparing a semiconductor package structure according to claim 9, wherein: A solder ball is provided and soldered to a side of the second redistribution structure facing away from the first redistribution structure, wherein the solder ball is electrically connected to the second redistribution structure.

13. The method for preparing a semiconductor package structure according to claim 9, wherein: The first function chip is an electrical chip, and the second function chip is an optical chip; the second function chip includes a second optical coupling structure, and a side portion of the second function chip is exposed to the second optical coupling structure; The method for preparing the semiconductor packaging structure further includes: providing an optical fiber, arranging one end section of the optical fiber toward the side of the second functional chip, and arranging the optical fiber relative to the second optical coupling structure of the second functional chip.

14. The method for preparing a semiconductor package structure according to claim 9, wherein: The first function chip is an optical chip, and the second function chip is an electrical chip; the first function chip includes a first optical coupling structure, and the front surface of the first function chip is exposed to the first optical coupling structure; the projection of the second function chip on the first rewiring structure and the projection of the first function chip on the first rewiring structure are staggered; The method for manufacturing the semiconductor package structure further includes: forming an optical channel penetrating the first redistribution structure in the first redistribution structure, wherein the optical channel is located above the first optical coupling structure and outside the second functional chip; An optical fiber is provided, and one end of the optical fiber is arranged in the optical channel and opposite to the first optical coupling structure.

15. The method for preparing a semiconductor package structure according to claim 9, wherein: Also includes: forming a first sub-package unit to an Nth sub-package unit, wherein the first sub-package unit to the Nth sub-package unit are located on a side of the second redistribution structure away from the first redistribution structure, where N is an integer greater than or equal to 1; The steps of forming the kth sub-packaging unit include: forming the k+2th rewiring structure; forming the k+1th conductive connector, the k+1th conductive connector is located on one side of the k+2 rewiring structure and is electrically connected to the k+2 rewiring structure; forming the kth functional chip unit, the kth functional chip unit is located between the k+2 rewiring structure and the second rewiring structure, and the k+1th conductive connector is located on the side of the kth functional chip unit; forming the k+1th plastic encapsulation layer, the k+1th plastic encapsulation layer is located between the k+2 rewiring structure and the second rewiring structure and covers the kth functional chip unit and the k+1th conductive connector; k is an integer greater than or equal to 1 and less than or equal to N.

16. The method for preparing a semiconductor package structure according to claim 15, wherein: When N is greater than or equal to 2, the first sub-package unit to the Nth sub-package unit are vertically stacked; the j+1th sub-package unit is located on a side of the jth sub-package unit away from the second redistribution structure; j is an integer greater than or equal to 1 and less than or equal to N-1; In the step of forming the k+1th conductive connector, the k+1th conductive connector is also electrically connected to the k+1th redistribution structure; in the step of forming the kth functional chip unit, the kth functional chip unit is located between the k+2th redistribution structure and the k+1th redistribution structure; in the step of forming the k+1th plastic encapsulation layer, the k+1th plastic encapsulation layer is located between the k+2th redistribution structure and the k+1th redistribution structure; The kth functional chip unit includes one or a combination of the kth additional electrical chip and the kth additional voltage supply chip; The method further includes providing a solder ball, soldering the solder ball to a side of the (N+2)th redistribution structure away from the second redistribution structure, wherein the solder ball is electrically connected to the (N+2)th redistribution structure.

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