Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, the array substrate comprises a substrate, a metal layer, a first signal line and a second signal line, the metal layer comprises a plurality of metal layers which are stacked on the substrate; at least part of the first signal line comprises a first metal line and a second metal line which are arranged in parallel, the first metal line and the second metal line are located in adjacent metal layers, and the metal layer where the first metal line is located or the metal layer where the second metal line is located is farther away from the substrate than other metal layers, and an insulating pad is arranged between the first metal line and the second metal line; the orthographic projection of the second signal line on the substrate at least partially overlaps the orthographic projection of the first metal line on the substrate and the orthographic projection of the second metal line on the substrate. In the above manner, the application can improve the stability of the display device and prolong the service life.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] With the development of display technology, display devices have been widely used in people's life, such as display screens of mobile phones, computers and televisions. The display device generally includes an array substrate and a light emitting device arranged on the array substrate. The array substrate usually includes pixel circuits and peripheral circuits arranged in a matrix. In the design of the array substrate, a laminated structure is sometimes used to design the metal trace to reduce the impedance of the metal trace, that is, the metal trace includes two parts respectively located on two adjacent metal layers, and at this time, the two metal layers are directly connected. When other metal traces are arranged below the laminated metal layer, water vapor is easily accumulated at the trench of the metal line, and when water vapor and oxygen invade, the metal line at the trench is eroded, and the erosion easily extends along the metal line. When the erosion extends to the laminated metal layer, because there is no insulating layer between the laminated metal layers, the erosion is more serious, and even the display area is eroded to cause display abnormalities. SUMMARY

[0003] The technical problem solved by the present application is to provide an array substrate and a display panel, which can improve the stability of the display panel and prolong the service life.

[0004] To solve the above technical problems, one technical solution adopted by the present application is to provide an array substrate, which includes a substrate, a metal layer, a first signal line and a second signal line, the metal layer includes a plurality of metal layers laminated on the substrate; at least part of the first signal line includes a first metal line and a second metal line arranged in parallel, the first metal line and the second metal line are located on adjacent metal layers, and the metal layer where the first metal line is located or the metal layer where the second metal line is located is farther away from the substrate than other metal layers, and an insulating pad is arranged between the first metal line and the second metal line; the metal layer where the second signal line is located is closer to the substrate than the metal layer where the first signal line is located, and the orthogonal projection of the second signal line on the substrate at least partially overlaps the orthogonal projection of the first metal line on the substrate and the orthogonal projection of the second metal line on the substrate.

[0005] Among them, the array substrate includes a first region and a second region, the orthogonal projection of the first region on the substrate overlaps the orthogonal projection of the display area of the display panel on the substrate, the orthogonal projection of the second region on the substrate overlaps the orthogonal projection of the non-display area of the display panel on the substrate, and the first metal line and the second metal line are located in the second region.

[0006] Among them, the insulating pad is a plurality of insulating pads, the plurality of insulating pads are arranged in an array, and the distribution density of the insulating pads gradually decreases in the direction from the second region to the first region.

[0007] The insulating pad is integrally arranged, a plurality of through holes are arranged on the surface of the insulating pad, the distribution density of the through holes gradually increases from the second region to the first region, and the first metal line and the second metal line are electrically connected through the through holes.

[0008] The material of the insulating pad is one or a mixture of both of silicon nitride and silicon oxide.

[0009] The array substrate includes a data driving circuit, the first signal line is connected to the data driving circuit, the first metal line and the second metal line are located in the peripheral region, and the regions where the first metal line and the second metal line are located are adjacent to the data driving circuit.

[0010] The first signal line is a power line, and the power line includes a VDD signal line or a VSS signal line.

[0011] The metal layer includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are stacked on the substrate; the power line located in the first region is arranged on the third metal layer; the power line located in the second region includes the first metal line and the second metal line, the first metal line is arranged on the third metal layer, and the second metal line is arranged on the fourth metal layer.

[0012] The metal layer includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are stacked on the substrate; the second signal line is a data line, the data line located in the first region is arranged on the third metal layer; and the data line located in the second region is arranged on the first metal layer and / or the second metal layer.

[0013] The array substrate further includes at least two dams which are arranged at intervals on the side of the metal layer away from the substrate, and the dams are arranged around the first region.

[0014] To solve the above technical problems, another technical solution adopted by the present application is to provide a display panel, which includes a plurality of light emitting devices and the array substrate of any one of the above.

[0015] The present application has the following advantages: Different from the prior art, the present application provides a scheme in which an insulating pad is arranged between the metal lines in the stack, when water vapor and oxygen invade, the insulating pad can block the water and oxygen erosion path, reduce the diffusion of erosion, improve the stability of the array substrate, and prolong the service life. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a circuit structure schematic diagram of the array substrate in the embodiment of the present application;

[0017] Figure 2 is a top perspective structure schematic diagram of the array substrate in the embodiment of the present application;

[0018] Figure 3 is a schematic diagram of the arrangement of insulating pads in an array substrate in an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of the arrangement of insulating pads in an array substrate in an embodiment of the present application;

[0020] Figure 5 is a schematic diagram of the perspective structure of an array substrate in an embodiment of the present application;

[0021] Figure 6 is a schematic diagram of the perspective structure of a display panel in the prior art. DETAILED DESCRIPTION

[0022] To make the objectives, technical solutions and effects of the present application clearer and more explicit, the present application is further described in detail below with reference to the accompanying drawings and embodiments.

[0023] The present application provides a display panel, which comprises an array substrate and a plurality of light emitting devices arranged on the array substrate. The display panel comprises a display area and a non-display area; the plurality of light emitting devices are arranged in the display area.

[0024] Please refer to Figure 1 , Figure 1 is a schematic diagram of the circuit structure of an array substrate in an embodiment of the present application. The array substrate comprises a first area and a second area, the first area is the projection area of the light emitting devices of the display panel on the array substrate, and the second area is the peripheral area surrounding the first area. Or, the orthographic projection of the first area on the substrate coincides with the orthographic projection of the display area of the display panel on the substrate, and the orthographic projection of the second area on the substrate coincides with the orthographic projection of the non-display area of the display panel on the substrate. The array substrate comprises a plurality of pixel circuits, a plurality of signal lines and a peripheral circuit.

[0025] The plurality of pixel circuits are arranged in the first area of the array substrate, each pixel circuit is connected with one light emitting device of the display panel and is used to drive the corresponding light emitting device to emit light. The plurality of pixel circuits are arranged in the first area of the array substrate in a predetermined rule, and each pixel circuit is connected with one or more corresponding signal lines. The pixel circuit comprises a transistor, for example, a thin film transistor (TFT) with large current passing capacity and good device stability. According to different designs of the pixel circuit, the number of transistors included in each pixel circuit can be adjusted and changed according to the specific design. For example, it can include seven transistors and one storage capacitor.

[0026] The array substrate includes a plurality of scan lines (Scan) and a plurality of data lines (Data). The plurality of scan lines can extend in the same direction and are arranged at intervals. The plurality of data lines can also extend in the same direction and are arranged at intervals. The extension direction of the scan lines intersects the extension direction of the data lines. Each pixel circuit is connected to at least one scan line and one data line. The scan line can provide a switching signal to the pixel circuit, and the data line can provide a gray scale signal to the pixel circuit. The array substrate can further include a power supply line, including a VDD signal line and a VSS signal line, for providing a power supply signal to the pixel circuit.

[0027] The peripheral circuit is arranged in the second region of the array substrate. The peripheral circuit includes a timing controller, a data driving circuit, a scan driving circuit, etc. The peripheral region can be provided with a data driving circuit, a scan driving circuit, etc. The data driving circuit can provide a data signal to the pixel circuit through the plurality of data lines DL. The scan driving circuit can provide a scan signal to the pixel circuit through the plurality of scan lines G1.

[0028] The scan driving circuit can be arranged on opposite sides of the first region (for example, on the left and right sides of the first region), and the data driving circuit can be arranged on one side of the display region (for example, on the upper or lower side of the first region). Each signal line can extend from the first region to the second region to connect the corresponding pixel circuit and the peripheral circuit.

[0029] The plurality of signal lines can be the scan lines, the data lines, the power supply lines, etc. described above. The plurality of signal lines extend in the first region and are led out to the second region to be connected to different peripheral circuits and pixel circuits.

[0030] In order to reduce the impedance, a thicker metal line or a plurality of parallel metal lines can be selected to set the signal line, for example, two layers of metal lines can be arranged in parallel. Since there is no insulating layer between the stacked metal lines, when water vapor or oxygen invades, the corrosion is easy to spread. Especially when the area of the stacked metal lines is large, or other metal wires are arranged below the stacked metal lines, the corrosion will be more serious, causing display abnormalities.

[0031] Therefore, the array substrate provided by the present application includes a substrate and a plurality of metal layers stacked on the substrate. The array substrate includes at least a first signal line and a second signal line. The first signal line and the second signal line are arranged on different metal layers, and the metal layer where the second signal line is arranged is closer to the substrate than the metal layer where the first signal line is arranged.

[0032] Specifically, the at least partial first signal line includes a first metal line and a second metal line arranged in parallel, the first metal line and the second metal line are located in adjacent metal layers, and the metal layer where the first metal line is located or the metal layer where the second metal line is located is farther away from the substrate than other metal layers, and an insulating pad is arranged between the first metal line and the second metal line; the orthogonal projection of the second signal line on the substrate at least partially overlaps the orthogonal projection of the first metal line on the substrate and the orthogonal projection of the second metal line on the substrate.

[0033] By arranging the first signal line as a plurality of metal lines in parallel, the impedance on the first signal line can be reduced. When the first metal line and the second metal line are stacked and arranged in parallel, the first metal line and the second metal line are usually arranged on two adjacent metal layers respectively, and the two metal layers are directly attached to realize the connection between the metal lines. In this case, since there is no insulating layer between the two metal layers, when water vapor and oxygen invade, the corrosion is easy to spread. Based on this, the embodiments provided in the present application are arranged with an insulating pad between the first metal line and the second metal line, which can block the corrosion path of water and oxygen when they invade, and protect the array substrate.

[0034] In an embodiment, the array substrate includes a substrate, and a semiconductor layer, a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3) stacked on the substrate. The semiconductor layer includes an active layer of a plurality of transistors; the first metal layer includes at least a gate electrode of the plurality of transistors and a first capacitor plate of a storage capacitor; the second metal layer includes at least a second capacitor plate of the storage capacitor; and the third metal layer includes at least a source / drain electrode of the plurality of transistors. The first metal layer, the second metal layer, and the third metal layer further include signal lines arranged thereon, each signal line extending from a first region to a second region to connect corresponding pixel circuits and peripheral circuits.

[0035] In an embodiment, the array substrate includes a first signal line, which can be a first power supply line. The first power supply line is a VDD signal line, which extends from a first region to a second region and is electrically connected to a data driving circuit in the second region to provide power supply signals for the pixel circuits and the data driving circuit.

[0036] In the embodiments provided in the present application, the VDD signal line is arranged on the third metal layer (M3) and extends in a first direction and can extend from the first region to the second region. In the second region, in order to reduce the impedance of the VDD signal line, a thicker metal line is usually selected to make the VDD signal line, or a plurality of metal lines in parallel are selected to arrange the VDD signal line.

[0037] The technical scheme provided in the present application selects a parallel multi-wire mode to set the VDD signal line in the second region, that is, the VDD signal line in the second region at least includes a first metal wire and a second metal wire arranged in parallel. Specifically, the array substrate further includes a fourth metal layer (M4); the first metal wire can be arranged in the third metal layer (M3), and the second metal wire can be arranged in the fourth metal layer (M4). That is, the VDD signal line includes a first part located in the first region and a second part located in the second region. The VDD signal line located in the first region can only have one metal wire; and the VDD signal line located in the second region can have two metal wires stacked, so that the impedance can be reduced.

[0038] In an embodiment, the array substrate includes a second signal line, which is a data line, the data line extending from the first region to the second region and being electrically connected to the data driving circuit in the second region; that is, the data line includes a first part (referred to as a data signal line) located in the first region and a second part (referred to as a fanout1 signal line) located in the second region.

[0039] In the first region, the plurality of data lines are located in the third metal layer (M3) and extend along the first direction; when the data line is transmitted from the first region to the second region, the data line will be changed to the gate layer (the first metal layer) from the source-drain layer (the third metal layer), and the data transmission is performed through the metal layer of the gate layer. In addition, in the existing panel structure, the data driving circuit is often arranged on the back of the array substrate, and the data line needs to be bent to be connected with the driving chip. Since the metal material of the existing gate layer is generally molybdenum, and the metal material of the source-drain layer is titanium-aluminum-titanium, the metal flexibility of titanium-aluminum-titanium is smaller than that of molybdenum, and it is not easy to break when bending. Therefore, when the data line is transmitted to the bending region, it needs to be changed to the source-drain layer with better metal flexibility again; and after the data line passes through the bending region, it is changed to the gate layer again. That is, in the second region, the data line will undergo twice cross-layer changing.

[0040] In an embodiment, with the development of display technology, the requirements for display panels are getting higher and higher, for example, smaller frames are required, so that the frame is narrowed, and the wiring requirement of the frame (that is, the second region) is higher. In order to reduce the frame, in the second region, when the data line is changed to the gate layer, a part of the data line can be arranged in the first metal layer (that is, the gate layer), and part of the data line can be arranged in the second metal layer by using the second metal layer, so as to further reduce the wiring difficulty on the basis of reducing the frame.

[0041] The array substrate can further include a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer. The first insulating layer is arranged between the semiconductor layer and the first metal layer, the second insulating layer is arranged between the first metal layer and the second metal layer, the third insulating layer is arranged between the second metal layer and the third metal layer, and the fourth insulating layer is arranged between the third metal layer and the fourth metal layer. In some examples, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be inorganic insulating layers.

[0042] In one aspect, the region corresponding to the VDD signal line in the fourth insulating layer is completely missing, that is, no insulating layer is arranged between the first metal line and the second metal line of the VDD signal line, but direct bonding is performed for electrical connection. In this case, when water vapor and oxygen invade, because there is no insulating layer between the first metal line and the second metal line, water and oxygen will diffuse along the metal line and invade the inside of the array substrate, causing damage to the substrate. On the one hand, in the horizontal direction, the corrosion will extend to the inside (the first region) along the structure of the metal line; on the other hand, in the vertical direction, it will also extend to other film layers, and the fourth metal layer is closer to the light emitting device layer. If the fourth metal layer is corroded, it will further extend to the upper layer of the display panel and extend to the light emitting device layer, causing corrosion to the light emitting device and display abnormalities.

[0043] For details, please refer to Figure 6 , Figure 6 is a top perspective structural schematic diagram of a display panel in the prior art. The first metal line and the second metal line of the first signal line (VDD) are arranged on the third metal layer (M3) and the fourth metal layer (M4) respectively, and the second signal line (fanout1) is arranged on the first metal layer (M1) and the second metal layer (M2). The orthographic projection of the second signal line on the substrate at least partially overlaps the orthographic projection of the first metal line on the substrate and the orthographic projection of the second metal line on the substrate, that is, the second signal line is located below the first signal line.

[0044] In the process of forming the line structure, generally, a whole layer of metal film layer is first formed, and the metal film layer is etched to form a line structure. For example, a whole layer of first metal film layer is formed on the first insulating layer, the first metal film layer is etched to form a line structure, and the metal line at least includes the second signal line. Then, a second insulating layer is formed on the first metal film layer, and then a second metal film layer is formed on the second insulating layer, and etched to form a second layer of metal line structure. In this way, the design of all line layers is completed.

[0045] The first insulating layer is a flat film layer, and after etching the first metal layer, the first insulating layer has a metal line in a partial region. After forming the second insulating layer, because of the design of the metal line, the second insulating layer is no longer a flat film layer, and the insulating layer material is generally inorganic material, which cannot fill the height difference caused by the metal line. In this way, the second metal layer, the third insulating layer, the third metal layer and the fourth insulating layer are no longer flat film layers, but are uneven with the metal line structure. Because the metal line is convex, when the insulating layer is deposited thereon, the trench adjacent to the metal line will affect the tightness of the insulating layer, causing water vapor to easily accumulate at the trench, corroding the metal line, and the corrosion will extend along the extension of the metal line to the inside of the display panel. On the one hand, in the horizontal direction, it will extend to the inside (the first region) along the structure of the metal line; on the other hand, in the vertical direction, it will also extend to other metal layers. When it extends to the third metal layer, because there is no insulating layer between the third metal layer and the fourth metal layer, the fourth metal layer is more easily corroded. If the fourth metal layer is corroded, it will further extend to the upper layer of the display panel and corrode the light emitting device layer, causing display abnormalities.

[0046] Please refer to Figure 2 , Figure 2 is a schematic diagram of a top perspective structure of an array substrate in an embodiment of the present application. In this embodiment, an insulating pad is arranged between the first metal line and the second metal line to block the water and oxygen corrosion path, reduce damage to the array substrate, and improve the stability thereof.

[0047] Specifically, the metal layer where the first metal line is located and the metal layer where the second metal line is located are not completely attached, but are electrically connected in a partial region, and the insulating pad is arranged in a partial region.

[0048] In an embodiment, the insulating pad is made of inorganic insulating material, for example, silicon nitride, silicon oxide, etc. On the one hand, it can play an insulating supporting role to improve the flatness of the array substrate, and on the other hand, the insulating pad of inorganic material can have good blocking ability to water and oxygen, break the water and oxygen corrosion path, and protect the stability of the array substrate.

[0049] Please refer to Figure 3 , Figure 3 is a schematic diagram of the arrangement of the insulating pad in the array substrate in an embodiment of the present application. In this embodiment, a plurality of insulating pads are arranged in an array in the stacked metal line region of the first signal line.

[0050] Further, because if water oxygen invades, the water oxygen entering path is from the edge to the interior, in order to be able to block water oxygen invasion to a greater extent, protect the internal circuit; the arrangement density of the insulating pads is more dense closer to the edge area, that is, along the direction from the second area to the first area, the distribution density of the insulating pads gradually becomes smaller. In this way, the water oxygen invasion path can be extended to a greater extent, and the internal circuit is protected. In other embodiments, the insulating pads can also be arranged in a staggered manner.

[0051] Please refer to Figure 4 , Figure 4 is a schematic diagram of the arrangement of insulating pads in the array substrate in an embodiment of the present application. In this embodiment, a plurality of insulating pads are connected as a whole. In this way, it can also be understood that an insulating layer is first formed between the two metal line layers, then the insulating layer is perforated, and the electrical connection between the two metal line layers is realized through the holes, and the remaining area forms a plurality of insulating pads connected as a whole. In this way, the invasion of water oxygen can be blocked to a greater extent. Further, along the direction from the second area to the first area, the distribution density of the through holes gradually becomes larger.

[0052] Please refer to Figure 5 , Figure 5 is a schematic diagram of the top perspective structure of the array substrate in an embodiment of the present application. In this embodiment, a dam is further provided on the array substrate; the dam extends around the first area to block water vapor and oxygen. The dam can be provided in multiple (i.e., dam1 and dam2), that is, a plurality of blocking walls can be formed around the first area to protect the line structure of the first area. The dam can be made of inorganic materials, for example, it can be silicon nitride, silicon oxide, etc.

[0053] In the above, the scheme provided by the present application can well block the invasion of water oxygen by providing insulating pads between the stacked metal lines, and improve the performance of the array substrate.

[0054] In other embodiments, the array substrate further includes other signal lines, for example, the first metal layer further includes: a plurality of scan lines extending along the second direction, a first control signal line, a second control signal line, and a light emitting control line; the third metal layer further includes a second power supply line, the second power supply line is a VSS signal line, a reference voltage line, and an initial voltage line. The first control signal line, the second control signal line, the light emitting control line, the reference voltage line, and the initial voltage line all extend along the second direction. The second direction is perpendicular to the first direction, the first direction can be a vertical direction, and the second direction can be a horizontal direction.

[0055] The scheme provided by the present application can be applied to any signal line area that needs to be provided with stacked metal lines. For example, the VSS signal can also include a metal line located in the third metal layer and a metal line located in the fourth metal layer, the two metal line layers are stacked, and an insulating pad can also be provided between the two metal lines.

[0056] In an embodiment, the array substrate includes a first region and a second region, the second region being a peripheral region surrounding the first region; the array substrate is rectangular, and the peripheral region includes a first peripheral region and a second peripheral region respectively located at left and right sides of the first region, and a third peripheral region and a fourth peripheral region respectively located at upper and lower sides of the first region. Generally, the data driving circuit is arranged in the fourth peripheral region, i.e. generally located at the outer frame of the array substrate. Preferably, an insulating pad is arranged between the stacked metal layers in the fourth peripheral region. Figure 1

[0057] The array substrate can be used for various display modes, and can be an array substrate of an organic light-emitting diode (OLED) display panel, or an array substrate of a liquid crystal display (LCD) panel, a micro light-emitting diode (Micro-LED), a mini light-emitting diode (Mini LED), or the like. In this document, the term "array substrate" can refer to a finished array substrate after all array process steps are completed, or can refer to a semi-finished array substrate at any process stage of the array step.

[0058] Based on this, the present application further provides a display panel, which includes an array substrate and a plurality of light-emitting devices, and the plurality of light-emitting devices are arranged on the array substrate. The array substrate can be the array substrate of any of the above embodiments, and the light-emitting device can be an OLED or the like.

[0059] Further, the present application further provides a display device, which includes a driving chip and a display panel, and the driving chip provides driving signals for the display panel. The display panel can be the display panel of any of the above embodiments.

[0060] The above description is merely an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.​

Claims

1. An array substrate, characterized in that, include: A substrate, and a multilayer metal layer stacked on the substrate; The first signal line, at least a portion of the first signal line includes a first metal line and a second metal line arranged in parallel, the first metal line and the second metal line are located in adjacent metal layers, and the metal layer where the first metal line is located or the metal layer where the second metal line is located is farther away from the substrate than other metal layers, and an insulating pad is provided between the first metal line and the second metal line. The second signal line, wherein the orthographic projection of the second signal line on the substrate at least partially coincides with the orthographic projection of the first metal line on the substrate and the orthographic projection of the second metal line on the substrate; The array substrate includes a first region and a second region. The orthographic projection of the first region onto the substrate coincides with the orthographic projection of the display area of ​​the display panel onto the substrate. The orthographic projection of the second region onto the substrate coincides with the orthographic projection of the non-display area of ​​the display panel onto the substrate. The first metal line and the second metal line are located in the second region. The array of insulating pads is arranged such that the distribution density of the insulating pads gradually decreases along the direction from the second region to the first region.

2. The array substrate according to claim 1, characterized in that, The insulating pad is integrally formed, and multiple through holes are provided on the surface of the insulating pad. The distribution density of the through holes gradually increases from the second region to the first region. The first metal wire and the second metal wire are electrically connected through the through holes.

3. The array substrate according to claim 1, characterized in that, The insulating pad is made of one or a mixture of silicon nitride and silicon oxide.

4. The array substrate according to claim 1, characterized in that, The first signal line is a power line, which includes a VDD signal line or a VSS signal line.

5. The array substrate according to claim 4, characterized in that, The metal layer includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked on the substrate; The power line located in the first region is disposed on the third metal layer, and the power line located in the second region includes the first metal line and the second metal line, wherein the first metal line is disposed on the third metal layer and the second metal line is disposed on the fourth metal layer.

6. The array substrate according to claim 4, characterized in that, The metal layer includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked on the substrate; Wherein, the second signal line is a data line, and the data line located in the first region is disposed on the third metal layer; the data line located in the second region is disposed on the first metal layer and / or the second metal layer.

7. The array substrate according to claim 1, characterized in that, The array substrate further includes: At least two dams are spaced apart on the side of the metal layer away from the substrate, and the dams are arranged around the first region.

8. A display panel, characterized in that, include: A plurality of light-emitting devices, and an array substrate as described in claims 1-7, wherein the plurality of light-emitting devices are disposed on the array substrate.

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