Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate, a method for preparing the same, and a display device. The display substrate includes a display area, a peripheral area located around the display area, a binding area, and a plurality of binding pins. The plurality of binding pins include at least one first power pin and at least one second power pin, the first power pin being used to transmit a high power signal to the display area, and the second power pin being used to transmit a low power signal to the display area. Within a plane perpendicular to the display substrate, the display substrate includes a base substrate, a drive circuit layer and sub-pixels disposed on the base substrate, the drive circuit layer including a semiconductor layer. The peripheral area also includes at least one ground line coupled to the semiconductor layer, the distance between the ground line and the binding pin being greater than the gap width between two adjacent binding pins. The present disclosure avoids the risk of short circuits caused by offset binding of a flexible circuit board, thereby improving the product's service life and yield.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display developed in recent years, and silicon-based organic light-emitting diode (OLED) is one of them. Silicon-based OLED has the characteristics of high pixel density (Pixels Per Inch, PPI), small size, and high contrast. It is made using the mature integrated circuit complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process, which realizes active addressing of pixels and can realize the preparation of various functional circuits including timing control (TCON) circuit, overcurrent protection (Over Current Protection, OCP) circuit on silicon-based substrate, which is conducive to reducing the system volume and achieving lightweight. Silicon-based OLED is widely used in the field of virtual reality and augmented reality near-eye display, especially in augmented reality (AR) / virtual reality (VR) head-mounted display devices. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a display area and a peripheral area located around the display area, wherein the display area includes a plurality of sub-pixels, the peripheral area includes a binding area, the binding area includes a plurality of binding pins, the plurality of binding pins including at least one first power pin and at least one second power pin, the first power pin being configured to transmit a high power signal to the display area, and the second power pin being configured to transmit a low power signal to the display area;

[0005] In a plane perpendicular to the display substrate, the display substrate includes a base substrate and a driving circuit layer and sub-pixels arranged on the base substrate, and the driving circuit layer includes a semiconductor layer; the peripheral area also includes at least one ground line, which is coupled to the semiconductor layer, and the distance between the ground line and the binding pin is greater than the gap width between two adjacent binding pins.

[0006] In an exemplary embodiment, the display substrate further includes a plurality of conductive layers disposed on the semiconductor layer;

[0007] The ground wire is provided on the same layer as at least one of the plurality of conductive layers;

[0008] The plurality of binding pins are arranged on the same layer as at least one of the plurality of conductive layers.

[0009] In an exemplary embodiment, the binding pins and the ground line are arranged on the same layer.

[0010] In an exemplary embodiment, the binding area is located on a first side of the peripheral area, the ground line includes at least a first portion, the first portion is also located on the first side of the peripheral area, and the distance between the first portion and the binding pin is greater than the width of 50 sub-pixels along the first direction.

[0011] In an exemplary embodiment, the bonding area is located on a first side of the peripheral area, and the ground line is located on any one, two, or three sides of the peripheral area except the first side.

[0012] In an exemplary embodiment, the distance between the ground line and the display area is greater than the width of 50 sub-pixels along the first direction.

[0013] In an exemplary embodiment, a width of the binding pin along the first direction is greater than a gap width between two adjacent binding pins.

[0014] In an exemplary embodiment, the sub-pixel includes a first electrode, an organic light-emitting layer, and a second electrode, wherein the first electrode includes at least one transparent conductive oxide layer;

[0015] Each of the binding pins includes a first sublayer and a second sublayer, the first sublayer is arranged on the same layer as at least one of the multiple conductive layers, the second sublayer is arranged on the same layer as the transparent conductive oxide layer, the first sublayer and the second sublayer are connected in parallel and electrically connected, and the second sublayer is located on the side of the first sublayer away from the substrate.

[0016] In an exemplary embodiment, the multiple binding pins are arranged along a first direction, the width of the second sublayer along the first direction is the same or approximately the same as the width of the first sublayer along the first direction, the length of the second sublayer along the second direction is between 1 times and 1.2 times the length of the first sublayer along the second direction, and the first direction intersects the second direction.

[0017] In an exemplary embodiment, the first electrode further comprises at least one metal conductive layer;

[0018] The display substrate also includes multiple test circuits, which are arranged on a side of the multiple binding pins close to the display area. The test circuits are not connected to the binding pins, and the distance between the test circuits and the binding pins is greater than the gap width between two adjacent binding pins.

[0019] In an exemplary embodiment, the display substrate further includes a protective electrode, which is arranged on a side of the plurality of test circuits away from the base substrate, the orthographic projection of the protective electrode on the base substrate covers the orthographic projection of the test circuit on the base substrate, and the plurality of protective electrodes are arranged on the same layer as the metal conductive layer.

[0020] In an exemplary embodiment, the plurality of binding pins further include at least two impedance testing pins, and the at least two impedance testing pins are located on both sides of the plurality of binding pins along the first direction;

[0021] The first power pin includes a first sub-pin and a second sub-pin, the second power pin includes a third sub-pin and a fourth sub-pin, the third sub-pin and the fourth sub-pin are respectively arranged adjacent to the impedance test pins on both sides of the multiple binding pins along the first direction, the first sub-pin is located on the side of the third sub-pin away from the impedance test pin, and the second sub-pin is located on the side of the fourth sub-pin away from the impedance test pin.

[0022] In an exemplary embodiment, the plurality of binding pins further includes at least one signal pin, and the at least one signal pin is located between the first sub-pin and the second sub-pin.

[0023] In a second aspect, an embodiment of the present disclosure provides a display device comprising a display substrate as described in any one of the above items.

[0024] In a third aspect, an embodiment of the present disclosure provides a method for preparing a display substrate, wherein the display substrate includes a display area and a peripheral area located around the display area, wherein the peripheral area includes a binding area, and the preparation method includes:

[0025] A driving circuit layer is formed on a base substrate, wherein the driving circuit layer in the binding area includes a plurality of binding pins, wherein the plurality of binding pins include at least one first power pin and at least one second power pin, wherein the first power pin is used to transmit a high power signal to the display area, and the second power pin is used to transmit a low power signal to the display area; the driving circuit layer in the peripheral area includes at least one ground line, and the driving circuit layer in the display area includes a semiconductor layer, wherein the ground line is coupled to the semiconductor layer, and the distance between the ground line and the binding pin is greater than the distance between two adjacent binding pins;

[0026] Sub-pixels are formed on the driving circuit layer.

[0027] The display substrate, preparation method thereof, and display device provided by the embodiments of the present disclosure avoid the risk of short circuit caused by the offset of the flexible circuit board binding by making the distance between the ground wire and the binding pin greater than the distance between two adjacent binding pins. While ensuring that the substrate size remains unchanged, the electrical connection can be reliable, which has the advantages of extending the service life of the product and improving the yield and integration of the product. In addition, there is no voltage drop between the binding pin and the ground wire. During anodic etching, chloride ions are not easily accumulated at the binding pin, thereby improving the problem of the binding pin being easily corroded during anodic etching, thereby solving the problem of poor electrical connection performance of the binding pin and the reliability of the flexible circuit board module that cannot meet the requirements, and improving the disadvantage of the display substrate having a short service life in harsh environments.

[0028] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0030] Figure 1a and Figure 1b Schematic diagram of the structure of the display substrate in two examples of the embodiments of the present disclosure;

[0031] Figure 2 This is a schematic diagram showing a substrate connected to a flexible circuit board in an example of an embodiment of the present disclosure;

[0032] Figure 3 A partial cross-sectional view of a display area in an example of an embodiment of the present disclosure;

[0033] Figure 4 It is a plan view schematic diagram of a display substrate in an example of an embodiment of the present disclosure;

[0034] Figure 5 This is a structural diagram of a binding area in an example of an embodiment of the present disclosure;

[0035] Figure 6 For display area and Figure 5 Comparison diagram of the cross section in the AA direction. DETAILED DESCRIPTION

[0036] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0037] This application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0038] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0039] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0040] In the drawings, the sizes of components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0041] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components. The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures can refer to the general design.

[0042] Traditional silicon-based OLED display substrates feature a common ground line on the side of the bonding area away from the display area. This ground line connects the entire silicon substrate. However, this design creates a risk of short circuits when the flexible circuit board (FPC) bonding is offset. Furthermore, during the anode preparation process, chloride (CI) ions are present in the indium tin oxide (ITO) etching solution. These accumulated chloride ions corrode the bonding pins, degrading their electrical connection properties. This increases the contact resistance between the FPC and the silicon substrate, and can even cause a short circuit. Improving the reliability of FPC modules is a current concern for the industry.

[0043] An embodiment of the present disclosure provides a display substrate, including a display area and a peripheral area located around the display area, the display area including a plurality of sub-pixels, the peripheral area including a binding area, the binding area including a plurality of binding pins, the plurality of binding pins including at least one first power pin and at least one second power pin, the first power pin being used to transmit a high power signal to the display area, and the second power pin being used to transmit a low power signal to the display area; in a plane perpendicular to the display substrate, the display substrate includes a base substrate and a driving circuit layer and sub-pixels arranged on the base substrate, the driving circuit layer including a semiconductor layer; the peripheral area also includes at least one ground wire, the ground wire is coupled to the semiconductor layer, and the distance between the ground wire and the binding pin is greater than the distance between two adjacent binding pins.

[0044] The display substrate provided by the disclosed embodiment avoids the risk of short circuits caused by offset binding of the flexible circuit board by making the distance between the ground wire and the binding pin greater than the distance between two adjacent binding pins. This ensures reliable electrical connection while maintaining the substrate size, thus extending the service life of the product and improving the product yield and integration. In addition, there is no voltage drop between the binding pin and the ground wire, so chloride ions are less likely to accumulate at the binding pin, thereby improving the problem of the binding pin being easily corroded during ITO anode etching, thereby solving the problem of poor electrical connection performance of the binding pin and the reliability of the FPC module that cannot meet the requirements, and improving the shortcoming of the display substrate's short service life in harsh environments.

[0045] The display substrate of the present disclosure is described below using two examples.

[0046] Figure 1a and Figure 1b Schematic diagram of the structure of the display substrate in the second embodiment of the present disclosure. Figure 1a and Figure 1b As shown, the display substrate includes a display area 101 and a peripheral area 102 located around the display area 101. The peripheral area 102 includes a bonding area 103. The display area 101 includes a plurality of sub-pixels 105 arranged in an array. In a plane perpendicular to the display substrate, the display substrate comprises a silicon-based substrate 11, a drive circuit layer disposed on the silicon-based substrate 11, and sub-pixels 105 disposed on the drive circuit layer. The bonding area 103 includes a plurality of bonding pins.

[0047] Figure 1a and Figure 1bIn the structure shown, the length of the display substrate along the first direction X is greater than the length along the second direction Y. That is, in this example, a binding area 103 is set on one side of the long side of the display substrate, and a long-side pin layout is adopted. The area on one side of the long side is larger, which is convenient for placing circuit traces and chip probing (CP) structures, etc., and is conducive to the matching design of the optical-mechanical structure.

[0048] Figure 1a and Figure 1b In the illustrated structure, multiple binding pins include impedance test pins 1034. Impedance test pins 1034 are located on either side of the binding area 103 along the first direction X, with two on each side. These pins are used to monitor the electrical contact between the display substrate and the FPC. They also improve mechanical properties and resist harsh external environments. Moisture entering from the sides first reaches the impedance test pins 1034, extending the moisture entry path and helping to extend service life. Inside the impedance test pins 1034, a second power pin 1032 and a first power pin 1031 are located, one on each side. The first power pin 1031 is used to input a high power signal (VDD) to the display area 101, while the second power pin 1032 is used to input a low power signal (VSS) to the display area 101. This design not only ensures signal transmission but also improves reliability. The binding pin located between the two first power pins 1031 is a signal pin 1033, used to transmit drive signals.

[0049] In some exemplary embodiments, Figure 1a and Figure 1b As shown, the first power pin 1031 includes a first sub-pin 10311 and a second sub-pin 10312, the second power pin 1032 includes a third sub-pin 10321 and a fourth sub-pin 10322, the third sub-pin 10321 and the fourth sub-pin 10322 are respectively arranged adjacent to the impedance test pins 1034 on the left and right sides, the first sub-pin 10311 is located on the side of the third sub-pin 10321 away from the impedance test pin 1034, and the second sub-pin 10312 is located on the side of the fourth sub-pin 10322 away from the impedance test pin 1034.

[0050] In some exemplary embodiments, Figure 1a and Figure 1b As shown, the peripheral area 102 further includes at least one ground line 1021 , and a distance d1 between the ground line 1021 and the binding pin is greater than a gap width d2 between two adjacent binding pins.

[0051] Figure 2This is a schematic diagram of the display substrate connected to a flexible circuit board in an example of an embodiment of the present disclosure. The silicon-based substrate 11 is bonded to the flexible circuit board 20 via the bonding pins in the bonding area 103. The flexible circuit board 20 electrically connects the display substrate to the external circuit. Subpixels 105 are disposed on the silicon-based substrate 11. Each subpixel 105 includes multiple light-emitting elements, which emit light when driven by corresponding first and second electrodes. These light-emitting elements may be OLEDs. Cover glass 18 covers the subpixels 105. Light emitted by the multiple light-emitting elements can be transmitted through the cover glass 18 and then emitted. Cover glass 18 protects the light-emitting elements. The dimensions of cover glass 18 are larger than those of the display area 101 and smaller than those of the silicon-based substrate 11. A certain distance is reserved between the four sides of cover glass 18 and the silicon-based substrate 11 to facilitate connection to the optomechanical structure. To ensure light transmission, cover glass 18 can be made of a transparent material, such as plain glass with high transmittance.

[0052] In this example, the size of the silicon-based substrate 11 is 11.1mm*9.5mm, the cover glass 18 is 0.1mm smaller than the silicon substrate 11 on one side, and is 10.9mm*9.3mm. The size of the display area is 0.5mm smaller than the cover glass 18 on one side.

[0053] Figure 3 This is a partial cross-sectional view of the display area in an example of an embodiment of the present disclosure. Figure 3 As shown, in a plane perpendicular to the display substrate, the display area 101 includes: a driving circuit layer (not shown) sequentially disposed on a silicon-based substrate 11, a sub-pixel 105, a first thin-film encapsulation layer 15, a color film layer 16, a second thin-film encapsulation layer 17, and a cover glass 18. Sub-pixel 105 includes multiple light-emitting elements. Sub-pixel 105 includes: a first electrode 12, an organic light-emitting layer 13, and a second electrode 14 sequentially disposed on the driving circuit layer.

[0054] The first electrode 12 can be made of indium tin oxide (ITO), so it has the characteristics of high transmittance and high work function. The organic light-emitting layer 13 can be made of organic materials. Under the action of the voltage or current applied by the first electrode 12 of the light-emitting element and the second electrode 14 of the light-emitting element, holes and electrons are excited in the organic material to form excitons, and light is emitted after the electrons and holes recombine. The second electrode 14 of the light-emitting element can be made of metal materials or alloy materials, such as metals or alloys such as magnesium and silver. A first thin film encapsulation layer 15 is provided on the upper side of the second electrode 14, and a color film layer 16 is provided corresponding to the organic light-emitting layer 13, and can include RGB color films to achieve color display of the emitted light. A second thin film encapsulation layer 17 and a cover glass 18 are sequentially provided on the upper side of the color film layer 16, which can protect the color film layer 16. The second thin film encapsulation layer 17 can be made of a material with good sealing properties, such as an organic material, or a combination of one or more inorganic materials such as silicon oxide and silicon nitride. The second thin film encapsulation layer 17 cooperates with the first thin film encapsulation layer 15 to effectively block water vapor and oxygen, thereby helping to extend the service life of the display substrate.

[0055] Figure 4 FIG. 1 is a plan view of a display substrate in an example of an embodiment of the present disclosure. Figure 4 As shown, the orthographic projection of the organic light-emitting layer 13 on the silicon-based substrate 11 overlaps the orthographic projection of the first electrode 12 of the light-emitting element on the silicon-based substrate 11. The orthographic projection of the color film layer 16 on the silicon-based substrate 11 overlaps the orthographic projection of the organic light-emitting layer 13 on the silicon-based substrate 11. The orthographic projection of the cover glass 18 on the silicon-based substrate 11 overlaps the orthographic projection of the color film layer 16 on the silicon-based substrate 11. From the relationship between the orthographic projections, it can be seen that a certain distance is reserved between the four sides of the cover glass 18 and the silicon-based substrate 11 to facilitate the connection of the optical and mechanical structures.

[0056] In some exemplary embodiments, the first electrode 12 may include a metal film layer and a transparent metal oxide film layer located above the metal film layer. The metal film layer may include a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence; the transparent metal oxide film layer may be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0057] In other exemplary embodiments, the first electrode 12 may include two transparent metal oxide film layers and a metal film layer located between the two transparent metal oxide film layers. The material of the transparent metal oxide film layer may be indium tin oxide or indium zinc oxide, and the material of the metal film layer may be metallic silver.

[0058] In some exemplary embodiments, the display substrate further includes a plurality of test circuits (not shown in the figures), and the plurality of test circuits are arranged on a side of the plurality of binding pins close to the display area 101. The test circuits are not connected to the binding pins, and the distance between the test circuits and the binding pins is greater than the gap width d2 between two adjacent binding pins.

[0059] In some exemplary embodiments, Figure 1a 、 Figure 1b and Figure 5 As shown, the display substrate further includes multiple protection electrodes 104 disposed on a side of the multiple test circuits away from the silicon-based substrate 11. The orthographic projections of the protection electrodes 104 on the silicon-based substrate 11 overlap the orthographic projections of the test circuits on the silicon-based substrate 11. The multiple protection electrodes 104 are disposed on a side of the multiple binding pins that is close to the display area 101. The protection electrodes 104 can be fabricated in the same layer as the metal film layer of the first electrode 12 to protect the test circuits located below the protection electrodes 104, preventing laser light, ultraviolet (UV) light, and other factors present in the OLED process from affecting the characteristics of the test circuits.

[0060] In some exemplary embodiments, the protection electrode 104 may be formed in the same layer as any one or more of the first titanium layer, the aluminum layer, and the second titanium layer.

[0061] In some exemplary embodiments, Figure 1a and Figure 1b As shown, the first power pin 1031 and the second power pin 1032 are not connected to the ground line 1021 .

[0062] In this embodiment, multiple binding pins correspond one-to-one with pins on the flexible printed circuit (FPC), enabling drive signal transmission and ensuring a sufficient binding contact area. Both the first power pin 1031 and the second power pin 1032 are bound and connected to corresponding pins on the flexible printed circuit (FPC). The FPC enables electrical connection between the display substrate and the external circuit, thereby providing power signals through the external circuit.

[0063] In some exemplary embodiments, the process of forming the silicon-based substrate 11 may adopt a mature IC (Integrated Circuit) wafer process.

[0064] In some exemplary embodiments, the driving circuit layer can be prepared on the silicon-based substrate 11 by a silicon semiconductor process (such as a complementary metal oxide semiconductor (CMOS) process). The driving circuit layer may include multiple circuit units. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is located in the display area. The pixel driving circuit is connected to the scanning signal line and the data signal line respectively. The pixel driving circuit may include multiple transistors and storage capacitors. The transistor may include a control electrode, a first electrode, and a second electrode. The control electrode, the first electrode, and the second electrode may be connected to corresponding connecting electrodes respectively through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces, etc.) through the connecting electrodes.

[0065] In some exemplary embodiments, the driving circuit layer may include a semiconductor layer (not shown), and the ground line 1021 is coupled to the semiconductor layer. In this embodiment, by coupling the ground line 1021 to the semiconductor layer, the potential of the entire display substrate is controlled to be consistent with the potential of the ground line.

[0066] In some exemplary embodiments, the display substrate may include a plurality of conductive layers (not shown) disposed on the semiconductor layer;

[0067] The ground line 1021 is provided on the same layer as at least one of the plurality of conductive layers;

[0068] The plurality of binding pins are arranged on the same layer as at least one of the plurality of conductive layers.

[0069] In some exemplary embodiments, the bonding pins and the ground line 1021 are disposed on the same layer.

[0070] In some exemplary embodiments, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence on a silicon-based substrate 11, the first semiconductor layer includes an active layer of multiple polysilicon transistors, the first conductive layer includes gate electrodes of multiple polysilicon transistors and a first plate of a storage capacitor, the second conductive layer includes a second plate of the storage capacitor, the second semiconductor layer includes an active layer of multiple oxide transistors, the third conductive layer includes gate electrodes of multiple oxide transistors, the fourth conductive layer includes first and second electrodes of multiple polysilicon transistors and first and second electrodes of multiple oxide transistors, and the fifth conductive layer includes a power line or a data signal line.

[0071] In some exemplary embodiments, the ground line 1021 may be disposed on the same layer as the fifth conductive layer.

[0072] In some exemplary embodiments, the plurality of binding pins may be a single-layer structure, and the plurality of binding pins may be disposed in the same layer as at least one of the plurality of conductive layers. For example, the plurality of binding pins may be disposed in the same layer as the fifth conductive layer.

[0073] In some exemplary embodiments, Figure 1b As shown, the binding area 103 is located on the first side of the peripheral area 102, the ground line 1021 includes at least a first portion, and the first portion is also located on the first side of the peripheral area 102, and the distance d1 between the ground line 1021 and the binding pin is greater than the width of 50 sub-pixels along the first direction X.

[0074] It should be noted that the width d4 of each sub-pixel 105 along the first direction X may be between 3 μm and 8 μm. In some exemplary embodiments, the distance d1 between the ground line 1021 and the binding pin may be between the width of 100 sub-pixels along the first direction X and the width of 150 sub-pixels along the first direction X, that is, d1 may be between 100*d4 and 150*d4. For example, the distance d1 between the ground line 1021 and the binding pin may be the width of 120 sub-pixels along the first direction X, that is, d1 may be between 120*3 μm and 120*8 μm.

[0075] In some exemplary embodiments, Figure 1a As shown, the binding area 103 is located on a first side of the peripheral area 102 , and the ground line 1021 is located on any one, two, or three sides of the peripheral area 102 except the first side.

[0076] For example, the first side of the peripheral region 102 may be located on a side of the peripheral region 102 along the opposite direction of the second reverse direction Y; the second side of the peripheral region 102 may be located on a side of the peripheral region 102 along the second reverse direction Y; the third side of the peripheral region 102 may be located on a side of the peripheral region 102 along the opposite direction of the first reverse direction X; and the fourth side of the peripheral region 102 may be located on a side of the peripheral region 102 along the first reverse direction X.

[0077] In some exemplary embodiments, Figure 1a and Figure 1b As shown, the distance d3 between the ground line 1021 and the display area 101 is greater than the width of 50 sub-pixels along the first direction X.

[0078] It should be noted that the width d4 of each sub-pixel 105 along the first direction X may be between 3 μm and 8 μm. In some exemplary embodiments, the distance d1 between the ground line 1021 and the display area 101 may be between the width of 100 sub-pixels along the first direction X and the width of 150 sub-pixels along the first direction X, that is, d3 may be between 100*d4 and 150*d4. For example, the distance d3 between the ground line 1021 and the display area 101 may be between the width of 120 sub-pixels along the first direction X, that is, d3 may be between 120*3 μm and 120*8 μm.

[0079] In some exemplary embodiments, Figure 1a and Figure 1b As shown, the width W of the binding pin along the first direction X is greater than the gap width d2 between two adjacent binding pins.

[0080] In some exemplary embodiments, a sub-pixel may include a first electrode 12, an organic light-emitting layer 13, and a second electrode 14. The first electrode 12 includes at least one transparent conductive oxide layer. For example, the transparent conductive oxide layer may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0081] In some exemplary embodiments, the first electrode 12 may be an anode, and the second electrode 14 may be a cathode.

[0082] In some exemplary embodiments, Figure 5 and Figure 6 As shown, multiple binding pins can be a double-layer structure, each binding pin includes a first sublayer 103a and a second sublayer 103b, the first sublayer 103a is arranged in the same layer as at least one of the multiple conductive layers, the second sublayer 103b is arranged in the same layer as the transparent conductive oxide layer, the first sublayer 103a and the second sublayer 103b are connected in parallel and electrically connected, and the second sublayer 103b is located on the side of the first sublayer 103a away from the silicon-based substrate 11.

[0083] In the display substrate of this embodiment, while manufacturing the anode of the display area 101, the binding pins in the binding area 103 are covered by a transparent conductive oxide layer film. This makes the binding pins less susceptible to corrosion by chloride ions, thereby improving the electrical connection performance between the binding pins and the FPC, ensuring the tolerance of the FPC module in different environments, and improving the product yield.

[0084] During the binding process of silicon-based OLED display modules, the compatibility of the binding machine must be taken into consideration. The binding pins need to ensure sufficient yield and reliability during the display module binding process. In the FPC module, there needs to be sufficient contact area between the FPC and the binding pins, and there are certain area requirements for the binding pins.

[0085] In some exemplary embodiments, the plurality of binding pins are arranged along a first direction X, a width W2 of the second sublayer 103b along the first direction X is the same as or approximately the same as a width W1 of the first sublayer 103a along the first direction X, a length L2 of the second sublayer 103b along the second direction Y is between 1 and 1.2 times a length L1 of the first sublayer 103a along the second direction Y, and the first direction X intersects the second direction Y.

[0086] It should be noted that the “approximately the same” mentioned in the present disclosure means that a certain process error range is allowed between the width W2 of the second sub-layer 103b along the first direction X and the width W1 of the first sub-layer 103a along the first direction X. For example, the process error range can be between 0 and 15um.

[0087] In some exemplary embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0088] Exemplarily, the width W1 of the first sublayer 103a along the first direction X is 70um, the length L1 of the first sublayer 103a along the second direction Y is 600um, the width W2 of the second sublayer 103b along the first direction X is the same as the width W1 of the first sublayer 103a along the first direction X, and the length L2 of the second sublayer 103b along the second direction Y is 10um to 80um longer than the length L1 of the first sublayer 103a along the second direction Y.

[0089] In some exemplary embodiments, the material of the first sub-layer 103 a may be metallic copper or aluminum.

[0090] The present disclosure also provides a method for preparing a display substrate, for preparing the display substrate provided in the above embodiment. In some exemplary embodiments, the display substrate has a display area and a peripheral area located around the display area, wherein the peripheral area includes a binding area. The method for preparing the display substrate may include the following steps:

[0091] A driving circuit layer is formed on the base substrate, wherein the driving circuit layer in the binding area includes a plurality of binding pins, the plurality of binding pins including at least one first power pin and at least one second power pin, the first power pin being used to transmit a high power signal to the display area, and the second power pin being used to transmit a low power signal to the display area; the driving circuit layer in the peripheral area includes at least one ground line, the driving circuit layer in the display area includes a semiconductor layer, the ground line is coupled to the semiconductor layer, and a distance between the ground line and the binding pin is greater than a distance between two adjacent binding pins;

[0092] Sub-pixels are formed on the driving circuit layer.

[0093] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display device. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0094] In an exemplary embodiment, a process for preparing a display substrate may include the following steps:

[0095] (11) Forming a substrate. For example, the substrate may be a silicon-based substrate. The process for forming the substrate may adopt a well-established IC (Integrated Circuit) wafer process, which will not be described in detail here.

[0096] (12) Forming a driving circuit layer. The driving circuit layer can be prepared on a substrate by a silicon semiconductor process (e.g., a complementary metal oxide semiconductor (CMOS) process). The driving circuit layer can include a plurality of circuit units. The circuit units can include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line respectively. The pixel driving circuit can include a plurality of transistors and a storage capacitor. The transistor can include a control electrode, a first electrode, and a second electrode. The control electrode, the first electrode, and the second electrode can be connected to corresponding connection electrodes respectively through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (e.g., traces, etc.) through the connection electrodes.

[0097] (13) Forming a first insulating layer. In an exemplary embodiment, forming the first insulating layer pattern includes: depositing a first insulating film on the base substrate on which the aforementioned pattern is formed, and patterning the first insulating film through a patterning process to form a first insulating layer pattern covering the driving circuit layer.

[0098] (14) Forming a first electrode. In an exemplary embodiment, forming the first electrode pattern includes: depositing a first electrode material thin film on the base substrate on which the aforementioned pattern is formed, and patterning the first electrode material thin film through a patterning process to form a first electrode layer pattern disposed on the first insulating layer.

[0099] In some exemplary embodiments, the material of the first electrode may be metal or metal oxide.

[0100] In some exemplary embodiments, the first electrode may have a stacked structure.

[0101] In some exemplary embodiments, the first electrode may include a metal film layer and a transparent metal oxide film layer located above the metal film layer. The metal film layer may include a first titanium layer, an aluminum layer, and a second titanium layer sequentially stacked on the first insulating layer; the transparent metal oxide film layer may be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0102] In other exemplary embodiments, the first electrode may include two transparent metal oxide film layers and a metal film layer located between the two transparent metal oxide film layers. The material of the transparent metal oxide film layer may be indium tin oxide (ITO) or indium zinc oxide (IZO), and the material of the metal film layer may be metallic silver.

[0103] (15) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern includes: coating a pixel definition film on the base substrate forming the aforementioned structure, and forming a pixel definition layer (PDL) pattern through masking, exposure, and development processes, wherein the pixel definition layer has a pixel opening in the display area, and the pixel opening exposes at least a portion of the surface of the first electrode.

[0104] (16) An organic light-emitting layer and a second electrode pattern are formed.

[0105] In some exemplary embodiments, the subsequent preparation process may include forming a first encapsulation layer, a color filter structure layer, a second encapsulation layer, and a cover layer.

[0106] In an exemplary embodiment, the first encapsulation layer and the second encapsulation layer may be made of thin film encapsulation (TFE) to ensure that external moisture cannot enter the sub-pixels. The cover layer may be made of glass or plastic colorless polyimide.

[0107] In an exemplary embodiment, the color film structure layer may include a black matrix (BM) and a color filter (CF), the position of the color filter may correspond to the position of the light-emitting device, the black matrix may be located between adjacent color filters, and the color filter is configured to filter the white light emitted by the light-emitting device into red (R) light, green (G) light, and blue (B) light to form red sub-pixels, green sub-pixels, and blue sub-pixels.

[0108] The present disclosure also provides a display device comprising the display substrate of any of the above embodiments. In some exemplary embodiments, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. However, the present disclosure is not limited to this.

[0109] In the description of the embodiments of the present disclosure, the terms "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present disclosure.

[0110] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: The display device includes a display area and a peripheral area located around the display area, wherein the display area includes a plurality of sub-pixels, the peripheral area includes a binding area, the binding area includes a plurality of binding pins, and the plurality of binding pins include at least one first power pin and at least one second power pin, wherein the first power pin is used to transmit a high power signal to the display area, and the second power pin is used to transmit a low power signal to the display area; In a plane perpendicular to the display substrate, the display substrate includes a base substrate and a driving circuit layer arranged on the base substrate, and the driving circuit layer includes a semiconductor layer; the peripheral area also includes at least one ground wire, which is coupled to the semiconductor layer, and the distance between the ground wire and the binding pin is greater than the gap width between two adjacent binding pins.

2. The display substrate according to claim 1, wherein: The binding pins and the ground wire are arranged on the same layer.

3. The display substrate according to claim 1, wherein The binding area is located on the first side of the peripheral area, the ground line includes at least a first portion, the first portion is also located on the first side of the peripheral area, and the distance between the first portion and the binding pin is greater than the width of 50 sub-pixels along the first direction.

4. The display substrate according to claim 1, wherein The binding area is located on a first side of the peripheral area, and the ground line is located on any one side, two sides, or three sides of the peripheral area except the first side.

5. The display substrate according to claim 1, wherein The distance between the ground line and the display area is greater than the width of 50 sub-pixels along the first direction.

6. The display substrate according to claim 1, wherein: The width of the binding pin along the first direction is greater than the gap width between two adjacent binding pins.

7. The display substrate according to claim 1, wherein: The display substrate further includes a plurality of conductive layers disposed on the semiconductor layer; The ground wire is provided on the same layer as at least one of the plurality of conductive layers; The plurality of binding pins are arranged on the same layer as at least one of the plurality of conductive layers.

8. The display substrate according to claim 7, wherein: The sub-pixel includes a first electrode, an organic light-emitting layer, and a second electrode, wherein the first electrode includes at least one transparent conductive oxide layer; Each of the binding pins includes a first sublayer and a second sublayer, the first sublayer is arranged on the same layer as at least one of the multiple conductive layers, the second sublayer is arranged on the same layer as the transparent conductive oxide layer, the first sublayer and the second sublayer are connected in parallel and electrically connected, and the second sublayer is located on the side of the first sublayer away from the substrate.

9. The display substrate according to claim 8, wherein: The multiple binding pins are arranged along a first direction, the width of the second sublayer along the first direction is the same or approximately the same as the width of the first sublayer along the first direction, the length of the second sublayer along the second direction is between 1 times and 1.2 times the length of the first sublayer along the second direction, and the first direction intersects the second direction.

10. The display substrate according to claim 8, wherein The display substrate also includes multiple test circuits, which are arranged on a side of the multiple binding pins close to the display area. The test circuits are not connected to the binding pins, and the distance between the test circuits and the binding pins is greater than the gap width between two adjacent binding pins.

11. The display substrate according to claim 10, wherein: The first electrode further comprises at least one metal conductive layer; The display substrate further includes a protective electrode, which is arranged on a side of the multiple test circuits away from the base substrate. The orthographic projection of the protective electrode on the base substrate covers the orthographic projection of the test circuit on the base substrate. The multiple protective electrodes are arranged on the same layer as the metal conductive layer.

12. The display substrate according to claim 1, wherein The plurality of binding pins further include at least two impedance testing pins, and the at least two impedance testing pins are located on both sides of the plurality of binding pins along the first direction; The first power pin includes a first sub-pin and a second sub-pin, the second power pin includes a third sub-pin and a fourth sub-pin, the third sub-pin and the fourth sub-pin are respectively arranged adjacent to the impedance test pins on both sides of the multiple binding pins along the first direction, the first sub-pin is located on the side of the third sub-pin away from the impedance test pin, and the second sub-pin is located on the side of the fourth sub-pin away from the impedance test pin.

13. The display substrate according to claim 12, wherein: The plurality of binding pins further include at least one signal pin, and the at least one signal pin is located between the first sub-pin and the second sub-pin.

14. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 13.

15. A method for preparing a display substrate, characterized in that: The display substrate includes a display area and a peripheral area located around the display area, wherein the peripheral area includes a binding area. The preparation method includes: A driving circuit layer is formed on a base substrate, wherein the driving circuit layer in the binding area includes a plurality of binding pins, wherein the plurality of binding pins include at least one first power pin and at least one second power pin, wherein the first power pin is used to transmit a high power signal to the display area, and the second power pin is used to transmit a low power signal to the display area; the driving circuit layer in the peripheral area includes at least one ground line, and the driving circuit layer in the display area includes a semiconductor layer, wherein the ground line is coupled to the semiconductor layer, and the distance between the ground line and the binding pin is greater than the distance between two adjacent binding pins; Sub-pixels are formed on the driving circuit layer.

Images