Display device

Abstract

A display device is disclosed. The display device includes a substrate including a display area and a non-display area surrounding the display area; a plurality of pixels disposed in the display area; a plurality of signal lines disposed on the substrate and electrically connected to the pixels; an encapsulation layer disposed on the substrate; and a first crack sensing line disposed on the encapsulation layer in the non-display area, wherein the signal lines include gate lines and data lines, and the first crack sensing line is electrically connected to the data lines.

Description

[0001] This application is a divisional application of the invention patent application filed with the State Intellectual Property Office on May 26, 2016, entitled "Display Device" and with application number 201610357509.0. Technical Field

[0002] The technology described generally relates to a display device. Background Technology

[0003] With the increasing popularity of portable display devices, the demand for flexible display devices is growing even faster.

[0004] When substrate cracks occur during manufacturing, moisture can seep through the entire display area. This leads to degradation and eventual failure. Therefore, accurately detecting the timing and location of crack formation is crucial.

[0005] As an example, cracks can form along the edges of the thin film layer that covers the display area and the non-display area surrounding the display area.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the background of the described technology, and therefore may contain information that does not constitute prior art known in the country to a person skilled in the art. Summary of the Invention

[0007] One aspect of the invention relates to a display device that can prevent degradation of the display device caused by cracks occurring at the edge of a thin film layer (covering the display area and the non-display area that serves as the edge of the display device) by easily detecting cracks.

[0008] Another aspect is a display device comprising: a substrate configured to include a display area and a non-display area formed in a peripheral area of ​​the display area; a plurality of pixels formed in the display area of ​​the substrate; a plurality of signal lines formed in the substrate and connected to the pixels; and an encapsulation portion (or encapsulation layer) formed on the substrate, wherein the plurality of signal lines include: a plurality of gate lines and a plurality of data lines formed on the substrate, and a first data line connected to the data lines and formed at a portion overlapping with the encapsulation portion as a first crack sensing line.

[0009] The encapsulation portion can be formed in the display area and the non-display area, and the first crack sensing line can be formed in the non-display area.

[0010] The display device may also include a touch portion (or touch layer) formed on the encapsulation portion, and the first crack sensing line may be formed on the same layer as the touch wiring layer of the touch portion.

[0011] The signal lines may also include a first signal line and a second signal line formed in a non-display area of ​​the substrate. The first crack sensing line may be connected to the first data line and travel along one edge of the display area in a semi-circular shape. The data line may be connected to the first signal line via a first transistor and to the second signal line via a second transistor.

[0012] The first crack sensing line can be connected between the second signal line and the second transistor.

[0013] The display device may further include: a first gate line formed in a non-display area of ​​a substrate and connected to a first transistor; and a second gate line connected to a second transistor. When a first gate on-state voltage is supplied to the first gate line, a data line can receive a first signal from a first signal line; when a second gate on-state voltage is supplied to the second gate line, a data line can receive a second signal from the second signal line.

[0014] The second gate on-voltage can be applied after the first gate on-voltage is applied, and the first signal and the second signal can include different signals.

[0015] The display device may also include a second crack sensing line connected to a second data line in the data line, configured not to overlap with the encapsulation portion, and formed in a non-display area.

[0016] The second crack sensing line can be formed in the same layer as the gate line.

[0017] The display device may further include an insulating layer formed between the second crack sensing line and the gate line to have a contact hole for exposing a portion of the second crack sensing line, and the second crack sensing line can be connected to a second data line through the contact hole.

[0018] The second crack sensing line can be formed in the same layer as the gate line.

[0019] The signal lines may also include a first signal line and a second signal line formed in a non-display area of ​​the substrate. The first crack sensing line may be connected to the first data line and travel in a semi-circular shape along one edge of the display area. The second crack sensing line may travel in a semi-circular shape along the edge of the display area parallel to the first crack sensing line. The data line may be connected to the first signal line through a first transistor and to the second signal line through a second transistor.

[0020] The first crack sensing line can be connected between the second signal line and the second transistor, and the second crack sensing line can be connected between the second signal line and the second transistor.

[0021] Another aspect is a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a plurality of pixels formed in the display area; a plurality of signal lines formed on the substrate and electrically connected to the pixels; and an encapsulation layer formed on the substrate, wherein the signal lines include: a plurality of gate lines and a plurality of data lines formed on the substrate, and a first crack sensing line electrically connected to a first data line among the data lines and superimposed on the encapsulation layer in the depth dimension of the display device.

[0022] In the aforementioned display device, an encapsulation layer is formed in both the display area and the non-display area, wherein the first crack sensing line is formed in the non-display area. The display device further includes a touch layer, comprising touch wiring and formed on the encapsulation layer, wherein the first crack sensing line and the touch wiring of the touch layer are formed on the same layer. In the aforementioned display device, the signal lines also include a first signal line and a second signal line formed in the non-display area, wherein the first crack sensing line is electrically connected to a first data line and extends substantially in a semi-circular shape along the edge of the display area, wherein the data line is electrically connected to the first signal line via a first transistor and to the second signal line via a second transistor.

[0023] In the aforementioned display device, a first crack sensing line is electrically connected to a second signal line and a second transistor. The display device further includes: a first gate line formed in a non-display area and electrically connected to the first transistor; and a second gate line electrically connected to the second transistor, wherein a data line is configured to receive a first signal from the first signal line based on a first gate on-state voltage applied to the first gate line, and wherein a data line is configured to receive a second signal from the second signal line based on a second gate on-state voltage applied to the second gate line. In the aforementioned display device, the second gate on-state voltage is configured to be applied after the first gate on-state voltage is applied, wherein the first signal and the second signal are different.

[0024] The aforementioned display device further includes a second crack sensing line electrically connected to a second data line in the data line, wherein the second crack sensing line is formed in a non-display area and is not superimposed on the encapsulation layer in the depth dimension of the display device. In the aforementioned display device, the second crack sensing line and the gate line are formed on the same layer. The aforementioned display device further includes an insulating layer having contact holes and disposed between the second crack sensing line and the gate line, wherein the second crack sensing line is connected to the second data line via the contact holes.

[0025] In the aforementioned display device, the signal lines further include a first signal line and a second signal line formed in the non-display area. The first crack sensing line is electrically connected to the first data line and extends substantially in a semi-circular shape along the edge of the display area. The second crack sensing line extends substantially parallel to the first crack sensing line along the edge of the display area. The data line is electrically connected to the first signal line via a first transistor and to the second signal line via a second transistor. In the aforementioned display device, the first crack sensing line is electrically connected to the second signal line and the second transistor, and the second crack sensing line is electrically connected to the second signal line and the second transistor.

[0026] The aforementioned display device further includes: a first gate line formed in a non-display area and electrically connected to a first transistor; and a second gate line electrically connected to a second transistor, wherein a data line is configured to receive a first signal from a first signal line based on a first gate on-state voltage applied to the first gate line, and wherein a data line is configured to receive a second signal from a second signal line based on a second gate on-state voltage applied to the second gate line. In the aforementioned display device, the second gate on-state voltage is configured to be applied after the first gate on-state voltage is applied, wherein the first signal and the second signal are different.

[0027] In the aforementioned display device, the second crack sensing line and the gate line are formed on the same layer. In the aforementioned display device, the signal lines also include a first signal line and a second signal line formed in a non-display area of ​​the substrate. The first crack sensing line is electrically connected to a first data line and extends in a semi-circular shape along the edge of the display area. The second crack sensing line extends substantially parallel to the first crack sensing line along the edge of the display area. The data line is electrically connected to the first signal line via a first transistor and to the second signal line via a second transistor. In the aforementioned display device, the first crack sensing line is electrically connected to the second signal line and the second transistor. The second crack sensing line is electrically connected to the second signal line and the second transistor.

[0028] The aforementioned display device further includes: a first gate line formed in a non-display area of ​​the substrate and electrically connected to a first transistor; and a second gate line electrically connected to a second transistor, wherein a data line is configured to receive a first signal from a first signal line based on a first gate on-state voltage applied to the first gate line, and wherein a data line is configured to receive a second signal from a second signal line based on a second gate on-state voltage applied to the second gate line. In the aforementioned display device, the second gate on-state voltage is configured to be applied after the first gate on-state voltage is applied, wherein the first signal and the second signal include different signals. The aforementioned display device further includes: a touch layer including touch wiring and formed on an encapsulation layer, wherein a first crack sensing line is formed in the same layer as the touch wiring.

[0029] Another aspect is a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a plurality of pixels formed in the display area; an encapsulation layer formed on the substrate; a plurality of data lines formed on the substrate; and a first crack sensing line formed in the non-display area and electrically connected to the first data line in the data lines, wherein the first crack sensing line is superimposed on the encapsulation layer in the depth dimension of the display device.

[0030] The aforementioned display device further includes a second crack sensing line electrically connected to a second data line in the data line, wherein the second crack sensing line is formed in a non-display area and does not overlap with the encapsulation layer in the depth dimension of the display device. In the aforementioned display device, the second crack sensing line is further away from the first crack sensing line than the encapsulation layer.

[0031] According to at least one of the disclosed embodiments, cracks in the thin film layer covering the display area and edges of the display device can be easily detected to prevent deterioration of the display device. Attached Figure Description

[0032] Figure 1 This is a top view of a display device according to an exemplary embodiment.

[0033] Figure 2 This is a circuit diagram of a display device according to an exemplary embodiment.

[0034] Figure 3 This is a waveform diagram showing the signals of a display device according to an exemplary embodiment.

[0035] Figure 4A , Figure 4B and Figure 4C Is Figure 3 The waveform of the voltage supplied to the pixel during the first and second time periods.

[0036] Figure 5 It is shown Figure 3 The diagram shows a top view of the connection structure between the test transistor and the crack sensing line, as well as between the test transistor and the resistor.

[0037] Figure 6 It is along Figure 5 A sectional view taken by line I-I'.

[0038] Figure 7 It is along Figure 5 The sectional view taken from line II-II'.

[0039] Figure 8 It is partially shown Figure 2 The image shows a cross-sectional view of the display device.

[0040] Figure 9 This is a partial illustration according to another exemplary embodiment. Figure 2 The image shows a cross-sectional view of the display device. Detailed Implementation

[0041] In the following description, the technology will be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments of the described technology. Those skilled in the art will recognize that the described embodiments can be modified in various ways without departing from the spirit or scope of the described technology.

[0042] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Throughout the specification, the same reference numerals indicate the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly on" another element, there are no intermediate elements. In this disclosure, the term "substantially" includes completely, almost completely, or, in some applications, to any extent that would be apparent to a person skilled in the art. Furthermore, "formed on" may also mean "formed over". The term "connection" may include electrical connections.

[0043] First, refer to Figure 1 A display device according to an exemplary embodiment is described.

[0044] Figure 1 This is a top view of a display device according to an exemplary embodiment.

[0045] Reference Figure 1 The display device according to this exemplary embodiment includes a substrate SUB, an encapsulation portion EN, and a touch portion TM.

[0046] The substrate SUB is an insulating substrate comprising glass, polymer, or stainless steel. The substrate SUB can be flexible, stretchable, foldable, bendable, or rollable. Because the substrate SUB is flexible, stretchable, foldable, bendable, or rollable, the display device can be completely flexible, stretchable, foldable, bendable, or rollable. For example, the substrate SUB is formed as a flexible film comprising a resin such as polyimide.

[0047] The substrate SUB includes a display area DA for displaying an image and a non-display area NDA formed around the display area DA. Although the non-display area NDA has been described as surrounding the display area DA in this exemplary embodiment, in a display device according to another exemplary embodiment, the non-display area NDA may be formed on the opposite side of the display area DA.

[0048] The display area DA of the base SUB consists of multiple pixels. A pixel is the smallest unit used to display an image.

[0049] An encapsulation portion (or encapsulation layer) EN is formed on a substrate SUB, covering the entire display area DA and the non-display area NDA, and encapsulates the pixels of the display area DA together with the substrate SUB. The encapsulation portion EN can be formed as a thin-film encapsulation portion. The encapsulation portion EN includes an organic layer OL formed on the display area DA and an inorganic layer IL formed on the organic layer OL. According to another exemplary embodiment, the encapsulation portion EN can include one or more organic layers and one or more inorganic layers stacked alternately. For example, the inorganic layers and organic layers each include a plurality of inorganic layers and a plurality of organic layers, which can be stacked alternately. For example, the encapsulation portion EN includes at least one sandwich structure in which at least one organic layer is inserted between at least two inorganic layers.

[0050] In the following text, reference will be made to Figure 1 and Figure 2 The settings of a display device according to an exemplary embodiment are described. Figure 2 This is a circuit diagram of a display device according to an exemplary embodiment.

[0051] Reference Figure 1 and Figure 2 The display device according to this exemplary embodiment includes a display area DA having a plurality of pixels RP and a non-display area NDA formed around the display area.

[0052] The display device according to an exemplary embodiment includes a plurality of pixels RP and a plurality of signal lines formed on a substrate SUB, wherein the pixels RP are formed in a display area DA of the substrate SUB, and at least a portion of the signal lines are formed on a non-display area NDA of the substrate SUB.

[0053] The signal lines include gate lines S1-Sn and data lines D1a-Dma formed in the display area DA of the substrate SUB, and a first crack sensing line CD1, a second crack sensing line CD2, a third crack sensing line CD11, and a fourth crack sensing line CD22 formed in the non-display area NDA of the substrate SUB. It should be understood that the signal lines are not limited to these; the signal lines may also include other signal lines (not shown) disposed in the non-display area NDA.

[0054] The first crack sensing line CD1 and the second crack sensing line CD2 are formed on the same layer as the touch wiring formed at the touch portion (or touch layer) TM. The first crack sensing line CD1 and the second crack sensing line CD2 are formed on the encapsulation portion EN. The third crack sensing line CD11 and the fourth crack sensing line CD22 are formed on the same layer as a portion of the signal line (e.g., gate wiring or data wiring). The third crack sensing line CD11 and the fourth crack sensing line CD22 are formed in the non-display area NDA and at the edge of the substrate SUB that does not overlap with the encapsulation portion EN.

[0055] The non-display area NDA, which has the first crack sensing line CD1, the second crack sensing line CD2, the third crack sensing line CD11, and the fourth crack sensing line CD22, can be bent.

[0056] Data pads DP1-DPo, initialization control pads IP1, IP2, and IP3, first test control pad TP1, test voltage pads TVP1 and TVP2, initialization transistors IT1, IT2, and IT3, test transistor TT1, and resistor R are formed in the non-display area NDA of the substrate SUB. Here, "o" represents a positive integer greater than m.

[0057] Data pads DP1-DPo are connected to data lines D1a-Dma via initialization transistors IT1, IT2, and IT3. Initialization voltage can be supplied to data pads DP1-DPo at startup.

[0058] Although not shown, the display device may also include a source driver IC. In this case, data pads DP1-DPo are connected to the source driver IC. Specifically, the source driver IC can supply data voltage to the data pads DP1-DPo, so that the data voltage is supplied to the data lines D1a-Dma of the display device.

[0059] In the exemplary embodiment shown, initialization control pads IP1, IP2, and IP3, and initialization transistors IT1, IT2, and IT3 are formed. In this case, the first initialization control pad IP1 can be connected to the control electrode of the first initialization transistor IT1, the second initialization control pad IP2 can be connected to the control electrode of the second initialization transistor IT2, and the third initialization control pad IP3 can be connected to the control electrode of the third initialization transistor IT3. A first initialization signal, a second initialization signal, and a third initialization signal can be supplied to the first initialization control pad IP1, the second initialization control pad IP2, and the third initialization control pad IP3, respectively.

[0060] The first test control pad TP1 is connected to each control electrode of the test transistor TT1. Test control signals are supplied to the first test control pad TP1.

[0061] Test voltage pads TVP1 and TVP2 are connected to the first electrode of test transistor TT1. A test voltage is supplied to test voltage pads TVP1 and TVP2. The same or different test voltages can be supplied to the first test voltage pad TVP1 and the second test voltage pad TVP2. For example, the first test voltage is supplied to the first test voltage pad TVP1, and the second test voltage is supplied to the second test voltage pad. At this point, the first test voltage can be the same as or different from the second test voltage.

[0062] Initialization transistors IT1, IT2, and IT3 are connected between data lines D1a-Dma and data pads DP1-DPo. The control electrode of the first initialization transistor IT1 can be connected to the first initialization control pad IP1, the control electrode of the second initialization transistor IT2 can be connected to the second initialization control pad IP2, and the control electrode of the third initialization transistor IT3 can be connected to the third initialization control pad IP3.

[0063] For example, the control electrode of each first initialization transistor IT1 is connected to the first initialization control pad IP1, its first electrode is connected to a corresponding data line among the data lines D1a-Dma, and its second electrode is connected to a corresponding data pad among the data pads DP1-DPo. The control electrode of each second initialization transistor IT2 can be connected to the second initialization control pad IP2, its first electrode can be connected to a corresponding data line among the data lines D1a-Dma, and its second electrode can be connected to a corresponding data pad among the data pads DP1-DPo. The control electrode of each third initialization transistor IT3 can be connected to the third initialization control pad IP3, its first electrode can be connected to a corresponding data line among the data lines D1a-Dma, and its second electrode can be connected to a corresponding data pad among the data pads DP1-DPo.

[0064] Test transistor TT1 can be connected between data lines D1a-Dma and test voltage pads TVP1 and TVP2. The control electrode of test transistor TT1 is connected to the first test control pad TP1. For example, the control electrode of each test transistor TT1 is connected to the first test control pad TP1, the first electrode is connected to a corresponding test voltage pad among test voltage pads TVP1 and TVP2, and the second electrode is connected to a corresponding data line among data lines D1a-Dma. Additionally, the display device may include a first gate line and a second gate line located in the non-display area NDA, the first gate line being electrically connected to the initialization transistor, and the second gate line being electrically connected to the test transistor, such as... Figure 2 As shown in the image.

[0065] A crack sensing line can be formed between the test voltage pad and the first electrode of the test transistor TT1.

[0066] A first crack sensing line CD1 is formed between the first test voltage pad TVP1 and the first electrode of the test transistor TT1 connected to the first data line D1b. A second crack sensing line CD2 is formed between the second test voltage pad TVP2 and the first electrode of the test transistor TT1 connected to the second data line Dmb. A third crack sensing line CD11 is formed between the second test voltage pad TVP2 and the first electrode of the test transistor TT1 connected to the third data line D1a. A fourth crack sensing line CD22 is formed between the first test voltage pad TVP1 and the first electrode of the test transistor TT1 connected to the fourth data line Dma.

[0067] The first crack sensing line CD1, the second crack sensing line CD2, the third crack sensing line CD11, and the fourth crack sensing line CD22 can be formed in the non-display area NDA, which is formed outside the display area DA. For example, the first crack sensing line CD1 and the third crack sensing line CD11 are formed on the outer left side of the display area DA, and the second crack sensing line CD2 and the fourth crack sensing line CD22 are formed on the outer right side of the display area DA. Furthermore, when a gate driver (not shown) is formed in the non-display area NDA formed outside the display area DA, the first crack sensing line CD1, the second crack sensing line CD2, the third crack sensing line CD11, and the fourth crack sensing line CD22 can be formed further outward than the gate driver.

[0068] Each of the first crack sensing line CD1, the second crack sensing line CD2, the third crack sensing line CD11, and the fourth crack sensing line CD22 can be configured to travel around the outside of the display area DA.

[0069] The first crack sensing line CD1 and the third crack sensing line CD11 can be configured to travel around the outer left side of the display area DA, and the second crack sensing line CD2 and the fourth crack sensing line CD22 can be configured to travel around the outer right side of the display area DA.

[0070] Resistor R can be formed between the test voltage pads TVP1 and TVP2 and the first electrode of the test transistor TT1 that is not connected to the first crack sensing line CD1, the second crack sensing line CD2, the third crack sensing line CD11, and the fourth crack sensing line CD22. By adjusting resistor R, the test voltage difference can be compensated based on the wiring resistance of the first crack sensing line CD1, the second crack sensing line CD2, the third crack sensing line CD11, and the fourth crack sensing line CD22.

[0071] In the illustrated exemplary embodiment, test transistor TT1 and resistor R are shown as being formed in the upper portion of the non-display area NDA. Data pads DP1-DPo, initialization control pads IP1, IP2, and IP3, first test control pad TP1, test voltage pads TVP1 and TVP2, and initialization transistors IT1, IT2, and IT3 are shown as being formed in the lower portion of the non-display area NDA. However, the arrangement of pad cells, transistors, and signal lines in the non-display area NDA is not limited thereto. For example, the signal lines in the non-display area NDA may also include a first signal line (not shown) connected to data pads DP1-DPo and a second signal line (not shown) connected to test voltage pads TVP1 and TVP2, such that the data line is connected to the first signal line via the data pad to receive a first signal (e.g., initialization voltage), and the crack sensing line is electrically connected to the second signal line via the test voltage pad to receive a second signal (e.g., test voltage).

[0072] In the following text, reference will be made to Figure 3 Describes the signals supplied to the display device. Figure 3 This is a waveform diagram showing the signals of a display device according to an exemplary embodiment.

[0073] exist Figure 3 The diagram shows initialization signals IS1, IS2, and IS3 supplied to initialization control pads IP1, IP2, and IP3; test control signal TS supplied to the first test control pad TP1; initialization voltage IV supplied to data pads DP1-DPo; test voltage TV supplied to test voltage pads TVP1 and TVP2; and first to third and nth scan signals SCAN1, SCAN2, SCAN3, and SCANn.

[0074] Reference Figure 3A frame period consists of multiple horizontal periods, and a horizontal period consists of a first time period t1 and a second time period t2. A frame period represents the time period during which data voltage is supplied to all pixels of the display panel, and a horizontal period represents the time period during which data voltage is supplied to pixels connected to a scan line.

[0075] The first initialization signal IS1 is formed with a first gate on-state voltage Von1 during a first time period t1 of the odd-numbered horizontal period oh, and with a first gate off-state voltage Voff1 during a second time period t2 of the odd-numbered horizontal period oh and an even-numbered horizontal period eh. The second initialization signal IS2 is formed with a first gate on-state voltage Von1 during a first time period t1 of the even-numbered horizontal period eh, and with a first gate off-state voltage Voff1 during a second time period t2 of the even-numbered horizontal period eh and an odd-numbered horizontal period oh. The third initialization signal IS3 is formed with a first gate on-state voltage Von1 during a first time period t1 of each horizontal period, and with a first gate off-state voltage Voff1 during a second time period t2.

[0076] The test control signal TS is configured to have a first gate cutoff voltage Voff1 during the first time period t1 of each horizontal cycle, and to have a first gate on-voltage Von1 during the second time period t2 of each horizontal cycle. For example... Figure 3 As shown, when the initialization transistors IT1, IT2, and IT3, and the test transistor TT1 are configured as P-type, the first gate on-state voltage Von1 can have a lower voltage level than the first gate off-state voltage Voff1. That is, the test control signal TS and the third initialization signal IS3 can have opposite levels, as shown... Figure 3 As shown in the image.

[0077] The initialization voltage IV can be set to the peak white-gray voltage PWV, and the test voltage TV can be set to the peak black-gray voltage PBV. When the driving transistor DT is configured as P-type, the voltage level of the peak white-gray voltage PWV can be lower than the voltage level of the peak black-gray voltage PBV, such as... Figure 3 As shown. Meanwhile, Figure 3 Only examples of initialization voltage IV and test voltage TV are shown, therefore the initialization voltage IV and test voltage TV are not limited to these.

[0078] The first to third and nth scan signals SCAN1, SCAN2, SCAN3, and SCANn can be formed with a second gate cutoff voltage Voff2 during the first time period t1 of each horizontal cycle and can be formed with a second gate on-voltage Von2 during the second time period t2 of each horizontal cycle. Although Figure 3 The first to third and nth scan signals SCAN1, SCAN2, SCAN3, and SCANn are shown to have a second gate on-state voltage Von2 during a shorter time period than the second time period t2 within each horizontal period, but this exemplary embodiment is not limited thereto. For example, the first to third and nth scan signals SCAN1, SCAN2, SCAN3, and SCANn are formed with a second gate on-state voltage Von2 during the second time period t2 of each horizontal period. When the scan transistor ST is formed as a P-type, the second gate on-state voltage Von2 may have a voltage level lower than the voltage level of the second gate off-state voltage Voff2, such as... Figure 3 As shown.

[0079] Meanwhile, when the scanning transistor ST of pixel RP is designed to have the same transistor characteristics as the first to third initialization transistors IT1, IT2 and IT3 and the test transistor TT1, the second gate on voltage Von2 can have a basically the same voltage level as the first gate on voltage Von1, and the second gate off voltage Voff2 can have the same voltage level as the first gate off voltage Voff1.

[0080] In the following text, reference will be made to Figures 4A to 4C as well as Figure 2 and Figure 3 The present invention describes in detail a crack inspection method for a display device according to an exemplary embodiment. Figures 4A to 4C Is Figure 3 The waveform of the voltage supplied to the pixel during the first and second time periods.

[0081] First, during the first time period t1 of the odd-level period oh, the first initialization signal IS1 and the third initialization signal IS3 are configured with a first gate on-state voltage Von1. The second initialization signal IS2 and the test control signal TS are configured with a first gate off-state voltage Voff1. Therefore, the first initialization transistor IT1 and the third initialization transistor IT3 are turned on, while the second initialization transistor IT2 and the test transistor TT1 are turned off. As a result, the initialization voltage IV is supplied to the data lines D1a-Dma through the first initialization transistor IT1 and the third initialization transistor IT3.

[0082] Next, during the second time period t2 of the odd-numbered horizontal period oh, the first to third initialization signals IS1, IS2, and IS3 are configured with a first gate cutoff voltage Voff1, and the test control signal TS is configured with a first gate turn-on voltage Von1. Therefore, the first to third initialization transistors IT1, IT2, and IT3 are turned off, and the test transistor TT1 is turned on. As a result, the test voltage TV is supplied to the data lines D1a-Dma through the test transistor TT1.

[0083] Furthermore, when the first scan signal SCAN1 is formed to have a second gate on-state voltage Von2 within the second time period t2 of the odd-level period oh, the voltage of the data lines D1a-Dma is supplied to the pixel RP connected to the first scan line S1.

[0084] When the initialization voltage IV is the peak white-grayscale voltage PWV and the test voltage TV is the peak black-grayscale voltage PBV, such as Figure 4A As shown, the voltage to be supplied to pixel RP decreases to the peak white-grayscale voltage PWV during the first time period t1 and increases to the peak black-grayscale voltage PBV during the second time period t2. However, when a crack occurs in the display device, the data lines D1a-Dma or the first to fourth crack sensing lines CD1, CD2, CD11, and CD22 may disconnect, or the wiring resistance of the data lines D1a-Dma or the first to fourth crack sensing lines CD1, CD2, CD11, and CD22 may increase.

[0085] For example, when data lines D1a-Dma or the first to fourth crack sensing lines CD1, CD2, CD11, and CD22 break due to a crack generated in the display device, such as Figure 4B As shown, during the second time period t2, there is no peak grayscale voltage PBV. The voltage to be supplied to the pixel RP decreases to the peak white grayscale voltage PWV during the first time period t1 and remains at the peak white grayscale voltage PWV during the second time period t2. As a result, since the pixel RP connected to the data line or crack sensing line that is broken due to the crack displays the peak white grayscale, a bright line can be observed.

[0086] Furthermore, if the wiring resistance of data lines D1a-Dma or the first to fourth crack sensing lines CD1, CD2, CD11, and CD22 increases due to cracks generated in the display device, although the peak black-grayscale voltage PBV is supplied during the second time period t2, as Figure 4CAs shown, due to the increased wiring resistance, the voltage to be supplied to pixel RP decreases to its peak white-grayscale voltage PWV during the first time period t1, but does not increase to the peak black-grayscale voltage PBV during the second time period t2. As a result, pixel RP connected to the data line or crack sensing line whose wiring resistance has increased due to the generated crack displays a gray-grayscale, and weak bright lines can be observed.

[0087] As described above, according to this exemplary embodiment, by supplying an initialization voltage IV via initialization transistors IT1, IT2, and IT3 during a first time period t1 of each horizontal cycle and a test voltage TV via test transistor TT1 during a second time period t2 of each horizontal cycle, it is possible to determine whether a crack has occurred in the display device by using the disconnection of data lines D1a-Dma or the change in their wiring resistance, and the disconnection of the crack sensing line formed outside the display area DA or the change in its wiring resistance. As a result, when a strong or weak bright line is observed, it is determined that a crack has occurred.

[0088] Thus, according to this exemplary embodiment of the display device, when a crack is generated at a portion of the encapsulation portion EN of the non-display area NDA formed around the display area DA, a strong or weak bright line is observed from the pixel connected to the data line connected to the first crack sensing line CD1 and the second crack sensing line CD2 superimposed on the encapsulation portion EN.

[0089] Furthermore, when a crack is formed at the outermost part of the non-display area NDA surrounding the display area DA, damage is applied to the third crack sensing line CD11 and the fourth crack sensing line CD22 formed at the outermost part of the non-display area NDA surrounding the display area DA. Therefore, strong or weak bright lines are observed from pixels connected to the data lines connected to the third crack sensing line CD11 and the fourth crack sensing line CD22.

[0090] Thus, the display device according to this exemplary embodiment is able to detect cracks generated in the region where the encapsulation portion EN is formed and in the non-display region NDA where the encapsulation portion EN is not formed.

[0091] In the following text, reference will be made to Figures 5 to 7 Describe the connection structures between the test transistor and the crack sensing line, and between the test transistor and the resistor. Figure 5 It is shown Figure 2 The top view shows the connection structure between the test transistor and the crack sensing line, and between the test transistor and the resistor. Figure 6 It is along Figure 5 A cross-sectional view taken by line I-I'. Figure 7 It is along Figure 5 The sectional view taken from line II-II'.

[0092] For ease of description, Figure 5 Only three data lines D1, D2, and D3, and three test transistors TT1 connected to them are shown.

[0093] exist Figure 6 In the test transistor TT1 connected to the crack sensing line CD, it is called the first test transistor TT1-1, and the test transistor TT1 connected to the resistor R is called the second test transistor TT1-2.

[0094] Reference Figure 5 and Figure 6 The control electrode TT_G of the first test transistor TT1-1 is stacked with the first active layer TT_ACT in a predetermined region. The first end of the first active layer TT_ACT of the first test transistor TT1-1 is connected to the data line D1 through the first contact hole CNT1, and the second end of the first active layer TT_ACT is connected to the first end of the crack sensing line CD through the second contact hole CNT2. Figure 2 As shown, the crack sensing line CD is formed to travel around the outside of the display area DA. In this case, the second end of the crack sensing line CD is connected to the bridge electrode BE through the third contact hole CNT3. The bridge electrode BE can be connected to the test voltage line TVL through the fourth contact hole CNT4. The test voltage line TVL is a line connected to either the test voltage pads TVP1 and TVP2, which are supplied with the test voltage TV.

[0095] The bridge electrode BE and the control electrode TT_G of the first test transistor TT1-1 can be formed in a first metal pattern, the first active layer TT_ACT of the first test transistor TT1-1 can be formed in a semiconductor pattern, and the data line D1 and the test voltage line TVL can be formed in a second metal pattern. Here, the first metal pattern can be a gate metal pattern, and the second metal pattern can be a source / drain metal pattern. The semiconductor pattern can be formed of polysilicon, but this exemplary embodiment is not limited thereto. For example, the semiconductor pattern can be formed of monocrystalline silicon, amorphous silicon, or oxide semiconductor material. A gate insulating layer GI can be formed between the first metal pattern and the semiconductor pattern to insulate the first metal pattern and the semiconductor pattern from each other. Furthermore, an insulating layer IL can be formed between the semiconductor pattern and the second metal pattern to insulate the semiconductor pattern and the second metal pattern from each other. In the exemplary embodiment shown, the crack sensing line CD has been described as being formed on the same layer as the data line D1 and the test voltage line TVL. However, according to another exemplary embodiment, the first crack sensing line CD1 and the second crack sensing line CD2 may be formed on the same layer as the touch wiring formed at the touch portion TM, and the third crack sensing line CD11 and the fourth crack sensing line CD22 may be formed on the same layer as a portion of the signal lines (e.g., gate wiring or data wiring) formed in the display area DA.

[0096] Reference Figure 5 and Figure 7 The control electrode TT_G of the second test transistor TT1-2 is stacked with the first active layer TT_ACT in a predetermined region. The first end of the first active layer TT_ACT of the second test transistor TT1-2 is connected to either of the two data lines D2 and D3 through the first contact hole CNT1, and the second end of the first active layer TT_ACT is connected to the bridge electrode BE through the fifth contact hole CNT5. The bridge electrode BE can be connected to the test voltage line TVL through the fourth contact hole CNT4.

[0097] The bridge electrode BE and the control electrode TT_G of the second test transistor TT1-2 can be formed in the first metal pattern. The first active layer TT_ACT of the second test transistor TT1-2 can be formed in the semiconductor pattern. The two data lines D2 and D3 and the test voltage line TVL can be formed in the second metal pattern. Here, the first metal pattern can be a gate metal pattern, and the second metal pattern can be a source / drain metal pattern. The semiconductor pattern can be formed of polysilicon, but this exemplary embodiment is not limited thereto. For example, the semiconductor pattern can be formed of monocrystalline silicon, amorphous silicon, or oxide semiconductor material. A gate insulating layer GI can be formed between the first metal pattern and the semiconductor pattern to insulate the first metal pattern and the semiconductor pattern from each other. Furthermore, an insulating layer IL can be formed between the semiconductor pattern and the second metal pattern to insulate the semiconductor pattern and the second metal pattern from each other.

[0098] Simultaneously, the first active layer TT_ACT of the second test transistor TT1-2 is formed to be longer than the first active layer TT_ACT of the first test transistor TT1-1. For example, the first active layer TT_ACT of the second test transistor TT1-2, which is formed to be longer than the first active layer TT_ACT of the first test transistor TT1-1, is used as a resistor R. For example, the doped first active layer TT_ACT of the second test transistor TT1-2 functions as a resistor R. In this case, by designing the resistance of the resistor R to be substantially the same as the wiring resistance of the crack sensing line CD, the deviation of the test voltage caused by the wiring resistance of the crack sensing line CD can be minimized.

[0099] In the following text, except Figure 1 and Figure 2 In addition, it will also refer to Figure 8 Describes the layer structure of a display device according to an exemplary embodiment. Figure 8 It is partially shown Figure 2 The cross-sectional view of the display device shown.

[0100] Reference Figure 8 as well as Figure 1 and Figure 2 Each pixel in the display area DA includes an organic light-emitting diode (OLED) and a thin-film transistor (TFT) connected thereto.

[0101] TFTs include a second active layer AL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0102] The second active layer, AL, can be formed of polycrystalline silicon or oxide semiconductors. The oxide semiconductor can include any of the following: oxides such as titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (GE), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), and oxides such as indium gallium zinc oxide (InGaZnO4), indium zinc oxide (Zn-In-O), zinc tin oxide (Zn-Sn-O), indium gallium oxide (In-Ga-O), indium tin oxide (In-Sn-O), indium zirconium oxide (In-Zr-O), indium zirconium zinc oxide (In-Zr-Zn-O), indium zirconium tin oxide (In-Zr-Sn-O), indium zirconium gallium oxide (In-Zr-Ga-O), and indium aluminum oxide (In-Al). A composite oxide of indium zinc aluminum oxide (In-Zn-Al-O), indium tin aluminum oxide (In-Sn-Al-O), indium aluminum gallium oxide (In-Al-Ga-O), indium tantalum oxide (In-Ta-O), indium tantalum zinc oxide (In-Ta-Zn-O), indium tantalum tin oxide (In-Ta-Sn-O), indium tantalum gallium oxide (In-Ta-Ga-O), indium germanium oxide (In-Ge-O), indium germanium zinc oxide (In-Ge-Zn-O), indium germanium tin oxide (In-Ge-Sn-O), indium germanium gallium oxide (In-Ge-Ga-O), titanium indium zinc oxide (Ti-In-Zn-O), and hafnium indium zinc oxide (Hf-In-Zn-O).

[0103] The second active layer AL includes an undoped channel region and source and drain regions formed on opposite sides of the channel region by doping. These impurities can vary depending on the type of thin-film transistor and can include N-type or P-type impurities. When the second active layer AL is formed of an oxide semiconductor, an additional passivation layer can be formed to protect the oxide semiconductor from environmental damage, including high-temperature processing.

[0104] The gate electrode GE is formed on the first insulating layer IL1 covering the second active layer AL, and the source electrode SE and drain electrode DE are formed on the second insulating layer IL2 covering the gate electrode GE, so as to be connected to the source region and drain region of the second active layer AL, respectively, through contact holes formed in the second insulating layer IL2 and the first insulating layer IL1. The drain electrode DE is connected to the first electrode E1 of the OLED through the contact hole.

[0105] The OLED includes a first electrode E1 connected to the drain electrode DE of the TFT, an organic emission layer EL formed on the first electrode E1, and a second electrode E2 formed on the organic emission layer EL.

[0106] The first electrode E1 can be an anode used as a hole injection electrode, and can be any one of a light-reflective electrode, a light-transmitting and reflective electrode, and a transmissive electrode. Meanwhile, according to another exemplary embodiment, the first electrode E1 can be a cathode used as an electron injection electrode.

[0107] An organic emitting layer EL is formed on the first electrode E1. The organic emitting layer EL can be formed from a low-molecular-weight organic material or a high-molecular-weight organic material such as poly(3,4-ethylenedioxythiophene) (PEDOT). Furthermore, the organic emitting layer EL can include at least one of a red organic emitting layer for emitting red light, a green organic emitting layer for emitting green light, and a blue organic emitting layer for emitting blue light. The red, green, and blue organic emitting layers are formed in the red, green, and blue pixels, respectively, to achieve a color image. The organic emitting layer EL can also achieve a color image by laminating the red, green, and blue organic emitting layers together in the red, green, and blue pixels and forming a red, green, and blue color filter for each pixel. As another example, a white organic emitting layer emitting white light is formed in all the red, green, and blue pixels, and a red, green, and blue color filter is formed for each pixel, thereby achieving a color image. When implementing a color image using a white organic emitting layer and a color filter as the organic emitting layer (EL), it is not necessary to use a deposition mask for depositing red, green, and blue organic emitting layers on individual pixels (i.e., red, green, and blue pixels). In another example, the white organic emitting layer can be formed from a single organic emitting layer and can include a structure configured to emit white light by laminating multiple organic emitting layers. For example, the white organic emitting layer includes: a structure that emits white light by combining at least one yellow organic emitting layer and at least one blue emitting layer; a structure that emits white light by combining at least one cyan organic emitting layer and at least one red emitting layer; a structure that emits white light by combining at least one magenta organic emitting layer and at least one green emitting layer, etc.

[0108] A second electrode E2 is formed on the organic emitting layer EL and can be a cathode used as an electron injection electrode. The second electrode E2 can be any one of a light-reflective electrode, a light-transmitting and reflective electrode, and a transmissive electrode. The second electrode E2 is formed as a display area DA covering the organic emitting layer EL across the substrate SUB. In another exemplary embodiment, the second electrode E2 is an anode used as a hole injection electrode.

[0109] The encapsulation portion EN is formed on the substrate SUB, distributing over the display area DA and the non-display area NDA, and encapsulates the display area DA together with the substrate SUB. The encapsulation portion EN includes an organic layer OL formed on the display area DA and an inorganic layer IL formed on the organic layer OL.

[0110] The organic layer OL is formed of a polymer and can be a single layer or stacked layers formed from any of, for example, polyethylene terephthalate, polyimide, polycarbonate, epoxy resin, polyethylene, and polyacrylate. For example, the organic layer OL is formed from polyacrylate (e.g., a material produced by polymerizing a monomer component comprising diacrylate and triacrylate monomers). Here, the monomer component may also include monoacrylate monomers, and may also include photoinitiators such as TPO, but the described techniques are not limited thereto.

[0111] The inorganic layer IL can be a single layer or multiple layers formed of metal oxides or metal nitrides. For example, the inorganic layer IL is formed from any one of SiNx, Al2O3, SiO2, and TiO2.

[0112] The inorganic layer IL, which is the uppermost layer of the encapsulation portion EN, is stacked over a wider area than the organic layer OL to cover the ends of the organic layer OL, which is another layer. For example, in the non-display area NDA of the substrate SUB, the inorganic layer IL covers the ends of the organic layer OL. That is, an upper inorganic layer stacked over a wider area than other layers can be formed on the uppermost layer of the encapsulation portion EN to cover the ends of other layers. Therefore, external moisture penetrating into the OLED can be suppressed by the inorganic layer IL.

[0113] The touch portion TM includes a first touch line TL1 and a second touch line TL2 formed on an encapsulation portion EN corresponding to the display area DA of the substrate SUB. When the touch portion TM is touched, and the touch portion TM can be capacitive, and a voltage is applied to the first touch line TL1 and the second touch line TL2 respectively, thus charging is applied to each of the first touch line TL1 and the second touch line TL2 or between the first touch line TL1 and the second touch line TL2, the capacitance of the touch portion, which is one of the first touch line TL1 and the second touch line TL2, is changed to detect the position of the touch portion. The touch portion TM may also include one or more insulating layers covering the first touch line TL1 and the second touch line TL2. Each touch line in the first touch line TL1 and the second touch line TL2 may be formed of one or more of the following: transparent conductive materials (such as ITO, IZO, IGZO, etc.), metal mesh patterned in a grid pattern, conductive polymers (such as poly(3,4-ethylenedioxythiophene) (PEDOT), etc.), nanoscale conductive materials (such as silver nanowires (AGNW), etc.).

[0114] The first crack sensing line CD1 and the second crack sensing line CD2 are formed at the edge of the inorganic layer IL formed on the uppermost layer of the encapsulation portion EN. In this case, the first crack sensing line CD1 and the second crack sensing line CD2 are formed on the same layer as the first touch line TL1 and the second touch line TL2. The first crack sensing line CD1 and the second crack sensing line CD2 can be formed in the non-display area NDA adjacent to the display area DA, and can also be formed on the encapsulation portion EN.

[0115] The third crack sensing line CD11 and the fourth crack sensing line CD22 are formed at the outermost part of the unencapsulated portion EN of the non-display area NDA. The third crack sensing line CD11 and the fourth crack sensing line CD22 can be formed on the same layer as the gate electrode GE of the display area DA.

[0116] In the following text, reference will be made to Figure 9 A display device according to an exemplary embodiment is described. Figure 9 This is a partial illustration of another exemplary embodiment in Figure 2 A cross-sectional view of the display device shown in the image. (Refer to...) Figure 1 , Figure 2 and Figure 9 Each pixel in the display area DA includes an OLED that emits light and a TFT connected to the OLED.

[0117] TFTs include a second active layer AL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0118] The OLED includes a first electrode E1 connected to the drain electrode DE of the TFT, an organic emission layer EL formed on the first electrode E1, and a second electrode E2 formed on the organic emission layer EL.

[0119] The encapsulation portion EN is formed on the substrate SUB, distributing over the display area DA and the non-display area NDA, and encapsulates the display area DA together with the substrate SUB. The encapsulation portion EN includes an organic layer OL formed on the display area DA and an inorganic layer IL formed on the organic layer OL.

[0120] The touch portion TM includes a first touch line TL1 and a second touch line TL2 formed on an encapsulation portion EN corresponding to the display area DA of the substrate SUB.

[0121] The first crack sensing line CD1 and the second crack sensing line CD2 are formed at the edge of the inorganic layer IL formed on the uppermost layer of the encapsulation portion EN. In this case, the first crack sensing line CD1 and the second crack sensing line CD2 are formed on the same layer as the first touch line TL1 and the second touch line TL2. The first crack sensing line CD1 and the second crack sensing line CD2 can be formed in the non-display area NDA adjacent to the display area DA, and can also be formed on the encapsulation portion EN.

[0122] The third crack sensing line CD11 and the fourth crack sensing line CD22 are formed at the outermost part of the unencapsulated portion EN of the non-display area NDA. The third crack sensing line CD11 and the fourth crack sensing line CD22 are formed on the same layer as the source electrode SE and drain electrode DE of the display area DA and the data line D.

[0123] According to at least one of the disclosed embodiments, the third crack sensing line CD11 and the fourth crack sensing line CD22 are described as being formed on the same layer as the gate electrode GE of the display area DA or the same layer as the source electrode SE, drain electrode DE, and data line D of the display area DA. However, according to another exemplary embodiment of the display device, the third crack sensing line CD11 and the fourth crack sensing line CD22 may be formed as comprising multiple layers, wherein the multiple layers include a first layer formed on the same layer as the gate electrode GE of the display area DA, and a second layer formed on the same layer as the source electrode SE, drain electrode DE, and data line D of the display area DA.

[0124] In the foregoing exemplary embodiments, the OLED display has been described as an example of a display device, but many features of the foregoing exemplary embodiments are applicable to various display devices such as liquid crystal displays (LCDs), plasma displays (PDs), field emission displays (FEDs), electrophoretic displays (EPDs), and electrowetting displays (EWDs), which include a display area for displaying images and a touch portion for recognizing touches.

[0125] Although the technology of the invention has been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A display device, the display device comprising: The substrate includes a display area and a non-display area surrounding the display area; Multiple pixels are disposed in the display area; Multiple signal lines are disposed on the substrate and electrically connected to the pixel; An encapsulation layer is disposed on the substrate; as well as A first crack sensing line is disposed on the encapsulation layer in the non-display area. The signal lines include: gate lines; data lines; and first signal lines and second signal lines, in the non-display area. The data line is electrically connected to the first signal line via a first transistor. One end of the first crack sensing line is electrically connected to the data line via a second transistor, and The other end of the first crack sensing line is electrically connected to the test pad via the second signal line.

2. The display device according to claim 1, wherein, The first crack sensing line is superimposed on the encapsulation layer in the depth dimension of the display device.

3. The display device according to claim 2, further comprising: The touch layer includes touch wiring disposed on the encapsulation layer, wherein the first crack sensing line and the touch wiring of the touch layer are disposed on the same layer.

4. The display device according to claim 2, further comprising: The second crack sensing line is located in the non-display area and does not overlap with the encapsulation layer in the depth dimension of the display device.

5. The display device according to claim 4, wherein, The second crack sensing line is disposed on the same layer as the gate line.

6. The display device according to claim 1, further comprising: The touch layer includes touch wiring disposed on the encapsulation layer, wherein the first crack sensing line and the touch wiring of the touch layer are disposed on the same layer.

7. The display device according to claim 1, further comprising: The second crack sensing line is located in the non-display area and does not overlap with the encapsulation layer in the depth dimension of the display device.

8. The display device according to claim 7, wherein, The second crack sensing line is disposed on the same layer as the gate line.

9. The display device according to claim 1, further comprising: A first gate line is disposed in the non-display area and electrically connected to the first transistor; as well as The second gate line is electrically connected to the second transistor. The data line receives a first signal from the first signal line based on a first gate on-voltage applied to the first gate line, and The data line receives a second signal from the second signal line according to a second gate conduction voltage applied to the second gate line.

10. The display device according to claim 9, wherein, The second gate on-state voltage is applied after the first gate on-state voltage is applied, and The first signal and the second signal are different.

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