An amplifier based on power adaptive bias adjustment technique

Abstract

The application discloses an amplifier based on a power adaptive bias adjustment technology, comprising an input ESD protection and direct-current isolation matching network, a first power adaptive bias adjustment amplification network, a second power adaptive bias adjustment amplification network, a double-path differential mode filtering network and an output phase synthesis matching network. The amplifier is based on an improved stacked Darlington amplification structure of the power adaptive bias adjustment technology, can obtain a higher high-frequency gain index, can realize a high linearity index under a wide dynamic range by combining a harmonic parasitic component phase compensation technology, and can filter out redundant differential mode signals of the improved stacked Darlington amplification structure by using a differential mode filtering network between the two amplification networks, so as to improve the stability of the amplifier.

Description

Technical Field

[0001] This invention belongs to the field of 5G communication and integrated circuit technology, and specifically relates to the design of an amplifier based on power adaptive bias adjustment technology. Background Technology

[0002] With the development of technologies such as software-defined radio, broadband instruments, and 5G communication, system bandwidth rates are constantly increasing, leading to higher market demands for the linearity of broadband amplifiers. Especially for processing high-speed peak-to-average power ratio (PAPR) signals, amplifiers are required to possess good linearity across a wide dynamic range.

[0003] To improve the linearity of driver amplifier chips over a wide dynamic range, the following techniques can be employed during chip design; however, these techniques all have some shortcomings:

[0004] (1) Power back-off technology, that is, using a high-power transistor as a low-power transistor, so that the amplifier can operate in the back-off linear amplification region to obtain high linearity index. However, in order to achieve high linearity over a wider dynamic range, for example, a large transistor size is used, which greatly sacrifices the DC power consumption of the amplifier and the efficiency of the amplifier is very low.

[0005] (2) Envelope tracking technology uses detection circuits, bias adjustment technology and other methods to track the output power of the amplifier. The bias circuit of the amplifier is automatically adjusted according to the dynamic range of the output power, thereby avoiding the drawback of the "one-size-fits-all" approach to high-power transistors in power back-off technology. This method has a good improvement effect, but the circuit structure is extremely complex and difficult to integrate on the chip.

[0006] (2) Intermodulation component cancellation technology utilizes the main and auxiliary amplifiers to operate in class AB and class C modes respectively. The auxiliary class C generates a positive third-order intermodulation component, which cancels the negative third-order intermodulation component of the main class AB, thereby improving the amplifier's IP3 and P1dB performance. However, in this method of direct synthesis and cancellation between the main and auxiliary amplifiers, there is a difference between the fundamental and harmonic phases of the signal, which cannot achieve the best cancellation effect. Summary of the Invention

[0007] To address the aforementioned shortcomings in the existing technology, this invention provides an amplifier based on power adaptive bias adjustment technology. Based on an improved Darlington amplification structure derived from bias, combined with intermodulation cancellation technology, it achieves an amplifier structure with high linearity over a wide dynamic range, high high-frequency gain, and low power consumption.

[0008] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows: an amplifier based on power adaptive bias adjustment technology, comprising an input ESD protection and DC blocking matching network, a first power adaptive bias adjustment amplification network, a second power adaptive bias adjustment amplification network, an output phase synthesis matching network, and a dual-path differential mode filter network;

[0009] The input terminal of the input ESD protection and DC blocking matching network serves as the RF input terminal of the amplifier. The output terminal of the input ESD protection and DC blocking matching network is connected to the input terminals of the first power adaptive bias adjustment amplification network and the second power adaptive bias adjustment amplification network, respectively. The first output terminal of the first power adaptive bias adjustment amplification network is connected to the first input terminal of the output phase synthesis matching network. The first output terminal of the second power adaptive bias adjustment network is connected to the second input terminal of the output phase synthesis matching network. The output terminal of the output phase synthesis matching network serves as the RF output terminal of the amplifier.

[0010] The second output terminals of both the first power adaptive bias adjustment amplifier network and the second power adaptive bias adjustment amplifier network are connected to a dual-channel differential mode filter network.

[0011] The beneficial effects of this invention are as follows: the original bias-improved stacked Darlington amplifier structure based on power adaptive bias adjustment technology can obtain high high-frequency and high-gain performance. Combined with harmonic parasitic component phase compensation technology, it can achieve high linearity performance under wide dynamic range. At the same time, by using the differential mode filter network between the two amplification networks, the redundant differential mode signal of the improved stacked Darlington amplifier structure is filtered out, thereby improving the stability of the amplifier.

[0012] Furthermore, the input ESD protection and DC blocking matching network includes capacitor C1, inductor L1, and grounding capacitor C. 13 ;

[0013] One end of capacitor C1 serves as the input terminal of the input ESD protection and DC blocking matching network and is connected to the grounding inductor L1. The other end of capacitor C1 is connected to the grounding capacitor C. 13 It is connected and serves as the output of the input ESD protection and DC blocking matching network.

[0014] The beneficial effects of the above-mentioned further solution are: the network has ESD protection function, protecting the input terminal of the circuit amplifier from the threat of external ESD stress, and at the same time can achieve good matching function of input impedance in the low-frequency range.

[0015] Further, the first power adaptive bias adjustment amplification network includes transistors Q1, Q2, Q3, Q4, Q5, Q6, diodes D1 and D2, capacitors C3, C4, C5, C6, and C7, and resistors R3, R4, R5, R6, R7, R8, R9, and R... 10 Inductors L3, L4, and L5;

[0016] One end of the inductor L3 serves as the input terminal of the first power adaptive bias adjustment amplifier network. Its other end is connected to one end of the grounding capacitor C3 and one end of the inductor L4. The other end of the inductor L4 is connected to one end of the resistor R3, one end of the capacitor C4, and the base of the transistor Q3. The other end of the resistor R3 is connected to one end of the resistor R4 and the emitter of the transistor Q1. The other end of the resistor R4 is connected to the other end of the capacitor C4. The base of the transistor Q1 is connected to one end of the grounding capacitor C5, the anode of the diode D2, and one end of the resistor R6. The cathode of the diode D2 is connected to the anode of the diode D1, and the cathode of the diode D1 is grounded.

[0017] The other end of resistor R6 is connected to the collector of transistor Q1 and one end of resistor R5. The other end of resistor R5 is connected to grounding capacitor C6, one end of resistor R7, one end of resistor R8, and one end of inductor L5. The other end of resistor R7 is connected to the collector and base of transistor Q2. The emitter of transistor Q2 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to grounding resistor R9 and the base of transistor Q6. The other end of resistor R8 is connected to the collector and base of transistor Q4. The emitter of transistor Q4 is connected to the base of transistor Q5 and one end of capacitor C7. The other end of capacitor C7 is connected to grounding resistor R6. 10 The inductor L5 is connected as follows: the other end of the inductor L5 serves as the first output terminal of the first power adaptive bias adjustment amplification network and is connected to the collector of transistor Q5; the emitter of transistor Q5 serves as the second output terminal of the first power adaptive bias adjustment amplification network and is connected to the collector of transistor Q6; and the emitter of transistor Q6 is grounded.

[0018] The beneficial effects of the above-mentioned further scheme are as follows: The first power adaptive bias adjustment amplifier network, based on the power adaptive bias adjustment technology, has an improved stacked Darlington amplifier structure derived from bias, which can significantly improve the high-frequency gain characteristics of the amplifier and improve the isolation index. At the same time, the power adaptive bias structure based on transistors Q2 and Q4 can improve the bias state under a wide dynamic range and improve the linearity index. The amplifier's operating conduction angle is selected in the range of 190 to 210°, thereby obtaining the best power output capability and generating a third-order negative high-frequency parasitic component.

[0019] Furthermore, the second power adaptive bias adjustment network includes transistors Q7, Q8, Q9, and Q1. 10 Transistor Q 11 Transistor Q 12 Diode D3, Diode D4, Capacitor C8, Capacitor C9, Capacitor C 10 Capacitor C 11 Capacitor C 12 Resistance R 11 Resistance R 12 Resistance R 13 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 Inductors L6, L7, and L8;

[0020] One end of the inductor L7 serves as the input terminal of the second power adaptive bias adjustment network, and the other end is connected to the grounding capacitor C. 11 One end of inductor L8 is connected to the capacitor C8, and the other end of inductor L8 is connected to one end of resistor R16, one end of capacitor C8, and the base of transistor Q8. 16 The other end is connected to resistor R respectively 15 One end of the resistor is connected to the emitter of transistor Q7, and the resistor R 15 The other end is connected to the other end of capacitor C8, and the base of transistor Q7 is connected to ground capacitor C9, the positive terminal of diode D4, and resistor R, respectively. 17 One end of the transistor D4 is connected to the cathode of the diode D3, and the cathode of the diode D3 is grounded.

[0021] The resistor R 17 The other end is connected to the collector of transistor Q7 and resistor R, respectively. 18 One end is connected to the transistor R. 18 The other end is connected to the grounding capacitor C. 10 Resistance R 12 One end, resistor R 11One end of the resistor R is connected to one end of the inductor L6, and the resistor R 12 The other end is connected to the collector and base of transistor Q9, respectively. The emitter of transistor Q9 is connected to the collector of transistor Q8, and the emitter of transistor Q8 is connected to the grounding resistor R. 14 and transistor Q 12 The base connection, the resistor R 11 The other end is connected to transistor Q. 10 The collector and base are connected, and the transistor Q is... 10 The emitters are respectively connected to transistor Q. 11 The base and capacitor C 12 One end of the capacitor C is connected to the capacitor C. 12 The other end is connected to the grounding resistance R 13 The other end of the inductor L6 is connected to the first output terminal of the second power adaptive bias adjustment amplifier network, and is connected to the transistor Q. 11 The collector connection of the transistor Q 11 The emitter serves as the second output terminal of the second power adaptive bias adjustment amplifier network, and is connected to transistor Q. 12 The collector connection of the transistor Q 12 The emitter is grounded.

[0022] The beneficial effects of the above-mentioned further scheme are as follows: The second power adaptive bias adjustment amplifier network, based on the power adaptive bias adjustment technology, has an improved stacked Darlington amplifier structure derived from the bias improvement, which can significantly improve the high-frequency gain characteristics of the amplifier and improve the isolation index. At the same time, the power adaptive bias structure based on transistors Q9 and Q10 can improve the bias state under a wide dynamic range and improve the linearity index. The amplifier's operating conduction angle is selected in the range of 160 to 180°, thereby achieving a good trade-off between output power and low power consumption, and obtaining a third-order positive high-frequency parasitic component.

[0023] Furthermore, the output phase synthesis matching network includes a transformer T1 and a capacitor C. 14 Capacitor C 15 Capacitor C 16 and capacitor C 17 ;

[0024] The same-name terminal of the primary coil of transformer T1 serves as the first input terminal of the output phase synthesis matching network, and the non-same-name terminals of the primary coil of transformer T1 are respectively connected to the grounding capacitor C. 14 and power supply V C1 The connection is made between the first terminal of the secondary winding of the primary winding T1 of the transformer and the capacitor C. 16 One end of the capacitor C is connected to the capacitor C. 16The other end serves as the output terminal of the output phase synthesis matching network, and the non-identical terminals of the secondary coil of transformer T1 are respectively connected to the grounding capacitor C. 15 and power supply V C2 The second terminal of the secondary coil of transformer T1 is connected to the grounding capacitor C, and serves as the second input terminal of the output phase synthesis matching network. 17 connect.

[0025] The beneficial effects of the above-mentioned further scheme are as follows: the first power adaptive bias adjustment amplification network generates a third-order negative high-frequency parasitic component, the first power adaptive bias adjustment amplification network obtains a third-order positive high-frequency parasitic component, and the phase compensation of the harmonic parasitic component is realized through the output phase synthesis matching network, thereby improving the linearity index of the amplifier. At the same time, the transformer T1 simplifies the bias network of the amplifier.

[0026] Furthermore, the dual-path differential mode filter network includes an inductor L2, a capacitor C2, a resistor R1, and a resistor R2;

[0027] One end of the inductor L2 is connected to one end of the capacitor C2 and one end of the resistor R1. The other end of the resistor R1 is connected to the second output terminal of the first power adaptive bias adjustment amplifier network. The other end of the inductor L2 is connected to the other end of the capacitor C2 and one end of the resistor R2. The other end of the resistor R2 is connected to the second output terminal of the second power adaptive bias adjustment amplifier network.

[0028] The beneficial effects of the above-mentioned further scheme are: the differential-mode filter network in the middle of the two amplification networks filters out the redundant differential-mode signals of the improved stacked Darlington amplification structure, thereby improving the stability of the amplifier. Attached Figure Description

[0029] Figure 1 The diagram shown is a block diagram of an amplifier based on power adaptive bias adjustment technology provided in an embodiment of the present invention.

[0030] Figure 2 The diagram shown is an amplifier circuit diagram based on power adaptive bias adjustment technology provided by an embodiment of the present invention. Detailed Implementation

[0031] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0032] This invention provides an amplifier based on power adaptive bias adjustment technology, such as... Figure 1 As shown, it includes an input ESD protection and DC blocking matching network, a first power adaptive bias adjustment amplification network, a second power adaptive bias adjustment amplification network, an output phase synthesis matching network, and a dual-path differential mode filter network;

[0033] The input terminal of the input ESD protection and DC blocking matching network is used as the RF input terminal of the amplifier. The output terminal of the input ESD protection and DC blocking matching network is connected to the input terminals of the first power adaptive bias adjustment amplification network and the second power adaptive bias adjustment amplification network, respectively. The first output terminal of the first power adaptive bias adjustment amplification network is connected to the first input terminal of the output phase synthesis matching network. The first output terminal of the second power adaptive bias adjustment network is connected to the second input terminal of the output phase synthesis matching network. The output terminal of the output phase synthesis matching network is used as the RF output terminal of the amplifier.

[0034] The second output terminals of both the first power adaptive bias adjustment amplifier network and the second power adaptive bias adjustment amplifier network are connected to a dual-channel differential mode filter network.

[0035] like Figure 2 As shown, the first power adaptive bias adjustment amplifier network includes transistors Q1, Q2, Q3, Q4, Q5, Q6, diodes D1 and D2, capacitors C3, C4, C5, C6, and C7, and resistors R3, R4, R5, R6, R7, R8, R9, and R... 10 Inductors L3, L4, and L5;

[0036] One end of inductor L3 serves as the input of the first power adaptive bias adjustment amplifier network. Its other end is connected to one end of grounded capacitor C3 and one end of inductor L4. The other end of inductor L4 is connected to one end of resistor R3, one end of capacitor C4, and the base of transistor Q3. The other end of resistor R3 is connected to one end of resistor R4 and the emitter of transistor Q1. The other end of resistor R4 is connected to the other end of capacitor C4. The base of transistor Q1 is connected to grounded capacitor C5, the anode of diode D2, and one end of resistor R6. The cathode of diode D2 is connected to the anode of diode D1, and the cathode of diode D1 is grounded.

[0037] The other end of resistor R6 is connected to the collector of transistor Q1 and one end of resistor R5. The other end of resistor R5 is connected to grounding capacitor C6, one end of resistor R7, one end of resistor R8, and one end of inductor L5. The other end of resistor R7 is connected to the collector and base of transistor Q2. The emitter of transistor Q2 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to grounding resistor R9 and the base of transistor Q6. The other end of resistor R8 is connected to the collector and base of transistor Q4. The emitter of transistor Q4 is connected to the base of transistor Q5 and one end of capacitor C7. The other end of capacitor C7 is connected to grounding resistor R6. 10 The other end of inductor L5 serves as the first output terminal of the first power adaptive bias adjustment amplifier network and is connected to the collector of transistor Q5. The emitter of transistor Q5 serves as the second output terminal of the first power adaptive bias adjustment amplifier network and is connected to the collector of transistor Q6. The emitter of transistor Q6 is grounded.

[0038] like Figure 2 As shown, the second power adaptive bias adjustment network includes transistors Q7, Q8, Q9, and Q1. 10 Transistor Q 11 Transistor Q 12 Diode D3, Diode D4, Capacitor C8, Capacitor C9, Capacitor C 10 Capacitor C 11 Capacitor C 12 Resistance R 11 Resistance R 12 Resistance R 13 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 Inductors L6, L7, and L8;

[0039] One end of inductor L7 serves as the input to the second power adaptive bias adjustment network, and the other end is connected to the grounding capacitor C. 11 One end of inductor L8 is connected to the capacitor C8, and the other end of inductor L8 is connected to one end of resistor R16, one end of capacitor C8, and the base of transistor Q8. Resistor R 16 The other end is connected to resistor R respectively 15 One end is connected to the emitter of transistor Q7, and resistor R 15 The other end is connected to the other end of capacitor C8. The base of transistor Q7 is connected to ground capacitor C9, the positive terminal of diode D4, and resistor R. 17 One end of the transistor is connected, the negative terminal of transistor D4 is connected to the positive terminal of diode D3, and the negative terminal of diode D3 is grounded.

[0040] resistor R 17 The other end is connected to the collector of transistor Q7 and resistor R, respectively. 18 One end is connected to transistor R 18 The other end is connected to the grounding capacitor C. 10 Resistance R 12 One end, resistor R 11 One end is connected to one end of inductor L6, and resistor R 12 The other end is connected to the collector and base of transistor Q9, respectively. The emitter of transistor Q9 is connected to the collector of transistor Q8, and the emitter of transistor Q8 is connected to the grounding resistor R. 14 and transistor Q 12 The base connection, resistor R 11 The other end is connected to transistor Q. 10 The collector and base are connected, transistor Q 10 The emitters are respectively connected to transistor Q. 11 The base and capacitor C 12 One end is connected to capacitor C 12 The other end is connected to the grounding resistance R 13 The other end of inductor L6 serves as the first output of the second power adaptive bias regulation amplifier network, and is connected to transistor Q. 11 collector connection, transistor Q 11 The emitter serves as the second output terminal of the second power adaptive bias adjustment amplifier network, and is connected to transistor Q. 12 collector connection, transistor Q 12 The emitter is grounded.

[0041] like Figure 2 As shown, the output phase synthesis matching network includes transformer T1 and capacitor C. 14 Capacitor C 15 Capacitor C 16 and capacitor C 17 ;

[0042] The same-name terminal of the primary coil of transformer T1 serves as the first input terminal of the output phase synthesis matching network, and the non-same-name terminals of the primary coil of transformer T1 are respectively connected to the grounding capacitor C. 14 and power supply V C1 The connection is made between the first terminal of the secondary winding of the transformer primary winding T1 and the capacitor C. 16 One end is connected to capacitor C 16 The other end serves as the output terminal of the output phase synthesis matching network. The non-identical terminals of the secondary coil of transformer T1 are respectively connected to the grounding capacitor C. 15 and power supply V C2Connected to the second input terminal of the output phase synthesis matching network, the second terminal of the secondary coil of transformer T1 is connected to the grounding capacitor C. 17 connect.

[0043] like Figure 2 As shown, the dual-path differential mode filter network includes inductor L2, capacitor C2, resistor R1, and resistor R2;

[0044] One end of inductor L2 is connected to one end of capacitor C2 and one end of resistor R1. The other end of resistor R1 is connected to the second output terminal of the first power adaptive bias adjustment amplifier network. The other end of inductor L2 is connected to the other end of capacitor C2 and one end of resistor R2. The other end of resistor R2 is connected to the second output terminal of the second power adaptive bias adjustment amplifier network.

[0045] The following is combined with Figure 2 The specific working principle and process of this invention are described below:

[0046] The radio frequency (RF) signal enters the input ESD protection and DC blocking matching network. After input impedance matching, the RF signal simultaneously enters the first power adaptive bias adjustment amplification network and the second power adaptive bias adjustment amplification network with equal or unequal power distribution for signal amplification. Then, it simultaneously enters the output phase synthesis matching network for power and phase synthesis before entering the amplifier's output port. The first power adaptive bias adjustment amplification network's amplifier has an operating conduction angle of 190–210° to achieve optimal power output capability and generate a third-order negative high-frequency parasitic component. The second power adaptive bias adjustment amplification network's amplifier has an operating conduction angle of 160–180° to achieve a good trade-off between output power and low power consumption and also generates a third-order positive high-frequency parasitic component. The output phase synthesis matching network performs harmonic parasitic component phase compensation between the third-order negative high-frequency parasitic component generated by the first power adaptive bias adjustment amplification network and the third-order positive high-frequency parasitic component generated by the second power adaptive bias adjustment amplification network, thereby improving linearity.

Claims

1. An amplifier based on power adaptive bias adjustment technology, characterized in that, It includes an input ESD protection and DC blocking matching network, a first power adaptive bias adjustment amplification network, a second power adaptive bias adjustment amplification network, an output phase synthesis matching network, and a dual-path differential mode filter network; The input terminal of the input ESD protection and DC blocking matching network serves as the RF input terminal of the amplifier. The output terminal of the input ESD protection and DC blocking matching network is connected to the input terminals of the first power adaptive bias adjustment amplification network and the second power adaptive bias adjustment amplification network, respectively. The first output terminal of the first power adaptive bias adjustment amplification network is connected to the first input terminal of the output phase synthesis matching network. The first output terminal of the second power adaptive bias adjustment network is connected to the second input terminal of the output phase synthesis matching network. The output terminal of the output phase synthesis matching network serves as the RF output terminal of the amplifier. The second output terminals of both the first power adaptive bias adjustment amplification network and the second power adaptive bias adjustment amplification network are connected to a dual-channel differential mode filter network; the first power adaptive bias adjustment amplification network includes transistors Q1, Q2, Q3, Q4, Q5, Q6, diodes D1 and D2, capacitors C3, C4, C5, C6, and C7, resistors R3, R4, R5, R6, R7, R8, R9, and R10, and inductors L3, L4, and L5; One end of the inductor L3 serves as the input terminal of the first power adaptive bias adjustment amplifier network. Its other end is connected to one end of the grounding capacitor C3 and one end of the inductor L4. The other end of the inductor L4 is connected to one end of the resistor R3, one end of the capacitor C4, and the base of the transistor Q3. The other end of the resistor R3 is connected to one end of the resistor R4 and the emitter of the transistor Q1. The other end of the resistor R4 is connected to the other end of the capacitor C4. The base of the transistor Q1 is connected to one end of the grounding capacitor C5, the anode of the diode D2, and one end of the resistor R6. The cathode of the diode D2 is connected to the anode of the diode D1, and the cathode of the diode D1 is grounded. The other end of resistor R6 is connected to the collector of transistor Q1 and one end of resistor R5. The other end of resistor R5 is connected to grounding capacitor C6, one end of resistor R7, one end of resistor R8, and one end of inductor L5. The other end of resistor R7 is connected to the collector and base of transistor Q2. The emitter of transistor Q2 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to grounding resistor R9 and the base of transistor Q6. The other end of resistor R8 is connected to the collector and base of transistor Q4. The emitter of transistor Q4 is connected to the base of transistor Q5 and one end of capacitor C7. The other end of capacitor C7 is connected to grounding resistor R10. The other end of inductor L5 serves as the first output terminal of the first power adaptive bias adjustment amplification network and is connected to the collector of transistor Q5. The emitter of transistor Q5 serves as the second output terminal of the first power adaptive bias adjustment amplification network and is connected to the collector of transistor Q6. The emitter of transistor Q6 is grounded.

2. The amplifier based on power adaptive bias adjustment technology according to claim 1, characterized in that, The input ESD protection and DC blocking matching network includes capacitor C1, inductor L1 and grounding capacitor C13; One end of capacitor C1 serves as the input terminal of the input ESD protection and DC blocking matching network and is connected to the grounding inductor L1. The other end of capacitor C1 is connected to the grounding capacitor C13 and serves as the output terminal of the input ESD protection and DC blocking matching network.

3. The amplifier based on power adaptive bias adjustment technology according to claim 1, characterized in that, The second power adaptive bias adjustment network includes transistors Q7, Q8, Q9, Q10, Q11, and Q12; diodes D3 and D4; capacitors C8, C9, C10, C11, and C12; resistors R11, R12, R13, R14, R15, R16, R17, and R18; and inductors L6, L7, and L8. One end of the inductor L7 serves as the input terminal of the second power adaptive bias adjustment network. Its other end is connected to the grounding capacitor C11 and one end of the inductor L8. The other end of the inductor L8 is connected to one end of the resistor R16, one end of the capacitor C8, and the base of the transistor Q8. The other end of the resistor R16 is connected to one end of the resistor R15 and the emitter of the transistor Q7. The other end of the resistor R15 is connected to the other end of the capacitor C8. The base of the transistor Q7 is connected to the grounding capacitor C9, the anode of the diode D4, and one end of the resistor R17. The cathode of the transistor D4 is connected to the anode of the diode D3, and the cathode of the diode D3 is grounded. The other end of resistor R17 is connected to the collector of transistor Q7 and one end of resistor R18. The other end of transistor R18 is connected to ground capacitor C10, one end of resistor R12, one end of resistor R11, and one end of inductor L6. The other end of resistor R12 is connected to the collector and base of transistor Q9. The emitter of transistor Q9 is connected to the collector of transistor Q8. The emitter of transistor Q8 is connected to ground resistor R14 and the base of transistor Q12. The other end of resistor R11 is connected to the crystal... The collector and base of transistor Q10 are connected. The emitter of transistor Q10 is connected to the base of transistor Q11 and one end of capacitor C12, respectively. The other end of capacitor C12 is connected to grounding resistor R13. The other end of inductor L6 serves as the first output terminal of the second power adaptive bias adjustment amplifier network and is connected to the collector of transistor Q11. The emitter of transistor Q11 serves as the second output terminal of the second power adaptive bias adjustment amplifier network and is connected to the collector of transistor Q12. The emitter of transistor Q12 is grounded.

4. The amplifier based on power adaptive bias adjustment technology according to claim 1, characterized in that, The output phase synthesis matching network includes transformer T1, capacitor C14, capacitor C15, capacitor C16, and capacitor C17; The same-name terminal of the primary coil of transformer T1 serves as the first input terminal of the output phase synthesis matching network. The non-same-name terminals of the primary coil of transformer T1 are connected to the grounding capacitor C14 and the power supply VC1, respectively. The first same-name terminal of the secondary coil of transformer T1 is connected to one end of capacitor C16, and the other end of capacitor C16 serves as the output terminal of the output phase synthesis matching network. The non-same-name terminals of the secondary coil of transformer T1 are connected to the grounding capacitor C15 and the power supply VC2, respectively, and serve as the second input terminal of the output phase synthesis matching network. The second same-name terminal of the secondary coil of transformer T1 is connected to the grounding capacitor C17.

5. The amplifier based on power adaptive bias adjustment technology according to claim 1, characterized in that, The dual-path differential mode filter network includes an inductor L2, a capacitor C2, a resistor R1, and a resistor R2; One end of the inductor L2 is connected to one end of the capacitor C2 and one end of the resistor R1. The other end of the resistor R1 is connected to the second output terminal of the first power adaptive bias adjustment amplifier network. The other end of the inductor L2 is connected to the other end of the capacitor C2 and one end of the resistor R2. The other end of the resistor R2 is connected to the second output terminal of the second power adaptive bias adjustment amplifier network.

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